MAX16952_技术文档

EVALUATION KIT AVAILABLE

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

General Description

Features

The MAX16952 is a current-mode, synchronous PWM

step-down controller designed to operate with input volt-

ages from 3.5V to 36V while using only 50µA of quies-

cent current at no load. The switching frequency is

adjustable from 1MHz to 2.2MHz by an external resistor

and can be synchronized to an external clock up to

2.4MHz. The MAX16952 output voltage is pin program-

mable to be either 5V fixed, or adjustable from 1V to 10V.

The wide input voltage range, along with its ability to

operate in dropout during undervoltage transients,

makes it ideal for automotive and industrial applications.

o Wide 3.5V to 36V Input Voltage Range

o 42V Input Transient Tolerance

o High Duty Cycle During Undervoltage Transients

o 1MHz to 2.2MHz Adjustable Switching Frequency

o Adjustable (1V to 10V) Output Voltage with 2ꢀ

Accuracy

o Three Operating Modes

50µA Ultra-Low Quiescent Current Skip Mode

Forced Fixed-Frequency Mode

External Frequency Synchronization

The MAX16952 operates in fixed-frequency PWM mode

and low quiescent current skip mode. It features an

enable logic input, which is compatible up to 42V to dis-

able the device and reduce its shutdown current to

10µA. Protection features include overcurrent limit, over-

voltage, undervoltage, and thermal shutdown with auto-

matic recovery. The device also features a power-good

monitor to ease power-supply sequencing.

o Lowest BOM Count, Current-Mode Control

Architecture

o Power-Good Output

o Enable Input Compatible from 3.3V Logic Level to

42V

o Current-Limit, Thermal Shutdown, and

Overvoltage Protection

o -40°C to +125°C Automotive Temperature Range

o Automotive Qualified

The MAX16952 is available in a thermally enhanced

16-pin TSSOP package with an exposed pad, and is

specified for operation over the -40°C to +125°C automo-

tive temperature range.

Typical Operating Circuit

Applications

V

BAT

Automotive

Industrial

C

IN

NH

C

BST

SUP

DH

COMP

BST

LX

Military

L

R

COMP

C

COMP2

Point of Load

MAX16952

C

COMP1

Ordering Information

R

SENSE

DL

NL

PART

TEMP RANGE

PIN-PACKAGE

PGOOD

EN

PGND

MAX16952AUE/V+

-40°C to +125°C

16 TSSOP-EP*

FSYNC

CS

OUT

FB

/V denotes an automotive qualified part.

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

V

OUT

5V

FOSC

C

OUT

BIAS

R

FOSC

SGND

C

L

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

19-5789; Rev 1; 10/12

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

ABSOLUTE MAXIMUM RATINGS

SUP and EN to SGND ............................................-0.3V to +42V

LX to PGND ..............................................................-1V to +42V

BST to LX .................................................................-0.3V to +6V

BIAS, FB, PGOOD, FSYNC to SGND .......................-0.3V to +6V

DH to LX ...................................................................-0.3V to +6V

PGND to SGND .....................................................-0.3V to +0.3V

Continuous Power Dissipation (T = +70°C)

A

TSSOP (derate 26.1mW/°C above +70°C).......................2088.8mW

Operating Temperature Range .........................-40°C to +125°C

Junction Temperature......................................................+150°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

DL to PGND .............................................-0.3V to (V

FOSC to SGND ........................................-0.3V to (V

CS and OUT to SGND............................................-0.3V to +11V

+ 0.3V)

BIAS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

PACKAGE THERMAL CHARACTERISTICS (Note 1)

TSSOP

Junction-to-Ambient Thermal Resistance (θ ) .........38.3°C/W

JA

Junction-to-Case Thermal Resistance (θ )...................3°C/W

JC

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

ELECTRICAL CHARACTERISTICS

(V

= V = 14V, C = 10µF, C

= 94µF, C

= 2.2µF, C

= 0.1µF, R

= 14.3kΩ, T = T = -40°C to +125°C, unless

SUP

EN

IN

OUT

BIAS

BST

FOSC

A

J

otherwise noted. Typical values are at T = +25°C.) (Note 2)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SUP Input Voltage Range

V

(Note 3)

Fixed 5V output, fixed-frequency, PWM

3.5

36

V

SUP

mode, V = V

FB

, no external FETs

BIAS

SUP Operating Supply Current

I

1

mA

SUP

connected

Skip Mode Supply Current

I

No load, fixed 5V output

50

10

90

20

µA

SKIP

SUP Shutdown Supply Current

I

V

= 0V

EN

SHDN,SUP

= 3.5V, I

= 45mA

3.0

5.0

3.1

SUP

BIAS

BIAS Voltage

V

BIAS

6V < V

< 36V

4.7

1.0

5.3

3.4

SUP

BIAS Undervoltage Lockout

V

BIAS

V

BIAS

V

SUP

rising

UVBIAS

BIAS Undervoltage Lockout

Hysteresis

falling

200

45

mV

mA

BIAS Minimum Load

I

- V

> 200mV

BIAS

BIAS(MIN)

OUTPUT VOLTAGE (OUT)

Output Voltage Adjustable

Range

10

V

ꢀ

V

OUT Pulldown Resistance

R

V

= 0V or fault condition active

30

PULL_D

EN

= 6V to 36V, V = V ,

BIAS

SUP

FB

Output Voltage (5V Fixed Mode)

V

4.925

0.99

5.0

5.075

1.01

OUT

fixed-frequency mode (Note 4)

FB Feedback Voltage

(Adjustable Mode)

V

SUP

= 6V to 36V, 0V < (V - V

) < 80mV,

OUT

CS

V

FB

1.0

V

fixed-frequency mode

FB Current

I

FB

V

= 1.0V

0.02

µA

FB

FB Line Regulation

= V

, 6V < V < 36V (Note 4)

SUP

%/V

EN

SUP

Maxim Integrated

2

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

ELECTRICAL CHARACTERISTICS (continued)

(V

= V = 14V, C = 10µF, C

= 94µF, C

= 2.2µF, C

= 0.1µF, R

= 14.3kΩ, T = T = -40°C to +125°C, unless

SUP

EN

IN

OUT

BIAS

BST

FOSC

A

J

otherwise noted. Typical values are at T = +25°C.) (Note 2)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Transconductance (from FB to

COMP)

g

m,EA

1200

µS

Error-Amplifier Output

Impedance

R

30

Mꢀ

OUT,EA

R

= 30.1kꢀ

1000

2000

80

FOSC

Operating Frequency

f

kHz

SW

= 14.3kꢀ

1800

1.4

-1

2200

FOSC

Minimum On-Time

t

ns

ON(MIN)

Maximum FSYNC Frequency

f

2400

kHz

FSYNC(MAX)

f

> 110% of internal frequency (20%

FSYNC

Minimum FSYNC Frequency

f

1100

kHz

FSYNC(MIN)

duty cycle), f

= 1000kHz

SW

FSYNC Logic-High Threshold

FSYNC Logic-Low Threshold

V

FSYNC,HI

V

0.4

+1

FSYNC,LO

FSYNC Internal Pulldown

Resistance

1

Mꢀ

CURRENT LIMIT

CS Input Current

I

V

CS

= V

= 0V or V (Note 5)

BIAS

µA

CS

OUT

During normal operation

22

32

OUT Input Current

I

OUT

V

FB

= V

BIAS

CS Current-Limit Voltage

Threshold

V

LIMIT

V

CS

- V

, V

= 5V, V ꢁ 2.5V

OUT

68

80

92

mV

OUT BIAS

FAULT DETECTION

Output Overvoltage Trip

Threshold

V

= V , rising edge

108

113

2.5

118

%V

FB

FB,OV

OUT

FB

Output Overvoltage Trip

Hysteresis

%

Rising edge

Falling edge

25

Output Overvoltage Fault

Propagation Delay

t

µs

OVP

Output Undervoltage Trip

Threshold

V

= V ; with respect to slewed FB

OUT FB

V

FB,UV

83

88

93

%V

FB

threshold, falling edge

Output Undervoltage Trip

Hysteresis

2.5

%

Falling edge

25

Output Undervoltage

Propagation Delay

µs

Rising edge (excluding startup)

PGOOD Output Low Voltage

PGOOD Leakage Current

V

I

= 3mA

SINK

0.4

V

PGOOD,L

I

1

µA

°C

PGOOD

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

T

(Note 5)

+175

15

SHDN

3

Maxim Integrated

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

ELECTRICAL CHARACTERISTICS (continued)

(V

= V = 14V, C = 10µF, C

= 94µF, C

= 2.2µF, C

= 0.1µF, R

= 14.3kΩ, T = T = -40°C to +125°C, unless

SUP

EN

IN

OUT

BIAS

BST

FOSC

A

J

otherwise noted. Typical values are at T = +25°C.) (Note 2)

A

PARAMETER

GATE DRIVE

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

(V

- V ) forced to 5V

10

2

BST

LX

DH Gate-Driver On-Resistance

DL Gate-Driver On-Resistance

DH/DL Dead Time (Note 5)

BST Input Current

R

ꢀ

DH

- V ) forced to 0V

LX

BST

DL = high state

DL = low state

DL rising

3.5

2

R

DL

30

t

ns

DEAD

DH rising

V

= 0V, V

= 5V,

BST

LX

I

1

5

µA

BST

- V = V - V = 0V

PGND

DH

LX

DL

BST On-Resistance

ENABLE INPUT

(Note 5)

15

ꢀ

EN Input Threshold Low

EN Input Threshold High

V

1.2

V

EN,LO

V

2.2

EN,HI

EN Threshold Voltage

Hysteresis

0.2

0.5

V

EN Input Current

SOFT-START

I

t

µA

EN

Soft-Start Ramp Time

5

ms

SS

Note 2: Devices tested at T = +25°C. Limits over temperature are guaranteed by design.

A

Note 3: For 3.5V operation, the n-channel MOSFET’s threshold voltage should be compatible to (lower than) this input voltage.

Note 4: Device not in dropout condition.

Note 5: Guaranteed by design; not production tested.

Maxim Integrated

4

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

Typical Operating Characteristics

(V

= V = 14V, C = 47µF, C

= 94µF, C

= 2.2µF, C

= 0.1µF, R

= 13kΩ, V = V

, R

BIAS

= 75Ω, T = +25°C,

SUP

EN

IN

OUT

BIAS

BST

FOSC

FB

A

BST

unless otherwise noted.)

STARTUP RESPONSE (SKIP MODE)

MAX16952 toc02

MAX16952 toc01

2.2MHz/3.3V

10V/div

0V

10V/div

2V/div

V

SUP

2V/div

0V

OUT

2A/div

5V/div

I

LOAD

0A

5V/div

0V

V

PGOOD

2.2MHz/5V

2ms/div

SKIP MODE SUPPLY CURRENT vs. V

PWM MODE SUPPLY CURRENT vs. V

EFFICIENCY vs. LOAD CURRENT

SUP

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

FIXED-FREQUENCY MODE

2.2MHz/5V

V

= 5V

V

= 3.3V

OUT

0

6

11

16

21

26

31

36

6

11

16

21

26

31

36

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

LOAD CURRENT (A)

V

(V)

V

(V)

SUP

SWITCHING FREQUENCY vs. R

EFFICIENCY vs. LOAD CURRENT

FOSC

3.0

100

90

80

70

60

50

40

30

20

10

0

SKIP MODE

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

V

= 5V

OUT

V

= 3.3V

0.01

OUT

10

15

20

25

(kI)

30

35

40

0.0001 0.001

0.1

1

10

R

LOAD CURRENT (A)

FOSC

5

Maxim Integrated

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

Typical Operating Characteristics (continued)

(V

= V = 14V, C = 47µF, C

= 94µF, C

= 2.2µF, C

= 0.1µF, R

= 13kΩ, V = V

, R

BIAS

= 75Ω, T = +25°C,

A

BST

SUP

EN

IN

OUT

BIAS

BST

FOSC

FB

unless otherwise noted.)

LOAD TRANSIENT (PWM MODE)

MAX16952 toc09

MAX16952 toc08

2.2MHz/5V

2.2MHz/3.3V

V

OUT

(AC-COUPLED)

OUT

500mV/div

200mV/div

(AC-COUPLED)

2A/div

0A

2A/div

0A

I

LOAD

I

LOAD

100µs/div

SYNCHRONIZATION WITH

COLD CRANK TEST (PWM MODE)

EXTERNAL SIGNAL AT FSYNC

MAX16952 toc10

MAX16952 toc11

V

2.2MHz/5V

SUP

5V/div

0V

10V/div

0V

V

LX

OUT

V

FSYNC

(EXTERNAL

SIGNAL

5V/div

0V

2V/div

0V

AT FSYNC)

5V/div

0V

V

PGOOD

5V/div

0A

I

LOAD

400ns/div

10ms/div

LOAD DUMP TEST (SKIP MODE)

LOAD DUMP TEST (PWM MODE)

MAX16952 toc13

MAX16952 toc12

2.2MHz/5V

V

SUP

V

SUP

20V/div

0V

20V/div

0V

2V/div

0V

V

5V/div

0V

OUT

V

OUT

V

PGOOD

5V/div

0V

5V/div

0V

100ms/div

Maxim Integrated

6

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

Typical Operating Characteristics (continued)

(V

= V = 14V, C = 47µF, C

= 94µF, C

= 2.2µF, C

= 0.1µF, R

= 13kΩ, V = V

, R

BIAS

= 75Ω, T = +25°C,

SUP

EN

IN

OUT

BIAS

BST

FOSC

FB

A

BST

unless otherwise noted.)

OUTPUT RESPONSE TO SLOW

RAMP AT SUP (PWM MODE)

OUTPUT RESPONSE TO SLOW

RAMP AT SUP (SKIP MODE)

MAX16952 toc15

MAX16952 toc14

2.2MHz/5V

= 0A

2.2MHz/5V

= 4A

I

10V/div

0V

LOAD

V

10V/div

0V

SUP

V

SUP

5V/div

0V

5V/div

0V

OUT

V

OUT

10V/div

0V

10V/div

0V

V

LX

V

LX

5V/div

0V

5V/div

0V

V

PGOOD

V

PGOOD

4s/div

SHORT-CIRCUIT TEST (SKIP MODE)

MAX16952 toc16

MAX16952 toc17

2.2MHz/5V

2.2MHz/3.3V

2V/div

0V

2V/div

0V

V

OUT

V

OUT

5A/div

0A

5A/div

0A

I

LX

I

LX

5V/div

0V

5V/div

0V

V

PGOOD

V

PGOOD

100µs/div

LOAD REGULATION (PWM MODE)

LOAD REGULATION (SKIP MODE)

V

OUT

vs. TEMPERATURE

5.2

5.1

5.0

4.9

4.8

4.7

4.6

5.2

5.1

5.0

4.9

4.8

4.7

4.6

5.5

5.4

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

4.5

2.2MHz/5V

PWM MODE

2.2MHz/5V

-40°C

+125°C

-40°C

SKIP MODE/0A LOAD

PWM MODE/4A LOAD

+125°C

+25°C

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

-40 -25 -10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

I (A)

LOAD

I

(A)

LOAD

7

Maxim Integrated

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

Typical Operating Characteristics (continued)

(V

= V = 14V, C = 47µF, C

= 94µF, C

= 2.2µF, C

= 0.1µF, R

= 13kΩ, V = V

, R

BIAS

= 75Ω, T = +25°C,

SUP

EN

IN

OUT

BIAS

BST

FOSC

FB

A

BST

unless otherwise noted.)

V

vs. I

BIAS

LINE REGULATION (PWM MODE)

LINE REGULATION (SKIP MODE)

BIAS

5.2

5.0

4.8

4.6

4.4

4.2

5.20

5.10

5.00

4.90

4.80

4.70

4.60

5.5

5.4

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

2.2MHz/5V

-40°C

+25°C

-40°C

+25°C

+125°C

2.2MHz/5V

4.5

6

0

10 20 30 40 50 60 70 80 90 100

(mA)

6

11

16

21

26

31

36

11

16

21

26

31

36

V

(V)

V

SUP

(V)

I

SUP

BAIS

SWITCHING FREQUENCY

vs. LOAD CURRENT

SHUTDOWN CURRENT vs. TEMPERATURE

SHUTDOWN CURRENT vs. V

SUP

10.60

2.5

2.4

2.3

2.2

2.1

2.0

20

18

16

14

12

10

8

V

= 14V

= 0V

SUP

2.2MHz/5V

PWM MODE

EN

10.55

10.50

10.45

10.40

10.35

10.30

6

4

2

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

3

6

9

12 15 18 21 24 27 30 33 36

(V)

V

I

(A)

SUP

LOAD

DIPS AND DROP TEST (PWM MODE)

MAX16952 toc27

MAX16952 toc28

2.2MHz/5V

2.2MHz/3.3V

10V/div

0V

10V/div

0V

I

= 4A

I

= 4A

LOAD

V

SUP

5V/div

0V

5V/div

0V

OUT

10V/div

0V

10V/div

0V

V

LX

5V/div

0V

5V/div

0V

V

PGOOD

10ms/div

Maxim Integrated

8

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

Pin Configuration

TOP VIEW

+

SUP

EN

1

2

3

4

5

6

7

8

16 BST

15 DH

FOSC

FSYNC

SGND

COMP

FB

14 LX

MAX16952

13 BIAS

12 DL

11 PGND

10 PGOOD

EP

CS

9

OUT

TSSOP

Pin Description

NAME

FUNCTION

Input Supply Voltage. SUP is the input voltage to the internal linear regulator. Bypass SUP to PGND with a

1µF minimum value ceramic capacitor.

1

SUP

Active-High Enable Input. EN is compatible with 5V and 3.3V logic levels. Drive EN logic-high to enable the

output or drive EN logic-low to put the controller in low-power shutdown mode. Connect EN to SUP for

always-on operation. Do not leave EN unconnected.

2

3

4

EN

Oscillator-Timing Resistor Input. Connect a resistor from FOSC to SGND to set the oscillator frequency

from 1MHz to 2.2MHz. See the Setting the Switching Frequency section.

FOSC

FSYNC

Synchronization and Mode Selection Input. Connect FSYNC to BIAS to select fixed-frequency PWM mode

and disable skip mode. Connect FSYNC to SGND to select skip mode. Connect FSYNC to an external

clock for synchronization. FSYNC is internally pulled down to ground with a 1Mꢀ resistor.

Signal Ground. Connect SGND directly to the local ground plane. Connect SGND to PGND at a single

point.

5

6

SGND

COMP

Error Amplifier Output. Connect COMP to the compensation feedback network. See the Compensation

Design section.

Feedback Regulation Point. Connect FB to BIAS for a fixed 5V output voltage. In adjustable mode,

connect to the center tap of a resistive divider from the output (V

The FB voltage regulates to 1V (typ).

) to SGND to set the output voltage.

7

8

FB

CS

OUT

Positive Current-Sense Input. Connect CS to the positive terminal of the current-sense element. Figure 4

shows two different current-sensing options: 1) accurate sense with a sense resistor or 2) lossless

inductor DCR sensing.

9

Maxim Integrated

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

Pin Description (continued)

NAME

FUNCTION

Output Sense and Negative Current-Sense Input. When using the internal preset 5V feedback divider

(FB = BIAS), the controller uses OUT to sense the output voltage. Connect OUT to the negative terminal

of the current-sense element.

9

OUT

Open-Drain Power-Good Output. A logic-high voltage on PGOOD indicates that the output voltage is in

10

PGOOD regulation. PGOOD is pulled low when the output voltage is out of regulation. Connect a 10kꢀ pullup

resistor from PGOOD to the digital interface voltage.

Power Ground. Connect the input and output filter capacitors’ negative terminals to PGND. Connect

PGND externally to SGND at a single point.

11

12

13

14

15

16

—

PGND

Low-Side Gate-Driver Output. DL swings from V

to PGND. If a resistor is needed between DL and the

BIAS

DL

BIAS

LX

gate of the MOSFET, contact the factory for the optimum value.

Internal 5V Linear Regulator Output. BIAS provides power for bias and gate drive. Connect a 2.2µF to

10µF ceramic capacitor from BIAS to PGND.

External Inductor Connection. Connect LX to the switched side of the inductor. LX serves as the lower

supply rail for the DH high-side gate driver.

High-Side Gate-Driver Output. DH swings from LX to BST. If a resistor is needed between DH and the gate

of the MOSFET, contact the factory for the optimum value.

DH

Boost Flying Capacitor Connection. Connect a ceramic capacitor between BST and LX. See the Boost-

Flying Capacitor Selection section for details.

BST

EP

Exposed Pad. Internally connected to ground. Connect EP to a large contiguous copper plane at SGND

potential to improve thermal dissipation. Do not use as the main ground connection.

Maxim Integrated

10

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

Functional Diagram

SUP

BST

EN

LDO

BST

SWITCH

EN

DH

LX

UG

MAX16952

SGND

BIAS

DL

BUCK

CONTROLLER

PGOOD

FB

REF

BIAS

LG

PWM

ILIM

EAFB

COMP

EA

REF

PGND

OSC

CLK

FOSC

CS

ZX

MODE

SYNC

FSYNC

CS

MODE

OUT

FBI

SGND

11

Maxim Integrated

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

A logic-low at EN shuts down the device. During shut-

Detailed Description

down, the internal linear regulator and gate drivers turn

off. Shutdown is the lowest power state and reduces

the quiescent current to 10µA (typ).

The MAX16952 is a current-mode, synchronous PWM

buck controller designed to drive logic-level MOSFETs.

The device tolerates a wide input voltage range from

3.5V to 42V and generates an adjustable 1V to 10V or

fixed 5V output voltage. This device can operate in

dropout mode, making it ideal for automotive and

industrial applications with undervoltage transients.

To protect the low-side MOSFET during shutdown, the

step-down regulator cannot be enabled until the output

voltage drops below 1.25V. An internal 30Ω pulldown

switch helps discharge the output. If the EN pin is tog-

gled low then high, the switching regulator shuts down

and remains off until the output voltage decays to

1.25V. At this point, the MAX16952 turns on using the

soft-start sequence.

The internal switching frequency is adjustable from

1MHz to 2.2MHz with an external resistor and can be

synchronized to an external clock. The high switching

frequency reduces output ripple and allows the use of

small external components. The device operates in

both fixed-frequency PWM mode and a low quiescent

current skip mode. While working in skip mode, the

operating current is as low as 50µA.

Fixed 5V Linear Regulator (BIAS)

The MAX16952 has an internal 5V linear regulator to

provide its own 5V bias from a high-voltage input supply

at SUP. This bias supply powers the gate drivers for the

external n-channel MOSFETs and provides the power

required for the analog controller, reference, and logic

blocks. The bias rail needs to be stabilized by a 2.2µF or

greater capacitance at BIAS, and can provide up to

45mA (typ) total current.

The device features an enable logic input to disable the

device and reduce its shutdown current to 10µA.

Protection features include cycle-by-cycle current limit,

overvoltage detection, and thermal shutdown. The

device also features integrated soft-start and a power-

good monitor to help with power sequencing.

The linear regulator has an overcurrent threshold of

approximately 100mA. In case of an overcurrent event,

the current is limited to 100mA and the BIAS voltage

Supply Voltage Range (SUP)

The supply voltage range (V ) of the MAX16952 is com-

SUP

starts to droop. As soon as V

drops to 2.9V (typ),

BIAS

patible to the typical automotive battery voltage range

from 3.5V to 36V and can tolerate up to 42V transients.

the step-down converter shuts down and the power

MOSFETs are turned off.

Slow Ramp-Up of the Input Voltage

Oscillator Frequency and

External Synchronization

The MAX16952 provides an internal oscillator

adjustable from 1MHz to 2.2MHz. To set the switching

frequency, connect a resistor from FOSC to SGND. See

the Setting the Switching Frequency section.

If the input voltage (V

) ramps up slowly, the device

SUP

operates in dropout mode until V

is greater than the

SUP

regulated output voltage. The dropout mode is detected

by monitoring high-side FET on for eight clock cycles.

Once dropout mode is detected, the controller issues a

forced low-side pulse at the rising edge of switching

clock to refresh the BST capacitor. This maintains the

proper BST voltage to turn on the high-side MOSFET

when the device is in dropout mode.

The MAX16952 can also be synchronized to an external

clock by connecting the external clock signal to

FSYNC. For proper frequency synchronization,

FSYNC’s input frequency must be at least 10% higher

than the programmed internal oscillator frequency. A

rising clock edge on FSYNC is interpreted as a syn-

chronization input. If the FSYNC signal is lost, the inter-

nal oscillator takes control of the switching rate,

returning to the switching frequency set by the resistor

connected to FOSC. This maintains output regulation

even with intermittent FSYNC signals. The maximum

synchronizable frequency is 2.4MHz.

System Enable (EN) and Soft-Start

An enable control input (EN) activates the MAX16952

from its low-power shutdown mode. EN is compatible

with inputs from automotive battery level down to

3.5V. The high-voltage compatibility allows EN to be

connected to SUP, KEY/KL30, or the inhibit pin (INH)

of a CAN transceiver.

A logic-high at EN turns on the internal regulator. Once

V

BIAS

is above the internal lockout level, V

= 3.1V (typ),

UVL

When FSYNC is connected to SGND, the device oper-

ates in skip mode. When FSYNC is connected to BIAS

or driven by an external clock, the MAX16952 operates

in skip mode during soft-start and transitions to fixed-

frequency PWM mode after soft-start is over.

the controller starts up with a 5ms fixed soft-start time.

Once regulation is reached, PGOOD goes high

impedance.

Maxim Integrated

12

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

applications. PGOOD can sink up to 3mA of current

while low.

Error Detection and Fault Behavior

Several error-detection mechanisms prevent damage to

the MAX16952 and the application circuit:

PGOOD asserts low during the following conditions:

•

Overcurrent protection

•

Standby mode

Output overvoltage protection

Undervoltage lockout at BIAS

Power-good detection of the output voltage

Overtemperature protection of the IC

Undervoltage with V

value

below 88% (typ) its set

OUT

•

Overvoltage with V

value

above 113% (typ) its set

OUT

The power-good levels are measured at FB if a feed-

back divider is used. If the MAX16952 is used in 5V

mode with FB connected to BIAS, OUT is used as a

feedback path for voltage regulation and power-good

determination.

Overcurrent Protection

The MAX16952 provides cycle-by-cycle current limiting

as long as the FB voltage is greater than 0.7V (i.e., 70%

of the regulated output voltage). If the output voltage

drops below 70% of the regulation point due to overcur-

rent event, 16 consecutive current-limit events initiate

restart. If the overcurrent is still present during restart,

the MAX16952 shuts down and initiates restart. This

automatic restart continues until the overcurrent condi-

tion disappears. If the overcurrent condition disappears

at any restart attempt, the device enters the normal

soft-start routine.

Overtemperature Protection

Thermal-overload protection limits total power dissipa-

tion in the MAX16952. When the junction temperature

exceeds +175°C (typ), an internal thermal sensor shuts

down the step-down controller, allowing the IC to cool.

The thermal sensor turns on the IC again after the junc-

tion temperature cools by 15°C and the output voltage

has dropped below 1.25V (typ).

If the output is shorted through a long wire, output volt-

age can fall significantly below ground before reaching

the overcurrent limit. Under this condition, the

MAX16952 stops switching and initiates restart as soon

as output drops to 20% of its regulation point.

A continuous overtemperature condition can cause

on-/off-cycling of the device.

Fixed-Frequency, Current-Mode

PWM Controller

Output Overvoltage Protection

The MAX16952’s step-down controller uses a PWM,

current-mode control scheme. An internal transconduc-

tance amplifier establishes an integrated error voltage.

The heart of the PWM controller is an open-loop com-

parator that compares the integrated voltage-feedback

signal against the amplified current-sense signal plus

the slope compensation ramp, which are summed into

the main PWM comparator to preserve inner-loop sta-

bility and eliminate inductor stair-casing. At each falling

edge of the internal clock, the high-side MOSFET turns

on until the PWM comparator trips, the maximum duty

cycle is reached, or the peak current limit is reached.

During this on-time, current ramps up through the

inductor, storing energy in its magnetic field and sourc-

ing current to the output. The current-mode feedback

system regulates the peak inductor current as a func-

tion of the output-voltage error signal. The circuit acts

as a switch-mode transconductance amplifier and elim-

inates the influence of the output LC filter double pole.

The MAX16952 features an internal output overvoltage

protection. If V

intended regulation voltage, the high-side MOSFET

turns off and the low-side MOSFET turns on. The low-

side MOSFET stays on until V

lation. Once V

cycles continue.

increases by 13% (typ) of the

OUT

goes back into regu-

OUT

is in regulation, the normal switching

OUT

Undervoltage Lockout (UVLO)

The BIAS input undervoltage lockout (UVLO) circuitry

inhibits switching if the 5V bias supply (BIAS) is below

its UVLO threshold, 3.1V (typ). If the BIAS voltage

drops below the UVLO threshold, the controller stops

switching and turns off both high-side and low-side

gate drivers until the BIAS voltage recovers.

Power-Good Detection (PGOOD)

The MAX16952 includes a power-good comparator

with added hysteresis to monitor the step-down con-

troller’s output voltage and detect the power-good

threshold. The PGOOD output is open drain and should

be pulled up with an external resistor to the supply volt-

age of the logic input it drives. This voltage should not

exceed 6V. A 10kΩ pullup resistor works well in most

During the second half of the cycle, the high-side

MOSFET turns off and the low-side MOSFET turns on.

The inductor releases the stored energy as the current

ramps down, providing current to the output. The out-

put capacitor stores charge when the inductor current

13

Maxim Integrated

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

exceeds the required load current and discharges

when the inductor current is lower, smoothing the volt-

age across the load. Under soft-overload conditions,

when the peak inductor current exceeds the selected

current limit, the high-side MOSFET is turned off imme-

diately. The low-side MOSFET is turned on and

remains on to let the inductor current ramp down until

the next clock cycle.

output, another on-time cannot begin until the output

voltage drops below the feedback threshold. Because

the zero-crossing comparator prevents the switching

regulator from sinking current, the controller must skip

pulses. Therefore, the controller regulates the valley of

the output ripple under light-load conditions.

Automatic Pulse-Skipping Crossover

In skip mode, an inherent automatic switchover to pulse

frequency modulation (PFM) takes place at light loads.

This switchover is affected by a comparator that trun-

cates the low-side switch on-time at the inductor cur-

rent’s zero crossing. The zero-crossing comparator

senses the inductor current across CS to OUT. Once

Forced Fixed-Frequency PWM Mode

The low-noise forced fixed-frequency PWM mode

(FSYNC connected to BIAS or an external clock) dis-

ables the zero-crossing comparator, which controls the

low-side switch on-time. This forces the low-side gate-

driver waveform to constantly be the complement of the

high-side gate-drive waveform. The inductor current

reverses at light loads while DH maintains a duty factor

(V

- V

) drops below the 6mV zero-crossing, cur-

OUT

CS

rent-sense threshold, the comparator forces DL low.

This mechanism causes the threshold between pulse-

skipping PFM and nonskipping PWM operation to coin-

cide with the boundary between continuous and

discontinuous inductor-current operation (also known

as the critical conduction point). The load-current level

of V

/V

.

OUT SUP

The benefit of forced fixed-frequency PWM mode is to

keep the switching frequency fairly constant. However,

forced fixed-frequency PWM operation comes at a cost:

the no-load 5V supply current can be up to 45mA,

depending on the external MOSFETs and switching fre-

quency. Forced fixed-frequency PWM mode is most

useful for avoiding audio frequency noises and improv-

ing load-transient response.

at which PFM/PWM crossover occurs, I

given by:

, is

LOAD(SKIP)

V

− V

V

(

)

SUP

OUT OUT

I

A =

[ ]

)

LOAD SKIP

(

2× V

× f

MHz × L µH

[

]

[

]

SUP SW

The switching waveforms can appear noisy and asyn-

chronous when light-loading causes pulse-skipping

operation. This is a normal operating condition that

results in high light-load efficiency. Trade-offs in PFM

noise vs. light-load efficiency is made by varying the

inductor value. Generally, low inductor values pro-

duce a broader efficiency versus load current, while

higher values result in higher full-load efficiency

(assuming that the coil resistance remains constant)

and less output-voltage ripple. Drawbacks of using

higher inductor values include larger physical size

and degraded load-transient response (especially at

low input-voltage levels).

Light-Load Low-Quiescent Operating

(Skip) Mode

The MAX16952 includes a light-load operating mode

control input (FSYNC = SGND) used to enable or dis-

able the zero-crossing comparator. When the zero-

crossing comparator is enabled, the regulator forces

DL low when the current-sense inputs detect zero

inductor current. This keeps the inductor from discharg-

ing the output capacitor and forces the regulator to skip

pulses under light-load conditions to avoid overcharg-

ing the output.

The lowest operating currents can be achieved in skip

mode. When the MAX16952 operates in skip mode with

no external load current, the overall current consump-

tion can be as low as 50µA. A disadvantage of skip

mode is that the operating frequency is not fixed.

MOSFET Gate Drivers (DH and DL)

The DH and DL drivers are optimized for driving logic-

level n-channel power MOSFETs. The DH high-side n-

channel MOSFET driver is powered by charge pumping

at BST, while the DL synchronous rectifier drivers are

powered directly by the 5V linear regulator (BIAS).

Skip-Mode Current-Sense Threshold

When skip mode is enabled, the on-time of the step-

down controller terminates when the output voltage

exceeds the feedback threshold and when the current-

sense voltage exceeds the idle-mode current-sense

An adaptive dead-time circuit monitors the DH and DL

outputs and prevents the opposite-side MOSFET from

turning on until the other MOSFET is fully off. Thus, the

circuit allows the high-side driver to turn on only when

the DL gate driver has been turned off. Similarly, it pre-

vents the low-side (DL) from turning on until the DH

gate driver has been turned off.

threshold (V

). See Figure 1. Under light-load

CS,IDLE

conditions, the on-time duration depends solely on the

skip-mode current-sense threshold, which is 25mV (typ).

This forces the controller to source a minimum amount

of power with each cycle. To avoid overcharging the

Maxim Integrated

14

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

High-Side Gate-Drive Supply (BST)

The high-side MOSFET is turned on by closing an inter-

nal switch between BST and DH. This provides the

necessary gate-to-source voltage to turn on the high-

side MOSFET, an action that boosts the gate-drive signal

above V

. The boost capacitor connected between

SUP

V

BST and LX holds up the voltage across the flying gate

driver during the high-side MOSFET on-time.

OUT

f

t

=

ON(SKIP)

V

SUP SW

I

PK

The charge lost by the boost capacitor for delivering

the gate charge is refreshed when the high-side

MOSFET is turned off and the LX node swings down

to ground. When the LX node is low, an internal high-

voltage switch connected between BIAS and BST

recharges the boost capacitor to the BIAS voltage.

See the Boost-Flying Capacitor Selection section to

choose the right size of the boost capacitor.

I

= I /2

LOAD PK

0

TIME

ON-TIME

Dropout Behavior During Undervoltage Transition

The controller generates a low-side pulse every eight

clock cycles to refresh the BST capacitor during low-

dropout operation. This guarantees that the MAX16952

operates in dropout mode during undervoltage tran-

sients like cold crank. See the Boost-Flying Capacitor

Selection section for more details.

Figure 1. Pulse-Skipping/Discontinuous Crossover Point

The adaptive driver dead-time allows operation without

shoot-through with a wide range of MOSFETs, minimiz-

ing delays and maintaining efficiency. There must be a

low-resistance, low-inductance path from the DL and

DH drivers to the MOSFET gates for the adaptive dead-

time circuits to work properly. Otherwise, because of

the stray impedance in the gate discharge path, the

sense circuitry could interpret the MOSFET gates as off

Current Limiting and Current-Sense Inputs

(CS and OUT)

The current-limit circuit uses differential current-sense

inputs (CS and OUT) to limit the peak inductor current.

If the magnitude of the current-sense signal exceeds

the current-limit threshold, the PWM controller turns off

the high-side MOSFET. The actual maximum load cur-

rent is less than the peak current-limit threshold by an

amount equal to half the inductor ripple current.

Therefore, the maximum load capability is a function of

the current-sense resistance, inductor value, switching

while the V

of the MOSFET is still high. To minimize

GS

stray impedance, use very short, wide traces (50 mils to

100 mils wide if the MOSFET is 1in from the controller).

Synchronous rectification reduces conduction losses in

the rectifier by replacing the normal low-side Schottky

catch diode with a low-resistance MOSFET switch. The

internal pulldown transistor that drives DL low is robust,

with a 2Ω (typ) on-resistance. This low on-resistance

helps prevent DL from being pulled up during the fast

rise time of the LX node, due to capacitive coupling

from the drain to the gate of the low-side synchronous

rectifier MOSFET. Applications with high-input voltages

and long-inductive driver traces can require additional

gate-to-source capacitance. This ensures that fast-ris-

ing LX edges do not pull up the low-side MOSFET’s

gate, causing shoot-through currents. The capacitive

coupling between LX and DL created by the MOSFET’s

frequency, and duty cycle (V

Current Sensing section.

/V

). See the

OUT SUP

Design Procedure

Effective Input Voltage Range

Although the MAX16952 controller can operate from

input supplies up to 42V and regulate down to 1V, the

minimum voltage conversion ratio (V

/V

) might

OUT SUP

be limited by the minimum controllable on-time. For

proper fixed-frequency PWM operation, the voltage

conversion ratio should obey the following condition:

gate-to-drain capacitance (C

= C

GD

), gate-to-

RSS

GD

source capacitance (C = C

- C ), and additional

GS

ISS

board parasitic should not exceed the following mini-

mum threshold:

V

OUT

> t

× f

ON(MIN) SW

V

SUP

⎛

⎜

⎝

⎞

⎟

⎠

C

RSS

V

> V

SUP

GS(TH)

C

where t

is 80ns and f

quency in Hz. If the desired voltage conversion does

is the switching fre-

SW

ON(MIN)

ISS

15

Maxim Integrated

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

not meet the above condition, then pulse skipping

occurs to decrease the effective duty cycle. To avoid

this, decrease the switching frequency or lower the

OUT

input voltage (V

).

SUP

R

FB1

FB2

Setting the Output Voltage

Connect FB to BIAS to enable the fixed step-down con-

troller output voltage (5V), set by a preset, internal

resistive voltage-divider connected between the output

(OUT) and SGND.

FB

To achieve other output voltages between 1V to 10V,

connect a resistive divider from OUT to FB to SGND

MAX16952

(Figure 2). Select R

(FB to SGND resistor) less than

FB2

or equal to 100kΩ. Calculate R

(OUT to FB resistor)

FB1

with the following equation:

⎡

⎤

⎛

⎞

⎟

⎠

V

OUT

R

= R

− 1

⎢⎜

⎥

FB1

FB2

⎢ V

⎥

⎦

⎝

⎣

FB

Figure 2. Adjustable Output Voltage

where V = 1V (typ) (see the Electrical Characteristics

FB

table) and V

can range from 1V to 10V.

OUT

SWITCHING FREQUENCY vs. R

FOSC

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

Setting the Switching Frequency

The switching frequency, f , is set by a resistor

SW

(R

) connected from FOSC to SGND. See Figure 3

FOSC

to select the correct R

switching frequency.

value for the desired

FOSC

For example, a 2MHz switching frequency is set with

= 14.3kΩ. Higher frequencies allow designs with

R

FOSC

lower inductor values and less output capacitance.

Consequently, peak currents and I²R losses are lower

at higher switching frequencies, but core losses, gate-

charge currents, and switching losses increase.

Inductor Selection

Three key inductor parameters must be specified for

operation with the MAX16952: inductance value (L),

10

15

20

25

(kI)

30

35

40

R

FOSC

inductor saturation current (I

DCR

), and DC resistance

SAT

Figure 3. Switching Frequency vs. R

FOSC

(R

). To select inductance value, the ratio of inductor

peak-to-peak AC current to DC average current (LIR)

must be selected first. A good compromise between

size and loss is a 30% peak-to-peak ripple current to

average-current ratio (LIR = 0.3). The switching fre-

quency, input voltage, output voltage, and selected LIR

then determine the inductor value as follows:

load current. The switching frequency is set by R

(see the Setting the Switching Frequency section).

FOSC

The MAX16952 uses internal frequency independent

slope compensation to ensure stable operation at duty

cycles above 50%. Use the equation below to select

the inductor value:

V

− V

(

)

OUT SUP(MIN)

OUT

L =

V

[V]

V

× f × I

× LIR

OUT

SUP(MIN) SW OUT(MAX)

= 1 25%

L[µH]× f [MHz]

SW

where V

is the minimum supply voltage, V

is

SUP(MIN)

the typical output voltage, and I

OUT

is the maximum

OUT(MAX)

Maxim Integrated

16

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

However, if it is necessary, higher inductor values can

be selected.

while the inductor is ramping up and the voltage sag

before the next pulse can occur:

The exact inductor value is not critical and can be

adjusted to make trade-offs among size, cost, efficien-

cy, and transient response requirements. Table 1

shows a comparison between small and large inductor

sizes.

2

L ∆I

∆I

t − ∆t

(

)

(

)

LOAD(MAX)

V

=

+

SAG

C

2C

V

× D

− V

OUT

(

)

(

)

OUT

SUP

MAX

where D

is the maximum duty factor (see the

MAX

Electrical Characteristics table), L is the inductor

value in µH, C is the output capacitor value in µF, t

Table 1. Inductor Size Comparison

OUT

is the switching period (1/f ) in µs, and ∆t equals

SW

INDUCTOR SIZE

(V

/V

) × t when in fixed-frequency PWM mode, or

OUT SUP

SMALLER

Lower price

LARGER

L × 0.2 × I

/(V

- V

) when in skip mode. The

OUT

MAX SUP

Smaller ripple

Higher efficiency

amount of overshoot (V

) during a full-load to no-

SOAR

load transient due to stored inductor energy can be cal-

culated as:

Smaller form factor

Larger fixed-frequency range

in skip mode

Faster load response

2

∆I

L

(

)

LOAD(MAX)

V

≈

SOAR

2C

V

OUT OUT

The minimum practical inductor value is one that

causes the circuit to operate at the edge of critical

conduction (where the inductor current just touches

zero with every cycle at maximum load). Inductor val-

ues lower than this grant no further size-reduction

benefit. The optimum operating point is usually found

between 25% and 45% ripple current. When pulse

skipping (FSYNC low and light loads), the inductor

value also determines the load-current value at which

PFM/PWM switchover occurs.

Current Sensing

For the most accurate current sensing, use a current-

sense resistor (R ) between the inductor and the

SENSE

output capacitor. Connect CS to the inductor side of

, and OUT to the capacitor side. Size R

R

SENSE

such that its maximum current (I ) induces a voltage

OC

of V

(68mV minimum) across R

.

LIMIT

SENSE

If a higher voltage drop across R

must be tolerated,

SENSE

divide the voltage across the sense resistor with a

For the selected inductance value, the actual peak-to-

voltage-divider between CS and OUT to reach V

(68mV minimum).

LIMIT

peak inductor ripple current (∆I ) is defined by:

INDUCTOR

The current-sense method (Figure 4) and magnitude

determine the achievable current-limit accuracy and

power loss. Typically, higher current-sense limits

provide tighter accuracy, but also dissipate more

power. For the best current-sense accuracy and over-

current protection, use a 1% tolerance current-sense

resistor with low parasitic inductance between the

inductor and output as shown in Figure 4a.

V

− V

(

)

OUT SUP

OUT

∆I

=

INDUCTOR

V

× f × L

SUP SW

where ∆I

is in mA, L is in µH, and f

is in kHz.

INDUCTOR

SW

The core must be large enough not to saturate at the

peak inductor current (I ):

PEAK

Alternatively, high-power applications that do not

require highly accurate current-limit protection can

reduce the overall power dissipation by connecting a

series RC circuit across the inductor (Figure 4b) with an

equivalent time constant:

∆I

INDUCTOR

I

= I

+

PEAK LOAD(MAX)

2

Transient Response

The inductor ripple current also impacts transient

response performance, especially at low V - V

differentials. Low inductor values allow the inductor cur-

rent to slew faster, replenishing charge removed from

the output filter capacitors by a sudden load step. The

total output voltage sag is the sum of the voltage sag

SUP

OUT

R

⎛

⎞

2

R

=

R

DCR

CSHL

⎜

⎝

⎟

⎠

R1+ R2

17

Maxim Integrated

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

and:

Carefully observe the PCB layout guidelines to ensure

the noise and DC errors do not corrupt the differential

current-sense signals seen by CS and OUT. Place the

sense resistor close to the IC with short, direct traces,

making a Kelvin-sense connection to the current-sense

resistor.

L

1

⎛

⎞

R

=

+

⎜

⎝

⎟

⎠

DCR

C

R1 R2

EQ

where R

is the required current-sense resistor and

is the inductor’s series DC resistance. Use the

CSHL

R

DCR

typical inductance and R

inductor manufacturer.

values provided by the

DCR

INPUT (V )

IN

C

IN

MAX16952

NH

NL

DH

LX

DL

L

R

SENSE

C

OUT

DL

GND

CS

OUT

a) OUTPUT SERIES RESISTOR SENSING

INPUT (V )

IN

C

IN

MAX16952

NH

DH

INDUCTOR

L

R

DCR

LX

NL

C

OUT

DL

R1

R2

R

=

R

CSHL

DCR

(_{R1 + R2})

GND

L

1

R

DCR

=

+

[_R1]

C

R2

CS

EQ

OUT

b) LOSSLESS INDUCTOR SENSING

Figure 4. Current-Sense Configurations

Maxim Integrated

18

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

load to no-load conditions without tripping the overvolt-

age fault protection. When using high-capacitance,

low-ESR capacitors, the filter capacitor’s ESR domi-

nates the output-voltage ripple. The size of the output

capacitor depends on the maximum ESR required to

Input Capacitor

The input filter capacitor reduces peak currents drawn

from the power source and reduces noise and voltage

ripple on the input caused by the circuit’s switching.

The input capacitor RMS current requirement (I

defined by the following equation:

) is

RMS

meet the output-voltage ripple (V

tions:

) specifica-

RIPPLE(P-P)

V

− V

(

)

OUT SUP OUT

I

= I

RMS LOAD(MAX)

V

= ESR × I

× LIR

RIPPLE(P−P)

LOAD(MAX)

V

SUP

I

has a maximum value when the input voltage

RMS

In skip mode, the inductor current becomes discontinu-

ous, with the peak current set by the skip-mode current-

equals twice the output voltage (V

= 2V

), so

OUT

SUP

I

= I

/2.

RMS(MAX)

LOAD(MAX)

sense threshold (V

= 32mV, typ). In skip mode, the

SKIP

Choose an input capacitor that exhibits less than +10°C

self-heating temperature rise at the RMS input current

for optimal long-term reliability.

no-load output ripple can be determined as follows:

V

× ESR

SKIP

R

V

=

RIPPLE(P−P)

The input-voltage ripple comprises ∆V (caused by the

capacitor discharge) and ∆V

Q

SENSE

(caused by the ESR of

ESR

the capacitor). Use low-ESR ceramic capacitors with

high-ripple current capability at the input. Assume the

contribution from the ESR and capacitor discharge is

equal to 50%. Calculate the input capacitance and ESR

required for a specified input voltage ripple using the

following equations:

The actual capacitance value required relates to the

physical size needed to achieve low ESR, as well as to

the chemistry of the capacitor technology. Thus, the

capacitor is usually selected by ESR and voltage rating

rather than by capacitance value.

When using low-value filter capacitors, such as ceramic

capacitors, size is usually determined by the capacity

∆V

ESR

=

IN

∆I

needed to prevent V

and V

from causing

SOAR

SAG

L

I

+

OUT

problems during load transients. Generally, once

enough capacitance is added to meet the overshoot

requirement, undershoot at the rising load edge is no

2

where:

and:

longer a problem (see the V

and V

equations

SOAR

SAG

V

− V

× V

× L

(

)

SUP

OUT OUT

in the Transient Response section). However, low-value

filter capacitors typically have high-ESR zeros that can

affect the overall stability.

∆I =

L

V

× f

SUP

SW

Compensation Design

The MAX16952 uses an internal transconductance error

amplifier with its inverting input and its output available

to the user for external frequency compensation. The

output capacitor and compensation network determine

the loop stability. The inductor and the output capacitor

are chosen based on performance, size, and cost.

Additionally, the compensation network optimizes the

control-loop stability.

I

× D 1− D

(

)

OUT

C

=

IN

∆V × f

Q

SW

where:

V

OUT

D =

V

SUP

The controller uses a current-mode control scheme that

regulates the output voltage by forcing the required

current through the external inductor. The MAX16952

uses the voltage drop across the DC resistance of the

inductor or the alternate series current-sense resistor to

measure the inductor current. Current-mode control

eliminates the double pole in the feedback loop caused

Output Capacitor

The output filter capacitor must have low enough ESR

to meet output ripple and load-transient requirements,

yet have high enough ESR to satisfy stability require-

ments. The output capacitance must be high enough to

absorb the inductor energy while transitioning from full-

19

Maxim Integrated

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

by the inductor and output capacitor, resulting in a

smaller phase shift and requiring less elaborate error-

amplifier compensation than voltage-mode control. A

The feedback voltage-divider has a gain of GAIN

FB OUT FB

=

FB

V

/V

, where V is 1V (typ).

The transconductance error amplifier has a DC gain of

simple single-series resistor (R ) and capacitor (C )

C

GAIN

= g

× R

, where g

is the

m,EA

EA(dc)

m,EA

OUT,EA

m,EA

are required to have a stable, high-bandwidth loop in

applications where ceramic capacitors are used for

output filtering (Figure 5). For other types of capacitors,

due to the higher capacitance and ESR, the frequency

of the zero created by the capacitance and ESR is

lower than the desired closed-loop crossover frequen-

cy. To stabilize a nonceramic output capacitor loop,

error amplifier transconductance, and R

OUT,EA

output resistance of the error amplifier. Use g

of

2500µS (max) and R

of 30MΩ (typ) for compen-

OUT,EA

sation design with the highest phase margin.

A dominant pole (f ) is set by the compensation

dpEA

capacitor (C ), the compensation resistor (R ), and the

C

amplifier output resistance (R

). A zero (f

) is

zEA

OUT,EA

add another compensation capacitor (C ) from COMP

F

to SGND to cancel this ESR zero.

set by the compensation resistor (R ) and the compen-

C

sation capacitor (C ). There is an optional pole (f

)

C

pEA

The basic regulator loop is modeled as a power modu-

lator, output feedback divider, and an error amplifier.

set by C and R to cancel the output capacitor ESR

F

C

zero if it occurs near the crossover frequency (f ,

C

The power modulator has a DC gain set by g

×

mc

, the out-

where the loop gain equals 1 (0dB)).

Thus:

R

, with a pole and zero pair set by R

LOAD

put capacitor (C

), and its ESR. The following equa-

OUT

tions determine the approximate value for the gain of

the power modulator (GAIN ), neglecting the

effect of the ramp stabilization. Ramp stabilization is

necessary when the duty cycle is above 50% and is

internally and automatically done for the MAX16952:

1

f

=

MOD(dc)

dpEA

2π × C × R

+ R

C

(

)

C

OUT,EA

1

f

=

zEA

2π × C × R

C

R

× f × L

LOAD SW

GAIN

≅ g

×

MOD(dc)

mc

R

+ f × L

(

)

LOAD

SW

1

f

pEA

2π × C × R

where R

= V

/I

in Ω, f

is the switch-

SW

LOAD

OUT OUT(MAX)

F

C

ing frequency in MHz, L is the output inductance in µH,

and g = 1/(A × R ) in S. A is the voltage

The loop-gain crossover frequency (f ) should be set

C

mc

V_CS

DC

V_CS

below 1/5 the switching frequency and much higher

gain of the current-sense amplifier and is typically

than the power-modulator pole (f

):

pMOD

11V/V. R

current-sense resistor in Ω.

is the DC-resistance of the inductor or the

DC

f

SW

In a current-mode step-down converter, the output

capacitor, its ESR, and the load resistance introduce a

pole at the following frequency:

f

<< f ≤

C

pMOD

5

The total loop gain as the product of the modulator

gain, the feedback voltage-divider gain, and the error

1

f

=

pMOD

⎛

⎞

R

× f × L

amplifier gain at f should be equal to 1. So:

C

LOAD SW

⎜

⎟

2π × C

×

+ ESR

OUT

R

+ f × L

(

)

⎝ LOAD

SW

⎠

V

FB

GAIN

×

× GAIN

= 1

The output capacitor and its ESR also introduce a zero at:

MOD fC

EA fC

(

)

(

)

V

OUT

1

f

=

zMOD

For the case where f

is greater than f :

C

zMOD

2π × ESR × C

OUT

GAIN

= g

× R

When C

is composed of n identical capacitors in

m,EA

C

EA fC

OUT

(

)

parallel, the resulting C

= n × C

, and ESR

OUT

OUT(EACH)

f

pMOD

= ESR

/n. Note that the capacitor zero for a paral-

(EACH)

GAIN

= GAIN

×

MOD(dc)

MOD fC

(

)

f

lel combination of like capacitors is the same as for an

individual capacitor.

C

Maxim Integrated

20

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

Therefore:

GAIN

Solving for R :

C

V

× f

V

OUT

C

FB

R

=

×

× g

× R = 1

C

m,EA C

MOD fC

(

)

g

× V × GAIN

× f

zMOD

C

V

m,EA

FB

MOD f

OUT

(

)

Solving for R :

Set the error-amplifier compensation zero formed by R

C

and C at the f

(f

= f

):

C

pMOD zEA

pMOD

V

OUT

R

=

C

1

g

× V × GAIN

FB

MOD fC

m,EA

(

)

C

=

C

2π × f

× R

C

2MOD

Set the error-amplifier compensation zero formed by R

C

and C (f

) at the f

. Calculate the value of C

If f

is less than 5 × f , add a second capacitor C

C

zEA

pMOD

zMOD C F

as follows:

from COMP to SGND. Set f

= f

and calculate

pEA

1

zMOD

C as follows:

F

1

C

=

C

2π × f

× R

C

pMOD

C =

F

2π × R × f

C

zMOD

If f

F

is less than 5 x f , add a second capacitor,

C

zMOD

MOSFET Selection

C , from COMP to SGND and set the compensation

The MAX16952’s controller drives two external logic-

level n-channel MOSFETs as the circuit switch ele-

ments. The key selection parameters to choose these

MOSFETs include:

pole formed by R and C (f

Calculate the value of C as follows:

) at the f

.

zMOD

C

F

pEA

F

1

C =

F

•

On-resistance (R

)

DS(ON)

2π × f

× R

C

zMOD

Maximum drain-to-source voltage (V

)

DS(MAX)

Minimum threshold voltage (V

)

TH(MIN)

As the load current decreases, the modulator pole also

decreases; however, the modulator gain increases

accordingly and the crossover frequency remains the

same.

Total gate charge (Q )

G

Reverse-transfer capacitance (C

Power dissipation

)

RSS

For the case where f

is less than f :

C

zMOD

The power-modulator gain at f is:

C

V

OUT

f

pMOD

GAIN

= GAIN

×

MOD fC

MOD dc

(

)

(

)

f

R1

R2

zMOD

The error-amplifier gain at f is:

C

COMP

g

m

f

zMOD

V

REF

GAIN

= g

× R ×

m,EA C

EA fC

(

)

f

C

R

C

Therefore:

GAIN

C

F

V

f

zMOD

FB

×

× g

× R ×

= 1

m,EA

C

MOD fC

(

)

V

f

OUT

C

Figure 5. Compensation Network

21

Maxim Integrated

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

Both n-channel MOSFETs must be logic-level types

with guaranteed on-resistance specifications at V

detected, the LSFET is forced on for one-half clock

cycle minimum. This is to ensure that the charge on the

boost capacitor is replenished fully.

=

GS

4.5V. Ensure that the conduction losses at minimum

input voltage do not exceed MOSFET package thermal

limits or violate the overall thermal budget. Also, ensure

that the conduction losses, plus switching losses at the

maximum input voltage, do not exceed package ratings

or violate the overall thermal budget. The MAX16952’s

DL gate driver must drive the low-side MOSFET (NL). In

particular, check that the dV/dt caused by the high-side

MOSFET (NH) turning on does not pull up the NL gate

through its drain-to-gate capacitance. This is the most

frequent cause of cross-conduction problems.

The worst case operation is when the MAX16952 is

close to dropout, but not fully in dropout with no load on

the output. This means consecutive minimum off-time

pulses are < 8. In this scenario, ensure that the amount

of charge lost per cycle is replenished in 100ns.

In some applications external boost resistor is added to

slow down the turn-on time for the HSFET. This causes

an extra voltage drop on the BST capacitor per cycle

and can require a parallel boostrap diode.

Let us assume:

Gate-charge losses are dissipated by the driver and do

not heat the MOSFET. Therefore, if the drive current is

taken from the internal LDO regulator, the power dissi-

pation due to drive losses must be checked. Both

MOSFETs must be selected so that their total gate

charge is low enough; therefore, BIAS can power both

drivers without overheating the IC:

Q

= total gate charge for HSFET

G

= BST charge lost per cycle

BST

V = BIAS voltage = 5V (typ)

L

V

BST

= BST voltage (BST - LX)

R

= external boost resistor used (connected

BST_EXT

P

= (V

- V

) × Q

× f

SW

between BST capacitor and BST pin)

R = internal boost switch resistance = 5Ω (typ)

BST

DRIVE

SUP

BIAS

G_TOTAL

where Q

is the sum of the gate charges of both

G_TOTAL

MOSFETs.

With the above set of parameters ensure that:

Q

> Q for every 100ns minimum off-time

G

Boost-Flying Capacitor Selection

BST

The bootstrap capacitor stores the gate voltage for the

internal switch. Its size is constrained by the switching

frequency and the gate charge of the high-side

MOSFET. Ideally the bootstrap capacitance should be

at least nine times the gate capacitance:

= (V - V

)/(R

+ R

) x 100ns

L

BST

BST_EXT

BST

The threshold voltage (V ) of the external HSFET used

determines the V - V

HSFET threshold voltage, V - V

TH

number. If 3V is the external

L

BST

= 2V.

BST

L

Now, if Q

bootstrap Schottky diode is required.

> Q is not satisfied, an external parallel

G

BST

Q

G

C

= 9×

BST(TYP)

V

BIAS

Applications Information

PCB Layout Guidelines

Make the controller ground connections as follows: cre-

ate a small analog ground plane near the IC by using

any of the PCB layers. Connect this plane to SGND and

use this plane for the ground connection for the SUP

bypass capacitor, compensation components, feed-

back dividers, and FOSC resistor.

This results in a 10% voltage drop when the gate is

driven. However, if this value becomes too large to be

recharged during the minimum off-time, a smaller

capacitor must be chosen.

During recharge, the internal bootstrap switch acts as a

resistor, resulting in an RC circuit with the associated

time constants. Two τs (time constants) are necessary

to charge from 90% to 99%. The maximum allowable

capacitance is, therefore:

If possible, place all power components on the top side

of the board and run the power stage currents, espe-

cially large high-frequency components, using traces or

copper fills on the top side only, without adding vias.

t

OFF(MIN)

C

=

BST(MAX)

On the top side, lay out a large PGND copper area for

the output, and connect the bottom terminals of the

high-frequency input capacitors, output capacitors, and

the source terminals of the low-side MOSFET to that

area.

2× R

BST(MAX)

The minimum off-time allowed for the MAX16952 is

100ns (typ). If eight consecutive 100ns pulses are

Maxim Integrated

22

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

V

BAT

5.5V TO 36V

C2

47µF

50V

C11

C1

0.1µF

4.7µF

50V

R1

51.1kΩ

1

1%

15

16

N1

FDS8449

SUP

DH

2

V

EN

BST

L1

1.5µH

R2

10kΩ

C4

0.1µF

10

14

12

V

L_IN

PGOOD

LX

DL

MAX16952

D2

N2

FDS8449

D1

6

4

COMP

FSYNC

B360B

R5

7.5kΩ

11

8

C8

OPEN

PGND

CS

C9

3300pF

R8

13kΩ

1%

R3

3

5

0.015Ω

FOSC

SGND

1%

9

V

OUT

5V

C6

C5

BIAS

13

FB

47µF

7

6.3V

C7

2.2µF

CONNECT FSYNC TO BIAS FOR FIXED-FREQUENCY PWM MODE.

CONNECT FSYNC TO SGND FOR SKIP MODE.

THE MAX16952 CAN WORK DOWN TO 3.5V.

Figure 6. Typical Operating Circuit for V

= 5V

OUT

Then, make a star connection of the SGND plane to the

top copper PGND area with few vias in the vicinity of

the source terminal sensing. Do not connect PGND and

SGND anywhere else. Refer to the MAX16952 evalua-

tion kit data sheet for guidance.

Route high-speed switching nodes (BST, LX, DH, and

DL) away from the sensitive analog areas (FOSC,

COMP, and FB). Group all SGND-referred and feed-

back components close to the IC. Keep the FB and

compensation network nets as small as possible to pre-

vent noise pickup.

Keep the power traces and load connections short,

especially at the ground terminals. This practice is

essential for high efficiency and jitter-free operation. Use

thick copper PCBs (2oz vs. 1oz) to enhance efficiency.

Chip Information

PROCESS: BiCMOS

Place the controller IC adjacent to the synchronous

rectifier MOSFET (NL) and keep the connections for LX,

PGND, DH, and DL short and wide. Use multiple small

vias to route these signals from the top to the bottom

side. The gate current traces must be short and wide,

measuring 50 mils to 100 mils wide if the low-side

MOSFET is 1in from the controller IC. Connect the

PGND trace from the IC close to the source terminal of

the low-side MOSFET.

Package Information

For the latest package outline information and land patterns (foot-

prints), go to www.maximintegrated.com/packages. Note that a

“+”, “#”, or “-” in the package code indicates RoHS status only.

Package drawings may show a different suffix character, but the

drawing pertains to the package regardless of RoHS status.

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

16 TSSOP-EP

U16E+3

21-0108

90-0120

23

Maxim Integrated

MAX16952

36V, 2.2MHz Step-Down Controller

with Low Operating Current

Revision History

REVISION REVISION

DESCRIPTION

PAGES

CHANGED

NUMBER

DATE

3/11

0

1

Initial release

Changed V

—

10/12

limit to 10V

1, 2, 12, 16

OUT

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent

licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and

max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

24 ________________________________Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.


型号：	MAX16952
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	36V, 2.2MHz Step-Down Controller with Low Operating Current 36V ， 2.2MHz的降压型控制器，具有低工作电流控制器
文件：	总24页 (文件大小：1934K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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