MAX1609EEE-T [MAXIM]
Parallel I/O Port, 8 I/O, CMOS, PDSO16, 0.150 INCH, 0.025 INCH PITCH, MO-137D, QSOP-16;
| 型号： | MAX1609EEE-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Parallel I/O Port, 8 I/O, CMOS, PDSO16, 0.150 INCH, 0.025 INCH PITCH, MO-137D, QSOP-16 光电二极管 外围集成电路 |
| 文件： | 总16页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1639; Rev 0; 1/00
Octal SMBus-to-Parallel I/O Expanders
General Description
Features
The MAX1608/MAX1609 provide remote input/output (I/O)
expansion through an SMBus™ 2-wire serial interface.
Each device has eight high-voltage open-drain outputs
that double as TTL-level logic inputs, providing continuous
bidirectional capabilities. The open-drain outputs tailor the
MAX1608/MAX1609 for use in load-switching and other
level-shifting applications as well as general-purpose I/O
applications.
ꢀ Serial-to-Parallel or Parallel-to-Serial Conversions
ꢀ 8 General-Purpose Digital I/O Pins
(withstand +28V)
ꢀ SMBus 2-Wire Serial Interface
ꢀ Supports SMBSUS Asynchronous Suspend
ꢀ 9 Pin-Selectable Slave Addresses
ꢀ Outputs High Impedance on Power-Up (MAX1609)
ꢀ Outputs Low on Power-Up (MAX1608)
ꢀ 2.5µA Supply Current
Two complete sets of registers allow the device and its
outputs to be toggled between two states using the
SMBSUS input, without the inherent latency of reprogram-
ming outputs over the serial bus. The eight I/O lines are
continuously monitored and can be used as inputs. Each
line can generate asynchronous maskable interrupts on
the falling edge, the rising edge, or both edges.
ꢀ +2.7V to +5.5V Supply Range
ꢀ 16-Pin QSOP Package
For load-switching applications, the MAX1608 is designed
to drive N-channel MOSFETs, and its outputs are low
upon power-up; the MAX1609 is designed to drive P-
channel MOSFETs, and its I/Os are high impedance upon
power-up. Other features of both devices include thermal-
overload and output-overcurrent protection, ultra-low sup-
ply current, and a wide +2.7V to +5.5V supply range. The
MAX1608/MAX1609 are available in space-saving 16-pin
QSOP packages.
Ordering Information
PART
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
MAX1608EEE
MAX1609EEE
16 QSOP
16 QSOP
Applications
Parallel I/O Expansion
Power-Plane Switching
Notebook and Desktop Computers
Servers and Workstations
Typical Operating Circuits
Notebook Docking Stations
Industrial Equipment
+2.7V TO +5.5V
Pin Configuration
100k
100k
100k
V+
TOP VIEW
0.1µF
MAX1609
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
1
2
3
4
5
6
7
8
16 V+
P-CH
ALERT
IO1
15 SMBSUS
14 SMBCLK
13 ALERT
12 SMBDATA
11 ADD1
SMBUS
TO/
FROM
HOST
SMBDATA
SMBCLK
SMBSUS
IO2
IO3
MAX1608
MAX1609
ADD1
ADD
LOAD1
LOAD2
LOAD3
IO7
GND
10 ADD0
9
GND
Typical Operating Circuits continued at end of data sheet.
QSOP
SMBus is a trademark of Intel Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
Octal SMBus-to-Parallel I/O Expanders
ABSOLUTE MAXIMUM RATINGS
V+ to GND................................................................-0.3V to +6V
IO_ to GND.............................................................-0.3V to +30V
IO_ Sink Current..................................................-1mA to +50mA
SMBCLK, SMBDATA, SMBSUS
SMBDATA and ALERT Sink Current ...................-1mA to +50mA
Continuous Power Dissipation (T = +70°C)
A
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
and ALERT to GND .............................................-0.3V to +6V
ADD_ to GND ...............................................-0.3V to (V+ + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = +2.7V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage Range
2.7
5.5
V
Static, outputs in any combination of on or off
states up to 28V
7
18
9
Supply Current (Note 2)
Static, all IOs low or pulled to 0
3.5
7
µA
SMBus interface operating,
clock frequency = 100kHz
POR Threshold Voltage
I/O Sink Current
Falling edge of V+
IO_ forced to 0.4V
IO_ forced to 1.0V, V+ = 4.5V
IO_, V+ = 4.5V
1.2
2
1.8
2.5
V
mA
8
13
25
I/O Current Limit
15
50
2
mA
µA
I/O Leakage Current
IO_ forced to 28V
SMBCLK to IO_
0.5
2.5
1
Propagation Delay
µs
SMBSUS to IO_
10
IO_ to ALERT
IO_ Data Set-Up Time
10% or 90% of I/O to 10% of SMBCLK (Note 3)
10
µs
IO_ Data Hold Time
(Note 3)
3
0
µs
V
SMBus Logic Input Voltage Range
Logic Input High Voltage
5.5
0.8
SMBSUS, SMBCLK, SMBDATA (Note 2)
IO_, SMBSUS, SMBCLK, SMBDATA
IO_, SMBSUS, SMBCLK, SMBDATA
SMBDATA forced to 0.6V
ALERT forced to 0.4V
2.1
V
Logic Input Low Voltage
V
SMBus Output Low Sink Current
ALERT Output Low Sink Current
ALERT Output High Leakage Current
Thermal Shutdown
6
1
mA
mA
µA
°C
1
1
ALERT forced to 5.5V
10°C typical hysteresis
140
20
ADD_ during address sampling (POR, SPOR,
and RAP) to V+ and GND (Note 4)
Sample Address Input Impedance
kΩ
Logic Input Current
-1
µA
pF
SMBDATA, SMBCLK, SMBUS, ADD_
SMBus Input Capacitance
SMBCLK, SMBDATA
5
2
_______________________________________________________________________________________
Octal SMBus-to-Parallel I/O Expanders
TIMING CHARACTERISTICS
(V+ = +2.7V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
DC
4.7
4
TYP
MAX
UNITS
kHz
µs
SMBus Clock Frequency
SMBCLK Clock Low Time
SMBCLK Clock High Time
SMBus Rise Time
(Note 5)
100
t
10% to 10% points
LOW
t
90% to 90% points
µs
HIGH
SMBCLK, SMBDATA; 10% to 90% points
SMBCLK, SMBDATA; 90% to 10% points
1
µs
SMBus Fall Time
300
ns
SMBus Start-Condition
Setup Time
4.7
500
4
µs
ns
µs
µs
SMBus Repeated Start-
Condition Setup Time
t
90% to 90% points
SU:STA
HD:STA
SU:STO
SMBus Start-Condition Hold
Time
t
t
t
10% of SMBDATA to 90% of SMBCLK
90% of SMBCLK to 10% of SMBDATA
SMBus Stop-Condition Setup
Time
4
SMBus Data Valid to SMBCLK
Rising Edge Time
10% or 90% of SMBDATA to 10% of SMBCLK
250
300
ns
ns
µs
SU:DAT
HD:DAT
SMBus Data Hold Time
t
SMBCLK Falling Edge to
SMBDATA Valid Time
Master clocking in data
3
Note 1: Specifications from 0°C to -40°C are guaranteed by design, not production tested.
Note 2: For supply current, SMBus logic inputs driven to 0 or V+.
Note 3: Data hold and set-up times measured from falling edge of 9th clock.
Note 4: Must be driven to GND, V+, or floating. See SMBus Addressing section.
Note 5: The SMBus logic block is a static design and will work with clock frequencies down to DC. While slow operation is possible,
it violates the 10kHz minimum clock frequency and SMBus specifications and may use excessive space on the bus.
Typical Operating Characteristics
(V+ = +5V, T = +25°C, unless otherwise noted.)
A
IO_ SINK CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
16
14
12
10
8
15.0
12.5
10.0
7.5
5.0
2.5
0
15.0
12.5
10.0
7.5
5.0
2.5
0
V
= 1.0V
IO_
IOs = 1111 1111 PULLED UP TO +28V
IOs = 0000 0000
IOs = 1111 1111 PULLED UP TO +28V
IOs = 0000 0000
V
= 0.4V
IO_
6
4
2
0
0
1
2
3
4
5
6
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40 -20
0
20
40
60
80 100
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
_______________________________________________________________________________________
3
Octal SMBus-to-Parallel I/O Expanders
Typical Operating Characteristics (continued)
(V+ = +5V, T = +25°C, unless otherwise noted.)
A
IO_ CURRENT LIMIT vs. SUPPLY VOLTAGE
IO_ CURRENT LIMIT vs. TEMPERATURE
IO_ CURRENT LIMIT vs. IO_ VOLTAGE
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
30
25
20
15
10
5
IO_ = 0 PULLED UP TO +28V
V
= 15V
IO_
V+ = 4.5V
IO_ = 0
IO_ = 0
0
0
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40 -20
0
20
40
60
80 100
0
5
10
15
(V)
20
25
30
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
V
IO_
SUSPEND-STATE DELAY
(IO_ RISING)
IO_ BIAS CURRENT vs. IO_ VOLTAGE
IO_ BIAS CURRENT vs. TEMPERATURE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.8
0.6
0.4
0.2
0
PULL-UP = 10kΩ to 28V
V+ = 5V
IO_ = 1 PULLED UP TO 28V
IO_
10V/div
SMBSUS
5V/div
IO_ = 1
0
5
10
15
(V)
20
25
30
-40 -20
0
20
40
60
80 100
100ns/div
V
IO_
TEMPERATURE (°C)
SUSPEND-STATE DELAY
(IO_ FALLING)
ALERT DELAY
(IO_ RISING)
PULL-UP = 10kΩ to 28V
IO_
10V/div
IO_
2V/div
SMBSUS
5V/div
ALERT
5V/div
IO_ DRIVEN EXTERNALLY
40ns/div
100ns/div
4
_______________________________________________________________________________________
Octal SMBus-to-Parallel I/O Expanders
Typical Operating Characteristics (continued)
(V+ = +5V, T = +25°C, unless otherwise noted.)
A
MAX1608
IO_ POWER-UP RESPONSE
ALERT DELAY
(IO_ FALLING)
PULL-UP = 10kΩ to V+
V
IO_
2V/div
IO_
500mV/div
V+
2V/div
ALERT
5V/div
IO_ DRIVEN EXTERNALLY
200ns/div
Pin Description
PIN
1–8
9
NAME
FUNCTION
IO0– IO7
GND
Combined Input/Output. Open-drain output. Can withstand +28V.
Ground
10, 11
12
ADD0, ADD1
SMBDATA
ALERT
SMBus Address Select. See Table 1.
SMBus Serial-Data Input/Output. Open-drain output. Requires external pull-up resistor.
Active-Low Interrupt Output. Open-drain output. Requires external pull-up resistor.
SMBus Serial Clock Input
13
14
SMBCLK
SMBus Suspend-Mode Control Input. The device will enter the state previously stored in
the suspend-mode registers if low, or enter the state previously stored in the normal-mode
registers if high.
15
16
SMBSUS
V+
Supply Voltage Input, +2.7V to +5.5V. Bypass to GND with a 0.1µF capacitor.
set the output states and two interrupt mask registers.
Detailed Description
The SMBSUS line selects which set of registers control
the device state. The input register is used to perform
readback of the actual IO states.
The MAX1608/MAX1609 convert 2-wire SMBus serial
data into eight latched parallel outputs (IO0–IO7). These
devices are intended for general-purpose remote I/O
expansion. Each device has eight high-voltage open-
drain outputs that double as TTL-level logic inputs.
Typical applications range from high-side MOSFET load-
switch drivers in power-management systems, to push-
button switch monitors, to general-purpose digital I/Os.
The MAX1608/MAX1609 operate from a single +2.7V
to +5.5V supply with a typical quiescent current of
2.5µA, making them ideal for portable applications.
Additionally, the devices include an ALERT function to
alert the master of change of condition (Figure 1).
The MAX1608/MAX1609 include two complete sets of
registers, each consisting of one output data register to
_______________________________________________________________________________________
5
Octal SMBus-to-Parallel I/O Expanders
SMBCLK
COMMAND
DECODER
8
SMB
SMBDATA
IO1
IO2
8
INPUT
REGISTER
8
NORMAL RISING
INTERRUPT
MASK REGISTER
8
IO7
8
ADD0
ADD1
TRANSITION
DETECTORS
SUSPEND RISING
INTERRUPT
ADDRESS
DECODER
1
1
MASK REGISTER
7
NORMAL FALLING
INTERRUPT
MASK REGISTER
ALERT
RESPONSE
REGISTER
SUSPEND FALLING
INTERRUPT
MASK REGISTER
ALERT
R
NORMAL
OUTPUT
REGISTER
S
FAULT
LATCH
8
8
THERMAL
SHUTDOWN
1
SUSPEND
OUTPUT
REGISTER
SMBSUS
Figure 1. Functional Diagram
6
_______________________________________________________________________________________
Octal SMBus-to-Parallel I/O Expanders
SMBus Interface Operation
The SMBus serial interface is a 2-wire interface with
Table 1. Slave Addresses
multi-mastering capability. The MAX1608/MAX1609 are
2-wire slave-only devices and employ standard SMBus
write-byte, send-byte, read-byte, and receive-byte
protocols (Figure 2) as documented in “System
Management Bus Specification v1.08” (available at
www.sbs-forum.org). SMBDATA and SMBCLK are
Schmitt-triggered inputs that can accommodate slower
edges; however, the rising and falling edges should still
be faster than 1µs and 300ns, respectively.
ADDRESS (A6–A0)
MAX1608
ADD0
ADD1
MAX1609
0100 100
0100 101
0100 110
1101 100
1101 101
1101 110
0110 000
0110 001
0110 010
GND
GND
GND
High-Z
High-Z
High-Z
V+
GND
High-Z
V+
0010 100
0010 101
0010 110
1100 100
1100 101
1100 110
0111 000
0111 001
0111 010
GND
High-Z
V+
Communication starts with the master signaling the
beginning of a transmission with a START condition,
which is a high-to-low transition on SMBDATA while
SMBCLK is high. When the master has finished com-
municating with the slave, it issues a STOP condition,
which is a low-to-high transition on SMBDATA while
SMBCLK is high (Figures 3 and 4). The bus is then free
for another transmission from any master on the bus.
GND
High-Z
V+
V+
V+
The address byte, command byte, and data byte are
transmitted between the START and STOP conditions.
Figures 3 and 4 show the timing diagrams for signals
on the 2-wire interface. The SMBDATA state is allowed
to change only while SMBCLK is low, except for the
START and STOP conditions. Data is transmitted in 8-
bit words and is sampled on the rising edge of SMB-
CLK. Nine clock cycles are required to transfer each
byte in or out of the MAX1608/MAX1609 (Figure 2),
since either the master or the slave acknowledges
receipt of the correct byte during the ninth clock. The
IC responds to the address selected by the ADD0 and
ADD1 pins (Table 1).
MAX1608/MAX1609 recognizes its own address, it
sends an acknowledgment pulse by pulling SMBDATA
low.
Each slave responds to only two addresses: its own
unique address (set by ADD1 and ADD0, Table 1), and
the alert response address (0x19). The device’s unique
address is determined at power-up, with a software
sample-address-pin command (SAP), or a software
power-on-reset command (SPOR). The MAX1608/
MAX1609 address pins (ADD1–ADD0) are high imped-
ance except when ADD1–ADD0 are sampled, which
occurs during power-up and when requested (SPOR,
RAP). During sampling, the equivalent input circuit can
be described as a resistor-divider from V+ to GND
(20kΩ each), which momentarily bias the pins to mid-
supply if they are left floating. To set the ADD_ pins
high or low, connect or drive the pins to the rails (V+ or
GND) to guarantee a correct level detection. During
sampling, the pins draw a momentary input bias cur-
rent (V+ / 20kΩ). Also, stray capacitance in excess of
50pF on the ADD_ pins when floating may cause
address recognition problems.
If the MAX1608/MAX1609 receive the correct slave
address followed by RW = 0, the selected device
expects to receive one or two bytes of information. If
the device detects a START or STOP condition prior to
clocking in a full additional byte of data, it considers
this an error condition and disregards all of the data. If
no error occurs, the registers are updated immediately
after the falling edge of the acknowledge clock pulse
(Figure 5). If the MAX1608/MAX1609 receive the cor-
rect slave address followed by RW = 1, the selected
device expects to clock out the contents of the previ-
ously accessed register during the next byte transfer.
SMBus Commands
The 8-bit command byte (Table 2) is the master index
that points to the registers within the MAX1608/MAX1609.
The devices include ten registers: the data registers
(NDR1–NDR3, SDR1–SDR3) are accessed through
both the read-byte and write-byte protocols (Figure 2),
the RSB and MDIF registers are accessed with the
read-byte protocols, and the RAP and SPOR registers
A third interface line (SMBSUS) is used to execute com-
mands asynchronously from previously stored registers
(see SMBSUS (Suspend-Mode) Input section).
SMBus Addressing
After the START condition, the master transmits a 7-bit
address followed by the RW bit (Figure 2). If the
_______________________________________________________________________________________
7
Octal SMBus-to-Parallel I/O Expanders
use the send-byte protocol. The shorter receive-byte
protocol can be used instead of the read-byte protocol,
provided the correct data register was previously
selected by a read-byte or write-byte instruction. Use
caution with the shorter protocols in multimaster sys-
tems, since a second master could overwrite the com-
mand byte without informing the first master. The
register selected at POR is 0b0000 0000 so that a
receive-byte transmission that occurs immediately after
initial power-up returns the setting of NDR1. SPOR
does not reset the register pointer.
When using an external pull-up, high impedance corre-
sponds to an output high. To use the IO_ pins as TTL
inputs only, set the corresponding bit high. The
MAX1608 powers up with all IO_ pins set low; the
MAX1609 powers up with all IO_ pins set to high
impedance (Table 3).
Register 2 (NDR2 and SDR2) are used to mask rising-
edge triggered interrupts, while Register 3 are used to
mask falling-edge triggered interrupts. On power-up, all
interrupts are masked (Tables 4 and 5).
The IO_ Status Data Register (RSB, Table 6) reads the
actual TTL-logic level of the IO_ pins. The IO_ pins are
sampled on the falling edge of the third byte’s acknowl-
edge (ACK) for a read-byte format, or on the falling
edge of the first byte’s ACK for a receive-byte protocol
(Figure 5). There is a 15µs data-setup time require-
ment, due to the slow level translators needed for high-
voltage (28V) operation. Data-hold time is 300ns. Do
not write to the RSB register because writes to read-
only registers are redirected to NDR1. SMBus sends
Data Registers
The MAX1608/MAX1609 each have seven data regis-
ters, three normal registers, three suspend registers,
and one readback register. The SMBUS line deter-
mines which registers controls the output states and
the interrupt mask states (normal registers if SUSBUS =
1, suspend registers if SMBSUS = 0).
Registers 1 (NDR1 and SDR1) set the state of each of
the eight outputs to either low or high impedance.
Write-Byte Format
S
ADDRESS
WR
ACK
COMMAND
ACK
DATA
ACK
P
7 bits
1b
1b
8 bits
1b
8 bits
1b
Slave Address
Command Byte: selects
which register you are
writing to
Data Byte: data goes into the register
set by the command byte
Read-Byte Format
ADDRESS WR ACK
S
COMMAND
ACK
S
ADDRESS
7 bits
RD ACK
1b 1b
DATA
///
P
7 bits
1b
1b
8 bits
1b
8 bits
1b
Slave Address
Command Byte: selects
which register you are
reading from
Slave Address: repeated
due to change in data-
flow direction
Data Byte: reads from
the register set by the
command byte
Send-Byte Format
ADDRESS WR ACK COMMAND ACK
7 bits 1b 1b 8 bits 1b
Receive-Byte Format
S
P
S
ADDRESS
RD ACK
DATA
///
P
7 bits
1b
1b
8 bits
1b
Data Byte: reads data from
the register commanded
by the last read-byte or
write-byte transmission;
also used for SMBus Alert
Response return address
Command Byte: sends command
with no data; usually used for one-
shot command
Slave Address
S = Start condition
P = Stop condition
Shaded = Slave transmission
Ack= Acknowledged = 0
/// = Not acknowledged = 1
WR = Write = 0
RD = Read =1
Figure 2. SMBus Protocols
_______________________________________________________________________________________
8
Octal SMBus-to-Parallel I/O Expanders
A
B
C
D
E
F
G
H
I
J
K
L
M
t
t
HIGH
LOW
SMBCLK
SMBDATA
t
t
t
t
t
HD:DAT
HD:STA
SU:STA
SU:DAT
HD:DAT
t
t
SU:STO
BUF
A = START CONDITION
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMBDATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
Figure 3. SMBus Write Timing
A
B
C
D
E
F
G
H
I
J
K
t
t
HIGH
LOW
SMBCLK
SMBDATA
t
t
t
t
t
t
t
BUF
SU:STA HD:STA
SU:DAT
HD:DAT
SU:DAT
SU:STO
A = START CONDITION
E = SLAVE PULLS SMBDATA LINE LOW
I = ACKNOWLEDGE CLOCK PULSE
J = STOP CONDITION
K = NEW START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
Figure 4. SMBus Read Timing
data MSB first; therefore, IO7, MASK7, and data 7 bit
correspond to the MSB (first bit of the data byte).
MFID uses the read-byte protocol to access the ID reg-
ister. Do not use write-byte protocol to MFID because
data is redirected to NDR1.
Other Registers
RAP uses the send-byte protocol to resample the
address pins. Do not use read- and write-byte proto-
cols to RAP because data is redirected to NDR1
although the ADD_ pins will be sampled.
SMBSUS (Suspend-Mode) Input
The state of the SMBSUS input selects which register
contents (NDR1 or SDR1) are applied to the IO_ pins
and which set of registers are used to mask the inter-
rupts (NDR2, NDR3 or NDR2, SDR3). Driving SMBSUS
low selects the suspend-mode registers, while driving
SMBSUS high selects the normal registers. This feature
allows the system to select between two different I/O
SPOR uses the send-byte protocol to resample the
address pins and reset the registers to the POR state.
Do not use read- and write-byte protocols to SPOR
because data is redirected to NDR1 although the func-
tion will be performed.
_______________________________________________________________________________________
9
Octal SMBus-to-Parallel I/O Expanders
configurations asynchronously, eliminating latencies
introduced by the serial bus.
LAST BIT
CLOCKED
ACKNOWLEDGE
BIT CLOCKED
INTO MASTER
ALERT
INTO SLAVE**
The MAX1608/MAX1609 can generate hardware inter-
rupts whenever the logic states of the IO_ pins change
or when thermal shutdown occurs. Interrupts are sig-
naled on the ALERT pin. The IO_ interrupts can be
masked individually through the mask registers.
Registers NDR2 and SDR2 mask the IO_ rising-edge
interrupts, while NDR3 and SDR3 mask the IO_ falling-
edge interrupts. The power-on-reset state masks all
interrupts (Tables 4 and 5).
SCL
SDA
SLAVE PULLING
SDA LOW
t
t
DH:DAT
DH:DAT
STOP
The thermal-shutdown protection also generates an
interrupt. This interrupt cannot be masked (see Thermal
Shutdown section). An interrupt can be cleared with a
SPOR or an Alert Response. However, after an interrupt
has occurred, masking will not clear it.
REGISTERS
UPDATED*
IO_TRANSITION
Alert Response Address (0b00011001)
The alert response (interrupt pointer) address provides
quick fault identification for simple slave devices that
cannot initiate communication as a bus master. When a
slave device generates an interrupt, the host (bus mas-
ter) interrogates the bus slave devices through a special
receive-byte operation that includes the alert response
address (0x19). The offending slave device returns its
own address during this receive-byte operation.
IO_
t
SCL:IO
*NDR#, SDR# ARE LOADED. RAP, SPOR ARE INITIATED. RSB IS SAMPLED.
**DURING A RECEIVE-BYTE PROTOCOL, CORRESPONDS TO THE R/W BIT. DURING A
READ/WRITE-BYTE PROTOCOL, CORRESPONDS TO LAST BIT OF DATA.
The interrupt pointer address can activate several dif-
ferent slave devices simultaneously. If more than one
Figure 5. Registers/IO_ Update Timing Diagram
Table 2. Command-Byte/Register Assignment
POR STATE
REGISTER
COMMAND
FUNCTION
MAX1608
0000 0000
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
—
MAX1609
NDR1
NDR2
NDR3
SDR1
SDR2
SDR3
RSB
00h
01h
02h
03h
04h
05h
06h
07h
08h
FEh
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
—
Normal Data Register 1. Sets the IO_ states.
Normal Data Register 2. Masks the L/H interrupt.
Normal Data Register 3. Masks the H/L interrupt.
Suspend Data Register 1. Sets the IO_ states.
Suspend Data Register 2. Masks the L/H interrupt.
Suspend Data Register 3. Masks the H/L interrupt.
IO_ Status Data Register. Read pin state.
RAP
—
—
Sample the address pins.
SPOR
MFID
—
—
Execute software POR and samples address pins.
Read manufacturer ID (ASCII code for "M"axim).
4Dh
4Dh
10 ______________________________________________________________________________________
Octal SMBus-to-Parallel I/O Expanders
Table 3. Data Register 1 (NDR1 and SDR1) Bit Assignments (read or write)
POR STATE
BIT
NAME
FUNCTION
MAX1608 MAX1609
7
6
5
4
3
2
1
0
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Sets IO7 state. 0 = on (low state), 1 = off (high-impedance).
Sets IO6 state. 0 = on (low state), 1 = off (high-impedance).
Sets IO5 state. 0 = on (low state), 1 = off (high-impedance).
Sets IO4 state. 0 = on (low state), 1 = off (high-impedance).
Sets IO3 state. 0 = on (low state), 1 = off (high-impedance).
Sets IO2 state. 0 = on (low state), 1 = off (high-impedance).
Sets IO1 state. 0 = on (low state), 1 = off (high-impedance).
Sets IO0 state. 0 = on (low state), 1 = off (high-impedance).
Table 4. Data Register 2 (NDR2 and SDR2) Bit Assignments (read or write)
BIT
7
NAME
POR STATE
FUNCTION
MASKH7
MASKH6
MASKH5
MASKH4
MASKH3
MASKH2
MASKH1
MASKH0
1
1
1
1
1
1
1
1
Masks IO7 low-to-high interrupt. 0 = interrupts, 1 = masked.
Masks IO6 low-to-high interrupt. 0 = interrupts, 1 = masked.
Masks IO5 low-to-high interrupt. 0 = interrupts, 1 = masked.
Masks IO4 low-to-high interrupt. 0 = interrupts, 1 = masked.
Masks IO3 low-to-high interrupt. 0 = interrupts, 1 = masked.
Masks IO2 low-to-high interrupt. 0 = interrupts, 1 = masked.
Masks IO1 low-to-high interrupt. 0 = interrupts, 1 = masked.
Masks IO0 low-to-high interrupt. 0 = interrupts, 1 = masked.
6
5
4
3
2
1
0
slave attempts to respond, bus arbitration rules apply,
with the lowest address code going first. The other
device(s) will not generate an acknowledge and will
continue to hold the ALERT pin low until it is allowed to
clear its own interrupt.
External pull-up resistors and IO_ sink capability can
affect the outputs’ rise and fall times. When using the
MAX1608/MAX1609 to control an external MOSFET in
power-switching applications, pull-up and/or series resis-
tance can be used together with the MOSFET’s gate
capacitance or additional external capacitance (Figure 6)
to control the transition time of the switched source.
Clearing the interrupt has no effect on the state of the
status registers.
The input logic levels are TTL compatible and are sam-
pled during a readback SMBus transmission (see RSB
register in Data Registers section ).
Input/Output Pins
Each IO_ pin is protected by an internal 20mA (typical)
current-limit circuit. Typical pull-down on-resistance at
V
= +2.7V and +5.5V is 100Ω and 66Ω, respectively.
Power-On Reset
The MAX1608/MAX1609’s power-on-reset circuit
ensures that the IO_ states are defined when V+ is first
applied or when the supply dips below the UVLO
CC
When the IO_ is high impedance, it actually has a
0.5µA pull-down current source included as part of the
read-back functionality.
______________________________________________________________________________________ 11
Octal SMBus-to-Parallel I/O Expanders
Table 5. IO_ Status Data Register (RSB) Bit Assignments (read only)
BIT
7
NAME
POR STATE
FUNCTION
MASKL7
MASKL6
MASKL5
MASKL4
MASKL3
MASKL2
MASKL1
MASKL0
1
1
1
1
1
1
1
1
Masks IO7 high-to-low interrupt. 0 = interrupts, 1 = masked.
Masks IO6 high-to-low interrupt. 0 = interrupts, 1 = masked.
Masks IO5 high-to-low interrupt. 0 = interrupts, 1 = masked.
Masks IO4 high-to-low interrupt. 0 = interrupts, 1 = masked.
Masks IO3 high-to-low interrupt. 0 = interrupts, 1 = masked.
Masks IO2 high-to-low interrupt. 0 = interrupts, 1 = masked.
Masks IO1 high-to-low interrupt. 0 = interrupts, 1 = masked.
Masks IO0 high-to-low interrupt. 0 = interrupts, 1 = masked.
6
5
4
3
2
1
0
Table 6. Data Register 3 (NDR3 and SDR3) Bit Assignments (read or write)
BIT
7
NAME
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
FUNCTION
Indicates the current state of IO7. 1 = high, 0 = low.
Indicates the current state of IO6. 1 = high, 0 = low.
Indicates the current state of IO5. 1 = high, 0 = low.
Indicates the current state of IO4. 1 = high, 0 = low.
Indicates the current state of IO3. 1 = high, 0 = low.
Indicates the current state of IO2. 1 = high, 0 = low.
Indicates the current state of IO1. 1 = high, 0 = low.
Indicates the current state of IO0. 1 = high, 0 = low.
6
5
4
3
2
1
0
threshold. The power-on states can also be reset with
the SPOR command through the SMBus.
Thermal Shutdown
These devices have internal thermal-shutdown circuitry
that sets all outputs to a high-impedance state (IO_
pins) when the junction temperature exceeds +140°C
typical. Thermal shutdown only occurs during an over-
load condition on the IO_ pins. The device cycles
between thermal shutdown and the overcurrent condi-
tion (with 10°C hysteresis) until the overload condition
is removed. The device asserts ALERT low while it is in
thermal shutdown, indicating this fault status. ALERT
will be reasserted immediately after it is cleared if the
device is still hot. ALERT can only be completely
cleared once the fault condition is removed and the
device has cooled. Alternatively, forcing the IO_ to high
impedance will allow the junction to cool down.
The MAX1608’s outputs reset to a low state, while the
MAX1609’s outputs reset to a high-impedance state.
Below V+ = 0.8V (typical), the POR states can’t be
enforced, and the I/O pins of both devices exhibit
increasingly weak pull-down current capability, eventu-
ally becoming high impedance.
The MAX1608 is designed for applications that control
N-channel MOSFETs, while the MAX1609 is designed
to control P-channel MOSFETs. The power-on state
keeps the external MOSFETs off at power-up. Both
devices are suited for applications that use the parallel
input for serial functionality, although IO_s serving as
inputs must first be programmed to high impedance
when using the MAX1608.
12 ______________________________________________________________________________________
Octal SMBus-to-Parallel I/O Expanders
+5V
10k
10k
10k
10k
10k
10k
0.01µF*
0.01µF*
0.01µF*
V+
0.1µF
MAX1609
200k
200k
200k
IO0
IRF7406
IRF7406
IRF7406
ALERT
IO1
IO2
SMBDATA
SMBCLK
TO/FROM
HOST
SMBSUS
ADD0
LOAD1
LOAD2
LOAD3
ADD1
IO7
GND
+12V
+5V
10k
10k
10k
10k
10k
10k
V+
0.1µF
IRF7413
IRF7413
IRF7413
MAX1608
200k
200k
200k
0.01µF*
0.01µF*
0.01µF*
ALERT
IO0
SMBDATA
SMBCLK
TO/FROM
HOST
IO1
IO2
SMBSUS
ADD0
LOAD1
LOAD2
LOAD3
*OPTIONAL
ADD1
IO7
GND
Figure 6. Load Switch with Controlled Turn-On
Battery Switch with
Back-to-Back MOSFETs
Many battery-operated applications use back-to-back
MOSFETs to prevent reverse currents from the load to
the supply (Figure 7). This protects the battery from
potential damage and isolates the load from the power
source.
Application Examples
P-Channel/N-Channel High-Side Load
Switch with Controlled Turn-On
In load-switching applications, when a controlled volt-
age ramp or inrush current limiting is required, add a
series resistor to slow the switch turn-on and turn-off
times. The external MOSFET gate has a typical capaci-
tance of 150pF to 2000pF, but an optional external
capacitance can be added to further slow the switching
time (Figure 6). If a slow turn-on time is required, simply
use an N-channel MOSFET with a high-value pull-up
resistor and no series resistor. Similarly, if a fast turn-on
and a slow turn-off are desired, use a P-channel MOS-
FET with a high-value pull-up resistor and no series
resistor.
LED Driver
A MAX1608/MAX1609 can be used as programmable
LED drivers (Figure 8). With their low quiescent current,
these devices are ideal for use as indicator light drivers
on the front panel of a notebook computer.
______________________________________________________________________________________ 13
Octal SMBus-to-Parallel I/O Expanders
+5V
+3.3V TO +28V
100k
10k
10k
10k
V+
0.1µF
IRF7406
IRF7406
P
P
MAX1609
75k*
1M
ALERT
IO0
IO7
SMBDATA
SMBCLK
TO/FROM
HOST
SMBSUS
ADD0
ADD1
GND
LOAD
NOTE: OTHER OUTPUTS CAN BE CONFIGURED SIMILARLY.
*75kΩ RESISTOR FOR VOLTAGES GREATER THAN +12V.
Figure 7. Battery Switch with Back-to-Back MOSFETs
+5V
1k
1k
1k
10k
10k
V+
0.1µF
MAX1608
MAX1609
ALERT
IO0
SMBDATA
SMBCLK
SMBSUS
IO1
IO2
TO/FROM
HOST
ADD0
ADD1
IO7
GND
Figure 8. LED Driver
Mechanical Switch Monitor
Simple High-Voltage Switch
The MAX1608/MAX1609’s ability to perform IO_ logic-
state readback makes them suitable for checking sys-
tem status. They can be used as an “open-lid indicator,”
sensing a change in the IO_ and sending an interrupt
to the master to indicate a change in status (Figure 9).
The same can be done to detect a chassis intrusion, a
reset switch, or a card insertion.
For applications requiring a higher voltage, use a sim-
ple resistive divider to protect the gate from breakdown
yet allow the MOSFETs to handle higher voltage appli-
cations (Figure 10).
___________________Chip Information
TRANSISTOR COUNT: 5762
14 ______________________________________________________________________________________
Octal SMBus-to-Parallel I/O Expanders
+5V
0.1µF
100k
100k
100k
10k
10k
10k
V+
MAX1608
MAX1609
ALERT
I/O0
SMBDATA
SMBCLK
SMBSUS
I/O1
I/O2
TO/FROM
HOST
ADD0
ADD1
IO7
GND
Figure 9. Mechanical Switch Monitor
+5V
V
= 10V TO 28V
IN
200k
10k
10k
10k
0.1µF
V
CC
0.01µF*
MAX1609
200k
IRF7406
ALERT
IO1
SMBCLK
IO2
IO3
IO4
TO/FROM
HOST
SMBDATA
SMBSUS
ADD0
ADD1
LOAD
IO7
GND
Figure 10. Simple High-Voltage Switch
______________________________________________________________________________________ 15
Octal SMBus-to-Parallel I/O Expanders
Typical Operating Circuits (continued)
+12V
+2.7V TO +5.5V
100k
100k
100k
V+
0.1µF
MAX1608
ALERT
I00
N-CH
SMBUS
TO/
FROM
HOST
SMBDATA
SMBCLK
SMBSUS
I01
I02
ADD0
LOAD1
LOAD2
LOAD3
ADD1
GND
I07
Package Information
Note: MAX1608/MAX1609 do not have a heat slug.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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