MAX1600EAI+ [MAXIM]
Power Supply Management Circuit, Fixed, 2 Channel, PDSO28, 0.200 INCH, SSOP-28;
| 型号： | MAX1600EAI+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Power Supply Management Circuit, Fixed, 2 Channel, PDSO28, 0.200 INCH, SSOP-28 开关 电源开关 PC |
| 文件： | 总16页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1388; Rev 0; 11/98
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l,
1 0 8 k s p s , S e ria l 1 0 -Bit ADCs in 8 -P in µMAX
7/MAX159
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX157/MAX159 low-power, 10-bit analog-to-digi-
tal converters (ADCs) are available in 8-pin µMAX and
DIP p a c ka g e s . Both d e vic e s op e ra te with a s ing le
+2.7V to +5.25V supply and feature a 7.4µs succes-
sive-approximation ADC, automatic power-down, fast
wake-up (2.5µs), an on-chip clock, and a high-speed,
3-wire serial interface.
♦ Single-Supply Operation (+2.7V to +5.25V)
♦ Two Single-Ended Channels (MAX157)
Single Pseudo-Differential Channel (MAX159)
♦ Low Power
0.9mA (at 108ksps, +3V)
100µA (at 10ksps, +3V)
10µA (at 1ksps, +3V)
<0.2µA (power-down mode)
Power consumption is only 3.2mW (V = +3.6V) at the
DD
maximum sampling rate of 108ksps. At slower through-
p ut ra te s , the 0.2µA a utoma tic s hutd own furthe r
reduces power consumption.
♦ Internal Track/Hold
The MAX157 provides 2-channel, single-ended opera-
♦ 108ksps Sampling Rate
tion and accepts input signals from 0 to V
. The
REF
♦ SPI/QSPI/MICROWIRE-Compatible 3-Wire
MAX159 accepts pseudo-differential inputs ranging
from 0 to V . An e xte rna l c loc k a c c e s s e s d a ta
Serial Interface
REF
throug h the 3-wire s e ria l inte rfa c e , whic h is SPI™,
QSPI™, and MICROWIRE™ compatible.
♦ Space-Saving 8-Pin µMAX Package
♦ Pin-Compatible 12-Bit Upgrades Available
Excellent dynamic performance and low power, com-
bined with ease of use and a small package size, make
these converters ideal for battery-powered and data
a c q uis ition a p p lic a tions , or for othe r c irc uits with
demanding power-consumption and space require-
ments. For pin-compatible 12-bit upgrades, see the
MAX144/MAX145 data sheet.
Ord e rin g In fo rm a t io n
TEMP.
RANGE
PIN-
PACKAGE
INL
(LSB)
PART
Ap p lic a t io n s
MAX157ACUA
MAX157BCUA
MAX157ACPA
MAX157BCPA
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
8 µMAX
±0.5
±1
Battery-Powered Systems
Portable Data Logging
Instrumentation
8 µMAX
Test Equipment
8 Plastic DIP
8 Plastic DIP
8 µMAX
±0.5
±1
Isolated Data Acquisition
Process-Control Monitoring
Medical Instruments
System Supervision
MAX157AEUA -40°C to +85°C
MAX157BEUA -40°C to +85°C
MAX157AEPA -40°C to +85°C
MAX157BEPA -40°C to +85°C
±0.5
±1
8 µMAX
8 Plastic DIP
8 Plastic DIP
±0.5
±1
P in Co n fig u ra t io n
MAX157AMJA -55°C to +125°C 8 CERDIP*
MAX157BMJA -55°C to +125°C 8 CERDIP*
±0.5
±1
TOP VIEW
MAX159ACUA
MAX159BCUA
MAX159ACPA
MAX159BCPA
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
8 µMAX
±0.5
±1
V
1
2
3
4
8
7
6
5
SCLK
DOUT
CS/SHDN
REF
DD
8 µMAX
8 Plastic DIP
8 Plastic DIP
8 µMAX
±0.5
±1
CH0 (CH+)
CH1 (CH-)
GND
MAX157
MAX159
MAX159AEUA -40°C to +85°C
MAX159BEUA -40°C to +85°C
MAX159AEPA -40°C to +85°C
MAX159BEPA -40°C to +85°C
±0.5
±1
8 µMAX
8 Plastic DIP
8 Plastic DIP
±0.5
±1
µMAX/DIP
MAX159AMJA -55°C to +125°C 8 CERDIP*
MAX159BMJA -55°C to +125°C 8 CERDIP*
±0.5
±1
( ) ARE FOR MAX159 ONLY.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
*Contact factory for availability.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l,
1 0 8 k s p s , S e ria l 1 0 -Bit ADCs in 8 -P in µMAX
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND..............................................................-0.3V to +6V
Operating Temperature Ranges
CH0, CH1 (CH+, CH-) to GND...................-0.3V to (V + 0.3V)
REF to GND................................................-0.3V to (V + 0.3V)
DD
Digital Inputs to GND ...............................................-0.3V to +6V
DOUT to GND.............................................-0.3V to (V + 0.3V)
DD
MAX157/MAX159_C_A .......................................0°C to +70°C
MAX157/MAX159_E_A ....................................-40°C to +85°C
MAX157/MAX159_MJA................................. -55°C to +125°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
DD
DOUT Sink Current ............................................................ 25mA
Continuous Power Dissipation (T = +70°C)
A
µMAX (derate 4.1mW/°C above +70°C) ......................330mW
Plastic DIP (derate 9.09mW/°C above +70°C) ............727mW
CERDIP (derate 8.00mW/°C above +70°C).................640mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
7/MAX159
ELECTRICAL CHARACTERISTICS
(V
DD
= +2.7V to +5.25V, V
= 2.5V, 0.1µF c a p a c itor a t REF, f
= 2.17MHz, 16 c loc ks /c onve rs ion c yc le (108ks p s ),
REF
SCLK
CH- = GND for MAX159, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX
A
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RES
INL
10
Bits
MAX15_A
MAX15_B
±0.5
±1
Relative Accuracy (Note 2)
LSB
Differential Nonlinearity
Offset Error
DNL
No missing codes over temperature
±0.5
±2
LSB
LSB
Gain Error (Note 3)
Gain Temperature Coefficient
±2
LSB
External reference, V
= 2.5V
±0.8
ppm/°C
REF
Channel-to-Channel Offset
Matching
±0.02
LSB
LSB
Channel-to-Channel Gain
Matching
±0.02
DYNAMIC SPECIFICATIONS (f (sine wave) = 10kHz, V = 2.5Vp-p, 108ksps, external f
= 2.17MHz, CH- = GND for MAX159)
IN
IN
SCLK
Signal-to-Noise Ratio plus
Distortion
SINAD
66
dB
dB
Total Harmonic Distortion
(including 5th-order harmonic)
THD
-70
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Small-Signal Bandwidth
SFDR
70
-75
2.25
1.0
dB
dB
f
= 65kHz, V = 2.5Vp-p (Note 4)
IN
IN
-3dB rolloff
MHz
MHz
Full-Power Bandwidth
2
_______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l,
1 0 8 k s p s , S e ria l 1 0 -Bit ADCs in 8 -P in µMAX
7/MAX159
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.7V to +5.25V, V
= 2.5V, 0.1µF c a p a c itor a t REF, f
= 2.17MHz, 16 c loc ks /c onve rs ion c yc le (108ks p s ),
DD
REF
SCLK
CH- = GND for MAX159, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE
External clock, f
cycles per conversion
= 2.17MHz, 16 clock
SCLK
7.4
5
Conversion Time (Note 5)
t
µs
CONV
Internal clock
7
T/H Acquisition Time
Aperture Delay
Aperture Jitter
t
2.5
µs
ns
ps
ACQ
25
<50
External clock mode
0.1
0
2.17
5
MHz
Serial Clock Frequency
f
SCLK
Internal clock mode, for data transfer only
ANALOG INPUTS
Analog Input Voltage Range
(Note 6)
V
IN
0
V
REF
V
Multiplexer Leakage Current
Input Capacitance
On/off-leakage current, V = 0 to V
±0.01
16
±1
µA
µA
IN
DD
C
IN
EXTERNAL REFERENCE
Input Voltage Range (Note 7)
Input Current
V
REF
0
V
+ 50mV
140
V
DD
V
REF
= 2.5V
100
25
µA
kΩ
µA
Input Resistance
18
Shutdown REF Input Current
0.01
10
DIGITAL INPUTS (CS/SHDN, SCLK) AND DIGITAL OUTPUT (DOUT)
V
≤ 3.6V
2.0
3.0
DD
Input High Voltage
V
IH
V
V
DD
> 3.6V
Input Low Voltage
Input Hysteresis
V
0.8
V
V
IL
V
HYS
0.2
0.5
Input Leakage Current
Input Capacitance
I
IN
V
= 0 or V
DD
±1
15
µA
pF
IN
C
(Note 8)
= 5mA
IN
I
0.4
SINK
Output Low Voltage
Output High Voltage
V
OL
V
V
I
= 16mA
SINK
V
OH
I
= 0.5mA
V
DD
- 0.5
SOURCE
Three-State Output Leakage
Current
±10
15
µA
pF
CS/SHDN = V
DD
Three-State Output Capacitance
C
OUT
CS/SHDN = V (Note 8)
DD
_______________________________________________________________________________________
3
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l,
1 0 8 k s p s , S e ria l 1 0 -Bit ADCs in 8 -P in µMAX
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.7V to +5.25V, V
= 2.5V, 0.1µF c a p a c itor a t REF, f
= 2.17MHz, 16 c loc ks /c onve rs ion c yc le (108ks p s ),
DD
REF
SCLK
CH- = GND for MAX159, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
POWER REQUIREMENTS
Positive Supply Voltage
Positive Supply Current
Positive Supply Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
+2.7
+5.25
2.0
5
V
I
DD
Operating mode
Shutdown, CS/SHDN = GND
0.9
0.2
mA
µA
I
DD
Power-Supply Rejection
(Note 9)
PSR
V
DD
= 2.7V to 5.25V, full-scale input
±0.15
mV
TIMING CHARACTERISTICS (Figure 7)
(V
= +2.7V to +5.25V, V
= 2.5V, 0.1µF c a p a c itor a t REF, f
= 2.17MHz, 16 c loc ks /c onve rs ion c yc le (108ks p s ),
DD
REF
SCLK
7/MAX159
CH- = GND for MAX159, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
µs
Wake-Up Time
t
2.5
WAKE
t
C
C
C
= 100pF (Figure 1)
120
120
ns
CS/SHDN Fall to Output Enable
DV
L
L
L
CS/SHDN Rise to Output
Disable
t
= 100pF (Figure 1)
ns
ns
TR
SCLK Fall to Output Data Valid
SCLK Clock Frequency
t
= 100pF
20
0.1
0
120
2.17
5
DO
External clock
f
MHz
SCLK
Internal clock, SCLK for data transfer only
External clock
215
SCLK Pulse Width High
SCLK Pulse Width Low
t
ns
ns
CH
Internal clock, SCLK for data transfer only
(Note 8)
50
215
50
External clock
t
CL
Internal clock, SCLK for data transfer only
(Note 8)
t
60
60
ns
ns
SCLK to CS/SHDN Setup
CS/SHDN Pulse Width
SCLKS
t
CS
Note 1: Tested at V = +2.7V.
DD
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Note 3: Offset nulled.
Note 4: The on channel is grounded; the sine wave is applied to off channel (MAX157 only).
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from GND to V (MAX159 only).
DD
Note 7: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 8: Guaranteed by design. Not subject to production testing.
Note 9: Measured as V (2.7V) - V (5.25V).
FS
FS
4
_______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l,
1 0 8 k s p s , S e ria l 1 0 -Bit ADCs in 8 -P in µMAX
7/MAX159
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
= 2.17MHz, 16 clocks/conversion cycle (108ksps); CH- = GND for
(V = +3.0V, V
= 2.5V, 0.1µF capacitor at REF, f
DD
REF
SCLK
MAX159; T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT
SUPPLY CURRENT
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1500
vs. TEMPERATURE
vs. SAMPLING RATE
1500
1250
1000
750
10,000
V
REF
= V
DD
V
= V
DD
V
REF
= V
DD
REF
CODE = 1010101000
R = ∞
R = ∞
L
L
C = 50pF
L
1300
1100
900
1000
100
10
C = 50pF
CODE = 1010101000
C = 50pF
L
L
CODE = 1010101000
700
1
500
500
0.1
-60 -40 -20
0
20 40 60 80 100 120 140
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
0.1
1
10
100
1k
10k
100k
TEMPERATURE (°C)
V
SAMPLING RATE (sps)
DD
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN CURRENT
vs. TEMPERATURE
1000
800
600
400
200
0
1000
800
600
400
200
0
V
REF
= V
DD
V
REF
= V
DD
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
-60 -40 -20
0
20 40 60 80 100 120 140
V
TEMPERATURE (°C)
DD
OFFSET ERROR vs. TEMPERATURE
OFFSET ERROR vs. SUPPLY VOLTAGE
0.20
0.15
0.10
0.05
0
0.20
0.15
0.10
0.05
0
-60 -35 -10 15 40 65 90 115 140
TEMPERATURE (°C)
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
DD
_______________________________________________________________________________________
5
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l,
1 0 8 k s p s , S e ria l 1 0 -Bit ADCs in 8 -P in µMAX
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +3.0V, V
= 2.5V, 0.1µF capacitor at REF, f
= 2.17MHz, 16 clocks/conversion cycle (108ksps); CH- = GND for
DD
REF
SCLK
MAX159; T = +25°C, unless otherwise noted.)
A
GAIN ERROR
vs. SUPPLY VOLTAGE
0.2
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
GAIN ERROR
vs. TEMPERATURE
0.03
0.02
0.01
0
0.2
0.1
0
0.1
0
-0.1
-0.2
-0.01
-0.02
-0.03
-0.1
-0.2
7/MAX159
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
-60 -35 -10 15 40 65 90 115 140
TEMPERATURE (°C)
0
250
500
750
1000
V
OUTPUT CODE
DD
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
INTEGRAL NONLINEARITY
vs. TEMPERATURE
0.20
0.20
0.15
0.10
0.05
0
0.15
0.10
0.05
0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
-60 -35 -10 15 40 65 90 115 140
TEMPERATURE (°C)
V
DD
6
_______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l,
1 0 8 k s p s , S e ria l 1 0 -Bit ADCs in 8 -P in µMAX
7/MAX159
P in De s c rip t io n
PIN
1
NAME
FUNCTION
V
DD
Positive Supply Voltage, +2.7V to +5.25V
2
CH0 (CH+)
CH1 (CH-)
GND
Analog Input, MAX157: Single-Ended (CH0); MAX159: Differential (CH+).
Analog Input, MAX157: Single-Ended (CH1); MAX159: Differential (CH-).
Analog and Digital Ground
3
4
External Reference Voltage Input. Sets analog voltage range. Bypass with a 100nF capacitor close to the
part.
5
6
REF
Active-Low Chip-Select Input, Active-High Shutdown Input. Pulling CS/SHDN high puts chip into
shutdown with a maximum current of 5µA.
CS/SHDN
7
8
DOUT
SCLK
Serial Data Output. Data changes state at SCLK’s falling edge. High impedance when CS/SHDN is high.
Serial Clock Input. DOUT changes on the falling edge of SCLK.
V
DD
DOUT
6k
DOUT
6k
C
L
C
L
GND
a) HIGH-Z TO V , V TO V , AND V TO HIGH-Z
GND
b) HIGH-Z TO V , V TO V , AND V TO HIGH-Z
0H 0L
0H
OH
0L 0H
0L
OL
Figure 1. Load Circuits for Enable and Disable Time
the same channel by toggling CS/SHDN twice between
conversions. If only one channel is required, CH0 and
CH1 may be connected together; however the output
d a ta will s till c onta in the c ha nne l id e ntific a tion b it
(before the MSB).
De t a ile d De s c rip t io n
The MAX157/MAX159 a na log -to-d ig ita l c onve rte rs
(ADCs) use a successive-approximation conversion
(SAR) technique and on-chip track/hold (T/H) structure
to convert an analog signal to a serial, 10-bit digital out-
put data stream.
For the MAX159, the input channels form a single differ-
ential channel pair (CH+, CH-). This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side IN- must remain stable
within ± 0.5LSB (± 0.1LSB for op timum re s ults ) with
respect to GND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- to GND.
This flexible serial interface provides easy interface to
microprocessors (µPs). Figure 2 shows a simplified
functional diagram of the internal architecture for both
the MAX157 (2 c ha nne ls , s ing le -e nd e d ) a nd the
MAX159 (1 channel, pseudo-differential).
S in g le -En d e d (MAX1 5 7 ) a n d P s e u d o -
Diffe re n t ia l (MAX1 5 9 ) An a lo g In p u t s
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
. The
HOLD
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode (MAX157), both chan-
nels CH0 and CH1 are referred to GND and can be
connected to two different signal sources. Following the
power-on reset, the ADC is set to convert CH0. After
CH0 has been converted, CH1 will be converted, and
the c onve rs ions will c ontinue to a lte rna te b e twe e n
channels. Channel switching is performed by toggling
the CS/SHDN pin. Conversions can be performed on
acquisition interval spans from when CS/SHDN falls to
the falling edge of the second clock cycle (external
clock mode) or from when CS/SHDN falls to the first
falling edge of SCLK (internal clock mode). At the end
of the acquisition interval, the T/H switch opens, retain-
ing charge on C
as a sample of the signal at IN+.
HOLD
The conversion interval begins with the input multiplex-
er switching C from the positive input (IN+) to the
HOLD
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input.
_______________________________________________________________________________________
7
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l,
1 0 8 k s p s , S e ria l 1 0 -Bit ADCs in 8 -P in µMAX
The c a p a c itive d ig ita l-to-a na log c onve rte r (DAC)
adjusts during the remainder of the conversion cycle
to restore node ZERO to 0V within the limits of 10-bit
resolution. This action is equivalent to transferring a
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor forms
an RC filter, limiting the ADC’s signal bandwidth.
16pF · [(V +) - (V -)] charge from C
ry-weighted capacitive DAC, which in turn forms a digi-
tal representation of the analog input signal.
to the bina-
IN
IN
HOLD
In p u t Ba n d w id t h
The MAX157/MAX159 T/H stage offers both a 2.25MHz
small-signal and a 1MHz full-power bandwidth, which
makes it possible to use the parts for digitizing high-
speed transients and measuring periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended. Most
aliasing problems can be fixed easily with an external
resistor and a capacitor. However, if DC precision is
re q uire d , it is us ua lly b e s t to c hoos e a c ontinuous
or switched-capacitor filter, such as the MAX7410/
MAX7414 (Figure 4). Their Butterworth characteristic
generally provides the best compromise (with regard to
rolloff and attenuation) in filter configurations, is easy to
design, and provides a maximally flat passband re-
sponse.
Tra c k /Ho ld
The ADC’s T/H stage enters its tracking mode on the
fa lling e d g e of CS/SHDN. For the MAX157 (s ing le -
ended inputs), IN- is connected to GND and the con-
verter samples the positive (“+”) input. For the MAX159
(pseudo-differential inputs), IN- connects to the nega-
tive input (“-”), and the difference of [(V +) - (V -)] is
sampled. At the end of the conversion, the positive
IN
IN
input connects back to IN+ and C
input signal.
charges to the
HOLD
7/MAX159
The time required for the T/H stage to acquire an input
signal is a function of how fast its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
t
, is the maximum time the device takes to acquire
ACQ
An a lo g In p u t P ro t e c t io n
Internal protection diodes, which clamp the analog
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation:
input to V
and GND, allow each input channel to
DD
swing within GND - 300mV to V
+ 300mV without
DD
d a ma g e . Howe ve r, for a c c ura te c onve rs ions b oth
inputs must not exceed V + 50mV or be less than
GND - 50mV.
t
= 7(R + R )C
S IN IN
ACQ
DD
where R is the source impedance of the input signal,
S
R
(9kΩ) is the input resistance, and C (16pF) is the
IN
IN
If an off-channel analog input voltage exceeds the
supplies, limit the input current to 4mA.
input capacitance of the ADC. Source impedances
below 4kΩ have no significant impact on the AC perfor-
mance of the MAX157/MAX159.
CAPACITIVE DAC
REF
CS/SHDN
SCLK
COMPARATOR
INPUT
MUX
INTERNAL
CLOCK
ZERO
–
+
CH1
(CH-)
C
16pF
DOUT
HOLD
CONTROL
LOGIC
OUTPUT
REGISTER
R
9k
TO SAR
IN
CH0
(CH+)
C
SWITCH
CH0
(CH+)
HOLD
SCLK
TRACK
T/H
ANALOG
INPUT
10+2 BIT
T/H
SAR
ADC
IN
OUT
MAX157
MAX159
CH1
(CH-)
MUX
(2 CHANNEL)
CONTROL
LOGIC
GND
REF
SINGLE-ENDED MODE: CHO, CH1 = IN+; GND = IN-
DIFFERENTIAL MODE: CH+ = IN+; CH- = IN-
( ) ARE FOR MAX159
( ) ARE FOR MAX159
Figure 2. MAX157/MAX159 Simplified Functional Diagram
Figure 3. Analog Input Channel Structure
8
_______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l,
1 0 8 k s p s , S e ria l 1 0 -Bit ADCs in 8 -P in µMAX
7/MAX159
S e le c t in g Clo c k Mo d e
To s ta rt the c onve rs ion p roc e s s on the MAX157/
MAX159, p ull CS/SHDN low. At CS/SHDN’s fa lling
edge, the part wakes up, the internal T/H enters track
mode, and a conversion begins. In addition, the state of
SCLK at CS/SHDN’s falling edge selects internal (SCLK
= high) or external (SCLK = low) clock mode.
ing SCLK high during a high/low transition of CS/SHDN.
The first SCLK falling edge samples the data and initi-
ates a conversion using the integrated on-chip oscilla-
tor. After the conversion, the oscillator shuts off and
DOUT g oe s hig h, s ig na ling the e nd of c onve rs ion
(EOC). Data can then be read out with SCLK.
External Clock (f
= 100kHz to 2.17MHz)
SCLK
Internal Clock (f
< 100kHz or f
> 2.17MHz)
External clock mode (Figure 6) is selected by transition-
ing CS/SHDN from high to low while SCLK is low. The
external clock signal not only shifts data out, but also
drives the analog-to-digital conversion. The input is
sampled and conversion begins on the falling edge of
the second clock pulse. Conversion must be completed
within 140µs to prevent degradation in the conversion
results caused by droop on the T/H capacitors. External
clock mode provides the best throughput for clock fre-
quencies between 100kHz and 2.17MHz.
SCLK
SCLK
In internal clock mode, the MAX157/MAX159 run from
an internal, laser-trimmed oscillator to within 20% of the
2MHz specified clock rate. This releases the system
microprocessor from running the SAR conversion clock
and allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0 to
5MHz. Operating the MAX157/MAX159 in internal clock
mode is necessary for serial interfaces operating with
clock frequencies lower than 100kHz or greater than
2.17MHz. Select internal clock mode (Figure 5) by hold-
V
DD
1
4
5
V
DD
7
V
DD
2
EXTERNAL
REFERENCE
0.1µF
CH0
SHDN
REF
470Ω
5
8
OUT
CLK
MAX7410
MAX7414
MAX157
2
3
8
7
6
IN
CH1
DOUT
f
= 15kHz
CORNER
0.01µF
CS/SHDN
SCLK
µP/µC
COM
OS
GND
GND
4
1
6
3
1.5MHz
CLOCK
0.01µF
Figure 4. Analog Input with Anti-Aliasing Filter Structure
ACTIVE POWER ACTIVE
DOWN
t
t
CONV
WAKE
t
CS
(t
)
ACQ
CS/SHDN
SCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
HIGH-Z
EOC
1
1 CHID MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0
DOUT
HIGH-Z
SAMPLING INSTANT
Figure 5. Internal Clock Mode Timing
_______________________________________________________________________________________
9
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l,
1 0 8 k s p s , S e ria l 1 0 -Bit ADCs in 8 -P in µMAX
Ou t p u t Da t a Fo rm a t
Table 1 illustrates the 16-bit, serial data-stream output
format for both the MAX157 and MAX159. The first three
bits are always logic high (including the EOC bit for
internal clock mode), followed by the channel identifica-
tion (CHID = 0 for CH0, CHID = 1 for CH1, CHID = 1 for
MAX159), the 10 bits of data in MSB first format, and
two sub-LSB bits (S1 and S0). After the last bit has been
read out, additional SCLK pulses will clock out trailing
zeros. DOUT transitions on the falling edge of SCLK.
The output remains high impedance when CS/SHDN is
high.
Au t o m a t ic P o w e r-Do w n Mo d e
Whe ne ve r the MAX157/MAX159 a re not s e le c te d
(CS/SHDN = V ), the parts enter their shutdown mode.
DD
In shutdown all internal circuitry is turned off, which
reduces the supply current to typically less than 0.2µA.
With an external reference stable to within 1LSB, the
wake-up time is 2.5µs. If the external reference is not sta-
ble within 1LSB, the wake-up time must be increased to
allow the reference to stabilize.
Ap p lic a t io n s In fo rm a t io n
S ig n a l-t o -No is e Ra t io (S NR)
For a waveform perfectly reconstructed from digital
samples, SNR is the ratio of full-scale analog input
(RMS value) to the RMS quantization error (residual
error). The ideal, theoretical minimum analog-to-digital
noise is caused by quantization error only and results
directly from the ADC’s resolution (N bits):
Ex t e rn a l Re fe re n c e
An external reference is required for both the MAX157
and MAX159. At REF, the DC input resistance is a mini-
mum of 18kΩ. During a conversion, a reference must
be able to deliver 250µA of DC load current and have
a n outp ut imp e d a nc e of 10Ω or le s s . Us e a 0.1µF
bypass capacitor for best performance. The reference
7/MAX159
SNR
= (6.02 · N + 1.76)dB
(MAX)
input structure allows a voltage range of 0 to (V
+
DD
50mV) although noise levels will decrease effective res-
olution at lower reference voltages.
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
ACTIVE POWER ACTIVE
DOWN
SAMPLING INSTANT
t
WAKE
t
CS
(t
)
ACQ
CS/SHDN
SCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
HIGH-Z
HIGH-Z
CHID MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0
DOUT
Figure 6. External Clock Mode Timing
• • •
CS/SHDN
t
CH
t
CS
t
SCLKS
t
CL
SCLK
• • •
t
DV
t
DO
t
TR
HIGH-Z
HIGH-Z
DOUT
• • •
Figure 7. Detailed Serial-Interface Timing Sequence
10 ______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l,
1 0 8 k s p s , S e ria l 1 0 -Bit ADCs in 8 -P in µMAX
7/MAX159
Table 1. Serial Output Data Stream for Internal and External Clock Mode
SCLK CYCLE
DOUT (Internal Clock)
DOUT (External Clock)
1
EOC
1
2
1
1
3
1
1
4
5
6
7
8
9
10
D4
D4
11
D3
D3
12
D2
D2
13
D1
D1
14
D0
D0
15
S1
S1
16
S0
S0
CHID D9
CHID D9
D8
D8
D7
D7
D6
D6
D5
D5
etc. Therefore, SNR is computed by taking the ratio of
the RMS signal to the RMS noise (which includes all
spectral components minus the fundamental), the first
five harmonics, and the DC offset.
serial clock for the MAX157/MAX159. Select a clock fre-
quency from 100kHz to 2.17MHz (external clock mode).
1) Use a general-purpose I/O line on the CPU to pull
CS/SHDN low while SCLK is low.
2) Wait for the minimum wake-up time (t
fied before activating SCLK.
) speci-
S ig n a l-t o -No is e P lu s Dis t o rt io n (S INAD)
Signal-to-noise plus distortion is the ratio of the funda-
mental input frequency’s RMS amplitude to RMS equiv-
alent of all other ADC output signals:
WAKE
3) Activate SCLK for a minimum of 16 clock cycles. The
first falling clock edge will generate a serial data-
stream of three leading ones, followed by the chan-
ne l id e ntific a tion, the MSB of the d ig itize d inp ut
s ig na l, a nd two s ub -b its . DOUT tra ns itions on
SCLK’s falling edge and is available in MSB-first for-
mat. Observe the SCLK to DOUT valid timing char-
acteristic. Data should be clocked into the µP on
SCLK’s rising edge.
SignalRMS
SINAD(dB) = 20 log
(Noise + Distortion)RMS
Effe c t ive Nu m b e r o f Bit s (ENOB)
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. With an
input range equal to the full-scale range of the ADC,
calculate the effective number of bits as follows:
4) Pull CS/SHDN high at or after the 16th falling clock
edge. If CS/SHDN remains low, trailing zeros will be
clocked out after the sub-bits.
ENOB = (SINAD - 1.76) / 6.02
5) With CS/SHDN high, wait at least 60ns (t ), before
CS
starting a new conversion by pulling CS/SHDN low.
A conversion can be aborted by pulling CS/SHDN
high before the conversion ends; wait at least 60ns
before starting a new conversion.
To t a l Ha rm o n ic Dis t o rt io n (THD)
THD is the ratio of the RMS sum of the first five harmon-
ics of the input signal to the fundamental itself. This is
expressed as:
Data can be output either in two 8-bit sequences or
continuously. The bytes will contain the result of the
conversion padded with three leading ones, the chan-
nel identification before the MSB, and two trailing sub-
bits. If the serial clock hasn’t been idled after the last
sub-bit (S0) and CS/SHDN is kept low, DOUT sends
trailing zeros.
2
2
2
2
V
+ V + V + V
2
3
4
5
(
)
THD = 20 log
2
V
1
where V is the fundamental amplitude and V through
1
2
S P I a n d MICROWIRE In t e rfa c e
When using SPI (Figure 8a) or MICROWIRE (Figure 8b)
interfaces, set CPOL = 0 and CPHA = 0. Conversion
begins with a falling edge on CS/SHDN (Figure 8c). Two
consecutive 8-bit readings are necessary to obtain the
entire 10-bit result from the ADC. DOUT data transitions
on the serial clock’s falling edge and is clocked into the
µP on SCLK’s rising edge. The first 8-bit data stream
contains three leading ones, followed by channel identi-
fication and the first four data bits starting with the MSB.
The second 8-bit data stream contains the remaining
bits, D5 through D0, and the sub-bits S1 and S0.
V are the amplitudes of the 2nd through 5th-order har-
monics.
5
S p u rio u s -Fre e Dyn a m ic Ra n g e (S FDR)
SFDR is the ratio of RMS amplitude of the fundamental
(maximum signal component) to the RMS value of the
next largest spurious component, excluding DC offset.
Co n n e c t io n t o S t a n d a rd In t e rfa c e s
The MAX157/MAX159 interface is fully compatible with
SPI/QSPI and MICROWIRE standard serial interfaces.
If a serial interface is available, establish the CPU’s seri-
al interface as master so that the CPU generates the
______________________________________________________________________________________ 11
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l,
1 0 8 k s p s , S e ria l 1 0 -Bit ADCs in 8 -P in µMAX
I/O
SCK
CS/SHDN
SCLK
I/O
SK
SI
CS/SHDN
SCLK
MISO
DOUT
DOUT
V
DD
SPI
MICROWIRE
MAX157
MAX159
MAX157
MAX159
SS
Figure 8a. SPI Connections
Figure 8b. MICROWIRE Connections
1ST BYTE READ
2ND BYTE READ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
7/MAX159
CS/SHDN
HIGH-Z
CHID D9
MSB
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
S1
S0
DOUT*
SAMPLING
INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH -Z
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
QS P I In t e rfa c e
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX157/MAX159 supports a maxi-
CS
SCK
CS/SHDN
SCLK
mum f
of 2.17MHz. The QSPI circuit in Figure 9a
SCLK
can be programmed to perform a conversion on each
of the two channels for the MAX157.
MISO
DOUT
V
DD
QSPI
Figure 9b shows the QSPI interface timing.
MAX157
MAX159
P IC1 6 w it h S S P Mo d u le
a n d P IC1 7 In t e rfa c e
SS
The MAX157/MAX159 are compatible with a PIC16/
PIC17 microcontroller (µC), using the synchronous seri-
al port (SSP) module.
Figure 9a. QSPI Connections
To establish SPI communication, connect the controller
as shown in Figure 10a and configure the PIC16/PIC17
as system master by initializing its synchronous serial
port control register (SSPCON) and synchronous serial
port status register (SSPSTAT) to the bit patterns shown
in Tables 2 and 3.
three leading ones, the channel identification, and the
first four data bits starting with the MSB. The second 8-
bit data stream contains the remaining bits, D5 through
D0, and the two sub-bits S1 and S0.
La yo u t , Gro u n d in g , a n d Byp a s s in g
For b e s t p e rforma nc e us e p rinte d c irc uit b oa rd s
(PCBs), wire-wrap configurations are not recommend-
ed, since the layout should ensure proper separation of
analog and digital traces. Run analog and digital lines
anti-parallel to each other, and don’t layout digital sig-
nal paths underneath the ADC package. Use separate
analog and digital PCB ground sections with only one
In SPI mode, the PIC16/PIC17 µCs allow eight bits of
data to be synchronously transmitted and received
simultaneously. Two consecutive 8-bit readings (Figure
10b) are necessary to obtain the entire 10-bit result
from the ADC. DOUT d a ta tra ns itions on the s e ria l
c loc k’s fa lling e d g e a nd is c loc ke d into the µC on
SCLK’s rising edge. The first 8-bit data stream contains
12 ______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l,
1 0 8 k s p s , S e ria l 1 0 -Bit ADCs in 8 -P in µMAX
7/MAX159
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
CS/SHDN
HIGH-Z
CHID D9
SAMPLING INSTANT MSB
*WHEN CS/SHDN IS HIGH, DOUT = HIGH - Z
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
S1
S0
DOUT
Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
star-point (Figure 11) connecting the two ground sys-
tems (analog and digital). For lowest-noise operation,
ensure the ground return to the star ground’s power
supply is low impedance and as short as possible.
Route digital signals far away from sensitive analog and
reference inputs.
V
V
DD
DD
SCLK
DOUT
SCK
SDI
I/O
CS/SHDN
High-frequency noise in the power supply (V ) could
DD
influence the proper operation of the ADC’s fast com-
MAX157
MAX159
PIC16/PIC17
parator. Bypass V
to the star ground with a network
DD
of two parallel capacitors, 0.1µF and 1µF, located as
c los e a s p os s ib le to the p owe r s up p ly p in of the
MAX157/MAX159. Minimize capacitor lead length for
best supply-noise rejection and add an attenuation
resistor (10Ω) if the power supply is extremely noisy.
GND
GND
Figure 10a. SPI Interface Connection for a PIC16/PIC17
Controller
1ST BYTE READ
2ND BYTE READ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
CS/SHDN
HIGH-Z
CHID D9
SAMPLING INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH - Z
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
S1
S0
DOUT*
MSB
Figure 10b. SPI Interface Timing Sequence with PIC16/17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3–SSPM0 = 0001)
POWER SUPPLIES
+3V
+3V
GND
R* = 10Ω
1µF
0.1µF
GND
V
DD
+3V DGND
DIGITAL
CIRCUITRY
MAX157
MAX159
* OPTIONAL FILTER RESISTOR
Figure 11. Power-Supply Bypassing and Grounding
______________________________________________________________________________________ 13
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l,
1 0 8 k s p s , S e ria l 1 0 -Bit ADCs in 8 -P in µMAX
Table 2. Detailed SSPCON Register Content
MAX157/MAX159
CONTROL BIT
SYNCHRONOUS SERIAL PORT CONTROL REGISTER (SSPCON)
SETTINGS
WCOL
Bit 7
Bit 6
X
X
Write Collision Detection Bit
SSPOV
Receive Overflow Detect Bit
Synchronous Serial Port Enable Bit
SSPEN
Bit 5
1
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI pins as serial port pins.
CKP
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3
SSPM2
SSPM1
SSPM0
Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects
f
= f
/ 16.
CLK
OSC
7/MAX159
X = Don’t care
Table 3. Detailed SSPSTAT Register Content
MAX157/MAX159
CONTROL BIT
SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT)
SETTINGS
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output
time.
SMP
Bit 7
0
CKE
D/A
P
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.
X
X
X
X
X
X
Data Address Bit
Stop Bit
S
Start Bit
R/W
UA
BF
Read/Write Bit Information
Update Address
Buffer Full Status Bit
X = Don’t care
14 ______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l,
1 0 8 k s p s , S e ria l 1 0 -Bit ADCs in 8 -P in µMAX
7/MAX159
Ch ip In fo rm a t io n
TRANSISTOR COUNT: 2,058
SUBSTRATE CONNECTED TO GND
P a c k a g e In fo rm a t io n
______________________________________________________________________________________ 15
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l,
1 0 8 k s p s , S e ria l 1 0 -Bit ADCs in 8 -P in µMAX
P a c k a g e In fo rm a t io n (c o n t in u e d )
7/MAX159
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1998 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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