MAX1576 [MAXIM]
480mA White LED 1x/1.5x/2x Charge Pump for Backlighting and Camera Flash; 480mA白光LED 1X /倍/1.5倍/ 2倍电荷泵，用于背光和相机闪光灯
| 型号： | MAX1576 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 480mA White LED 1x/1.5x/2x Charge Pump for Backlighting and Camera Flash |
| 文件： | 总22页 (文件大小：2249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BLOCK DIAGRAM
12
DATA IN
CLOCK
D
C
24–1/2–STAGE
SHIFT REGISTER
18
11
DATA OUT
4
10
4
4
4
4
4
ENABLE
PIN 3 = V
PIN 14 = V
SS
DD
BitGrabber
DISPLAY REGISTER
24 BITS
BitGrabber
CONFIGURATION REGISTER
8 BITS
4
4
4
4
4
4
NIBBLE MUX AND
DECODER ROM
5
OSCILLATOR AND
CONTROL LOGIC
POR
7
a TO g
h
DIM/BRIGHT
8
5
BLANK
ANODE DRIVERS
(CURRENT SOURCES)
Rx
BANK SWITCHES (FETs)
7
6
5
4
2
1
20 19
g h
9
13
15
16
17
a
b
c
d
e
f
BANK 1 BANK 2 BANK 3 BANK 4 BANK 5
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
This device contains protection circuitry to
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
guard against damage due to high static volt-
ages or electric fields. However, precautions
must be taken to avoid applications of any volt-
age higher than maximum rated voltages to this
high–impedance circuit. For proper operation,
V
DD
– 0.5 to + 6.0
V
in
DC Input Voltage
– 0.5 to V
+ 0.5
V
DD
V
out
DC Output Voltage
– 0.5 to V
+ 0.5
V
DD
V
V
and V should be constrained to the range
in
out
I
in
DC Input Current — per Pin
(Includes Pin 8)
± 15
mA
≤ (V or V ) ≤ V
in out
.
DD
SS
Unused inputs must always be tied to an ap-
propriate logic voltage level (e.g., either V
or
I
DC Output Current —
mA
SS
out
V
DD
). Unused outputs must be left open.
Pins 1, 2, 4 – 7, 19, 20 Sourcing
Sinking
– 40
10
Pins 9, 13, 15, 16, 17 Sinking
Pin 18
320
± 15
I
, I
DC Supply Current, V
and V
Pins
SS
± 350
mA
DD SS
DD
T
J
Chip Junction Temperature
– 40 to + 130
°C
R
Device Thermal Resistance,
Junction–to–Ambient (see Thermal
°C/W
θJA
Considerations section)
Plastic DIP
90
SOG Package
100
T
Storage Temperature
– 65 to + 150
260
°C
°C
stg
T
Lead Temperature, 1 mm from Case for
10 Seconds
L
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
MC14489B
2
MOTOROLA
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V , T = – 40° to 130°C* unless otherwise indicated)
SS
J
V
DD
V
Guaranteed
Limit
Symbol
Parameter
Test Condition
Unit
V
V
DD
Power Supply Voltage Range of LED Drive Circuitry
—
—
4.5 to 5.5
3.0
V
(stby) Minimum Standby Voltage
Bits Retained in Display and
Configuration Registers, Data
Port Fully Functional
V
DD
V
Maximum Low–Level Input Voltage
(Data In, Clock, Enable)
3.0
5.5
0.9
1.65
V
V
V
V
IL
V
IH
Minimum High–Level Input Voltage
(Data In, Clock, Enable)
3.0
5.5
2.1
3.85
V
Hys
Minimum Hysteresis Voltage
(Data In, Clock, Enable)
3.0
5.5
0.2
0.4
V
OL
Maximum Low–Level Output Voltage
(Data Out)
I
= 20 µA
3.0
5.5
0.1
0.1
out
I
I
= 1.3 mA
4.5
0.4
out
V
OH
Minimum High–Level Output Voltage
(Data Out)
= – 20 µA
3.0
5.5
2.9
5.4
V
out
I
= – 800 µA
4.5
5.5
5.5
4.1
out
I
in
Maximum Input Leakage Current
(Data In, Clock, Enable)
V
= V
or V
± 2.0
± 0.1
µA
in
DD
DD
SS
SS
V
= V
or V
,
in
J
T = 25°C only
i
Minimum Sinking Current
(a, b, c, d, e, f, g, h)
V
= 1.0 V
4.5
5.0
5.0
0.2
mA
mA
OL
out
i
Peak Sourcing Current — See Figure 7 for currents up to
35 mA (a, b, c, d, e, f, g, h)
Rx = 2.0 kΩ, V
Dimmer Bit = High
= 3.0 V,
= 3.0 V,
13 to 17.5
6 to 9
OH
out
Rx = 2.0 kΩ, V
out
Dimmer Bit = Low
I
Maximum Output Leakage Current
(Bank 1, Bank 2, Bank 3, Bank 4, Bank 5)
V
= V
= V
(FET Leakage)
(FET Leakage),
5.5
5.5
50
1
µA
OZ
out
DD
DD
V
out
T = 25°C only
J
V
= V
(Protection Diode
SS
5.5
5.0
5.5
1
out
Leakage)
R
Maximum ON Resistance
(Bank 1, Bank 2, Bank 3, Bank 4, Bank 5)
I
= 0 to 200 mA
10
Ω
on
out
I
, I
Maximum Quiescent Supply Current
Device in Low–Power Mode,
= V or V , Rx in
100
µA
DD SS
V
in
SS
DD
Place, Outputs Open
Same as Above, T = 25°C
5.5
5.5
20
J
I
ss
Maximum RMS Operating Supply Current
Device NOT in Low–Power
1.5
mA
(The V
SS
leg does not contain the Rx current component. Mode, V = V
in
or V
,
DD
SS
See Pin Descriptions.)
Outputs Open
* See Thermal Considerations section.
MOTOROLA
MC14489B
3
AC ELECTRICAL CHARACTERISTICS (T = – 40° to 130°C*, C = 50 pF, Input t = t = 10 ns)
J
L
r
f
V
DD
V
Guaranteed
Limit
Symbol
Parameter
Serial Data Clock Frequency, Single Device or Cascaded Devices
NOTE: Refer to Clock t below
w
(Figure 1)
Unit
f
3.0
4.5
5.5
dc to 3.0
dc to 4.0
dc to 4.0
MHz
clk
t
t
,
Maximum Propagation Delay, Clock to Data Out
(Figures 1 and 5)
3.0
4.5
5.5
140
80
80
ns
ns
Hz
pF
PLH
t
PHL
,
Maximum Output Transistion Time, Data Out
(Figures 1 and 5)
3.0
4.5
5.5
70
50
50
TLH
t
THL
f
R
Refresh Rate — Bank 1 through Bank 5
(Figures 2 and 6)
3.0
4.5
5.5
NA
700 to 1900
700 to 1900
C
Maximum Input Capacitance — Data In, Clock, Enable
—
10
in
* See Thermal Considerations section.
TIMING REQUIREMENTS (T = – 40° to 130°C*, Input t = t = 10 ns unless otherwise indicated)
J
r
f
V
DD
V
Guaranteed
Limit
Symbol
, t
Parameter
Unit
t
Minimum Setup and Hold Times, Data In versus Clock
(Figure 3)
3.0
4.5
5.5
50
40
40
ns
su
h
t
, t ,
Minimum Setup, Hold, ** and Recovery Times, Enable versus Clock
(Figure 4)
3.0
4.5
5.5
150
100
100
ns
µs
ns
ns
ms
su
h
t
rec
t
Minimum Active–Low Pulse Width, Enable
(Figure 4)
3.0
4.5
5.5
4.5
3.4
3.4
w(L)
t
Minimum Inactive–High Pulse Width, Enable
(Figure 4)
3.0
4.5
5.5
300
150
150
w(H)
t
Minimum Pulse Width, Clock
(Figure 1)
3.0
4.5
5.5
167
125
125
w
t , t
Maximum Input Rise and Fall Times — Data In, Clock, Enable
(Figure 1)
3.0
4.5
5.5
1
1
1
r
f
*See Thermal Considerations section.
**For a high–speed 8–Clock access, t for Enable is determined as follows:
h
V
V
= 3 to 4.5 V, f
> 1.78 MHz: t = 4350 – (7500/f
)
)
DD
DD
clk
h
clk
clk
= 4.5 to 5.5 V, f > 2.34 MHz: t = 3300 – (7500/f
clk
clk
h
where t is in ns and f
h
is in MHz.
NOTES:
1. This restriction does NOT apply for f rates less than those listed above. For “slow” f rates, use the t limits in the above table.
clk clk
h
2. This restriction does NOT apply for an access involving more than 8 Clocks. For > 8 Clocks, use the t limits in the above table.
h
MC14489B
MOTOROLA
4
t
t
r
f
V
V
DD
90%
50%
10%
CLOCK
SS
t
t
w
w
1/f
clk
t
t
PHL
PLH
90%
50%
10%
BANK
OUTPUT
DATA OUT
50%
t
t
1/f
TLH
THL
R
Figure 1.
Figure 2.
t
(L)
t (H)
w
w
V
V
V
V
DD
SS
DD
SS
VALID
ENABLE
50%
V
V
DD
50%
D
ATA IN
t
t
h
su
t
rec
SS
t
t
h
su
CLOCK
V
V
50%
FIRST
CLOCK
DD
50%
CLOCK
LAST
CLOCK
SS
Figure 3.
Figure 4.
V
DD
TEST POINT
TEST POINT
56
Ω
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
*
C
*
L
C
L
*Includes all probe and fixture capacitance.
*Includes all probe and fixture capacitance.
Figure 5.
Figure 6.
MOTOROLA
MC14489B
5
Enable (Pin 10)
PIN DESCRIPTIONS
DIGITAL INTERFACE
Active–Low Enable Input. This pin allows the MC14489B to
be used on a serial bus, sharing Data In and Clock with other
peripherals. When Enable is in an inactive high state, Data
Out is forced to a known (low) state, shifting is inhibited, and
the port is held in the initialized state. To transfer data to the
device, Enable (which initially must be inactive high) is taken
low, a serial transfer is made via Data In and Clock, and
Enable is taken high. The low–to–high transition on Enable
transfers data to either the configuration or display register,
depending on the data stream length.
Data In (Pin 12)
Serial Data Input. The bit stream begins with the MSB and
is shifted in on the low–to–high transition of Clock. When the
device is not cascaded, the bit pattern is either 1 byte (8 bits)
long to change the configuration register or 3 bytes (24 bits)
long to update the display register. For two chips cascaded,
the pattern is either 4 or 6 bytes, respectively. The display
does not change during shifting (until Enable makes a low–
to–high transition) which allows slow serial data rates, if de-
sired.
The bit stream needs neither address nor steering bits due
to the innovative BitGrabber registers. Therefore, all bits in
the stream are available to be data for the two registers. Ran-
dom access of either register is provided. That is, the regis-
ters may be accessed in any sequence. Data is retained in
the registers over a supply range of 3 to 5.5 V. Formats are
shown in Figures 8 through 14 and summarized in Table 2.
Information on the segment decoder is given in Table 1.
Every rising edge on Enable initiates a blanking interval
while data is loaded. Thus, continually loading the device with
the same data may cause the LEDs on some banks to appear
dimmer than others.
NOTE
Transitions on Enable must not be attempted
while Clock is high. This puts the device out of
synchronization with the microcontroller. Resyn-
chronization occurs when Enable is high and
Clock is low.
Data In typically switches near 50% of V
and has a
DD
Schmitt–triggered input buffer. These features combine to
maximize noise immunity for use in harsh environments and
bus applications. This input can be directly interfaced to
CMOS devices with outputs guaranteed to switch near rail–
to–rail. When interfacing to NMOS or TTL devices, either a
level shifter (MC14504B, MC74HCT04A) or pullup resistor of
1 kΩ to 10 kΩ must be used. Parameters to be considered
This input is also Schmitt–triggered and switches near 50%
of V , thereby minimizing the chance of loading erroneous
DD
data in the registers. See the last paragraph of Data In for
more information.
when sizing the resistor are the worst–case I
of the driving
Data Out (Pin 18)
OL
device, maximum tolerable power consumption, and maxi-
mum data rate.
Serial Data Output. Data is transferred out of the shift regis-
ter through Data Out on the high–to–low transition of Clock.
This output is a no connect, unless used in one of the man-
ners discussed below.
When cascading MC14489B’s, Data Out feeds Data In of the
next device per Figures 10, 11, 12, 13, and 14.
Data Out could be fed back to an MCU/MPU to perform a
wrap–around test of serial data. This could be part of a sys-
tem check conducted at power–up to test the integrity of the
system’s processor, pc board traces, solder joints, etc.
The pin could be monitored at an in–line Q.A. test during
board manufacturing.
Clock (Pin 11)
Serial Data Clock Input. Low–to–high transitions on Clock
shift bits available at Data In, while high–to–low transitions
shift bits from Data Out. The chip’s 24–1/2–stage shift regis-
ter is static, allowing clock rates down to dc in a continuous or
intermittent mode. The Clock input does not need to be syn-
chronous with the on–chip clock oscillator which drives the
multiplexing circuit.
Eight clock cycles are required to access the configuration
register, while 24 are needed for the display register when the
MC14489B is not cascaded. See Figures 8 and 9.
Finally, Data Out facilitates troubleshooting a system.
As shown in Figure 10, two devices may be cascaded. In
this case, 32 clock cycles access the configuration register
and 48 access the display register, as depicted in Figure 10.
Cascading of 3, 4, 5, and 6 devices is shown in Figures 11,
12, 13, and 14, respectively. Also, reference Table 2.
DISPLAY INTERFACE
Rx (Pin 8)
Clock typically switches near 50% of V
and has a
External Current–Setting Resistor. A resistor tied between
DD
Schmitt–triggered input buffer. Slow Clock rise and fall times
are tolerated. See the last paragraph of Data In for more in-
formation.
this pin and ground (V ) determines the peak segment drive
SS
current delivered at pins a through h. Pin 8’s resistor ties into
a current mirror with an approximate current gain of 10 when
bit D23 = high (brighten). With D23 = low, the peak current is
reduced about 50%. Values for Rx range from 700 Ω to infin-
ity. When Rx = ∞ (open circuit), the display is extinguished.
For proper current control, resistors having ± 1% tolerance
should be used. See Figure 7.
NOTE
To guarantee proper operation of the power–on
reset (POR) circuit, the Clock pin must NOT be
floated or toggled during power–up. That is, the
Clock pin must be stable until the V
reaches at least 3 V.
pin
DD
CAUTION
If control of the Clock pin during power–up is not
practical, then the MC14489B must be reset via bit
C0 in the C register. To accomplish this, C0 is re-
set low, then set high.
Small Rx values may cause the chip to overheat
if precautions are not observed. See Thermal
Considerations.
MC14489B
MOTOROLA
6
a through h (Pins 1, 2, 4 – 7, 19, 20)
Special design techniques are used on–chip to accommo-
date the high currents with low EMI (electromagnetic interfer-
ence) and minimal spiking on the power lines.
Anode–Driver Current Sources. These outputs are close-
ly–matched current sources which directly tie to the anodes
of external discrete LEDs (lamps) or display segment LEDs.
Each output is capable of sourcing up to 35 mA.
When used with lamps, outputs a, b, c, and d are used to
independently control up to 20 lamps. Output h is used to con-
trol up to 5 lamps dependently. (See Figure 17.) For lamps,
the No Decode mode is selected via the configuration regis-
ter, forcing e, f, and g inactive (low).
POWER SUPPLY
V
(Pin 14)
SS
Most–negative supply potential. This pin is usually ground.
Resistor Rx is externally tied to ground (V ). Therefore,
SS
pin does not contain the Rx current compo-
the chip’s V
nent.
SS
When used with segmented displays, outputs a through g
drive segments a through g, respectively. Output h is used to
drive the decimals. Refer to Figure 9. If unused, h must be left
open.
V
(Pin 13)
DD
Most–positive supply potential.
To guarantee data integrity in the registers and to ensure
the serial interface is functional, this voltage may range from
Bank 1 through Bank 5 (Pins 9, 13, 15, 16, 17)
3 to 6 volts with respect to V . For example, within this volt-
SS
Diode–Bank FET Switches. These outputs are low–resis-
age range, the chip could be placed in and out of the low–
power mode.
tance switches to ground (V ) capable of handling currents
SS
of up to 320 mA each. These pins directly tie to the common
cathodes of segmented displays or the cathodes of lamps
(wired with cathodes common).
To adequately drive the LEDs, this voltage must be 4.5 to
6 volts with respect to V
.
SS
The V
DD
pin contains the Rx current component plus the
The display is refreshed at a nominal 1 kHz rate to achieve
optimum brightness from the LEDs. A 20% duty cycle is uti-
lized.
chip’s current drain. In the low–power mode, the current mir-
ror and clock oscillator are turned off, thus significantly reduc-
ing the V
current, I
.
DD
DD
35
5 V SUPPLY
BIT D23 = HIGH (BRIGHTEN LEDs)
WITH D23 = LOW, i IS CUT BY 50%.
30
25
OH
20
15
10
5
400 800
1.2 k
1.6 k
2.0 k
2.4 k 2.8 k 3.2 k
3.6 k
4.0 k
Rx, EXTERNAL RESISTOR (
Ω)
NOTE: Drive current tolerance is approximately ± 15%.
Figure 7. a through h Nominal Current per Output versus Rx
MOTOROLA
MC14489B
7
Figure 8. Timing Diagrams for Non–Cascaded Devices
MOTOROLA
MC14489B
9
APPLICATIONS INFORMATION
+ 5 V
a
b
c
d
e
MC14489B
V
V
DD
SS
8
8
8
8
8
8
f
g
OPTIONAL
Rx
DATA OUT
Rx
a
g
h
f
b
c
h
+ 5 V
e
•
d
#5
#4
#3
#2
#1
BANK 5
BANK 4
CMOS
MCU/MPU
DATA IN
CLOCK
ENABLE
BANK 3
BANK 2
BANK 1
Figure 9. Non–Cascaded Application Example: 5 Character Common Cathode
LED Display with Two Intensities as Controlled via Serial Port
MC14489B
10
MOTOROLA
Table 2. Register Access for Two or More Cascaded Devices
Configuration Register Access
Display Register Access
Number of Leading
“Don’t Care” Bytes
Number of Leading
“Don’t Care” Bytes
Criteria*
Total Number of Bytes
Total Number of Bytes
If 3N is a Multiple of 4
If 3N – 1 is a Multiple of 4
If 3N – 2 is a Multiple of 4
If 3N – 3 is a Multiple of 4
3N
2
1
0
0
3N + 2
3N + 1
3N
2
1
0
0
3N – 1
3N – 2
3N – 2
3N
* N = number of devices that are cascaded. For example, to drive 10 digits, 2 devices are cascaded; therefore, N = 2. To drive 35 digits, seven
devices are cascaded; therefore N = 7.
LED DISPLAY
+ 5 V
8
5
+ 5 V
V
DD
R1
CMOS
MCU/MPU
Rx
MC14489B
R2
V
SS
NOTE: R1 limits the maximum current to avoid damaging the display and/or the MC14489B
due to overheating. See the Thermal Considerations section. An 1/8 watt resistor
may be used for R1. R2 is a 1 kΩ or 5 kΩ potentiometer (≥ 1/8 watt). R2 may be a
light–sensitive resistor.
Figure 15. Common–Cathode LED Display with Dial–Adjusted Brightness
MC14489B
16
MOTOROLA
UNIVERSAL OVERFLOW
(“1” OR “HALF–DIGIT”)
5–DIGIT DISPLAY
7
USE TO DRIVE LAMP
OR MINUS SIGN
h
1
2
3
4
5
a TO g
BANK OUTPUTS
MC14489B
3
INPUT LINES
NOTE: A Universal Overflow pins out all anodes and cathodes.
Figure 16. Driving 5 1/2 Digits
MOTOROLA
MC14489B
17
THESE LAMPS
INDEPENDENTLY
CONTROLLED WITH
BITS D0 TO D19
a
b
MC14489B
c
d
e
NC
NC
NC
f
g
h
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
THESE LAMPS DEPENDENTLY
CONTROLLED WITH
BITS D20, D21, AND D22*
3
CMOS
MCU/MPU
* If required, this group of lamps can be independently controlled. To accomplish independent control, only connect lamps to BANK 1 and
BANK 2 for output h (two lamps). Then, use bits D20, D21, and D22 for control of these two lamps.
Figure 17. 25–Lamp Application
MC14489B
18
MOTOROLA
4
•
4
4
4
a TO d
e TO h
BANK 1
TO
BANK 5
BANK 4
MC14489B
3
CMOS MCU/MPU
Figure 18. 4–Digit Display Plus Decimals with Four Annunciators
or 4–1/2–Digit Display Plus Sign
MUXED 5–DIGIT MONOLITHIC DISPLAY (CLUSTER)
HEWLETT–PACKARD 5082–7415 OR EQUIVALENT
14
12
3
6
2
10
8
5
1
13
4
9
7
9
7
6
5
4
2
1
20
19
17
16
15
13
8
MC14489B
3
INPUT LINES
Figure 19. Compact Display System with Three Components
MOTOROLA
MC14489B
19
THERMAL CONSIDERATIONS
The MC14489B is designed to operate with a chip–junction
That is, if T = 79°C, the maximum junction temperature is
130°C. The chip’s average temperature for this example is
lower than 130°C because all segments are usually not illumi-
A
temperature (T ) ranging from – 40 to 130°C, as indicated in
J
the electrical characteristics tables. The ambient operating
temperature range (T ) is dependent on R
, the internal
nated simultaneously for an indefinite period.
A
θJA
chip current, how many anode drivers are used, the number
of bank drivers used, the drive current, and how the package
is cooled. The maximum ratings table gives the thermal resis-
tance, junction–to–ambient, of the MC14489B mounted on a
pc board using natural convection to be 90°C per watt for the
plastic DIP. The SOG thermal resistance is 100°C per watt.
The following general equation (1) is used to determine the
power dissipated by the MC14489B.
Worst–Case Analysis Example 2:
16 lamps (4 banks and 4 anode drivers)
SOG without heat sink on PC board
i
= 30 mA max
= 1.8 V min
= 5.5 max
OH
V
LED
V
DD
P
= (30)(4)(5.5 – 1.8)(4/5) = 355 mW
Ref. (2)
Ref. (3)
Ref. (1)
D
P
= P + P
I
(1)
T
D
P = (1.5)(5.5) + 3[5.5 – 3(1.0)] = 16 mW
I
where
P
= Total power dissipation of the MC14489B
= Power dissipated in the driver circuitry (mW)
P = Power dissipated by the internal chip
T
Therefore, P = 355 + 16 = 371 mW
T
P
D
and ∆T
chip
= R
P = (100°C/W)(0.371) = 37°C
θJA T
I
circuitry (mW)
Finally, the maximum allowable
T = T max – ∆T = 130 – 37 = 93°C
A
J
chip
The equations for the two terms of the general equation
To extend the allowable ambient temperature range or to
are:
reduce T , which extends chip life, a heat sink such as shown
J
in Figure 20 can be used in high–current applications. Alter-
natively, heat–spreader techniques can be used on the PC
board, such as running a wide trace under the MC14489B and
using thermal paste. Wide, radial traces from the MC14489B
leads also act as heat spreaders.
P
= (i
OH
) (N)(V
– V
DD LED
)(B/5)
(2)
(3)
D
P = (1.5 mA)(V ) + I (V
– I Rx)
Rx DD Rx
I
DD
where
i
I
= Peak anode driver current (mA)
OH
Rx
= i
/10, with i
= the peak anode driver current
(mA) when the dimmer bit is high
OH
OH
N = Number of anode drivers used
B = Number of bank drivers used
Rx = External resistor value (kΩ)
V
= Maximum supply voltage, referenced to V
(volts)
DD
SS
V
= Minimum anticipated voltage drop across the
LED
LED
1.5 mA = Operating supply current of the MC14489B
AAVID #5804 or equivalent
(Tel. 603/524–4443, FAX 603/528–1478)
Motorola cannot recommend one supplier over another and
in no way suggests that this is the only heat sink supplier.
The following two examples show how to calculate the
maximum allowable ambient temperature.
Worst–Case Analysis Example 1:
Figure 20. Heat Sink
5–digit display with decimals (5 banks and 8 anode drivers)
DIP without heat sink on PC board
i
= 20 mA max
= 1.8 V min
= 5.25 max
OH
Table 3. LED Lamp and Common–Cathode Display
Manufacturers
V
LED
V
DD
Supplier
P
= (20)(8)(5.25 – 1.8)(5/5) = 552 mW
Ref. (2)
Ref. (3)
Ref. (1)
QT Optoelectronics
D
Hewlett–Packard (HP), Components Group
Industrial Electronic Engineers (IEE), Component Products Div.
Purdy Electronics Corp., AND Product Line
P = (1.5)(5.25) + 2[5.25 – 2(2)] = 10 mW
I
Therefore, P = 552 + 10 = 562 mW
T
and ∆T
chip
= R
P = (90°C/W)(0.562) = 51°C
θJA T
NOTE: Motorolacannotrecommendonesupplieroveranother
and in no way suggests that this is a complete listing of
LED suppliers.
Finally, the maximum allowable
T = T max – ∆T = 130 – 51 = 79°C
A
J
chip
MC14489B
20
MOTOROLA
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP
CASE 738–03
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
20
1
11
10
B
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
E
F
G
J
K
L
M
N
MIN
MAX
1.070
0.260
0.180
0.022
MIN
25.66
6.10
3.81
0.39
1.27 BSC
1.27
2.54 BSC
0.21
MAX
27.17
6.60
4.57
0.55
1.010
0.240
0.150
0.015
0.050 BSC
0.050
0.100 BSC
0.008
0.110
-T-
SEATING
PLANE
K
M
0.070
1.77
E
N
0.015
0.140
0.38
3.55
G
F
J 20 PL
2.80
0.300 BSC
15
0.040
7.62 BSC
15
0.51 1.01
D 20 PL
M
M
0.25 (0.010)
T
B
0°
°
0°
°
0.020
M
M
0.25 (0.010)
T
A
DW SUFFIX
SOG PACKAGE
CASE 751D–04
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
10X P
–B–
M
M
0.010 (0.25)
B
1
10
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
20X D
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
0.010 (0.25)
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
R X 45
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
MOTOROLA
MC14489B
21
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Mfax is a trademark of Motorola, Inc.
How to reach us:
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