MAX1559ETE [MAXIM]
5-Output Power-Management IC For Low-Cost PDAs; 5路输出电源管理IC，用于低成本PDA
| 型号： | MAX1559ETE |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 5-Output Power-Management IC For Low-Cost PDAs |
| 文件： | 总14页 (文件大小：526K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2962; Rev 1; 10/03
5-Output Power-Management IC For
Low-Cost PDAs
General Description
Features
The MAX1559 is a complete power-management chip
for low-cost personal digital assistants (PDAs) and
portable devices operating from a 1-cell lithium-ion
(Li+) or 3-cell NiMH battery. It includes all the regula-
tors, outputs, and voltage monitors necessary for small
PDAs while requiring a bare minimum of external com-
ponents. Featured are four linear regulators, a DC-DC
boost converter for LCD bias, a microprocessor reset
output, and low-battery shutdown in a miniature QFN
package. For a compatible Li+ charger for both USB
and AC adapter inputs, refer to the MAX1551*.
o Minimal External Components
o 3.3V, 500mA MAIN LDO
o 3.3V, 400mA SD Card Output
o 1V, 250mA Core LDO
o 1.8V, 30mA Second Core LDO
o High-Efficiency LCD Boost
o LCD 0V True Shutdown when Off
o 50µA Quiescent Current
The four linear regulators feature PMOS pass elements
for efficient low-dropout operation. A MAIN LDO sup-
plies 3.3V at 500mA. A signal-detect (SD) card-slot out-
put supplies 3.3V at 400mA. The COR1 LDO outputs 1V
at 250mA, and the COR2 LDO supplies 1.8V at 30mA.
The SD output and COR2 LDO have pin-controlled
shutdown. For other output-voltage combinations, con-
tact Maxim.
o 3.1V to 5.5V Input Range
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX1559ETE
-40°C to +85°C
16 Thin QFN
The DC-DC boost converter features an on-board MOSFET
and True Shutdown™ when off. This means that during
shutdown, input power is disconnected from the induc-
tor so that the boost output falls to 0V rather than
remaining one diode drop below the input voltage.
Typical Operating Circuit
INPUT
3.1V TO 5.5V
A µP reset output clears when the MAIN LDO achieves
regulation to ensure an orderly start. Thermal shutdown
protects the die from overheating.
IN
MAIN
SDIG
COR1
COR2
3.3V, 500mA
3.3V, 400mA
1.0V, 250mA
1.8V, 30mA
SWIN
The MAX1559 operates from a 3.1V to 5.5V supply and
consumes 50mA of no-load supply current. It is pack-
aged in a 1.3W, 16-pin thin QFN with a power pad on
the underside of the package. The MAX1559 is speci-
fied for operation from -40°C to +85°C.
MAX1559
REF
Applications
PDAs
ENSD
ON
ON
SDIG
COR2
LCD
OFF
OFF
Organizers
ENC2
SW
LX
Cellular and Cordless Phones
MP3 Players
ENLCD
ON
OFF
LCD 20V,
1mA
D1
Hand-Held Devices
TO MAIN
LFB
RS
RESET OUT
True Shutdown is a trademark of Maxim Integrated Products, Inc.
GND
*Protected by U.S. Patent #6,507,172.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
5-Output Power-Management IC For
Low-Cost PDAs
ABSOLUTE MAXIMUM RATINGS
IN, SWIN, ENSD, ENC2, ENLCD, RS,
SDIG to GND.........................................................-0.3V to +6V
LX to GND ..............................................................-0.3V to +30V
MAIN, COR1, COR2, REF, LFB to GND ......-0.3V to (V + 0.3V)
SWIN to IN.............................................................-0.3V to +0.3V
Current into LX or SWIN .............................................300mA
Current Out of SW ......................................................300mA
Continuous Power Dissipation (T = +70°C)
16-Pin Thin QFN (derate 16.9mW/°C above +70°C) ...1.349W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
A
IN
RMS
RMS
Output Short-Circuit Duration.....................................Continuous
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = V
= V
= V
= V
= 4.0V, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
IN
SWIN
ENSD
ENC2
ENLCD
A
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL
IN, SWIN Voltage Range
Operating
3.1
5.5
3.05
3.69
125
110
V
V
IN Complete Shutdown Threshold
IN Restart Threshold
V
V
V
falling
rising
2.95
3.51
3
IN
IN
3.6
100
90
V
IN, SWIN Operating Current—All On
= 1.3V
µA
µA
LFB
IN Operating Current—All On Except LCD
ENLCD = GND
ENLCD = ENC2 = ENSD = GND, LDO
loads = 0µA
IN Operating Current—MAIN and COR1 On
50
65
µA
IN, SWIN Operating Current—Shut Down
REF Output Voltage
V
= V = 2.9V
2
10
µA
V
SWIN
IN
I
= 0µA to 5µA
1.235
1.25
1.265
REF
LDOs
I
V
= 100µA to 300mA,
= 3.6V to 5.5V
LOAD
MAIN Output Voltage
3.2175
3.093
3.3
3.3825
3.252
V
IN
RS Deassert Threshold for MAIN Rising
RS Assert Threshold MAIN Falling
MAIN Current Limit
3.173
V
V
3.0100 3.094 3.1755
630
900
1
1200
mA
I
I
I
= 1mA
LOAD
LOAD
LOAD
MAIN Dropout Voltage
(0.7Ω typ)
= 300mA
= 500mA
210
350
310
525
mV
I
V
= 100µA to 200mA,
= 3.6V to 5.5V
LOAD
SDIG Output Voltage
SDIG Current Limit
3.2175
420
3.3
3.3825
825
V
IN
630
0.80
170
340
7
mA
I
I
I
= 1mA
LOAD
LOAD
LOAD
SDIG Dropout Voltage
(0.85Ω typ) (Note 1)
mV
= 200mA
= 400mA
300
600
15
SDIG Reverse Leakage Current
COR1 Output Voltage
V
= 5V, ENSD = V = GND
IN
µA
V
SDIG
I
V
= 100µA to 200mA,
LOAD
0.960
250
1
1.025
750
= 3.6V to 5.5V
IN
COR1 Current Limit
450
mA
2
_______________________________________________________________________________________
5-Output Power-Management IC For
Low-Cost PDAs
ELECTRICAL CHARACTERISTICS (continued)
(V = V
= V
= V
= V
= 4.0V, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
IN
SWIN
ENSD
ENC2
ENLCD
A
A
PARAMETER
CONDITIONS
= 100µA to 20mA,
MIN
1.755
30
TYP
1.8
50
MAX
1.845
100
UNITS
V
I
V
LOAD
COR2 Output Voltage
= 3.6V to 5.5V
IN
COR2 Current Limit
LCD
mA
LX Voltage Range
LX Current Limit
LX On-Resistance
LX Leakage Current
Maximum LX On-Time
28
V
mA
Ω
L1 = 10µH
210
250
1.7
285
V
= 28V
2
µA
µs
LX
8
11
1
14
V
V
> 1.1V
0.8
3.9
1.23
1.2
6.0
1.27
100
1
LFB
LFB
Minimum LX Off-Time
µs
< 0.8V (soft-start)
5
LFB Feedback Threshold
LFB Input Bias Current
SW Off Leakage Current
SW PMOS On-Resistance
SW PMOS Peak Current Limit
SW PMOS Ave Current Limit
Soft-Start Time
1.25
5
V
V
= 1.3V
nA
µA
Ω
LFB
SW = GND, V
= 5.5V, ENLCD = GND
0.01
1
SWIN
1.75
700
300
0.13
mA
mA
ms
C
= 1µF
SW
LOGIC IN AND OUT
EN_ Input Low Level
V
V
= 3.1V to 5.5V
= 3.1V to 5.5V
0.4
V
V
IN
IN
EN_ Input High Level
1.4
EN_ Input Leakage Current
RS, Output Low Level
0.01
0.25
1
0.4
1
µA
V
Sinking 1mA, V = 2.5V
IN
RS, Output High Leakage
THERMAL PROTECTION
V
= 5.5V
µA
OUT
Thermal-Shutdown Temperature
Rising temperature
+160
°C
_______________________________________________________________________________________
3
5-Output Power-Management IC For
Low-Cost PDAs
ELECTRICAL CHARACTERISTICS
(V = V
= V
= V
= V = 4.0V, T = -40°C to +85°C, unless otherwise noted.) (Note 2)
ENLCD A
IN
SWIN
ENSD
ENC2
PARAMETER
CONDITIONS
MIN
MAX
UNITS
GENERAL
IN, SWIN Voltage Range
Operating
3.1
5.5
3.05
3.69
125
110
V
V
IN Complete Shutdown Threshold
IN Restart Threshold
V
V
V
falling
rising
2.95
3.51
IN
IN
V
IN, SWIN Operating Current—All On
= 1.3V
µA
µA
LFB
IN Operating Current—All On Except LCD
ENLCD = GND
ENLCD = ENC2 = ENSD = GND, LDO
loads = 0µA
IN Operating Current—MAIN and COR1 On
65
10
µA
µA
IN, SWIN Operating Current—Shut Down
V
= V = 2.9V
IN
SWIN
LDOs
I
V
= 100µA to 300mA,
= 3.6V to 5.5V
LOAD
MAIN Output Voltage
3.2175
3.3825
V
IN
RS Deassert Threshold for MAIN Rising
RS Assert Threshold MAIN Falling
MAIN Current Limit
3.093
3.0100
630
3.252
3.1755
1200
310
V
V
mA
I
I
I
= 300mA
= 500mA
LOAD
LOAD
MAIN Dropout Voltage
(0.7Ω typ) (Note 1)
mV
525
= 100µA to 200mA,
= 3.6V to 5.5V
LOAD
SDIG Output Voltage
SDIG Current Limit
3.2175
420
3.3825
V
V
IN
825
800
300
600
15
mA
I
I
I
= 1mA
LOAD
LOAD
LOAD
SDIG Dropout Voltage (0.75Ω typ)
= 200mA
= 400mA
mV
SDIG Reverse Leakage Current
COR1 Output Voltage
COR1 Current Limit
V
= 5V, ENSD = V = GND
IN
µA
V
SDIG
I
V
= 100µA to 200mA,
= 3.6V to 5.5V
LOAD
0.96
250
1.025
750
IN
mA
V
I
V
= 100µA to 20mA,
= 3.6V to 5.5V
LOAD
COR2 Output Voltage
1.755
30
1.845
100
IN
COR2 Current Limit
LCD
mA
LX Voltage Range
LX Current Limit
LX Leakage Current
Maximum LX On-Time
28
285
2
V
L1 = 10µH
200
mA
µA
µs
V
= 28V
LX
8
14
V
V
> 1.1V
0.8
1.2
6.0
1.270
LFB
LFB
Minimum LX Off-Time
µs
V
< 0.8V (soft-start)
3.9
LFB Feedback Threshold
1.220
4
_______________________________________________________________________________________
5-Output Power-Management IC For
Low-Cost PDAs
ELECTRICAL CHARACTERISTICS (continued)
(V = V
= V
= V
= V = 4.0V, T = -40°C to +85°C, unless otherwise noted.) (Note 2)
ENLCD A
IN
SWIN
ENSD
ENC2
PARAMETER
CONDITIONS
MIN
MAX
100
1
UNITS
nA
LFB Input Bias Current
SW Off-Leakage Current
LOGIC IN AND OUT
V
= 1.3V
LFB
SW = GND, V
= 5.5V, ENLCD = GND
µA
SWIN
EN_ Input Low Level
V
V
= 3.1V to 5.5V
= 3.1V to 5.5V
0.4
V
V
IN
IN
EN_ Input High Level
EN_ Input Leakage Current
RS, Output Low Level
RS, Output High Leakage
1.4
1
0.4
1
µA
V
Sinking 1mA, V = 2.5V
IN
V
= 5.5V
µA
OUT
Note 1: Specification is guaranteed by design, not production tested.
Note 2: Specifications to -40°C are guaranteed by design, not production tested.
Typical Operating Characteristics
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
MAIN DROPOUT VOLTAGE
vs. LOAD CURRENT
SDIG DROPOUT VOLTAGE
vs. LOAD CURRENT
MAIN OUTPUT VOLTAGE
vs. LOAD CURRENT
500
400
300
200
100
0
300
250
200
150
100
50
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
0
0
100
200
300
(mA)
400
500
600
0
50
100
150
(mA)
200
250
300
0
100 200 300 400 500 600 700 800 900
I
I
I
(mA)
LOAD
LOAD
LOAD
_______________________________________________________________________________________
5
5-Output Power-Management IC For
Low-Cost PDAs
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
SDIG OUTPUT VOLTAGE
vs. LOAD CURRENT
COR1 OUTPUT VOLTAGE
vs. LOAD CURRENT
COR2 OUTPUT VOLTAGE
vs. LOAD CURRENT
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.2
1.0
0.8
0.6
0.4
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0
100
200 300 400 500 600
(mA)
0
100
200
300
400
0
10
20
30
40
50
I
I
(mA)
I (mA)
LOAD
LOAD
LOAD
LOAD STEP RESPONSE (MAIN)
LOAD STEP RESPONSE (COR1)
MAX1559 toc08
MAX1559 toc07
V
V
COR1
AC-COUPLED
20mV/div
MAIN
AC-COUPLED
50mV/div
0V
0V
I
I
LOAD
100mA/div
LOAD
100mA/div
0A
0A
40µs/div
40µs/div
INPUT CURRENT
vs. INPUT VOLTAGE
LCD SWITCH WAVEFORM
MAX1559 toc10
125
100
75
50
25
0
V
RISING
V
IN
IN
V
FALLING
IN
AC-COUPLED
20mV/div
0V
L
X
0V
0V
10V/div
LCD
AC-COUPLED
20mV/div
0
1
2
3
4
5
2µs/div
V
(V)
IN
6
_______________________________________________________________________________________
5-Output Power-Management IC For
Low-Cost PDAs
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
LCD EFFICIENCY vs. LOAD CURRENT
ENABLE RESPONSE TO ENSD
ENABLE RESPONSE TO LCD
MAX1559 toc12
MAX1559 toc11
85
80
75
70
65
60
R = 30Ω
L
C = 47µF
L
ENSD
5V/div
ENSD
V
= 18V
V
= 15V
LCD
LCD
0V
0V
0V
0V
2V/div
LCD
2V/div
LCD BOOST
SOFT-START
SW
TURN-ON
SDIG
1V/div
0
1
2
3
4
5
200µs/div
400µs/div
I
(mA)
LOAD
LCD OUTPUT VOLTAGE
vs. LOAD CURRENT
POWER-ON TIMING FOR 3.3V
MAIN AND RESET SIGNAL
LCD OUTPUT VOLTAGE
vs. INPUT VOLTAGE
MAX1559 toc16
19.00
18.75
18.50
18.25
18.00
17.75
17.50
17.25
17.00
19.00
18.75
18.50
18.25
18.00
17.75
17.50
17.25
17.00
V
IN
4V
1V/div
MAIN
1V/div
2.6V
3.3V MAIN ACTIVATED WHEN
RISES TO 3.6V
V
IN
0V
0V
COR1
1V/div
RS
1V/div
RS EXTERNAL RC
SET FOR 10ms DELAY
FROM 1V GOOD
0V
10ms/div
0
1
2
3
4
5
3.5
4.0
4.5
(V)
5.0
5.5
I
(mA)
V
IN
IN
POWER-ON TIMING FOR 3.3V
MAIN AND 1V CORE
POWER-OFF TIMING FOR 3.3V
MAIN, 1V CORE, AND RESET SIGNAL
MAX1559 toc17
MAX1559 toc18
V
IN
1V/div
4V
3.6V
MAIN
1V/div
3.3V
V
IN
COR1
1V/div
DEACTIVATED
AND RS LOW
WHEN MAIN
FALLS TO 3V
3.3V MAIN DEACTIVATED
COR1 NOT ACTIVATED
UNTIL 3.3V IN
WHEN V FALLS TO 3V
IN
REGULATION
0V
1V
MAIN
1V/div
COR1
1V/div
COR1
1V/div
2.4V
0V
0V
RS
1V/div
RS
1V/div
200µs/div
4ms/div
_______________________________________________________________________________________
7
5-Output Power-Management IC For
Low-Cost PDAs
Pin Description
PIN
FUNCTION
1
2
COR1
IN
1V, 250mA LDO Output for CPU Core. COR1 turns off when V < 3V or MAIN < 3.1V.
IN
Input Voltage to the Device. Bypass to GND with a 1µF capacitor.
3.3V, 400mA LDO Output for Secure Digital Card Slot. SDIG has reverse current protection so SDIG
3
SDIG
can be biased when no power is present at IN. SDIG output turns off when V < 3V or when ENSD
IN
goes low.
SDIG Enable Input. Drive ENSD low to turn off SDIG and high to turn on. SDIG cannot be activated
when V < 3V.
IN
4
5
6
ENSD
REF
RS
1.25V Reference. Bypass with 0.1µF to GND.
Reset Output. RS is an active-low, open-drain output that goes low when V
falls below 3.1V. RS
MAIN
deasserts when V
Not Connected
Ground
goes above 3.2V. Connect a 1MΩ pullup resistor from RS to MAIN.
MAIN
7
8
9
N.C.
GND
LX
LCD Boost Switch. Connect to a boost inductor and Schottky diode. See Figure 1.
LCD True Shutdown Switch Output. SW is the power source for the boost inductor. SW turns on when
ENLCD is high. For best efficiency, bypass SW with 4.7µF to GND.
10
11
12
13
14
SW
SWIN
LFB
LCD True Shutdown Switch Input. The SWIN-to-SW switch turns off when ENLCD goes low or when
V
< 3V. Connect SWIN to IN.
IN
LCD Feedback Input. Connect LFB to a resistor-divider network between the LCD output and GND.
The feedback threshold is 1.25V.
Enable Input for LCD (Boost Regulator). Drive ENLCD high to activate the LCD boost. Drive ENLCD
low to shut down the LCD output. The LCD cannot be activated when V < 3V.
IN
ENLCD
ENC2
Enable Input for Secondary Core LDO (COR2). Drive ENC2 high to turn on COR2 and low to turn off.
COR2 cannot be activated when V < 3V.
IN
15
16
COR2
MAIN
1.8V, 30mA LDO Output for Secondary Core. COR2 turns off when V < 3V or when ENC2 goes low.
IN
3.3V, 500mA LDO Output for Main Supply. MAIN output turns off when V < 3V.
IN
• COR1—1V for CPU core guarantees 250mA and a
Detailed Description
typical current limit of 450mA.
Linear Regulators
• COR2—1.8V for CODEC core guarantees 30mA and
The MAX1559 contains all power blocks and voltage
monitors for a small PDA. Power for logic and other
subsystems are provided by four LDOs:
a typical current limit of 50mA.
Note that it may not be possible to draw the rated cur-
rent of MAIN and SDIG at all operating input voltages
due to the dropout limitations of those regulators. The
typical dropout resistance of the MAIN regulator is 0.7Ω
(350mV drop at 500mA), and the typical dropout resis-
tance of the SDIG regulator is 0.85Ω (340mV drop at
400mA).
• MAIN—Provides 3.3V at a guaranteed 500mA with a
typical current limit of 900mA.
• SDIG—Provides 3.3V at a guaranteed 400mA for
secure digital cards with a typical current limit
of 630mA.
8
_______________________________________________________________________________________
5-Output Power-Management IC For
Low-Cost PDAs
MAIN and COR1 regulators are always on as long as
ESR and are commonly available in values up to 10µF.
X7R and X5R dielectrics are recommended. Note that
some ceramic dielectrics, such as Z5U and Y5V, exhib-
it large capacitance and ESR variation with temperature
and require larger than the recommended values to
maintain stability over temperature.
the IC is not in low-voltage shutdown (V < 3V). COR2
IN
and SDIG can be turned on and off independently by
logic signals at ENC2 and ENSD, respectively, but can-
not be activated if V < 3V.
IN
When SDIG is turned off, reverse current is blocked so
the SDIG output can be biased with an external source
when no power is present at IN. Leakage current is typ-
ically 3µA with 3.3V at SDIG.
LCD Boost Output
Selecting an Inductor
The LCD boost is designed to operate with a wide range
of inductor values (4.7µH to 22µH). Smaller inductance
values typically offer smaller size for a given series
resistance or saturation current. Smaller values make LX
switch more frequently for a given load and can reduce
efficiency at low load currents. Larger values reduce
switching losses due to less frequent switching for a
given load, but higher resistance can then reduce effi-
ciency. A 10µH inductor provides a good balance and
works well for most applications. The inductor’s satura-
tion current rating should be greater than the peak
switching current (250mA); however, it is generally
acceptable to bias some inductors into saturation by as
much as 20%, although this slightly reduces efficiency.
LCD DC-DC Boost
In addition to the LDOs, the MAX1559 also includes a
low-current, high-voltage DC-DC boost converter for
LCD bias. This circuit can output at up to 28V and can
be adjusted with either an analog or PWM control sig-
nal using external components.
SW provides an input-power disconnect for the LCD
when ENLCD is low (off). The input-power disconnect
function is ideal for applications that require the output
voltage to fall to 0V in shutdown (True Shutdown). If True
Shutdown is not required, the SW switch can be
bypassed by connecting the boost inductor directly to IN
and removing the bypass cap on SW (C9 in Figure 1).
Selecting a Diode
Schottky diodes rated at 250mA or more, such as the
Motorola MBRS0530 or Nihon EP05Q03L are recom-
mended. The diode reverse-breakdown voltage rating
must be greater than the LCD output voltage.
System Sleep
All regulated outputs turn off when V falls below 3V.
IN
The MAX1559 resumes normal operation when V
rises above 3.6V.
IN
Reset Output
falls below 3.094V. RS
Selecting Capacitors
For most applications, use a small 1µF LCD output
capacitor. This typically provides a peak-to-peak output
ripple of 30mV. In addition, bypass IN with 1µF and SW
with 4.7µF ceramic capacitors.
Reset (RS) asserts when V
MAIN
is an open-drain, active-low output. Connect a 1MΩ
resistor from RS to MAIN. To implement a reset
deassertion delay, add a capacitor from RS to GND. An
approximate 10ms delay can be generated with 1MΩ
and 22nF. This results in a 22ms time constant, but
assumes the input threshold of the CPU reset input is
approximately 1V and is reached approximately 10ms
after RS goes high impedance. Timing for RS, 3.3V
MAIN, and 1V COR1 is shown in Figure 3.
An LCD feed-forward capacitor, connected from the
output to FB, improves stability over a wide range of
battery voltages. A 10pF capacitor is sufficient for most
applications; however, this value is also affected by PC
board layout.
Applications Information
LDO Output Capacitors (MAIN, SDIG,
COR1, and COR2)
Setting the LCD Voltage
Adjust the output voltage by connecting a voltage-
divider from the output (V
) to FB (Figure 1). Select
OUT
R2 between 10kΩ and 200kΩ. Calculate R1 with the fol-
Capacitors are required at each output of the MAX1559
for stable operation over the full load and temperature
range. See Figure 1 for recommended capacitor values
for each output. To reduce noise and improve load
transients, large output capacitors at up to 10µF can be
used. Surface-mount ceramic capacitors have very low
lowing equation:
R = R [(V / V ) - 1]
OUT FB
1
2
where V
= 1.25V and V
can range from V to
FB
OUT
IN
28V. The input bias current of FB is typically only 5nA,
which allows large-value resistors to be used. For less
_______________________________________________________________________________________
9
5-Output Power-Management IC For
Low-Cost PDAs
AC ADAPTER
INPUT
MAX1559
MAX1551
3.5V TO 7V
DC
BATT
MAIN
SD
IN
3.3V, 500mA
MAIN POWER
C1
1µF
C2
4.7µF
1µF
1µF
SWIN
3.3V, 400mA
SD CARD SLOT
C3
4.7µF
USB INPUT
3.5V TO 6.0V
TO MAIN
USB
COR1
COR2
1V, 250mA
1µF
CPU CORE 1
C4
POWER
4.7µF
PRESENT
(EITHER DC
OR USB)
PG
POK LOW WHEN
EITHER USB OR DC
IS ABOVE UV AND
ABOVE BATT
1.8V, 30mA
CORE 2
C5
1µF
LCD OFF
SWITCH
SW
LX
ENSD
GND
C6
4.7µF
L1
ON
ENC2
10µH
OFF
MURATA
LQH3C
ENLCD
LCD
15V
TO MAIN
R1
1.5MΩ
C8
47pF
C7
LCD
BOOST
R3
1MΩ
1µF
LFB
RESET OUT
REF
RS
R2
100kΩ
C9
22nF
GND
REF
C10
0.1µF
CONNECTION FOR
PWM-CONTROLLED
LCD BIAS
Figure 1. Typical Operating Circuit with Charger and External PWM LCD Control
than 1% error, the current through R2 should be greater
than 100 times the feedback input bias current (I ).
FB
voltage (V
) can be calculated using the following
DOUT
formula:
LCD Adjustment
The LCD boost output can be digitally adjusted by
either a DAC or PWM signal.
1
R
R
(V
− V
)R
REF
DOUT 1
V
= V
1+
+
OUT
REF
R
2
D
DAC Adjustment
Using a PWM Signal
Adding a DAC and a resistor, R to the divider-circuit
D,
Many microprocessors have the ability to create PWM
outputs. These are digital outputs, based on either 16-bit
or 8-bit counters, with a programmable duty cycle. In
many applications, they are suitable for adjusting the
output of the MAX1559 as seen in Figure 1.
(Figure 4) provides DAC adjustment of V
. Ensure
OUT
that V
does not exceed the LCD panel rating.
OUT(MAX)
The output voltage (V
) as a function of the DAC
OUT
10 ______________________________________________________________________________________
5-Output Power-Management IC For
Low-Cost PDAs
MAX1559
3.3V, 500mA
MAIN
RS
IN
LDO
CONTROL
SWIN
RESET
OUTPUT
REF
LDO
COR1
SDIG
1V, 250mA
CONTROL
LDO
CONTROL
3.3V, 400mA
ENSD
ENC2
COR2
SW
LDO
CONTROL
ON
1.8V, 30mA
OFF
ENLCD
LCD OFF
SWITCH
LX
LCD
20V
1mA
LCD
BOOST
LFB
BIAS
CURRENT
REF
REF
GND
THSD
Figure 2. Functional Diagram
The circuit consists of the PWM source, capacitor C10,
and resistors R and R . To analyze the transfer func-
tion of the PWM circuit, it is easiest to first simplify it to
its Thevenin equivalent. The Thevenin voltage can be
calculated using the following formula:
where D is the duty cycle of the PWM signal, V
is the
OH
OL
PWM output high level (often 3.3V), and V
is the
D
W
PWM output low level (usually 0V). For CMOS logic, this
equation simplifies to:
V
THEV
= D ✕ V
DD
V
THEV
= (D ✕ V ) + (1 - D) ✕ V
OH OL
______________________________________________________________________________________ 11
5-Output Power-Management IC For
Low-Cost PDAs
where V
is the I/O voltage of the PWM output. The
DD
Thevenin impedance is the sum of resistors R and R :
W
D
R
= R + R
D W
THEV
3.3V ACTIVATED
3.3V DEACTIVATED
V
IN
WHEN V RISES
WHEN V FALLS
IN
IN
The output voltage (V
) as a function of the PWM
OUT
TO 3.6V
TO 3.0V
average voltage (V
) is:
THEV
3.3V
COR1 NOT ACTIVATED
R
(V
− V
)×R
1
REF
THEV 1
MAIN
UNTIL 3.3V IN REGULATION
V
= V
× 1+
+
OUT
REF
R
R
2
THEV
COR1 DEACTIVATED AND
RS LOW WHEN MAIN
FALLS TO 3V
1V
COR1
When using the PWM adjustment method, R isolates
D
the capacitor from the feedback loop of the MAX1559.
The cutoff frequency of the lowpass filter is defined as:
RS
OUTPUT
1
f =
RS EXTERNAL RC SET FOR
10ms DELAY FROM 1V GOOD
C
2× π ×R
THEV
The cutoff frequency should be at least 2 decades
below the PWM frequency to minimize the induced AC
ripple at the output.
Figure 3. RS and Power-On, Power-Off Timing for 3.3V and 1V
Core
An important consideration is the turn-on transient cre-
ated by the initial charge on the filter capacitor C10.
Thermal Considerations
In most applications, the circuit is located on a multilay-
er board and full use of the four or more layers is rec-
ommended. For heat dissipation, connect the exposed
backside pad of the QFN package to a large analog
ground plane, preferably on a surface of the board that
receives good airflow. Typical applications use multiple
ground planes to minimize thermal resistance. Avoid
large AC currents through the analog ground plane.
This capacitor forms a time constant with R
, which
THEV
causes the output to initialize at a higher than intended
voltage. This overshoot can be minimized by scaling
R
as high as possible compared to R1 and R2.
D
Alternately, the µP can briefly keep the LCD disabled
until the PWM voltage has had time to stabilize.
PC Board Layout and Grounding
Careful PC board layout is important for minimizing
ground bounce and noise. Keep the MAX1559’s
ground pin and the ground leads of the input and out-
put capacitors less than 0.2in (5mm) apart. In addition,
keep all connections to FB and LX as short as possible.
In particular, external feedback resistors should be as
close to FB as possible. To minimize output voltage rip-
ple and to maximize output power and efficiency, use a
ground plane and solder GND directly to the ground
plane. Refer to the MAX1559 evaluation kit for a layout
example.
12 ______________________________________________________________________________________
5-Output Power-Management IC For
Low-Cost PDAs
V
IN
FEEDBACK
RESISTORS
SIMPLIFIED DC-DC CONVERTER
R1
AV
DD
i
i
1
2
R
D
ERROR AMP
CONTROL
V
DOUT
DAC
V
OUT
(LCD BIAS)
V
REF
i
D
1.25V
R2
MAX1559
Figure 4. Adjusting the Output Voltage with a DAC
Chip Information
Pin Configuration
PROCESS: BiCMOS
TOP VIEW
TRANSISTOR COUNT: 1872
16
15
14
13
COR1
IN
LFB
SWIN
SW
1
2
3
4
12
11
10
9
MAX1559
SDIG
ENSD
LX
5
6
7
8
THIN QFN
______________________________________________________________________________________ 13
5-Output Power-Management IC For
Low-Cost PDAs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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