MAX1549ETL [MAXIM]
Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output; 双通道，交叉工作，固定频率降压型控制器，提供动态可调节输出
| 型号： | MAX1549ETL |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output |
| 文件： | 总35页 (文件大小：505K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3165; Rev 0; 1/04
Du a l, In t e rle a ve d , Fix e d -Fre q u e n c y S t e p -Do w n
Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX1549 dual pulse-width modulation (PWM) step-
down controller provides the high efficiency, excellent
transient response, and high DC-output accuracy nec-
essary for generating low-voltage chipset and RAM
power supplies in notebook computers. The controller
employs a fixed-frequency, current-mode PWM archi-
tecture that does not require complex compensation.
The MAX1549 also interleaves the dual step-down regu-
lators, minimizing the input capacitor requirements.
♦ Interleaved, Fixed-Frequency, Current-Mode
Control Architecture
♦ 1% V
Accuracy Over Line and Load
OUT
♦ Main Output (OUT1)
0.5V to 2.0V Adjustable Output
External Reference Input for Dynamically
Selectable Output Voltages
Four Digitally Selectable Output Voltages
Power-Good and Fault Blanking During
Transitions
The MAX1549 features differential current-sense inputs
for accurately sensing the inductor current across an
external current-sense resistor in series with the output
to ensure reliable overload protection. Alternatively, the
controller can provide overload protection using loss-
less inductor current-sensing methods, lowering power
dissipation and reducing system cost.
♦ Second Output (OUT2)
2.5V/1.8V Fixed or 0.5V to 2.7V Adjustable
Output
♦ Accurate Differential Current-Sense Inputs
Single-stage buck conversion allows the MAX1549 to
directly step down high-voltage batteries for the highest
possible efficiency. Very low output-voltage applica-
tions require two-stage conversion—stepping down
from another system supply rail instead of the battery.
♦ 100kHz/200kHz/300kHz/400kHz Selectable
Switching Frequency
♦ Output Overvoltage/Undervoltage Protection
♦ Soft-Start and Soft-Shutdown
The MAX1549 powers chipsets and graphics processor
cores that require dynamically adjustable output voltages,
or generates the active termination bus that must track
the input re fe re nc e . The ma in ste p-down c ontrolle r
(OUT1) regulates the dedicated reference input (REFIN)
voltage generated by a resistive voltage-divider from the
MAX1549’s reference. The MAX1549 also includes inter-
nal open-drain pulldowns with logic-level control inputs to
dynamically adjust the REFIN resistive-divider ratio. When
a transition occurs on these control inputs, the controller
enters forced-PWM mode and blanks the power-good
(PGOOD1) output and output fault protection. OUT2 uses
a Dual-Mode™ feedback input to provide either fixed
2.5V/1.8V or adjustable output voltage regulation. The
MAX1549 is available in a 40-pin, 6mm x 6mm thin QFN
package.
♦ Drives Large Synchronous-Rectifier FETs
♦ 2V ±0.6% Reference Output
♦ Separate Enable Inputs with Accurate Threshold
Voltages
♦ Separate Power-Good Window Comparators
Ord e rin g In fo rm a t io n
PART
TEMP RANGE PIN-PACKAGE
MAX1549ETL
-40°C to +85°C 40 Thin QFN 6mm x 6mm
P in Co n fig u ra t io n
Ap p lic a t io n s
Notebook Computers
TOP VIEW
40 39 38 37 36 35 34 33 32 31
Dynamically Adjustable Chipset Supplies
Video/GPU Core Supplies
GND
N.C.
REF
1
2
30 LX1
29 BST1
28 SKIP
27 DL1
3
V
CC
4
DDR Memory Termination
CC1
ILIM1
ILIM2
G0
5
26
V
DD
MAX1549
6
25 N.C.
24 DL2
23 PGND
22 BST2
21 LX2
CPU Core or V Supplies
CC
7
8
Fixed Chipset/RAM Supplies
Active Termination Buses
9
G1
10
FBLANK
11 12 13 14 15 16 17 18 19 20
THIN QFN
6mm x 6mm
Dual Mode is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Du a l, In t e rle a ve d , Fix e d -Fre q u e n c y S t e p -Do w n
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ABSOLUTE MAXIMUM RATINGS
V
V
DD
to GND..............................................................-0.3V to +6V
to PGND............................................................-0.3V to +6V
LX2 to BST2..............................................................-6V to +0.3V
DH2 to LX2 ..............................................-0.3V to (V + 0.3V)
CC
BST2
CSH_, CSL_, OUT_, PGOOD_,
OD_ to GND ...........................................-0.3V to (V + 0.3V)
GND to PGND .......................................................-0.3V to +0.3V
REF Short Circuit to GND...........................................Continuous
CC
G0, G1, ILIM_, REFIN to GND..................................-0.3V to +6V
FB2, SKIP, ON_ to GND ...........................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
40-Pin 6mm x 6mm Thin QFN (derated 26.3mW/°C
REF, CC1, FBLANK, FSEL to GND.............-0.3V to (V + 0.3V)
above +70°C).............................................................2105mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
DL1, DL2 to PGND .....................................-0.3V to (V + 0.3V)
DD
BST1, BST2 to PGND .............................................-0.3V to +36V
LX1 to BST1..............................................................-6V to +0.3V
DH1 to LX1 ..............................................-0.3V to (V
+ 0.3V)
BST1
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V = V = 5V, SKIP = GND, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
CC
DD
A
A
PARAMETER
INPUT SUPPLIES (Note 1)
Input Voltage Range
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
BIAS
V
, V
4.5
5.5
1.8
V
CC DD
OUT1 and FB2 forced above their
regulation points
Quiescent Supply Current (V
)
)
I
CC
1.0
1.5
mA
CC
OUT1 and FB2 forced above their
regulation points
Quiescent Supply Current (V
I
DD
5
µA
DD
Shutdown Supply Current (V
)
ON1 = ON2 = GND, SKIP = V
2.5
<1
5
5
µA
µA
CC
CC
Shutdown Supply Current (V
)
ON1 = ON2 = GND
DD
PWM CONTROLLERS
50% duty cycle
-5
0
+5
With respect to
REFIN, SKIP =
Main Output-Voltage Accuracy
(OUT1 Tracking)
V
V
-
REFIN
mV
OUT1
V
CC
or GND
10% to 90% duty cycle
FB2 = GND
-10
+10
2.475
1.780
0.490
0.485
2.5
1.8
2.525
1.820
0.510
0.515
Secondary Preset Output-Voltage
Accuracy (OUT2 Fixed)
SKIP = V , 50%
CC
V
V
V
OUT2
duty cycle (Note 1)
FB2 = V
CC
50% duty cycle
0.50
Secondary Feedback-Voltage
Accuracy (FB2 Adjustable)
SKIP = V
CC
(Note 1)
V
FB2
10% to 90% duty cycle
Load-Regulation Error
I
= 0 to 3A, SKIP = V
0.1
1
%
%
LOAD
CC
V
Line-Regulation Error
V
= 2V to 28V
IN
IN
OUT1 (tracks REFIN)
OUT2
0.5
0.5
-1
2.0
2.7
Output Adjust Range
V
OUT1 Input Bias Current
FB2 Input Bias Current
I
V
= 0.5V to 2.0V
= 0 to 2.7V
FB2
+1
µA
µA
OUT1
OUT1
I
V
-0.1
120
85
+0.1
460
335
FB2
FB2 = GND or adjustable
FB2 = V
250
180
OUT2 Input Resistance
R
kΩ
OUT2
CC
2
_______________________________________________________________________________________
Du a l, In t e rle a ve d , Fix e d -Fre q u e n c y S t e p -Do w n
Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = V = 5V, SKIP = GND, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
CC
DD
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUT_ Discharge-Mode
On-Resistance
R
12
40
Ω
DISCHARGE
OUT_ Synchronous-Rectifier
Discharge-Mode Turn-On Level
0.2
0.3
0.4
V
FSEL = GND
70
100
200
300
400
130
230
330
450
200
FSEL = REF
FSEL = open
170
270
350
Operating Frequency
f
(Note 2)
(Note 3)
kHz
OSC
FSEL = V
CC
Minimum On-Time
t
ns
%
ON(MIN)
Maximum Duty Cycle
D
91
93
MAX
Measured from the rising edge of ON_ to
full scale
512 /
Soft-Start Ramp Time
REFERENCE (REF)
Reference Voltage
t
s
SS
f
OSC
T
A
= +25°C
1.988
1.985
1.980
2.00
2.00
2.012
2.015
2.020
V
CC
= 4.5V to
V
REF
V
5.5V, I
= 0
REF
T
A
= 0°C to +85°C
Reference Load Regulation
REF Lockout Voltage
∆V
I
= -10µA to +100µA
V
V
REF
REF
V
Rising edge, hysteresis = 350mV
1.95
REF(UVLO)
REFIN Voltage Range
REFIN Input Bias Current
FAULT DETECTION
V
0.5
-50
2.0
V
REFIN
I
+50
nA
REFIN
Output Overvoltage
Trip Threshold
With respect to error-comparator threshold
12
65
14.5
10
17
75
%
µs
%
s
Output Overvoltage
Fault-Propagation Delay
OUT1 and FB2 forced 2% above trip
threshold
t
OVP
Output Undervoltage-Protection
Trip Threshold
With respect to error-comparator threshold
From rising edge of ON_
70
Output Undervoltage-Protection
Blanking Time
4096 /
t
BLANK
f
OSC
Output Undervoltage
Fault-Propagation Delay
t
10
-10
+10
10
µs
%
%
UVP
With respect to error-comparator threshold,
hysteresis = 1%
PGOOD_ Lower Trip Threshold
PGOOD_ Upper Trip Threshold
-12.5
+7.5
-7.5
With respect to error-comparator threshold,
hysteresis = 1%
+12.5
OUT1 and FB2 forced 2% beyond PGOOD_
trip threshold
PGOOD_ Propagation Delay
PGOOD_ Output Low Voltage
PGOOD_ Leakage Current
t
_
_
µs
V
PGOOD
I
= 4mA
0.3
1
SINK
OUT1 = REFIN and V
= 0.5V (PGOOD_
FB2
I
µA
PGOOD
high impedance), PGOOD_ forced to 5.5V
_______________________________________________________________________________________
3
Du a l, In t e rle a ve d , Fix e d -Fre q u e n c y S t e p -Do w n
Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = V = 5V, SKIP = GND, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
CC
DD
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
110
60
TYP
150
100
50
MAX
190
140
75
UNITS
FBLANK = V
CC
Fault-Blanking Time
t
µs
FBLANK = open
FBLANK = REF
Hysteresis = 15°C
FBLANK
22
Thermal-Shutdown Threshold
Undervoltage-Lockout
T
SHDN
+165
°C
V
V
Rising edge, PWM disabled below this
level, hysteresis = 50mV
CC
V
4.1
4.25
4.4
CC(UVLO)
Threshold
CURRENT LIMIT
ILIM_ Adjustment Range
Current-Limit Input Range
CSH_/CSL_ Input Bias Current
Current-Limit Threshold (Fixed)
0.25
0
V
V
V
REF
V
_, V
_
2.7
+0.15
75
CSH
CSL
V
CSH
_ = V
_ = 0 to 2.7V
-0.15
65
µA
mV
CSL
V
V
CSH
_ - V
_, ILIM_ = V
CC
70
200
100
50
LIMIT
CSL
V
ILIM
_ = 2.0V
_ = 1.0V
_ = 0.5V
170
91
230
109
58
Current-Limit Threshold
(Adjustable)
V
LIMIT
V
CSH
_ - V _
CSL
mV
V
ILIM
V
ILIM
42
Current-Limit Threshold
(Zero Crossing)
V
ZX
V
PGND
- V _, SKIP = GND
3
mV
mV
LX
ILIM_ = V
10
15
20
CC
With respect to
current-limit
threshold
Idle-Mode™ Threshold
V
CSH
_ - V
_
CSL
20
%
ILIM_ Leakage Current
GATE DRIVERS
-0.1
+0.1
µA
DH_ Gate-Driver On-Resistance
R
BST_ - LX_ forced to 5V
DL_, high state
1.5
1.5
0.5
6
6
Ω
Ω
DH
DL_ Gate-Driver On-Resistance
R
DL
DL_, low state
2.7
DH_ Gate-Driver Source/Sink
Current
I
DH
DH_ forced to 2.5V, BST_ - LX_ forced to 5V
1
A
DL_ Gate-Driver Source Current
DL_ Gate-Driver Sink Current
I
DL_ forced to 2.5V
DL_ forced to 2.5V
DL_ rising
1
3
A
A
DL (SOURCE)
I
DL (SINK)
35
26
Dead Time
t
ns
DEAD
DH_ rising
INPUTS AND OUTPUTS
OD_ On-Resistance
R
_
10
100
100
2.8
Ω
nA
V
OD
OD_ Leakage Current
ON_ Logic Input Threshold
I
OD
_
OD_ high impedance, V _ = 5.5V
OD
Rising edge, hysteresis = 600mV
2.4
2.4
2.6
High
Low
SKIP, G0, G1 hysteresis =
600mV
Logic Input Voltage
V
0.8
Idle Mode is a trademark of Maxim Integrated Products, Inc.
4
_______________________________________________________________________________________
Du a l, In t e rle a ve d , Fix e d -Fre q u e n c y S t e p -Do w n
Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = V = 5V, SKIP = GND, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
CC
DD
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
-1
TYP
MAX
+1
UNITS
Logic Input Current
ON_, SKIP, G0, G1
µA
High
Low
1.9
2.0
0.1
2.1
Dual-Mode Threshold Voltage
FB2
V
0.05
0.15
V
0.4V
-
CC
High
Open
REF
3.15
1.65
3.85
2.35
0.5
Four-Level Input Logic Levels
Four-Level Logic Input Current
FSEL, FBLANK
V
Low
FSEL, FBLANK forced to GND or V
-3
+3
µA
CC
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V = V = 5V, SKIP = GND, T = -40°C to +85°C, unless otherwise noted.) (Note 4)
CC
DD
A
PARAMETER
INPUT SUPPLIES (Note 1)
Input Voltage Range
SYMBOL
CONDITIONS
MIN
MAX
UNITS
V
BIAS
V
V
4.5
5.5
1.8
V
CC, DD
OUT1 and FB2 forced above their
regulation points
Quiescent Supply Current (V
)
)
I
CC
mA
CC
OUT1 and FB2 forced above their
regulation points
Quiescent Supply Current (V
I
DD
5
µA
DD
Shutdown Supply Current (V
)
ON1 = ON2 = GND, SKIP = V
5
5
µA
µA
CC
CC
Shutdown Supply Current (V
)
ON1 = ON2 = GND
DD
PWM CONTROLLERS
With respect to
REFIN, SKIP = V
or GND
50% duty cycle
-8
+8
Main Output-Voltage Accuracy
(OUT1 Tracking)
V
V
-
REFIN
mV
CC
OUT1
10% to 90% duty cycle
FB2 = GND
-10
+10
2.470
1.775
0.490
2.530
1.825
0.510
0.515
2.0
Secondary Preset Output-Voltage
Accuracy (OUT2 Fixed)
SKIP = V , 50%
CC
V
V
V
OUT2
duty cycle (Note 1)
FB2 = V
CC
50% duty cycle
Secondary Feedback-Voltage
Accuracy (FB2 Adjustable)
SKIP = V
CC
(Note 1)
V
FB2
10% to 90% duty cycle 0.485
OUT1 (tracks REFIN)
OUT2
0.5
0.5
Output Adjust Range
V
2.7
FB2 = GND or adjustable
FB2 = V
120
85
460
OUT2 Input Resistance
R
kΩ
Ω
OUT2
335
CC
OUT_ Discharge-Mode
On-Resistance
R
40
DISCHARGE
OUT_ Synchronous-Rectifier
Discharge-Mode Turn-On Level
0.2
0.4
V
_______________________________________________________________________________________
5
Du a l, In t e rle a ve d , Fix e d -Fre q u e n c y S t e p -Do w n
Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = V = 5V, SKIP = GND, T = -40°C to +85°C, unless otherwise noted.) (Note 4)
CC
DD
A
PARAMETER
SYMBOL
CONDITIONS
FSEL = GND
MIN
70
MAX
130
230
330
450
UNITS
kHz
FSEL = REF
FSEL = open
170
270
350
91
Operating Frequency
f
(Note 2)
OSC
FSEL = V
CC
Maximum Duty Cycle
REFERENCE (REF)
Reference Voltage
D
%
MAX
V
REF
V
CC
= 4.5V to 5.5V, I = 0
REF
1.985
1.980
0.5
2.015
2.020
2.0
V
V
V
Reference Load Regulation
REFIN Voltage Range
FAULT DETECTION
∆V
I
= -10µA to +100µA
REF
REF
Output Overvoltage
Trip Threshold
With respect to error-comparator threshold
With respect to error-comparator threshold
12
65
17
75
%
%
%
Output Undervoltage-Protection
Trip Threshold
With respect to error-comparator threshold,
hysteresis = 1%
PGOOD_ Lower Trip Threshold
-12.5
+7.5
-7.5
+12.5
With respect to error-comparator threshold,
hysteresis = 1%
PGOOD_ Upper Trip Threshold
PGOOD_ Output Low Voltage
%
V
I
= 4mA
0.3
190
140
75
SINK
FBLANK = V
110
60
CC
Fault-Blanking Time
t
µs
V
FBLANK = open
FBLANK = REF
FBLANK
22
V
CC
Undervoltage-Lockout
Rising edge, PWM disabled below this
level, hysteresis = 50mV
V
4.1
4.4
CC(UVLO)
Threshold
CURRENT LIMIT
ILIM_ Adjustment Range
Current-Limit Input Range
Current-Limit Threshold (Fixed)
0.25
0
V
V
V
REF
V
_, V
_
2.7
75
CSH
CSL
V
LIMIT
V
CSH
_ - V
_, ILIM_ = V
CC
65
mV
CSL
V
_ = 2.0V
_ = 1.0V
_ = 0.5V
170
89
230
111
58
ILIM
Current-Limit Threshold
(Adjustable)
V
LIMIT
V _ - V _
CSH CSL
mV
mV
V
ILIM
V
ILIM
42
Idle-Mode Threshold
V
CSH
_ - V
_, ILIM_ = V
CC
10
20
CSL
GATE DRIVERS
DH_ Gate-Driver On-Resistance
R
BST_ - LX_ forced to 5V
DL_, high state
6
6
Ω
Ω
DH
DL_ Gate-Driver On-Resistance
R
DL
DL_, low state
2.7
6
_______________________________________________________________________________________
Du a l, In t e rle a ve d , Fix e d -Fre q u e n c y S t e p -Do w n
Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = V = 5V, SKIP = GND, T = -40°C to +85°C, unless otherwise noted.) (Note 4)
CC
DD
A
PARAMETER
INPUTS AND OUTPUTS
OD_ On-Resistance
SYMBOL
CONDITIONS
MIN
MAX
UNITS
R
OD
_
100
2.8
Ω
ON_ Logic Input Threshold
Rising edge, hysteresis = 600mV
2.4
2.4
V
High
SKIP, G0, G1, hysteresis =
Logic Input Voltage
V
V
600mV
Low
High
Low
High
Open
REF
Low
0.8
2.1
1.9
Dual-Mode Threshold Voltage
Four-Level Input Logic Levels
FB2
0.05
0.15
V
- 0.4V
CC
3.15
1.65
3.85
2.35
0.5
FSEL, FBLANK
V
Note 1: When the inductor is in continuous conduction, the output voltage has a DC regulation level lower than the error-comparator
threshold by 50% of the ripple. In discontinuous conduction (SKIP = GND, light load), the output voltage has a DC regula-
tion level higher than the trip level by approximately 1.5% due to slope compensation.
Note 2: The MAX1549 cannot operate over all combinations of frequency, input voltage (V ), and output voltage. For large input-to-
IN
output differentials and high switching-frequency settings, the required on-time may be too short to maintain the regulation
specifications. Under these conditions, a lower operating frequency must be selected. The minimum on-time must be
greater than 150ns, regardless of the selected switching frequency. On-time and off-time specifications are measured from
the 50% point to the 50% point at the DH_ pin with LX_ = GND, V
= 5V, and a 250pF capacitor connected from DH_ to
BST_
LX_. Actual in-circuit times may differ due to MOSFET switching speeds.
Note 3: Specifications are guaranteed by design, not production tested.
Note 4: Specifications to -40°C are guaranteed by design, not production tested.
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(MAX1549 circuit of Figure 1, V = 12V, V = V = 5V, SKIP = GND, FSEL = open, T = +25°C, unless otherwise noted.)
IN
DD
CC
A
OUT1 EFFICIENCY vs. LOAD CURRENT
1.0V OUTPUT VOLTAGE (OUT1)
vs. LOAD CURRENT
OUT2 EFFICIENCY vs. LOAD CURRENT
(V = 2.5V)
(V
= 1.0V)
OUT1
OUT2
100
90
80
70
60
50
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
100
90
80
70
60
50
SKIP = GND
SKIP = V
SKIP = GND
SKIP = V
SKIP = GND
SKIP = V
CC
CC
CC
V
= 5V
IN
V
= 5V
IN
V
= 12V
IN
V
IN
= 12V
V
IN
= 20V
V
= 20V
IN
0.01
0.1
1
10
0
1
2
3
4
5
6
7
0.01
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
_______________________________________________________________________________________
7
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Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(MAX1549 circuit of Figure 1, V = 12V, V = V = 5V, SKIP = GND, FSEL = open, T = +25°C, unless otherwise noted.)
IN
DD
CC
A
2.5V OUTPUT VOLTAGE (OUT2)
vs. LOAD CURRENT
1.0V OUTPUT VOLTAGE (OUT1)
vs. INPUT VOLTAGE
IDLE-MODE CURRENT
vs. INPUT VOLTAGE
1.02
1.01
1.00
0.99
0.98
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
SKIP = GND
1.0V OUTPUT
SKIP = GND
SKIP = V
2.59
2.57
2.55
2.53
2.51
2.49
2.47
2.45
SKIP = V
CC
CC
0
1
2
3
4
5
6
7
0
5
10
15
20
0
4
8
12
16
20
LOAD CURRENT (A)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2.5V OUTPUT VOLTAGE (OUT2)
vs. INPUT VOLTAGE
SUPPLY CURRENT vs. INPUT VOLTAGE
(FORCED-PWM OPERATION)
IDLE-MODE CURRENT
vs. INPUT VOLTAGE
2.60
2.57
2.54
2.51
2.48
2.45
2.5
2.0
1.5
1.0
0.5
0
28
24
20
16
12
8
DUTY
CYCLE
LIMITED
SKIP = GND
SKIP = V
CC
I
BIAS
I
IN
4
NO LOAD
SKIP = ON1 = ON2 = V
2.5V OUTPUT
16
CC
0
0
5
10
15
20
0
4
8
12
20
0
4
8
12
16
20
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
SUPPLY CURRENT vs. INPUT VOLTAGE
(PULSE-SKIPPING OPERATION)
2.0V REFERENCE LOAD REGULATION
REFERENCE DISTRIBUTION
4
3
50
40
30
20
10
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
SAMPLE SIZE = 150
I
BIAS
2
I
IN
1
0
-1
-2
-3
-4
1mA LOAD
SKIP = GND
ON1 = ON2 = V
CC
-20
0
20
40
60
80
100
1.990
1.995
2.000
2.005
2.010
0
4
8
12
16
20
REFERENCE LOAD CURRENT (µA)
REFERENCE VOLTAGE (V)
INPUT VOLTAGE (V)
8
_______________________________________________________________________________________
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Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(MAX1549 circuit of Figure 1, V = 12V, V = V = 5V, SKIP = GND, FSEL = open, T = +25°C, unless otherwise noted.)
IN
DD
CC
A
SWITCHING FREQUENCY DISTRIBUTION
(300kHz OPERATION)
STARTUP WAVEFORM
(HEAVY LOAD)
STARTUP WAVEFORM
(LIGHT LOAD)
MAX1549 toc14
MAX1549 toc15
50
40
30
20
10
0
SAMPLE SIZE = 150
5V
5V
0
A
B
A
B
0
2.5V
0
2.5V
0
5A
0
2A
0
C
D
C
D
0
0
290
295
300
305
310
400µs/div
200µs/div
SWITCHING FREQUENCY (kHz)
A: ON2, 5V/div
C: INDUCTOR CURRENT, 5A/div
A: ON2, 5V/div
C: INDUCTOR CURRENT, 2A/div
B: 2.5V OUTPUT, 2V/div D: PGOOD2, 5V/div
B: 2.5V OUTPUT, 2V/div D: PGOOD2, 5V/div
0.5Ω LOAD
100Ω LOAD
SHUTDOWN WAVEFORM
SHUTDOWN WAVEFORM
INTERLEAVED OPERATION
(1Ω LOAD)
(100Ω LOAD)
MAX1549 toc18
MAX1549 toc16
MAX1549 toc17
5V
0
5V
0
A
A
B
12V
A
B
0
2.5V
2.5V
B
1.0V
0
0
5V
5V
C
D
C
D
12V
0
0
C
D
0
0
5V
0
5V
2.5V
E
E
0
0
2µs/div
C: LX2, 10V/div
B: 1.0V OUTPUT, 50mV/div D: 2.5V OUTPUT, 50mV/div
100µs/div
1ms/div
A: LX1, 10V/div
A: ON2, 5V/div
B: OUT2, 2V/div
C: DL2, 5V/div
D: INDUCTOR CURRENT, 5A/div
E: PGOOD2, 5V/div
A: ON2, 5V/div
B: OUT2, 2V/div
C: DL2, 5V/div
D: INDUCTOR CURRENT, 2A/div
E: PGOOD2, 5V/div
_______________________________________________________________________________________
9
Du a l, In t e rle a ve d , Fix e d -Fre q u e n c y S t e p -Do w n
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Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(MAX1549 circuit of Figure 1, V = 12V, V = V = 5V, SKIP = GND, FSEL = open, T = +25°C, unless otherwise noted.)
IN
DD
CC
A
2.5V OUTPUT LOAD TRANSIENT
(FORCED PWM)
2.5V OUTPUT LOAD TRANSIENT
(PULSE SKIPPING)
OUTPUT OVERLOAD
(UVP ENABLED)
MAX1549 toc21
MAX1549 toc19
MAX1549 toc20
5V
4A
0
4A
A
B
A
B
A
B
0
0
2.55V
2.50V
2.45V
10A
2.55V
0
2.5V
2.50V
C
D
0
5A
4A
0
4A
0
C
D
C
D
0
5V
12V
12V
E
0
0
0
40µs/div
= 0 TO 4A, 5A/div C: INDUCTOR CURRENT, 5A/div
20µs/div
= 0.2A TO 4A, 5A/div C: INDUCTOR CURRENT, 5A/div A: PGOOD2, 5V/div
OUT2
40µs/div
A: I
B: V
A: I
D: INDUCTOR CURRENT, 5A/div
B: LOAD (2.5A TO 10A), 10A/div E: DL2, 5V/div
OUT2
= 2.5V, 100mV/div D: LX2, 10V/div
B: V
= 2.5V, 50mV/div D: LX2, 10V/div
OUT2
OUT2
SKIP = V
SKIP = GND
C: 2.5V OUTPUT, 2V/div
CC
MAX1549 DYNAMIC OUTPUT VOLTAGE
MAX1549 DYNAMIC OUTPUT VOLTAGE
TRANSITION (C
= 100pF)
TRANSITION (C
= 1nF)
REFIN
MAX1549 toc23
REFIN
MAX1549 toc22
3.3V
3.3V
A
B
A
B
0
1.5V
0
1.5V
1.0V
1.5V
1.0V
1.5V
C
C
1.0V
12V
1.0V
12V
D
E
D
E
0
5A
0
2.5A
0
-2.5A
0
-5A
40µs/div
D: LX1, 10V/div
100µs/div
D: LX1, 10V/div
E: INDUCTOR CURRENT, 5A/div
A: GATE, 5V/div
B: REFIN1, 0.5V/div
A: GATE, 5V/div
E: INDUCTOR CURRENT, 10A/div B: REFIN1, 0.5V/div
C: OUT1 (1.0V TO 1.5V), 0.5V/div
200mA LOAD, SKIP = GND
C: OUT1 (1.0V TO 1.5V), 0.5V/div
200mA LOAD, SKIP = GND
10 ______________________________________________________________________________________
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P in De s c rip t io n
PIN
NAME
FUNCTION
Analog Ground. Connect backside pad to GND.
1
GND
2, 20,
25, 31
N.C.
REF
Not Internally Connected
2.0V Reference Voltage Output. Bypass to analog ground with a 0.1µF or greater ceramic capacitor. The
reference can source up to 100µA for external loads. Loading REF degrades output voltage accuracy
according to the REF load-regulation error. The reference shuts down when both MAX1549 outputs are
disabled.
3
Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through a series 20Ω
4
5
V
CC
resistor. Bypass V to analog ground with a 1µF or greater ceramic capacitor.
CC
Integrator Capacitor Connection. Connect a 47pF to 1000pF (470pF typ) capacitor from CC1 to analog
ground (GND) to set the integration time constant for the main MAX1549 controller (OUT1).
CC1
Current-Limit Threshold Adjustment for Controller 1. The current-limit threshold defaults to 70mV if ILIM1
is connected to V . In adjustable mode, the current-limit threshold across CSH1 and CSL1 is precisely
CC
1/10th the voltage seen at ILIM1 over a 0.5V to 2.0V range. The logic threshold for switchover to the
6
ILIM1
70mV default value is approximately V - 1V.
CC
Current-Limit Threshold Adjustment for Controller 2. The current-limit threshold defaults to 70mV if ILIM2
is connected to V . In adjustable mode, the current-limit threshold across CSH2 and CSL2 is precisely
CC
1/10th the voltage seen at ILIM2 over a 0.5V to 2.0V range. The logic threshold for switchover to the
7
ILIM2
70mV default value is approximately V - 1V.
CC
8, 9
G0, G1
Buffered N-Channel MOSFET Gate Inputs. See Table 4.
Fault-Blanking Select Input. This four-level logic input enables or disables fault blanking and sets the
minimum forced-PWM operation time (t ). When fault blanking is enabled, the MAX1549 blanks
FBLANK
the PGOOD1 output and main (OUT1) controller’s OVP/UVP fault protection for the selected time period
after the controller detects a transition on G0 or G1. Additionally, the main controller enters forced-PWM
10
FBLANK mode for the duration of t
anytime G0 or G1 changes states.
FBLANK
OUT1 fault protection and PGOOD1 blanking:
= 150µs, open = 100µs, REF = 50µs, GND = blanking disabled
V
CC
Automatic forced-PWM transition operation (OUT1 only):
= 150µs, open = 100µs, REF = 50µs, GND = 100µs
V
CC
Frequency-Select Input. This four-level logic input sets the controller’s switching frequency. Connect to
GND, REF, V , or leave FSEL unconnected (open) to select the following typical switching frequencies:
CC
11
12
FSEL
ON1
V
CC
= 400kHz, open = 300kHz, REF = 200kHz, GND = 100kHz
OUT1 Enable Input. Pull to GND to shut down controller 1 (OUT1). Connect to V for normal operation.
CC
The output is discharged through a 12Ω resistor between OUT1 and GND, and DL1 is forced high after
V
OUT1
drops below 0.3V. A rising edge on ON1 or ON2 clears the fault-protection latch.
OUT2 Enable Input. Pull to GND to shut down controller 2 (OUT2). Connect to V for normal operation.
CC
13
14
ON2
The output is discharged through a 12Ω resistor between OUT2 and GND, and DL2 is forced high after
V
OUT2
drops below 0.3V. A rising edge on ON1 or ON2 clears the fault-protection latch.
Positive Current-Sense Input for Controller 2. Connect to the positive terminal of the current-sense
element. Figure 8 describes current-sensing options. The PWM controller does not begin a cycle unless
the current sensed is less than the current-limit threshold programmed at ILIM2.
CSH2
______________________________________________________________________________________ 11
Du a l, In t e rle a ve d , Fix e d -Fre q u e n c y S t e p -Do w n
Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
P in De s c rip t io n (c o n t in u e d )
PIN
NAME
FUNCTION
Negative Current-Sense Input for Controller 2. Connect to the negative terminal of the current-sense
element. Figure 8 describes current-sensing options. The PWM controller does not begin a cycle unless
the current sensed is less than the current-limit threshold programmed at ILIM2.
15
CSL2
Dual-Mode Feedback Input for Controller 2. Connect to V for a +1.8V fixed output or to analog ground
CC
16
17
18
FB2
(GND) for a +2.5V fixed output. For an adjustable output (0.5V to 2.7V), connect FB2 to a resistive
divider from OUT2. The FB2 regulation level is +0.5V.
Output Voltage-Sense Connection for Controller 2. Connect directly to the positive terminal of the output
capacitors as shown in the Standard Applications Circuit (Figure 1). OUT2 senses the output voltage to
determine the on-time for the high-side switching MOSFET. OUT2 also serves as the feedback input
when using the preset internal output voltages as shown in Figure 5. The output capacitor is discharged
through an internal 12Ω resistor connected between OUT2 and ground.
OUT2
Open-Drain Power-Good Output. PGOOD2 is low when the output voltage is more than 10% (typ) above
PGOOD2 or below the normal regulation point. PGOOD2 is also low during soft-start and shutdown. After the soft-
start circuit has terminated, PGOOD2 is high impedance if the output is in regulation.
19
21
DH2
High-Side Gate-Driver Output for Controller 2. DH2 swings from LX2 to BST2.
Inductor Connection for Controller 2. Connect to the switched side of the inductor. LX2 serves as the
lower supply rail for the DH2 high-side gate driver.
LX2
Boost Flying-Capacitor Connection for Controller 2. Connect to an external capacitor and diode as
shown in Figure 6. An optional resistor in series with BST2 allows the DH2 pullup current to be adjusted.
22
BST2
23
24
PGND
DL2
Power Ground
Low-Side Gate-Driver Output for Controller 2. DL2 swings from PGND to V
.
DD
Supply Voltage Input for the DL_ Gate Driver. Connect to the system supply voltage (+4.5V to +5.5V).
Bypass V to power ground with a 1µF or greater ceramic capacitor.
26
27
V
DD
DD
DL1
Low-Side Gate-Driver Output for Controller 1. DL1 swings from PGND to V
.
DD
Pulse-Skipping Control Input. This CMOS logic-level input enables or disables the light-load pulse-
skipping operation of both outputs. Connect SKIP as follows:
28
29
SKIP
V
CC
= OUT1 and OUT2 in forced-PWM mode.
GND = OUT1 and OUT2 in pulse-skipping mode.
Boost Flying-Capacitor Connection for Controller 1. Connect to an external capacitor and diode as
shown in Figure 6. An optional resistor in series with BST1 allows the DH1 pullup current to be adjusted.
BST1
Inductor Connection for Controller 1. Connect to the switched side of the inductor. LX1 serves as the
lower supply rail for the DH1 high-side gate driver.
30
32
LX1
DH1
High-Side Gate-Driver Output for Controller 1. DH1 swings from LX1 to BST1.
12 ______________________________________________________________________________________
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P in De s c rip t io n (c o n t in u e d )
PIN
NAME
FUNCTION
Open-Drain Power-Good Output. PGOOD1 is low when the output voltage is more than 10% (typ) above
or below the normal regulation point. PGOOD1 is also low during soft-start and shutdown. After the soft-
33
PGOOD1 start circuit has terminated, PGOOD1 becomes high impedance if the output is in regulation. For the
MAX1549, PGOOD1 is blanked—forced high-impedance state—when FBLANK is enabled and the
controller detects a transition on GATE.
Output-Voltage Sense Connection for Controller 1. Connect directly to the positive terminal of the output
capacitors as shown in the Standard Applications Circuit (Figure 1). OUT1 senses the output voltage to
determine the on-time for the high-side switching MOSFET, and also serves as the feedback input. The
34
OUT1
output capacitor is discharged through an internal 12Ω resistor connected between OUT1 and ground.
Negative Current-Sense Input for Controller 1. Connect to the negative terminal of the current-sense
35
36
CSL1
CSH1
element. Figure 8 describes current-sensing options. The PWM controller does not begin a cycle unless
the current sensed is less than the current-limit threshold programmed at ILIM1.
Positive Current-Sense Input for Controller 1. Connect to the positive terminal of the current-sense
element. Figure 8 describes current-sensing options. The PWM controller does not begin a cycle unless
the current sensed is less than the current-limit threshold programmed at ILIM1.
OD1, OD2,
OD3
37, 38, 39
40
Open-Drain Output. Controlled by G0 and G1 as described in Table 4.
REFIN
External Reference Input. REFIN sets the main output voltage (V
= V
) of the MAX1549.
OUT1
REFIN
______________________________________________________________________________________ 13
Du a l, In t e rle a ve d , Fix e d -Fre q u e n c y S t e p -Do w n
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Table 1. Component Selection for Standard Applications
COMPONENT
Input Voltage (V
PWM1
PWM2
)
IN
5V to 16V
5V to 16V
G1
0
G0
V
OUT1
0
1.50V
1.30V
1.00V
0.70V
Output Voltage (V
)
0
1
2.50V
OUT
1
0
1
1
Load Current
6A
5A
Switching Frequency
300kHz
300kHz
(2) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
C
C
, Input Capacitor
IN_
470µF, 4V, 10mΩ
330µF, 6.3V, 10mΩ
Sanyo POSCAP 6TPD330M
, Output Capacitor
OUT_
Sanyo POSCAP 4TPD470M
Siliconix Si4800BDY or
Fairchild Semiconductor
FDS6612A
Siliconix Si4800BDY or
Fairchild Semiconductor
FDS6612A
N
High-Side MOSFET
H_
Siliconix Si4736DY or
Fairchild Semiconductor
FDS6670A
Siliconix Si4736DY or
Fairchild Semiconductor
FDS6670A
N
D
Low-Side MOSFET
Schottky Rectifier
L_
L_
1A, 30V, 0.45V
1A, 30V, 0.45V
f
f
(if needed)
Nihon EP10QS03L
Nihon EP10QS03L
2.5µH
4.7µH
L_ Inductor
Sumida CDRH104-2R5NC
Sumida CDRH124-4R7MC
12mΩ 1%, 0.5W resistor
IRC LR2010-01-R012F or
Dale WSL-2010-R012F
15mΩ 1%, 0.5W resistor
IRC LR2010-01-R015F or
Dale WSL-2010-R015F
R
CS_
14 ______________________________________________________________________________________
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Table 2. Component Suppliers
SUPPLIER
PHONE
WEBSITE
AVX
843-448-9411 (USA)
714-447-2345 (USA)
631-435-1110 (USA)
800-322-2645 (USA)
561-752-5000 (USA)
888-522-5372 (USA)
310-322-3331 (USA)
408-986-0424 (USA)
800-344-2112 (USA)
www.avx.com
BI Technologies
www.bitechnologies.com
www.centralsemi.com
www.coilcraft.com
Central Semiconductor
Coilcraft
Coiltronics
www.coiltronics.com
www.fairchildsemi.com
www.irf.com
Fairchild Semiconductor
International Rectifier
Kemet
www.kemet.com
Panasonic
www.panasonic.com/industrial
81-72-870-6310 (Japan)
408-749-9714 (USA)
Sanyo
www.secc.co.jp
www.vishay.com
www.sumida.com
Siliconix (Vishay)
Sumida
203-268-6261 (USA)
81-3-3667-3301 (Japan)
847-545-6700 (USA)
81-3-3833-5441 (Japan)
800-348-2496 (USA)
Taiyo Yuden
TDK
www.t-yuden.com
81-3-5201-7241 (Japan)
847-803-6100 (USA)
www.component.tdk.com
www.tokoam.com
81-3-3727-1161 (Japan)
847-297-0070 (USA)
TOKO
______________________________________________________________________________________ 15
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INPUT (V )
IN
5V TO 16V
+5V BIAS
SUPPLY
C
IN
(2) 10µF
C1
1µF
V
DD
D
BST
D
BST
N
H1
DH1
DH2
N
H2
BST1
BST2
C
BST
C
BST
0.1µF
0.1µF
LX1
DL1
LX2
DL2
D
L1
D
L2
N
L1
N
L2
L1
2.5µH
L2
4.7µH
PGND
GND
CSH1
CSH2
R
CS1
R
CS2
12mΩ
15mΩ
MAX1549
CSL1
OUT1
CSL2
OUT2
OUTPUT 1
= V
OUTPUT 2
V = 2.5V
OUT2
V
OUT1
REFIN
C
470µF
OUT1
C
330µF
C
470pF
OUT2
CC1
FB2
SKIP
CC1
REF
C
REF
0.22µF
FSEL
OPEN (300kHz)
ON1
ON2
ON OFF
R2
R1
20Ω
100kΩ
+5V BIAS
SUPPLY
ILIM1
ILIM2
V
CC
C2
R3
100kΩ
R4
100kΩ
1µF
100kΩ
R6
R7
100kΩ
PGOOD1
PGOOD2
POWER-GOOD
REF
R5
100kΩ
REFIN
R8
R10
100kΩ
66.5kΩ
OD3
R11
150kΩ
DYNAMIC OUT1
CONTROL INPUTS
G0
G1
OD2
R12
R9
487kΩ
301kΩ
OPEN (100µs)
FBLANK
OD1
C
470pF
REFIN
POWER GROUND
ANALOG GROUND
SEE TABLE 1 FOR COMPONENT SPECIFICATIONS.
Figure 1. Standard Applications Circuit
16 ______________________________________________________________________________________
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The 5V bias supply must provide V (PWM controller)
CC
De t a ile d De s c rip t io n
and V
(gate-drive power), so the maximum current
DD
The MAX1549 dual fixed-frequency step-down con-
troller designed for low-voltage power supplies is ideal
for g ra p hic p roc e s s or units (GPUs ). The Sta nd a rd
Applications Circuit (Figure 1) generates the dynami-
c a lly a d jus ta b le outp ut volta g e (OUT1) typ ic a lly
required by graphics processor cores, and a fixed 2.5V
output (OUT2) for the local memory used by the GPU.
The MAX1549 main output supports up to four output
voltages that can be dynamically selected for support-
ing multiple GPU frequency and sleep states. The inter-
leaved, fixed-frequency architecture provides 180°
out-of-phase operation to reduce the input capacitance
required to meet the RMS input-current ratings.
drawn is:
I
= I + f
(Q
+ Q
)
G(HIGH)
BIAS
CC
SW
G(LOW)
= 5mA to 50mA (typ)
is 1mA (typ), f is the switching frequency,
where I
CC
SW
a re the MOSFET d a ta
G(HIGH)
a nd Q
a nd Q
G(LOW)
sheet’s total gate-charge specification limits at V = 5V.
GS
The battery input (V ) and 5V bias inputs (V
and
IN
CC
V ) can be connected together if the input source is a
DD
fixed 4.5V to 5.5V supply. If the 5V bias supply powers
up prior to the battery supply, the enable signals (ON1
and ON2 going from low to high) must be delayed until
the battery voltage is present to ensure startup.
Each controller consists of a multi-input PWM compara-
tor, high-side and low-side gate drivers, fault protection,
power-good detection, adjustable current-limit circuitry,
soft-start, and shutdown logic. The main PWM controller
(OUT1) also includes a dedicated reference input; logic-
selected, open-drain outputs for dynamically adjusting
the output voltage; and an integrator output for improved
output-voltage accuracy. The second PWM controller
(OUT2) includes a dual-mode feedback network and a
multiplexer for preset 2.5V (FB2 = GND), 1.8V (FB2 =
Fix e d -Fre q u e n c y, Cu rre n t -Mo d e
P WM Co n t ro lle r
The heart of each current-mode PWM controller is a
multi-input, open-loop comparator that sums two sig-
nals: the output-voltage error signal with respect to the
reference voltage and the slope-compensation ramp
(Figure 3). The MAX1549 uses a direct-summing config-
uration, approaching ideal cycle-to-cycle control over
the output voltage without a traditional error amplifier
and the phase shift associated with it. The MAX1549
uses a relatively low loop gain, allowing the use of low-
cost output capacitors. The low loop gain results in the
0.1% (typ) load-regulation error and helps reduce the
output-capacitor size and cost by shifting the unity-gain
crossover frequency to a lower level.
V
CC
), or adjustable output-voltage operation.
See Table 1 for the standard applications circuit’s com-
ponent selection and Table 2 for component manufac-
turer contact information.
+5 V Bia s S u p p ly (V
a n d V
)
DD
CC
The MAX1549 requires an external 5V bias supply in
addition to the battery. Typically, this 5V bias supply is
the note b ook’s 95% e ffic ie nt, 5V s ys te m s up p ly.
Keeping the bias supply external to the IC improves
efficiency and eliminates the cost associated with the
5V linear regulator that would otherwise be needed to
supply the PWM circuit and gate drivers. If stand-alone
capability is needed, generate the 5V bias supply with
Integrator Amplifier (OUT1 Only)
A feedback amplifier forces the DC average of the feed-
back voltage to equal the reference threshold voltage.
This transconductance amplifier integrates the feedback
voltage and provides a fine adjustment to the regulation
voltage (Figure 2), allowing accurate DC output voltage
regulation regardless of the output voltage ripple. The
feedback amplifier has the ability to shift the output volt-
age by ±8%. The differential input voltage range is at
least ±80mV total, including DC offset and AC ripple. Use
a capacitor value of 47pF to 1000pF (470pF typ).
an external linear regulator (V > 5.5V) or regulated
IN
charge pump (V < 4.5V).
IN
______________________________________________________________________________________ 17
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Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
OSC
FSEL
SKIP
ILIM2
CSH2
CSL2
ILIM1
CSH1
CSL1
BST1
BST2
PWM
CONTROLLER 2
(FIGURE 3)
DH2
PWM
LX2
CONTROLLER 1
(FIGURE 3)
DH1
LX1
V
DD
DL2
V
DD
DL1
OUT2
FB2
PGND
FB2 DECODE
(FIGURE 10)
CC1
ON2
Gm
OUT1
ON1
REF
3R
V
CC
2.0V
REF
GND
R
REFIN
POWER-GOOD AND
FAULT PROTECTION
(FIGURE 7)
PGOOD1
POWER-GOOD AND
FAULT PROTECTION
(FIGURE 7)
PGOOD2
BLANK
FBLANK
G0
QUAD-LEVEL
DECODE AND
TIMER
GATE
LOGIC
G1
OD1
OD2
OD3
MAX1549
Figure 2. PWM-Controller Detailed Functional Diagram
18 ______________________________________________________________________________________
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Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
CSH
CSL
FROM FB
REF
SLOPE COMP
0.1 x V
LIMIT
R
S
Q
DH DRIVER
IDLE-MODE
CURRENT
SKIP
SOFT-START
COUNTER
CURRENT
LIMIT
ON
DAC
OSC
S
DL DRIVER
Q
R
LX
PGND
Figure 3. PWM-Comparator Functional Diagram
______________________________________________________________________________________ 19
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Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
Lig h t -Lo a d Op e ra t io n Co n t ro l (SKIP)
The MAX1549 includes a light-load operating-mode
control input (SKIP) used to independently enable or
disable the zero-crossing comparator for both con-
trolle rs . Whe n the ze ro-c ros s ing c omp a ra tors a re
enabled (SKIP = GND), each controller forces DL_ low
when its current-sense inputs detect zero inductor cur-
rent. This keeps the inductor from discharging the out-
put capacitors and forces the controller to skip pulses
under light-load conditions to avoid overcharging the
output. When the zero-crossing comparators are dis-
Table 3. FSEL Configuration
FSEL
SWITCHING FREQUENCY (kHz)
V
CC
400
300
200
100
Open
REF
GND
Frequency Selection (FSEL)
The FSEL input selects the PWM-mode switching fre-
quency as shown in Table 3. High-frequency (400kHz)
operation optimizes the application for the smallest
component size, trading off efficiency due to higher
s witc hing los s e s . This ma y b e a c c e p ta b le in ultra -
portable devices where the load currents are lower.
Low-frequency (100kHz) operation offers the best over-
all efficiency at the expense of component size and
board space.
abled (SKIP = V ), each controller maintains PWM
CC
operation under light-load conditions (forced-PWM).
The on-time of the ste p-down c ontrolle r te rmina te s
when the output voltage exceeds the feedback thresh-
old and when the current-sense voltage exceeds the
idle-mode current-sense threshold. Under heavy-load
conditions, the continuous inductor current remains
above the idle-mode current-sense threshold, so the
on-time depends only on the feedback-voltage thresh-
old. Under light-load conditions, the controller remains
above the feedback-voltage threshold, so the on-time
d ura tion d e p e nd s s ole ly on the id le -mod e c urre nt-
sense threshold, which is approximately 20% of the full-
load current-limit threshold set by ILIM_.
Fo rc e d -P WM Mo d e
The low-noise forced-PWM mode disables the zero-
c ros s ing c omp a ra tor, whic h c ontrols the low-s id e
switc h on-time . This forc e s the low-side ga te -drive
waveform to be constantly the complement of the high-
s id e g a te -d rive wa ve form, s o the ind uc tor c urre nt
reverses at light loads while DH_ maintains a duty fac-
When transitioning from pulse-skipping mode to forced-
PWM mod e (SKIP ris ing e d g e ), DL_ is p ulle d hig h
immediately if both drivers are low.
tor of V
/ V . The benefit of forced-PWM mode is
OUT_
IN
ke e p ing the s witc hing fre q ue nc y fa irly c ons ta nt.
However, forced-PWM operation comes at a cost: the
no-load 5V bias current remains between 5mA and
50mA, d e p e nd ing on the e xte rna l MOSFETs a nd
switching frequency. This additional supply current
reduces the light-load efficiency.
Idle-Mode Current-Sense Threshold
The idle-mode current-sense threshold forces a lightly
loaded regulator to source a minimum amount of power
with each on-time. Since the zero-crossing comparator
prevents the switching regulator from sinking current,
the controller must skip pulses to avoid overcharging
the output. When the clock edge occurs, if the output
voltage still exceeds the feedback threshold, the con-
troller does not initiate another on-time. This forces the
controller to actually regulate the valley of the output
voltage ripple under light-load conditions.
In particular, forced-PWM mode avoids audio-frequen-
cy noise under light-load conditions, improves the load-
transient response, and provides sink-current capability
for d yna mic outp ut-volta g e a d jus tme nts . The ma in
MAX1549 controller (OUT1) uses forced-PWM opera-
tion during all dynamic output-voltage transitions (G0 or
G1 transition detected) to ensure fast, accurate transi-
tions. Since forced-PWM operation disables the zero-
crossing comparator, the inductor current reverses
und e r lig ht loa d s , q uic kly d is c ha rg ing the outp ut
capacitors. FBLANK determines how long the main
MAX1549 controller maintains forced-PWM operation—
Automatic Pulse-Skipping Crossover
In skip mode, an inherent automatic switchover to PFM
takes place at light loads (Figure 4). This switchover is
affected by a comparator that truncates the low-side
switch on-time at the inductor current’s zero crossing.
The zero-crossing comparator differentially senses the
inductor current across the low-side MOSFET (LX_ to
150µs (FBLANK = V ), 100µs (FBLANK = open or
CC
GND), or 50µs (FBLANK = REF).
PGND). Onc e V
- V _ d rop s b e low the 3mV
PGND
LX
zero-crossing current limit, the comparator forces DL_
low (Figure 3).
20 ______________________________________________________________________________________
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Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
This mechanism causes the threshold between pulse-
skipping PFM and nonskipping PWM operation to coin-
c id e with the b ound a ry b e twe e n c ontinuous a nd
discontinuous inductor-current operation (also known as
the “critical conduction” point). The load-current level at
∆I
∆t
V - V
IN OUT
=
L
I
IDLE
which the PFM/PWM crossover occurs, I
, is
LOAD(SKIP)
equal to 1/2 the idle-mode inductor current:
I
= I / 2
LOAD IDLE
⎛
⎜
⎞
1
V
IDLE
I
=
LOAD(SKIP)
⎟
2 R
⎝
⎠
SENSE
where V
is the idle-mode threshold (V
= 0.2 x
IDLE
IDLE
V
LIMIT
where V
= 0.1 x V ; see the Setting the
ILIM
LIMIT
Current Limit section). The switching waveforms may
appear noisy and asynchronous when light loading caus-
es pulse-skipping operation, but this is a normal operat-
ing condition that results in high light-load efficiency.
Tradeoffs in PFM noise vs. light-load efficiency are made
by varying the inductor value. Generally, low inductor val-
ues produce a broader efficiency vs. load curve, while
higher values result in higher full-load efficiency (assum-
ing the coil resistance remains fixed) and less output volt-
age ripple. Penalties for using higher inductor values
inc lud e la rg e r s ize a nd d e g ra d e d loa d -tra ns ie nt
response (especially at low input-voltage levels).
0
ON-TIME
TIME
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
For PFM operation (discontinuous conduction), the out-
put voltage is defined by the following equation:
⎛
⎞
f
1
2
SW
V
= V
+
I
× ESR
OUT(PFM)
NOM
IDLE
⎜
⎟
f
⎝
⎠
OSC
where f
FSEL, f
is the maximum switching frequency set by
is the actual switching frequency, and I
OSC
SW
Ou t p u t Vo lt a g e
DC-output accuracy specifications in the Electrical
Cha ra c te ris tic s ta b le re fe r to the e rror-c omp a ra tor
threshold. When the inductor continuously conducts
(PWM operation), the MAX1549 regulates the peak of
the outp ut rip p le , s o the a c tua l DC outp ut volta g e
depends on the error-comparator threshold, the slope-
compensation amplitude, and the output voltage ripple.
For PWM operation (continuous conduction), the output
voltage is defined by the following equation:
IDLE
is the idle-mode inductor current when pulse skipping.
Dynamic Output Voltages (OUT1 Only)
The MAX1549 regulates OUT1 to the voltage set at
REFIN. By changing the voltage at REFIN, the MAX1549
can be used in applications that require dynamic output-
voltage changes between two set points. Figure 1 shows
a dynamically adjustable resistive voltage-divider network
at REFIN. Using the G0 and G1 gate inputs and the
open-drain outputs (OD1, OD2, and OD3), resistors can
be switched in and out of the REFIN resistor-divider,
dynamically changing the voltage at REFIN. The open-
drain outputs are activated by the G0 and G1 gate inputs
as shown in Table 4. The main output voltage is deter-
mined by the following equation:
⎛
⎞
A
V
V
RIPPLE
⎛
⎞
SLOPE NOM
V
= V
1 −
-
⎜
⎝
⎟
⎠
OUT _(PWM)
NOM
⎜
⎟
V
2
⎝
⎠
IN
where V
is the nominal output voltage, A
SLOPE
NOM
equals 1%, and V
is the output voltage ripple
RIPPLE
(typically V
the Output Capacitor Selection section).
= ESR x ∆I
as described in
RIPPLE
INDUCTOR
⎛
⎞
R
EQ
V
= V
REF
OUT1
⎜
⎟
R8 + R
⎝
⎠
EQ
In discontinuous conduction (I < I
), the
LOAD(SKIP)
OUT
MAX1549 regulates the valley of the output ripple, and
the output voltage has a DC regulation level higher than
the error-comparator threshold by approximately 1.5%
due to the slope compensation.
where R
is the equivalent resistance between REFIN
EQ
and ground (see Figure 1 and Table 4).
The main MAX1549 controller (OUT1) automatically
enters forced-PWM operation after detecting a G0 or
G1 transition (rising or falling edge), and remains in
forced-PWM mode for a minimum time selected by
FBLANK (Table 5).
______________________________________________________________________________________ 21
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Table 4. Open-Drain Output States
INPUTS
OUTPUTS
OD2
R
EQ
G1
0
G0
0
OD1
High-Z
0
OD3
High-Z
High-Z
High-Z
0
High-Z
High-Z
0
R9
0
1
R9 // R12
R9 // R11
R9 // R10
1
0
High-Z
High-Z
1
1
High-Z
Forced-PWM operation is required to ensure fast, accu-
rate negative voltage transitions when REFIN is low-
e re d . Sinc e forc e d -PWM op e ra tion d is a b le s the
zero-crossing comparator, the inductor current can
reverse under light loads, quickly discharging the out-
p ut c a p a c itors . If fa ult b la nking is e na b le d , the
MAX1549 disables the main controller’s (OUT1) output
fault protection (OVP and UVP), and forces PGOOD1 to
a high-impe da nc e sta te for the pe riod se le c te d by
FBLANK (Table 5).
Adding a capacitor across REFIN and GND filters noise
and controls the rate-of-change of the REFIN voltage
during dynamic transitions. With the additional capaci-
tance, the REFIN voltage slews between the two set
points with a time constant given by R
x C
,
REFIN
REFIN
where R
is the equivalent parallel resistance seen
REFIN
by the slew capacitor during the transition:
⎛
⎞
R8 × R
R8 + R
EQ
τ
=
C
REFIN
REFIN
⎜
⎟
⎝
⎠
EQ
For a step voltage change at REFIN, the rate-of-change
of the output voltage is limited by the inductor current
ramp, the total output capacitance, the current limit, and
the load during the transition. The inductor current ramp
is limited by the voltage across the inductor and the
inductance. The total output capacitance determines
how much current is needed to change the output volt-
age. Additional load current slows down the output-volt-
age change during a positive REFIN voltage change,
and speeds up the output-voltage change during a neg-
ative REFIN voltage change. Increasing the current-limit
setting speeds up a positive output-voltage change.
Dual-Mode Feedback (OUT2 Only)
The MAX1549’s dual-mode operation allows the selec-
tion of common voltages without requiring external
components (Figure 5). For the secondary controller
(OUT2), connect FB2 to GND for a fixed 2.5V output, to
for a fixed 1.8V output, or connect FB2 directly to
OUT2 for a fixe d 0.5V outp ut. The ma in c ontrolle r
(OUT1) of the MAX1549 regulates to the voltage set at
V
CC
REFIN (V
mode operation.
= V
) and does not support dual-
FB1
REFIN
OUT2
MAX1549
TO ERROR
AMPLIFIER
ADJUSTABLE
OUTPUT
FB2
FIXED OUTPUT (1.8V)
FB = V
CC
FIXED OUTPUT (2.5V)
FB = GND
REF / 20
REF
Figure 5. Second Controller’s Dual-Mode Feedback
22 ______________________________________________________________________________________
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Alternately, the secondary output voltage (OUT2) can
be adjusted from 0.5V to 2.7V using a resistive voltage-
divider. The MAX1549 regulates FB2 to a fixed 0.5V ref-
erence voltage, so the secondary output voltage can
be determined with the following equation:
DL_ and DH_ drivers to the MOSFET gates for the adap-
tive dead-time circuits to work properly. Otherwise, the
MAX1549 interprets the MOSFET gates as “off” while
charge actually remains on the gate. Use very short, wide
traces (50 mils to 100 mils wide if the MOSFET is 1in from
the driver).
⎛
⎞
R
R
A
V
= V
1 +
The internal pulldown transistor that drives DL_ low is
robust, with a 0.5Ω (typ) on-resistance. This helps prevent
DL_ from being pulled up due to capacitive coupling from
the drain to the gate of the low-side MOSFETs when the
OUT2
FB2
⎜
⎟
⎝
⎠
B
where V
= 0.5V, R is the resistor from the output to
A
FB2
FB2, and R is the resistor from FB2 to analog ground.
B
inductor node (LX_) quickly switches from ground to V .
IN
Cu rre n t -Lim it P ro t e c t io n (ILIM_)
The current-limit circuit uses differential current-sense
inputs (CSH_ and CSL_) to limit the peak inductor cur-
re nt. If the ma g nitud e of the c urre nt-s e ns e s ig na l
exceeds the current-limit threshold, the PWM controller
turns off the high-side MOSFET (Figure 3). At the next
rising edge of the internal oscillator, the PWM controller
does not initiate a new cycle unless the current-sense
signal drops below the peak current-limit threshold. The
actual maximum load current is less than the peak cur-
re nt-limit thre s hold b y a n a mount e q ua l to 1/2 the
inductor ripple current. Therefore, the maximum load
capability is a function of the current-limit threshold,
current-sense resistance, inductor value, switching fre-
Applications with high input voltages and long, inductive
driver traces may require additional gate-to-source
capacitance to ensure fast-rising LX_ edges do not pull
up the low-side MOSFETs’ gate voltage, causing shoot-
through currents. The capacitive coupling between LX_
and DL_ created by the MOSFETs’ gate-to-drain capaci-
tance (C
), gate-to-source capacitance (C
- C
),
RSS
ISS
RSS
and additional board parasitics should not exceed the fol-
lowing minimum threshold:
⎛
⎞
C
RSS
V
> V
IN
GS(TH)
⎜
⎟
C
⎝
⎠
ISS
Lot-to-lot variation of the threshold voltage can cause
p rob le ms in ma rg ina l d e s ig ns . Typ ic a lly, a d d ing a
quency, and duty cycle (V
/ V ).
OUT
IN
4700pF between DL_ and power ground (C in Figure
Connect ILIM_ to V for the 70mV default threshold, or
CC
NL
6), close to the low-side MOSFETs, greatly reduces the
voltage coupling. Do not exceed 22nF of total gate
capacitance to prevent excessive turn-off delays.
adjust the current-limit threshold with an external resistor-
divider at ILIM_. Use a 2µA to 20µA divider current for
accuracy and noise immunity. The current-limit threshold
a d jus tme nt ra ng e is from 50mV to 200mV. In the
adjustable mode, the current-limit threshold voltage
Alternately, shoot-through currents can be caused by a
combination of fast high-side MOSFETs and slow low-
side MOSFETs. If the turn-off delay time of the low-side
MOSFET is too long, the high-side MOSFETs turn on
before the low-side MOSFETs have actually turned off.
Adding a resistor less than 10Ω in series with BST_
slows down the high-side MOSFET turn-on time, elimi-
nating the shoot-through currents without degrading
the turn-off time (Figure 6). Slowing down the high-side
MOSFET also reduces the LX_ node rise time, thereby
reducing the EMI and high-frequency coupling respon-
sible for switching noise.
equals precisely 1/10th the voltage seen at ILIM_ (V
LIMIT
= 0.1V _). The logic threshold for switchover to the
ILIM
70mV default value is approximately V - 1V.
CC
Carefully observe the PC board layout guidelines to
ensure noise and DC errors do not corrupt the differen-
tial current-sense signals seen by CSH_ and CSL_.
Place the IC close to the sense resistor with short,
direct traces, making a Kelvin-sense connection to the
current-sense resistor.
MOS FET Ga t e Drive rs (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving mod-
erately sized, high-side and larger, low-side power
MOSFETs. This is consistent with the low duty factor seen
P o w e r-Up S e q u e n c e
Power-on reset (POR) occurs when V
rises above
CC
approximately 2V, resetting the fault latch and soft-start
counter, powering up the reference, and preparing the
in notebook applications, where a large V - V
differ-
IN
OUT
PWM controllers for operation. Until V reaches 4.25V
ential exists. An adaptive dead-time circuit monitors the
DL_ output and prevents the high-side MOSFET from
turning on until DL_ is fully off. A similar adaptive dead-
time circuit monitors the DH_ output to prevent the low-
side MOSFET from turning on until DH_ is fully off. There
must be a low-resistance, low-inductance path from the
CC
(typ), the V
undervoltage-lockout (UVLO) circuitry
CC
inhibits switching. The controller inhibits switching by
pulling DH_ low and forcing DL_ high. When V rises
CC
above 4.25V and ON_ is driven high, the activated con-
troller initializes soft-start and starts switching.
______________________________________________________________________________________ 23
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Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
S o ft -S h u t d o w n
Soft-shutdown slowly discharges the output capaci-
tance, providing a damped shutdown response. This
eliminates the slightly negative output voltages caused
C
BYP
by quickly discharging the output through the inductor
and low-side MOSFET. Both controllers contain sepa-
rate soft-shutdown circuits.
V
DD
MAX1549
D
BST
(R )*
BST
BST
When the controller is disabled—ON_ pulled low, the
UV fa ult la tc h s e t, or inp ut UVLO trig g e re d —the
MAX1549 discharges the respective output through an
internal 12Ω switch to ground. While the output dis-
charges, the MAX1549 forces DL_ low and disables the
PWM controller, but the reference remains active to
provide an accurate threshold. Once the output voltage
drops below 0.3V, the MAX1549 pulls DL_ high, effec-
tively clamping the output and LX_ switching node to
ground. The reference shuts down once both outputs
are disabled and discharged below 0.3V.
INPUT (V )
IN
C
BST
DH
LX
N
H
L
V
DD
DL
N
L
(C )*
NL
GND
P o w e r-Go o d Ou t p u t (P GOOD_)
The MAX1549 includes separate open-drain outputs for
the power-good window comparators (Figure 7) that
monitor each output continuously (except during main-
output fault blanking; see the Fault and Power-Good
Bla nking s e c tion). The c ontrolle r a c tive ly hold s
PGOOD_ low in shutdown and during soft-start. Once
the digital soft-start terminates, PGOOD_ becomes high
impedance as long as the respective output voltage is
within 10% of the nominal regulation voltage. When
either output voltage drops 10% below or rises 10%
above the nominal regulation voltage, the MAX1549
pulls the respective PGOOD_ output low. Any fault con-
dition forces both PGOOD1 and PGOOD2 low until the
fa ult la tc h is c le a re d b y tog g ling ON1 or ON2, or
(R )* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING
BST
THE SWITCHING-NODE RISE TIME.
(C )* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
NL
Figure 6. Optional Gate-Driver Circuitry
Dig it a l S o ft -S t a rt
Soft-start allows a gradual increase of the internal cur-
rent-limit level during startup to reduce the input surge
currents. Both controllers contain an internal digital
soft-start circuit. In shutdown mode or input UVLO, the
controller resets the soft-start counter to zero.
cycling V power below 1V. For logic-level output volt-
CC
a g e s , c onne c t a n e xte rna l p ullup re s is tor b e twe e n
PGOOD_ and V . A 100kΩ resistor works well in most
CC
The MAX1549 divides the soft-start period into five
phases. During the first phase, the controller limits the
peak current limit to only 20% of the full current limit. If
the output does not reach regulation within 128 clock
applications.
The power-good window comparators are completely
independent of the overvoltage and undervoltage-pro-
tection fault comparators.
cycles (1 / f
), soft-start enters the second phase
OSC
Fa u lt P ro t e c t io n
and increments the current limit by another 20%. This
process repeats until soft-start reaches the maximum
current limit after 512 clock cycles or until the output
re a c he s the nomina l re g ula tion volta g e , whic he ve r
occurs first (see the Soft-Start Waveforms in the Typical
Operating Characteristics). The exact rise time of the
output voltage depends on the output capacitance and
load current.
Overvoltage Protection (OVP)
If either output voltage rises above 114.5% of its nomi-
nal regulation voltage, the OVP circuit sets the fault
latch, pulls PGOOD1 and PGOOD2 low, shuts down
both PWM controllers, and immediately pulls DH_ low
and forces DL_ high. This turns on the synchronous-
rectifier MOSFETs with 100% duty, rapidly discharging
the output capacitors and clamping both outputs to
ground. However, immediately latching DL_ high typi-
cally causes slightly negative output voltages due to
24 ______________________________________________________________________________________
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Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
FAULT PROTECTION
Table 5. FBLANK Configuration Table
POWER-GOOD
OUT1 FAULT AND
PGOOD1 BLANKING
OUT1 FORCED-PWM
DURATION (TYP) (µs)
0.9 x
INT REF
1.1 x
INT REF
0.7 x
INT REF
1.14 x
INT REF
FBLANK
INTERNAL FB
V
Enabled (150µs)
Enabled (100µs)
Enabled (50µs)
Disabled
150
100
50
CC
Open
REF
GND
100
BLANK
(TRANSITION)
Fa u lt a n d P o w e r-Go o d Bla n k in g (FBLANK)
The main MAX1549 controller (OUT1) automatically
enters forced-PWM operation during all dynamic out-
put-voltage transitions (G0 or G1 transition detected) to
ensure fast, accurate transitions. FBLANK determines
how long the main controller maintains forced-PWM
FAULT
LATCH
FAULT
TIMER
POWER-GOOD
POR
operation (Table 5)—150µs (FBLANK = V ), 100µs
CC
(FBLANK = open or GND), or 50µs (FBLANK = REF).
When fault blanking is enabled (FBLANK = V , open,
CC
Figure 7. Power-Good and Fault Protection
or REF), the MAX1549 also disables the overvoltage
and undervoltage fault protection for OUT1, and forces
PGOOD1 to a high-impedance state during the transi-
tion period selected by FBLANK (Table 5). This pre-
vents fault protection from latching off the MAX1549
and keeps the PGOOD1 signal from going low while
the output-voltage transition occurs.
the energy stored in the output LC at the instant the OV
fault occurs. If the load cannot tolerate a negative volt-
age, place a power Schottky diode across the output to
act as a reverse-polarity clamp. If the condition that
caused the overvoltage persists (such as a shorted
high-side MOSFET), the battery fuse blows. The main
controller temporarily blanks OVP after transitions are
detected on G0 or G1 (FBLANK enabled). Toggle ON1
De s ig n P ro c e d u re
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design tradeoff lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
or ON2, or cycle V power below 1V, to clear the fault
latch and restart the controller.
CC
Undervoltage Protection (UVP)
Each controller has an output UVP circuit that activates
4096 c loc k c yc le s (1 / f
) a fte r the c ontrolle r is
OSC
enabled. If either output voltage drops below 70% of its
nominal regulation voltage, the MAX1549 sets the fault
la tc h, pulls PGOOD1 a nd PGOOD2 low, a nd shuts
down both controllers using discharge mode (see the
Soft-Shutd own s e c tion). Whe n e a c h outp ut volta g e
drops to 0.3V, its synchronous rectifier turns on and
clamps the output to GND. The main controller tem-
porarily blanks UVP after transitions are detected on G0
or G1 (FBLANK enabled). Toggle ON1 or ON2, or cycle
Input Voltage Range: The maximum value (V
)
IN(MAX)
must accommodate the worst-case, high AC-adapter
voltage. The minimum value (V ) must account for
IN(MIN)
the lowest battery voltage minus the voltage drops asso-
ciated with the connectors, fuses, and battery-selector
switches. If there is a choice at all, lower input voltages
result in better efficiency. The minimum and maximum
input voltage range is restricted by the minimum and
maximum duty-cycle limits specified in the Electrical
Characteristics table:
V
CC
power below 1V, to clear the fault latch and restart
the controller.
V
V
OUT
OUT
V
>
and V
<
Thermal Fault Protection
IN(MIN)
IN(MAX)
D
t
f
ON(MIN) OSC
MAX
The MAX1549 features a thermal fault-protection circuit.
When the junction temperature rises above +160°C, a
thermal sensor activates the fault latch, pulls PGOOD1
and PGOOD2 low, and shuts down both controllers
using discharge mode. Toggle ON1 or ON2, or cycle
whe re D
is the 91% ma ximum d uty-c yc le limit,
MAX
t
is the 200ns minimum off-time, and f
is the
ON(MIN)
OSC
switching frequency selected by FSEL. Since the maxi-
mum input voltage range is restricted by the switching
frequency and output voltage, lower frequency opera-
tion might be required for high input-to-output voltage
applications.
V
CC
power below 1V, to reactivate the controller after
the junction temperature cools by 15°C.
______________________________________________________________________________________ 25
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Maximum Load Current: There are two values to con-
sider. The peak inductor current (I ) determines the
instantaneous component stresses and filtering require-
me nts a nd thus d rive s outp ut c a p a c itor s e le c tion,
inductor saturation rating, and the design of the cur-
rent-limit circuit. The maximum continuous load current
Find a low-loss inductor with the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
PEAK
inductor current (I ):
PEAK
(I
) determines the thermal stresses and thus
LOAD(MAX)
LIR
2
⎛
⎞
drives the selection of input capacitors, MOSFETs, and
other critical heat-contributing components.
I
= I
1 +
⎜
⎝
⎟
⎠
PEAK
LOAD(MAX)
Switching Frequency: This choice determines the
basic tradeoff between size, efficiency, and maximum
input voltage range. The optimum frequency is largely
a function of maximum input voltage, due to MOSFET
switching losses that are proportional to frequency and
Most inductor manufacturers provide inductors in stan-
dard values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc.
Also look for nonstandard values, which can provide a
better compromise in LIR across the input voltage range.
If using a swinging inductor (where the no-load induc-
tance decreases linearly with increasing current), evalu-
ate the LIR with properly scaled inductance values.
V
2. The optimum frequency is also a moving target,
IN
due to rapid improvements in MOSFET technology that
are making higher frequencies more practical.
Tra n s ie n t Re s p o n s e
The ind uc tor rip p le c urre nt a ls o imp a c ts tra ns ie nt-
Inductor Operating Point: This choice provides trade-
offs between size vs. efficiency and transient response
vs. output ripple. Low inductor values provide better tran-
sient response and smaller size, but also result in lower
efficiency and higher output ripple due to increased rip-
ple currents. The minimum practical inductor value is one
that causes the circuit to operate at the edge of critical
conduction (where the inductor current just touches zero
with every cycle at maximum load). Inductor values lower
than this grant no further size-reduction benefit. The opti-
mum operating point is usually found between 20% and
50% ripple current. When pulse skipping (SKIP low and
light loads), the inductor value also determines the load-
current value at which PFM/PWM switchover occurs.
response performance, especially at low V - V
dif-
IN
OUT
fe re ntia ls . Low ind uc tor va lue s a llow the ind uc tor
current to slew faster, replenishing charge removed
from the output-filter capacitors by a sudden load step.
The total output voltage sag is the sum of the voltage
sag while the inductor is ramping up and the voltage
sag before the next pulse can occur:
2
L ∆I
(
)
LOAD(MAX)
V
=
SAG
2C
V
× D
- V
(
)
OUT IN
MAX
OUT
∆I
T - ∆T
(
)
LOAD(MAX)
C
In d u c t o r S e le c t io n
The switching frequency and inductor operating point
determine the inductor value as follows:
+
OUT
whe re D
is the ma ximum d uty fa c tor (s e e the
MAX
Electrical Characteristics table), T is the cycle period (1 /
), ∆T equals V / V x T when in PWM mode, or L
V
V
- V
OUT
(
)
OUT IN
I
f
OSC
OUT
IN
OUT
L =
V x f
x LIR
x 0.2 x I
/ (V - V
) when in skip mode. The
IN OSC x LOAD(MAX)
MAX
IN
amount of overshoot during a full-load to no-load transient
due to stored inductor energy can be calculated as:
For example: I
= 5A, V = 12V, V
=
LOAD(MAX)
IN
OUT
2.5V, f
= 300kHz, 30% ripple current or LIR = 0.3:
OSC
2
∆I
L
(
)
LOAD(MAX)
2.5V × (12V - 2.5V)
= 4.40µH
V
≈
SOAR
L =
2C
V
OUT OUT
12V × 300kHz × 5A × 0.3
26 ______________________________________________________________________________________
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Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
S e t t in g t h e P e a k Cu rre n t Lim it
The minimum c urre nt-limit thre shold must be gre a t
INPUT (V )
IN
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The
C
IN
MAX1549
DH_
N
H
peak inductor current occurs at I
ripple current; therefore:
plus 1/2 the
LOAD(MAX)
L
R
SENSE
LX_
I
LIR
⎛
⎞
C
OUT
LOAD(MAX)
2
N
L
D
L
I
> I
+
DL_
LIMIT
LOAD(MAX)
⎜
⎟
⎝
⎠
PGND
where I
equals the minimum current-limit thresh-
LIMIT_
old voltage divided by the current-sense resistance
(R ). For the 70mV default setting, the minimum
CSH_
CSL_
SENSE
current-limit threshold is 65mV.
Connect ILIM_ to V for a default 70mV current-limit
CC
A) OUTPUT SERIES RESISTOR SENSING
threshold. In adjustable mode, the current-limit thresh-
old is precisely 1/10th the voltage seen at ILIM_. For an
adjustable threshold, connect a resistive-divider from
REF to analog ground (GND) with ILIM_ connected to
the center tap. The external 500mV to 2V adjustment
range corresponds to a 50mV to 200mV current-limit
threshold. When adjusting the current limit, use 1% tol-
erance resistors and a divider current of approximately
10µA to prevent significant inaccuracy in the current-
limit tolerance.
INPUT (V )
IN
C
IN
MAX1549
N
H
DH_
INDUCTOR
LX_
C
OUT
C
EQL
R
N
L
EQL
D
L
DL_
PGND
The current-sense method (Figure 8) and magnitude
determine the achievable current-limit accuracy and
power loss. Typically, higher current-sense limits provide
more noise immunity, but also dissipate more power.
Mos t a p p lic a tions e mp loy a c urre nt-limit thre s hold
CSH_
CSL_
R
BIAS
= R
EQL
B) LOSSLESS INDUCTOR SENSING
(V ) of 50mV to 100mV, so the sense resistor can be
LIMIT
determined by:
Figure 8. Current-Sense Configurations
V
LIMIT
R
=
SENSE
the inductor’s DC resistance (R
= R
). Use the
SENSE
DCR
I
LIMIT
worst-case inductance and R
values provided by the
DCR
inductor manufacturer, adding some margin for the
inductance drop over temperature and load.
For the best current-sense accuracy and overcurrent
protection, use a 1% tolerance current-sense resistor
between the inductor and output as shown in Figure
8A. This configuration constantly monitors the inductor
current, allowing accurate current-limit protection.
Ou t p u t Ca p a c it o r S e le c t io n
The output-filter capacitor must have low enough equiv-
alent series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
Alternately, high-power applications that do not require
highly accurate current-limit protection can reduce the
overall power dissipation by connecting a series RC
circuit across the inductor (Figure 8B) with an equiva-
lent time constant:
For processor core voltage converters and other appli-
cations where the output is subject to severe load tran-
sients, the output capacitor’s size depends on how
much ESR is needed to prevent the output from dip-
ping too low under a load transient. Ignoring the sag
due to finite capacitance:
L
= C
× R
EQL
EQL
R
DCR
V
STEP
LOAD(MAX)
where R
is the inductor’s series DC resistance. In
DCR
R
≤
ESR
∆I
this configuration, the current-sense resistance equals
______________________________________________________________________________________ 27
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Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
In applications without large and fast load transients, the
output capacitor’s size often depends on how much ESR
is needed to maintain an acceptable level of output volt-
age ripple. The output voltage ripple of a step-down con-
troller equals the total inductor ripple current multiplied by
the output capacitor’s ESR. Therefore, the maximum ESR
required to meet the ripple specifications is:
Do not p ut hig h-va lue c e ra mic c a p a c itors d ire c tly
across the feedback sense point without taking precau-
tions to ensure stability. Large ceramic capacitors can
have a high-ESR zero frequency and cause erratic,
unstable operation. However, it is easy to add enough
series resistance by placing the capacitors a couple
inches downstream from the feedback sense point,
which should be as close as possible to the inductor.
V
RIPPLE
R
≤
ESR
Unstable operation manifests itself in two related but
distinctly different ways: duty-cycle variation and fast-
feedback loop instability. Duty-cycle variation occurs
due to noise on the output or because the ESR is so
low that there is not enough voltage ramp in the output-
voltage signal. This “fools” the error comparator into
extending the on-time, forcing the next cycle to termi-
na te its on-time e a rly. Duty-c yc le va ria tion is more
annoying than harmful, resulting in nothing worse than
increased output ripple. However, it can indicate the
possible presence of loop instability due to insufficient
ESR. Loop instability can result in oscillations at the out-
put after line or load steps. Such perturbations are usu-
ally damped, but can cause the output voltage to rise
above or fall below the tolerance limits.
I
LIR
LOAD(MAX)
The actual capacitance value required relates to the
size ne e de d to a c hie ve low ESR, a s we ll a s to the
c he mis try of the c a p a c itor te c hnolog y. Thus , the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tanta-
lums, OS-CONs, polymers, and other electrolytics).
Whe n using low-c a pa c ity filte r c a pa c itors, suc h a s
ceramic capacitors, size is usually determined by the
capacity needed to prevent V
and V
from
SAG
SOAR
causing problems during load transients. Generally,
once enough capacitance is added to meet the over-
shoot requirement, undershoot at the rising load edge
is no longer a problem (see the V
and V
equa-
SAG
SOAR
tions in the Transient Response section). However, low-
capacity filter capacitors typically have high ESR zeros
that can affect the overall stability (see the Output-
Capacitor Stability Considerations section).
The easiest method for checking stability is to apply a
ve ry fa s t ze ro-to-ma x loa d tra ns ie nt a nd c a re fully
observe the output-voltage-ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
Ou t p u t -Ca p a c it o r S t a b ilit y Co n s id e ra t io n s
The MAX1549 controllers rely on the output voltage ripple,
which can be defined as the inductor current ripple times
the output capacitor’s ESR, to generate the current-mode
control signal required for stable operation. Therefore, the
controller’s stability is determined by the value of the ESR
zero relative to the switching frequency. The boundary of
instability is given by the following equation:
In p u t Ca p a c it o r S e le c t io n
The input capacitor must meet the RMS ripple current
requirement (I
) imposed by the switching currents.
RMS
For a single step-down converter, the RMS input ripple
current is defined by the output load current (I ),
OUT
input voltage, and output voltage, with the worst-case
f
OSC
π
f
≤
ESR
condition occurring at V = 2V
:
IN
OUT
⎛
⎜
⎞
⎟
where:
V
V
- V
(
)
OUT IN
OUT
I
= I
OUT
1
RMS
f
=
⎜
V
⎟
ESR
IN
⎝
⎠
2πR
C
ESR OUT
For a dual 180° interleaved controller, the out-of-phase
operation reduces the RMS input ripple current, effec-
tively lowering the input capacitance requirements.
For a typical 300kHz application, the ESR zero frequency
must be well below 95kHz, preferably below 50kHz.
Tantalum and OS-CON capacitors in widespread use at
the time of publication have typical ESR zero frequencies
of 25kHz. In the design example used for inductor selec-
tion, the ESR needed to support 25mV ripple is 25mV /
P-P
1.5A = 16.7mΩ. One 220µF/4V Sanyo polymer (TPE)
capacitor provides 15mΩ (max) ESR. This results in a
zero at 48kHz, well within the bounds of stability.
28 ______________________________________________________________________________________
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Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
When both outputs operate with a duty cycle less than
50% (V > 2V ), the RMS input ripple current is
P o w e r MOS FET Dis s ip a t io n
Worst-case conduction losses occur at the duty-factor
IN
OUT
defined by the following equation:
extremes. For the high-side MOSFET (N ), the worst-
H
case power dissipation due to resistance occurs at
minimum input voltage:
⎛
⎞
V
OUT1
I
I
- I
(
)
OUT1 OUT1 IN
⎜
⎟
V
⎝
⎠
IN
⎛
⎞
I
=
V
2
RMS
OUT
PD (N Resistive) =
I
R
DS(ON)
(
)
⎛
⎞
H
LOAD
⎜
⎟
V
OUT2
V
⎝
⎠
+
I
I
(
- I
IN
)
OUT2 OUT2 IN
⎜
⎟
V
⎝
⎠
IN
Generally, use a small high-side MOSFET to reduce
switching losses at high input voltages. However, the
where I is the average input current:
IN
R
required to stay within package power-dissi-
DS(ON)
⎛
⎞
⎛
⎞
V
V
OUT2
V
IN
OUT1
pation limits often limits how small the MOSFET can be.
The optimum occurs when the switching losses equal
the conduction (R
I
=
I
+
I
OUT2
IN
OUT1
⎜
⎟
⎜
⎟
V
⎝
⎠
⎝
⎠
IN
) losses. High-side switching
DS(ON)
For most applications, nontantalum chemistries (ceram-
ic, aluminum, or OS-CON) are preferred due to their
resilience to power-up surge currents typical of sys-
tems with a mechanical switch or connector in series
with the input. If the MAX1549 is operated as the sec-
ond stage of a two-stage power-conversion system,
tantalum input capacitors are acceptable. In either con-
figuration, choose a capacitor that has less than 10°C
temperature rise at the RMS input current for optimal
reliability and lifetime.
losses do not become an issue until the input is greater
than approximately 15V.
Ca lc ula ting the p owe r d is s ip a tion in hig h-s id e
MOSFETs (N ) due to switching losses is difficult since
H
it must allow for difficult-to-quantify factors that influ-
e nc e the turn-on a nd turn-off time s . The s e fa c tors
inc lud e the inte rna l g a te re s is ta nc e , g a te c ha rg e ,
threshold voltage, source inductance, and PC-board-
layout characteristics. The following switching loss cal-
culation provides only a very rough estimate and is no
substitute for breadboard evaluation, preferably includ-
P o w e r MOS FET S e le c t io n
Most of the following MOSFET guidelines focus on the
c ha lle nge of obta ining high loa d-c urre nt c a pa bility
when using high-voltage (>20V) AC adapters. Low-cur-
rent applications usually require less attention.
ing verification using a thermocouple mounted on N :
H
2
V
C
f
I
(
)
IN(MAX)
RSS SW LOAD
PD (N Switching) =
H
I
GATE
The high-side MOSFET (N ) must be able to dissipate
H
the resistive losses plus the switching losses at both
where C
is the reverse transfer capacitance of N ,
H
RSS
and I
is the peak gate-drive source/sink current
GATE
V
and V . Ideally, the losses at V
IN(MAX) IN(MIN)
IN(MIN)
(1A typ).
should be roughly equal to the losses at V , with
IN(MAX)
lower losses in between. If the losses at V
significantly higher, consider increasing the size of N .
are
H
IN(MIN)
Switching losses in the high-side MOSFET can become
a heat problem when maximum AC-adapter voltages
are applied, due to the squared term in the switching-
Conversely, if the losses at V
are significantly
IN(MAX)
2
higher, consider reducing the size of N . If V does
H
IN
loss equation (C x V
x f ). If the high-side MOSFET
IN
SW
DS(ON)
not vary over a wide range, maximum efficiency is
achieved by selecting a high-side MOSFET (N ) that
has conduction losses equal to the switching losses.
chosen for adequate R
b e c ome s e xtra ord ina rily hot whe n s ub je c te d to
, c onside r c hoosing a nothe r MOSFET with
at low battery voltages
H
V
IN(MAX)
lower parasitic capacitance.
Choose a low-side MOSFET (N ) that has the lowest
L
possible on-resistance (R
), comes in a moder-
DS(ON)
For the low-side MOSFET (N ), the worst-case power
L
ate-sized package (i.e., 8-pin SO, DPAK, or D2PAK),
and is reasonably priced. Ensure that the MAX1549
DL_ gate driver can supply sufficient current to support
the gate charge and the current injected into the para-
sitic drain-to-gate capacitor caused by the high-side
MOSFET turning on; otherwise, cross-conduction prob-
lems can occur. Switching losses are not an issue for
the low-s id e MOSFET s inc e it is a ze ro-volta g e
switched device when used in the step-down topology.
dissipation always occurs at maximum battery voltage:
⎡
⎤
⎥
⎛
⎜
⎞
⎟
V
2
OUT
⎢
⎣
PD (N Resistive) = 1 -
I
R
DS(ON)
(
)
L
LOAD
V
⎢
⎥
⎦
⎝
IN(MAX) ⎠
______________________________________________________________________________________ 29
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Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
The absolute worst case for MOSFET power dissipation
occurs under heavy overload conditions that are greater
Ap p lic a t io n s In fo rm a t io n
Du t y-Cyc le Lim it s
than I
but are not high enough to exceed the
LOAD(MAX)
current limit and cause the fault latch to trip. To protect
against this possibility, “overdesign” the circuit to tolerate:
Minimum Input Voltage
The minimum input operating voltage (dropout voltage)
is restricted by the maximum duty-cycle specification
(see the Electrical Characteristics table). However,
keep in mind that the transient performance gets worse
as the step-down regulators approach the dropout volt-
age, so bulk output capacitance must be added (see
the volta g e s a g a nd s oa r e q ua tions in the De s ig n
Proc e d ure s e c tion). The a b s olute p oint of d rop out
occurs when the inductor current ramps down during
I
LIR
⎛
⎞
LOAD(MAX)
I
= I
-
LOAD
LIM
⎜
⎟
2
⎝
⎠
where I
is the peak current allowed by the current-limit
LIM
circuit, including threshold tolerance and sense-resis-
tance variation. The MOSFETs must have a relatively
large heatsink to handle the overload power dissipation.
the off-time (∆I
) as much as it ramps up during
the on-time (∆I ). This results in a minimum operating
Choose a Schottky diode (D ) with a forward-voltage
L
DOWN
UP
drop low enough to prevent the low-side MOSFET’s
body diode from turning on during the dead time. As a
general rule, select a diode with a DC current rating
equal to 1/3rd the load current. This diode is optional
and can be removed if efficiency is not critical.
voltage defined by the following equation:
⎛
⎞
1
V
=
V
+ V
+ h
− 1
V
+ V
(
)
IN(MIN)
OUT
CHG
OUT DIS
⎜
⎟
D
⎝
⎠
MAX
Bo o s t Ca p a c it o rs
) must be selected large
where V
and V
are the parasitic voltage drops in
CHG
DIS
The boost capacitors (C
BST
the charge and discharge paths, respectively. A rea-
sonable minimum value for h is 1.5, while the absolute
minimum input voltage is calculated with h = 1.
enough to handle the gate-charging requirements of
the hig h-s id e MOSFETs . Typ ic a lly, 0.1µF c e ra mic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current appli-
cations driving large, high-side MOSFETs require boost
capacitors larger than 0.1µF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the high-
side MOSFETs’ gates:
Maximum Input Voltage
The MAX1549 controller includes a minimum on-time
specification, which determines the maximum input
operating voltage that maintains the selected switching
frequency (see the Electrical Characteristics table).
Operation above this maximum input voltage results in
pulse-skipping operation, regardless of the operating
mod e s e le c te d b y SKIP. At the b e g inning of e a c h
cycle, if the output voltage is still above the feedback-
threshold voltage, the controller does not trigger an on-
time pulse, effectively skipping a cycle. This allows the
controller to maintain regulation above the maximum
input voltage, but forces the controller to effectively
operate with a lower switching frequency. This results
in an input-threshold voltage at which the controller
N × Q
GATE
200mV
C
=
BST
where N is the number of high-side MOSFETs used for
one regulator, and Q is the gate charge specified
in the MOSFET’s data sheet. For example, assume one
IRF7811W N-c ha nne l MOSFET is us e d on the hig h
side. According to the manufacturer’s data sheet, a sin-
gle IRF7811W has a maximum gate charge of 24nC
GATE
begins to skip pulses (V
):
IN(SKIP)
(V
= 5V). Using the above equation, the required
GS
⎛
⎞
boost capacitance is:
1
V
= V
OUT
⎜
⎟
IN(SKIP)
f
t
OSC ON(MIN)
⎝
⎠
1 × 24nC
200mV
C
=
= 0.12µF
BST
where f
is the switching frequency selected by FSEL.
OSC
Se le c ting the c lose st sta nda rd va lue , this e xa mple
requires a 0.1µF ceramic capacitor.
30 ______________________________________________________________________________________
Du a l, In t e rle a ve d , Fix e d -Fre q u e n c y S t e p -Do w n
Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
C1
1µF
+5V BIAS
SUPPLY
R1
20Ω
V
DD
INPUT (V )
IN
D
BST
V
CC
DH2
N
H2
C2
1µF
BST2
SKIP
C
BST
LX2
DL2
R7
R6
N
L2
D
L2
PGOOD1
PGOOD2
PGND
GND
L2
POWER-GOOD
CSH2
R
CS2
C
REF
MAX1549
0.22µF
REF
CSL2
OUT2
FB2
OUTPUT 2
= 2.5V
V
DDQ
R2
R3
V
DD
C
OUT2
ILIM1
ILIM2
D
BST
R4
R5
DH1
N
H1
BST1
C
BST
LX1
DL1
OUT2
R8
N
L1
D
L1
L1
REFIN
R9
C3
CSH1
R
CS1
CSL1
OUT1
OUTPUT 1
= V /2
FBLANK
OD3
OD2
0D1
V
TT DDQ
C
470pF
CC1
C
OUT1
UNUSED
CC1
FSEL
OPEN (300kHz)
G0
ON1
ON2
ON OFF
G1
POWER GROUND
ANALOG GROUND
Figure 9. Active Bus Termination
______________________________________________________________________________________ 31
Du a l, In t e rle a ve d , Fix e d -Fre q u e n c y S t e p -Do w n
Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
Figure 10 shows the connection of OUT_ and FB_ in volt-
age-positioned and nonvoltage-positioned circuits. In
nonvoltage-positioned circuits, the MAX1549 regulates
the voltage across the output capacitor. In voltage-posi-
tioned circuits, the MAX1549 regulates the voltage on the
inductor side of the current-sense resistor. The voltage-
positioned output voltage is reduced to:
Ac t ive Bu s Te rm in a t io n (OUT1 )
Active-bus-termination power supplies generate a voltage
rail that tracks a set reference. They are required to
source and sink current. DDR memory architecture
requires active bus termination. In DDR memory architec-
ture, the termination voltage is set at exactly 1/2 the mem-
ory s up p ly volta g e . Config ure the ma in MAX1549
controller (OUT1) to generate the termination voltage
using a resistive voltage-divider at REFIN. In such an
application, OUT1 must be kept in PWM mode (SKIP =
V
= V
- R I
SENSE LOAD
OUT(VPS)
OUT(NO LOAD)
For a conventional (nonvoltage-positioned) circuit, the
peak-to-peak voltage change is:
V
or open) for it to source and sink current. Figure 9
CC
∆V
= 2 x (ESR
x ∆I ) + V
LOAD SAG
shows OUT1 configured as a DDR termination regulator.
Connect GATE and FBLANK to GND when unused.
OUT(CONV)
COUT
SOAR
+ V
Vo lt a g e P o s it io n in g
Powe ring ne w mob ile p roc e s s ors (CPU or GPU)
requires careful attention to detail to reduce cost, size,
and power dissipation. As processors consume more
power, it was recognized that even the fastest DC-DC
converters were inadequate to handle the severe tran-
sient power requirements. After a load transient, the
whe re V
a nd V
a re d e fine d in Fig ure 11.
SOAR
SAG
Setting the converter to regulate at a lower voltage
when under load allows a larger voltage step when the
outp ut c urre nt s ud d e nly d e c re a s e s . The re fore , the
peak-to-peak voltage change for a voltage-positioned
circuit is:
∆V
= (ESR
x ∆I
) + V
+ V
OUT(VPS)
COUT
a re d e fine d in the De s ig n
SOAR
LOAD
SAG SOAR
outp ut ins ta ntly c ha ng e s b y ESR
x ∆I
.
COUT
LOAD
whe re V
a nd V
SAG
Conventional DC-DC converters respond by regulating
the output voltage back to its nominal state after the
load transient occurs (Figure 11), but the processor
only requires that the output voltage remains above a
specified minimum value. Dynamically positioning the
output voltage to this lower limit allows the use of fewer
output capacitors and reduces the power consumption
under load.
Procedure section. Since the amplitudes are the same
for both circuits (∆V = ∆V ), the volt-
age-positioned circuit tolerates twice the ESR. Since
the ESR specification is achieved by paralleling several
capacitors, fewer units are needed for the voltage-posi-
tioned circuit.
OUT(CONV)
OUT(VPS)
R1
+5V BIAS
SUPPLY
C2
V
DD
V
CC
D
BST
C1
V+
INPUT (V )
IN
C
IN
BST
N
H
REGULATED VOLTAGE
DH
VOLTAGE-POSITIONED
OUTPUT (V
C
BST
R
SENSE
L1
)
OUT(VPS)
MAX1549
LX
DL
N
L
C
OUT
D
L
GND
CSH
OUT
CSL
FB
V
= V
- R x I
OUT(VPS)
OUT(NO LOAD) SENSE OUT
Figure 10. Voltage-Positioned Applications Circuit
32 ______________________________________________________________________________________
Du a l, In t e rle a ve d , Fix e d -Fre q u e n c y S t e p -Do w n
Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
CAPACITIVE SOAR
(dV/dt = I / C
)
OUT OUT
VOLTAGE POSITIONING THE OUTPUT
ESR VOLTAGE STEP
(I x R
)
ESR
STEP
A
B
1.4V
1.4V
V
OUT
CAPACITIVE SAG
(dV/dt = I / C
)
RECOVERY
OUT OUT
A. CONVENTIONAL CONVERTER (50mV/div)
B. VOLTAGE-POSITIONED OUTPUT (50mV/div)
I
LOAD
Figure 11. Voltage-Positioning Transient Response
An additional benefit of voltage positioning is reduced
power consumption at high load currents. Since the out-
put voltage is lower under load, the processor draws less
current. The result is lower power dissipation in the
processor, although extra power is dissipated in the cur-
rent-sense element. However, the current-sense element
used for current-limit protection can also be used for
voltage positioning, further reducing the overall power
dissipation. In effect, the processor’s power dissipation
is saved and the power supply dissipates some of the
savings, but both the net savings and the transfer of dis-
sipation away from the hot processor are beneficial.
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance caus-
es a measurable efficiency penalty.
•
When tradeoffs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
•
•
Minimize c urre nt-s e ns ing e rrors b y c onne c ting
CSH_ and CSL_ directly across the current-sense
P C Bo a rd La yo u t Gu id e lin e s
Careful PC board layout is critical to achieving low switch-
ing losses and clean, stable operation. The switching
power stage requires particular attention (Figure 12). If
possible, mount all the power components on the top
side of the board, with their ground terminals flush
against one another. Refer to the MAX1549 evaluation kit
data sheet for a specific layout example. Follow these
guidelines for good PC board layout:
resistor (R
).
SENSE_
Route all high-speed switching nodes (BST_, LX_,
DH_, and DL_) away from sensitive analog areas
(REF, FB_, CSH_, and CSL_).
La yo u t P ro c e d u re
1) Place the power components first, with ground ter-
minals adjacent (N source, C , C , and D
L_
L_
IN
OUT_
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
•
•
•
Use a star-ground connection on the power ground
plane to minimize the crosstalk between OUT1 and
OUT2.
2) Mount the controller IC adjacent to the low-side
MOSFET, preferably on the back side opposite N
L_
Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
and N to keep LX_, DH_, and the DL_ gate-drive
H_
lines short and wide. The DL_ and DH_ gate traces
must be short and wide (50 mils to 100 mils wide if
the MOSFET is 1in from the controller IC) to keep
the driver impedance low and for proper adaptive
dead-time sensing.
Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
______________________________________________________________________________________ 33
Du a l, In t e rle a ve d , Fix e d -Fre q u e n c y S t e p -Do w n
Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
3) Group the gate-drive components (BST_ diode and
5) Connect the output power planes directly to the out-
put-filter-capacitor positive and negative terminals
with multiple vias. Place the entire DC-DC converter
circuit as close to the load as is practical.
capacitor, V bypass capacitor) together near the
DD
controller IC.
4) Make the DC-DC controller ground connections as
shown in Figures 1 and 12. These diagrams can be
vie we d a s ha ving two s e p a ra te g round p la ne s :
power ground for the high-power components, and
an analog ground plane for sensitive analog com-
ponents. These separate ground planes must meet
only at a single point directly at the IC. Additionally,
a star-ground connection (centered at PGND) must
be used on the power ground plane to minimize
any crosstalk between the two controllers.
Ch ip In fo rm a t io n
TRANSISTOR COUNT: 8823
PROCESS: BiCMOS
VIA TO ANALOG
GROUND PLANE
VIA TO 5V BIAS
SUPPLY (V
)
DD
VIA TO V
CC
BYPASS CAPACITOR
VIA TO POWER
GROUND
CONNECT THE
EXPOSED PAD TO
ANALOG GND
MAX1549
TOP LAYER
CONNECT GND
AND PGND TO THE
CONTROLLER AT
ONE POINT ONLY
AS SHOWN
KELVIN-SENSE VIAS
UNDER THE SENSE RESISTOR
(REFER TO THE EVALUATION KIT)
DUAL
N-CHANNEL
MOSFET
INDUCTOR
SINGLE
N-CHANNEL
MOSFETS
INDUCTOR
DH
LX
DL
C
OUT
C
OUT
INPUT
OUTPUT
C
OUT
OUTPUT
GROUND
INPUT
GROUND
HIGH-POWER LAYOUT
LOW-POWER LAYOUT
Figure 12. PC Board Layout Example
34 ______________________________________________________________________________________
Du a l, In t e rle a ve d , Fix e d -Fre q u e n c y S t e p -Do w n
Co n t ro lle r w it h a Dyn a m ic a lly Ad ju s t a b le Ou t p u t
P a c k a g e In fo rm a t io n
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
C
L
b
D/2
D2/2
k
E/2
E2/2
(NE-1) X
e
C
L
E
E2
k
L
e
(ND-1) X
e
e
L
C
C
L
L
L1
L
L
e
e
A
A1
A2
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
1
E
21-0141
2
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
2
E
21-0141
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0 ____________________ 35
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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