MAX1519ETL+ [MAXIM]
Switching Controller, Current-mode, 550kHz Switching Freq-Max, BICMOS, 6 X 6 MM, 0.80 MM HEIGHT, TQFN-40;
| 型号： | MAX1519ETL+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Switching Controller, Current-mode, 550kHz Switching Freq-Max, BICMOS, 6 X 6 MM, 0.80 MM HEIGHT, TQFN-40 控制器 |
| 文件： | 总43页 (文件大小：817K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2734; Rev 1; 9/03
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
General Description
Features
The MAX1519/MAX1545 are dual-phase, Quick-PWM™,
step-down controllers for desktop and mobile Pentium®4
(P4) CPU core supplies. Dual-phase operation reduces
input ripple current requirements and output voltage rip-
ple while easing component selection and layout difficul-
ties. The Quick-PWM control scheme provides
instantaneous response to fast load-current steps. The
MAX1519/MAX1545 include active voltage positioning
with adjustable gain and offset, reducing power dissipa-
tion and bulk output capacitance requirements.
o Dual-Phase, Quick-PWM Controllers
o ±±0.75 ꢀ Accuracy Over Line, Load, and
OUT
Temperature (103ꢀ)
o Active ꢀoltage Positioning with Adjustable Gain
and Offset
o 7-Bit On-Board DAC
Mobile: ±06±ꢀ to 10.7ꢀ Output Range
Desktop: 101±ꢀ to 1087ꢀ Output Range
o Selectable 1±±kHz/2±±kHz/3±±kHz/77±kHz
The MAX1519/MAX1545 are intended for two different
notebook CPU core applications: stepping down the bat-
tery directly or stepping down the 5V system supply to
create the core voltage. The single-stage conversion
method allows these devices to directly step down high-
voltage batteries for the highest possible efficiency.
Alternatively, two-stage conversion (stepping down the
5V system supply instead of the battery) at a higher
switching frequency provides the minimum possible
physical size.
Switching Frequency
o 4ꢀ to 28ꢀ Battery Input ꢀoltage Range
o Adjustable Slew-Rate Control
o Drive Large Synchronous Rectifier MOSFETs
o Output Overvoltage Protection (MAX1747 Only)
o Undervoltage and Thermal-Fault Protection
o Power Sequencing and Timing
o Selectable Suspend ꢀoltage (±06.7ꢀ to 1047ꢀ)
o Soft-Shutdown
The MAX1519/MAX1545 comply with Intel’s P4 specifi-
cations. The switching regulator features soft-start,
power-up sequencing, and soft-shutdown. The
MAX1519/MAX1545 also feature independent four-level
logic inputs for setting the suspend voltage (S0–S1).
o Selectable Single- or Dual-Phase Pulse Skipping
Ordering Information
The MAX1519/MAX1545 include output undervoltage
protection (UVP), thermal protection, and voltage regula-
tor power-OK (VROK) output. When any of these protec-
tion features detect a fault, the controller shuts down.
Additionally, the MAX1519/MAX1545 include overvoltage
protection.
PART
TEMP RANGE
PIN-PACKAGE
MAX1719ETL -40°C to +100°C
MAX1747ETL -40°C to +100°C
40 Thin QFN 6mm ✕ 6mm
40 Thin QFN 6mm ✕ 6mm
The MAX1519/MAX1545 are available in low-profile, 40-
pin, 6mm x 6mm thin QFN packages. For other CPU
platforms, refer to the pin-to-pin compatible MAX1544
and MAX1532/MAX1546/MAX1547 data sheets.
Pin Configuration
TOP VIEW
Applications
Desktop and Mobile P4 Computers
TIME
TON
SUS
S0
1
2
30
V
DD
29 DLM
28 DHM
27 LXM
26 BSTM
25 VROK
24 D0
Multiphase CPU Core Supply
3
Voltage-Positioned Step-Down Converters
Servers/Desktop Computers
4
S1
5
MAX1519
MAX1545
SHDN
OFS
REF
6
7
Low-Voltage, Digitally Programmable Power
Supplies
D1
8
23
ILIM
9
22 D2
21 D3
10
V
CC
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
Pentium is a registered trademark of Intel Corp.
THIN QFN
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
ABSOLUTE MAXIMUM RATINGS
V+ to GND..............................................................-0.3V to +30V
LXM to BSTM............................................................-6V to +0.3V
DHS to LXS..............................................-0.3V to (V + 0.3V)
LXS to BSTS .............................................................-6V to +0.3V
GND to PGND .......................................................-0.3V to +0.3V
REF Short-Circuit Duration .........................................Continuous
V
V
to GND..............................................................-0.3V to +6V
to PGND............................................................-0.3V to +6V
CC
DD
BSTS
SKIP, SUS, D0–D4 to GND.......................................-0.3V to +6V
ILIM, FB, OFS, CCV, CCI, REF, OAIN+,
OAIN- to GND.........................................-0.3V to (V
CMP, CSP, CMN, CSN, GNDS to GND......-0.3V to (V
TON, TIME, VROK, S0–S1, CODE to GND.-0.3V to (V
SHDN to GND (Note 1)...........................................-0.3V to +18V
DLM, DLS to PGND....................................-0.3V to (V + 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
Continuous Power Dissipation (T = +70°C)
40-Pin 6mm ✕ 6mm Thin QFN
(derate 23.2mW/°C above +70°C)...............................1.860W
Operating Temperature Range .........................-40°C to +100°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
A
CC
CC
CC
DD
BSTM, BSTS to GND ..............................................-0.3V to +36V
DHM to LXM ...........................................-0.3V to (V + 0.3V)
BSTM
Note 1: SHDN may be forced to 12V for the purpose of debugging prototype boards using the no-fault test mode, which disables
fault protection and overlapping operation.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, V
= V
= V
= V
= V
= V = V = V
= 5V, V = V
= V
= V = V
CSP CSN
CC
DD
SHDN
TON
SKIP
S0
S1
CODE
FB
CMP
CMN
= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; T = ±°C to +87°C, unless otherwise specified. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
Battery voltage, V+
, V
4
28
5.5
Input Voltage Range
V
V
4.5
-10
CC DD
DAC codes ≥ 1V
+10
V+ = 4.5V to 28V,
includes load
regulation error
DC Output Voltage Accuracy
(Note 2)
mV
DAC codes from
0.60V to 1V
-15
+15
Line Regulation Error
Input Bias Current
OFS Input Range
V
= 4.5V to 5.5V, V+ = 4.5V to 28V
5
mV
µA
V
CC
I
, I
FB, GNDS
OFS
-2
-0.1
0
+2
+0.1
2
FB GNDS
I
OFS
∆V
∆V
/∆V
OFS;
OUT
OFS
-0.129 -0.125 -0.117
-0.129 -0.125 -0.117
= V
V
= 0 to 1V
OFS, OFS
OFS Gain
A
OFS
V/V
∆V
∆V
/∆V
OFS;
OUT
OFS
= V
- V
V
= 1V to 2V
OFS
REF, OFS
GNDS Input Range
GNDS Gain
-20
0.97
900
460
225
+200
1.01
1100
540
mV
V/V
A
f
∆V
/∆V
GNDS
0.99
1000
500
GNDS
OUT
1000kHz nominal, R
= 15kΩ
TIME
500kHz nominal, R
250kHz nominal, R
= 30kΩ
= 60kΩ
TIME
TIME
TIME Frequency Accuracy
kHz
TIME
250
275
Shutdown, R
= 30kΩ
125
TIME
2
_______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= V
= V
= V
= V
= V = V = V
= 5V, V = V
= V
= V = V
CSP CSN
CC
DD
SHDN
TON
SKIP
S0
S1
CODE
FB
CMP
CMN
= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; T = 0°C to +85°C, unless otherwise specified. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
TON = GND
MIN
TYP
MAX
UNITS
155
180
205
390
(550kHz)
TON = REF
(300kHz)
320
475
920
355
525
V+ = 12V,
= V
On-Time (Note 3)
t
ns
ON
V
= 1.2V
CCI
FB
TON = open
(200kHz)
575
TON = V
CC
1000
1140
(100kHz)
TON = GND
TON = V , open, or REF
300
400
375
480
Minimum Off-Time (Note 3)
t
ns
OFF(MIN)
CC
BIAS AND REFERENCE
Measured at V , FB forced above the
CC
regulation point, OAIN- = FB,
Quiescent Supply Current (V
)
)
I
I
1.70
3.20
mA
CC
CC
V
= 1.3V
OAIN+
Measured at V , FB forced above the
DD
regulation point
Quiescent Supply Current (V
<1
25
5
µA
µA
DD
DD
Quiescent Battery Supply Current
(V+)
I
Measured at V+
40
V+
Shutdown Supply Current (V
Shutdown Supply Current (V
)
)
Measured at V , SHDN = GND
4
10
5
µA
µA
CC
CC
Measured at V , SHDN = GND
<1
DD
DD
Shutdown Battery Supply Current
(V+)
Measured at V+, SHDN = GND,
<1
5
µA
V
= V
= 0 or 5V
DD
CC
Reference Voltage
V
V
= 4.5V to 5.5V, I = 0
REF
1.990
-10
2.000
2.010
+10
V
REF
CC
Reference Load Regulation
FAULT PROTECTION
∆V
I
= -10µA to +100µA
mV
REF
REF
SKIP = V , measured at FB with respect
to unloaded output voltage
CC
13
16
2.00
10
19
73
%
V
Output Overvoltage Protection
Threshold (MAX1545 Only)
V
OVP
SKIP = REF or GND
Output Overvoltage Propagation
Delay (MAX1545 Only)
t
FB forced 2% above trip threshold
µs
OVP
Output Undervoltage Protection
Threshold
Measured at FB with respect to unloaded
output voltage
V
67
70
10
%
UVP
Output Undervoltage Propagation
Delay
t
FB forced 2% below trip threshold
µs
UVP
Lower threshold
(undervoltage)
-12
+8
-10
-8
Measured at FB
with respect to
unloaded output
voltage
VROK Threshold
%
Upper threshold
(overvoltage)
+10
+12
SKIP = V
CC
_______________________________________________________________________________________
3
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= V
= V
= V
= V
= V = V = V
= 5V, V = V
= V
= V = V
CSP CSN
CC
DD
SHDN
TON
SKIP
S0
S1
CODE
FB
CMP
CMN
= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; T = 0°C to +85°C, unless otherwise specified. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Undervoltage Fault and
VROK Transition Blanking Time
(Note 4)
Measured from the time when FB reaches
the voltage set by the DAC code; clock
t
24
Clks
BLANK
speed set by R
TIME
Measured from the time when FB first
reaches the voltage set by the DAC code
after startup
VROK Startup Delay
3
5
7
ms
µs
FB forced 2% outside the VROK trip
threshold
VROK Delay
t
10
VROK
VROK Output Low Voltage
VROK Leakage Current
I
= 3mA
0.4
1
V
SINK
High state, VROK forced to 5.5V
µA
V
Undervoltage Lockout
Rising edge, hysteresis = 90mV, PWM
disabled below this level
CC
V
4.0
28
4.25
160
4.4
V
UVLO(VCC)
Threshold
Thermal-Shutdown Threshold
CURRENT LIMIT AND BALANCE
T
Hysteresis = 10°C
°C
SHDN
Current-Limit Threshold Voltage
(Positive, Default)
V
V
CMP - CMN, CSP - CSN; ILIM = V
30
32
mV
mV
mV
mV
V
LIMIT
LIMIT
CC
V
V
= 0.2V
= 1.5V
8
10
75
12
77
ILIM
ILIM
Current-Limit Threshold Voltage
(Positive, Adjustable)
CMP - CMN,
CSP - CSN
73
Current-Limit Threshold Voltage
(Negative)
CMP - CMN, CSP - CSN; ILIM = V
,
CC
V
-41
-36
1.5
-31
LIMIT(NEG)
SKIP = V
CC
Current-Limit Threshold Voltage
(Zero Crossing)
V
CMP - CMN, CSP - CSN; SKIP = GND
ZERO
CMP, CMN, CSP, CSN Input
Ranges
0
-2
3
2
CMP, CMN, CSP, CSN Input
Current
V
V
= V
= 0 to 5V
CSN
+2
µA
CSP
ILIM
Secondary Driver-Disable
Threshold
V
-
-
CC
V
V
V
- 1
CC
V
nA
V
CSP
0.4
ILIM Input Current
I
= 0 to 5V
0.1
- 1
200
ILIM
Current-Limit Default Switchover
Threshold
V
CC
0.4
V
3
ILIM
CC
(V
- V
) - (V
- V
- V
) < 20mV,
); I
= 0,
CMP
CMN
CSP
CSN CCI
-20mV < (V
Current-Balance Offset
V
-2
+2
mV
µS
CMP
CMN
OS(IBAL)
1.0V < V
< 2.0V
CCI
Current-Balance
Transconductance
G
400
m(IBAL)
4
_______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= V
= V
= V
= V
= V = V = V
= 5V, V = V
= V
= V = V
CSP CSN
CC
DD
SHDN
TON
SKIP
S0
S1
CODE
FB
CMP
CMN
= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; T = 0°C to +85°C, unless otherwise specified. Typical values are at T = +25°C.)
A
A
PARAMETER
GATE DRIVERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DH_ Gate-Driver On-Resistance
R
BST_ - LX_ forced to 5V
1.0
1.0
0.4
4.5
4.5
2
Ω
Ω
ON(DH)
High state (pullup)
Low start (pulldown)
DL_ Gate-Driver On-Resistance
R
ON(DL)
DH_ Gate-Driver Source/Sink
Current
DH_ forced to 2.5V,
BST_ - LX_ forced to 5V
I
1.6
A
DH
DL_ Gate-Driver Sink Current
DL_ Gate-Driver Source Current
I
DL_ forced to 5V
DL_ forced to 2.5V
DL_ rising
4
A
A
DL(SINK)
I
1.6
35
26
DL(SOURCE)
Dead Time
t
ns
DEAD
DH_ rising
VOLTAGE-POSITIONING AMPLIFIER
Input Offset Voltage
V
-1
+1
mV
nA
OS
Input Bias Current
I
OAIN+, OAIN-
0.1
200
BIAS
V
0.4
-
CC
Op Amp Disable Threshold
V
3
0
V
- 1
V
V
OAIN-
CC
Common-Mode Input Voltage
Range
V
Guaranteed by CMRR test
2.5
CM
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
Large-Signal Voltage Gain
CMRR
PSRR
V
V
= V
= 0 to 2.5V
OAIN-
70
75
80
115
100
112
77
dB
dB
dB
OAIN+
= 4.5V to 5.5V
CC
A
R = 1kΩ to V /2
L CC
OA
V
V
- V
300
200
CC
FBH
|V
- V
OAIN-
| ≥ 10mV,
CC
OAIN+
Output Voltage Swing
mV
R = 1kΩ to V /2
L
47
FBL
Input Capacitance
11
pF
MHz
V/µs
pF
Gain-Bandwidth Product
Slew Rate
3
0.3
400
Capacitive-Load Stability
LOGIC AND I/O
No sustained oscillations
SHDN Input High Voltage
SHDN Input Low Voltage
SHDN No-Fault Threshold
V
0.8
V
V
V
IH
V
0.4
15
IL
V
12
2.7
1.2
SHDN
High
REF
Low
Three-Level Input Logic Levels
SUS, SKIP
V
2.3
0.8
+1
Logic Input Current
SHDN, SUS, SKIP
-1
µA
V
D0–D4 Logic Input High Voltage
D0–D4 Logic Input Low Voltage
1.6
0.8
V
_______________________________________________________________________________________
5
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= V
= V
= V
= V
= V = V = V
= 5V, V = V
= V
= V = V
CSP CSN
CC
DD
SHDN
TON
SKIP
S0
S1
CODE
FB
CMP
CMN
= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; T = 0°C to +85°C, unless otherwise specified. Typical values are at T = +25°C.)
A
A
PARAMETER
D0–D4 Input Current
SYMBOL
CONDITIONS
MIN
-2
TYP
MAX
UNITS
D0–D4
+2
µA
V
CODE Input High Voltage
CODE Input Low Voltage
CODE Input Current
2.4
0.8
+1
V
-1
µA
V
0.4
-
CC
High
Four-Level Input Logic Levels
Four-Level Input Current
TON, S0–S1
Open
REF
3.15
1.65
3.85
2.35
0.4
V
Low
TON, S0–S1 forced to GND or V
-3
+3
µA
CC
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, V
= V
= V
= V
= V
= V = V = V
= 5V, V = V
= V
= V
= V
CSN
CC
DD
SHDN
TON
SKIP
S0
S1
CODE
FB
CMP
CMN
CSP
= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; T = -40°C to +100°C, unless otherwise specified.) (Note 5)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
Battery voltage, V+
, V
4
28
5.5
Input Voltage Range
V
V
4.5
-13
CC DD
DAC codes ≥ 1V
+13
V+ = 4.5V to 28V,
includes load
regulation error
DC Output Voltage Accuracy
(Note 2)
mV
V
DAC codes from
0.60V to 1V
-20
0
+20
2
OFS Input Range
∆V
∆V
/∆V
OFS;
OUT
OFS
-0.131
-0.115
= V
V
= 0 to 1V
OFS, OFS
OFS Gain
A
V/V
OFS
∆V
∆V
/∆V
OFS;
OUT
OFS
-0.131
-0.115
= V
- V
V
= 1V to 2V
OFS
REF, OFS
GNDS Gain
A
f
∆V
/∆V
GNDS
0.94
880
450
220
1.01
1120
550
V/V
GNDS
OUT
1000kHz nominal, R
= 15kΩ
TIME
TIME Frequency Accuracy
500kHz nominal, R
= 30kΩ
= 60kΩ
kHz
TIME
TIME
TIME
250kHz nominal, R
280
TON = GND
(550kHz)
150
315
470
910
210
395
TON = REF
(300kHz)
V+ = 12V,
On-Time (Note 3)
t
ns
ns
ON
V
= V
= 1.2V
CCI
FB
TON = open
(200kHz)
580
TON = V
CC
1150
(100kHz)
TON = GND
TON = V , open, or REF
380
490
Minimum Off-Time (Note 3)
t
OFF(MIN)
CC
6
_______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= V
= V
= V
= V
= V = V = V
= 5V, V = V
= V
= V = V
CSP CSN
CC
DD
SHDN
TON
SKIP
S0
S1
CODE
FB
CMP
CMN
= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; T = -40°C to +100°C, unless otherwise specified.) (Note 5)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BIAS AND REFERENCE
Measured at V , FB forced above the
CC
Quiescent Supply Current (V
)
)
I
I
regulation point, OAIN- = FB,
3.2
mA
CC
CC
V
= 1.3V
OAIN+
Measured at V , FB forced above the
DD
regulation point
Quiescent Supply Current (V
20
50
µA
µA
DD
DD
Quiescent Battery Supply Current
(V+)
I
Measured at V+
V+
Shutdown Supply Current (V
Shutdown Supply Current (V
)
CC
)
DD
Measured at V , SHDN = GND
20
20
µA
µA
CC
Measured at V , SHDN = GND
DD
Shutdown Battery Supply Current
(V+)
Measured at V+, SHDN = GND,
20
µA
V
V
= V
= 0 or 5V
DD
CC
Reference Voltage
V
V
= 4.5V to 5.5V, I
= 0
REF
1.985
2.015
REF
CC
FAULT PROTECTION
Output Overvoltage Protection
Threshold (MAX1545 Only)
SKIP = V , measured at FB with respect
to unloaded output voltage
CC
V
V
13
67
19
73
-7
%
%
OVP
UVP
Output Undervoltage Protection
Threshold
Measured at FB with respect to unloaded
output voltage
Lower threshold
(undervoltage)
-13
Measured at FB
with respect to
unloaded output
voltage
VROK Threshold
%
Upper threshold
(overvoltage)
+7
+13
SKIP = V
CC
Measured from the time when FB first
reaches the voltage set by the DAC code
after startup
VROK Startup Delay
3
ms
V
V
Undervoltage Lockout
Rising edge, hysteresis = 90mV, PWM
disabled below this level
CC
V
3.90
4.45
33
UVLO(VCC)
Threshold
CURRENT LIMIT AND BALANCE
Current-Limit Threshold Voltage
(Positive, Default)
V
V
CMP - CMN, CSP - CSN; ILIM = V
27
mV
mV
mV
LIMIT
LIMIT
CC
V
V
= 0.2V
7
13
78
ILIM
ILIM
Current-Limit Threshold Voltage
(Positive, Adjustable)
CMP - CMN,
CSP - CSN
= 1.5V
72
Current-Limit Threshold Voltage
(Negative)
CMP - CMN, CSP - CSN; ILIM = V
,
CC
V
-30
-3
-42
LIMIT(NEG)
SKIP = V
CC
(V
CMP
- V
CMN
) - (V
- V ); I = 0,
CSN CCI
CSP
Current-Balance Offset
V
-20mV < (V
- V
CMN
) < 20mV,
+3
mV
OS(IBAL)
CMP
1.0V < V
< 2.0V
CCI
_______________________________________________________________________________________
7
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= V
= V
= V
= V
= V = V = V
= 5V, V = V
= V
= V = V
CSP CSN
CC
DD
SHDN
TON
SKIP
S0
S1
CODE
FB
CMP
CMN
= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; T = -40°C to +100°C, unless otherwise specified.) (Note 5)
A
PARAMETER
GATE DRIVERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DH_ Gate-Driver On-Resistance
R
BST_ - LX_ forced to 5V
4.5
4.5
2
Ω
Ω
ON(DH)
High state (pullup)
Low start (pulldown)
DL_ Gate-Driver On-Resistance
R
ON(DL)
VOLTAGE-POSITIONING AMPLIFIER
Input Offset Voltage
V
-2.0
0
+2.0
2.5
mV
V
OS
Common-Mode Input Voltage
Range
V
Guaranteed by CMRR test
CM
V
V
- V
300
200
CC
FBH
|V
- V
| ≥ 10mV,
CC
OAIN+
OAIN-
Output Voltage Swing
mV
R = 1kΩ to V /2
L
FBL
LOGIC AND I/O
SHDN Input High Voltage
SHDN Input Low Voltage
V
0.8
V
V
IH
V
0.4
IL
High
REF
Low
2.7
1.2
Three-Level Input Logic Levels
SUS, SKIP
2.3
0.8
V
D0–D4 Logic Input High Voltage
D0–D4 Logic Input Low Voltage
CODE Input High Voltage
1.6
2.4
V
V
V
V
0.8
0.8
CODE Input Low Voltage
V
0.4
-
CC
High
Open
REF
3.15
1.65
3.85
2.35
0.4
Four-Level Input Logic Levels
TON, S0–S1
V
Low
Note 2: DC output accuracy specifications refer to the trip level of the error amplifier. When pulse skipping, the output slightly rises
(< 0.5%) when transitioning from continuous conduction to no load.
Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DHM and DHS pins, with LX_ forced to
GND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in-
circuit times may be different due to MOSFET switching speeds.
Note 4: The output fault-blanking time is measured from the time when FB reaches the regulation voltage set by the DAC code.
During normal operation (SUS = GND), regulation voltage is set by the VID DAC inputs (D0–D4). During suspend mode
(SUS = REF or high), the regulation voltage is set by the suspend DAC inputs (S0–S1).
Note 5: Specifications to T = -40°C and +100°C are guaranteed by design and are not production tested.
A
8
_______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Typical Operating Characteristics
(Circuit of Figure 1, V = 12V, V
= V
= 5V, SHDN = SKIP = V , D0–D4 set for 1.5V (SUS = GND), S0–S1 set
IN
CC
DD CC
for 1V (SUS = V ), OFS = GND, T = +25°C, unless otherwise specified.)
CC
A
OUTPUT VOLTAGE vs. LOAD CURRENT
OUTPUT VOLTAGE vs. LOAD CURRENT
EFFICIENCY vs. LOAD CURRENT
(V
= 1.50V)
(V
= 1.00V)
(V
= 1.50V)
OUT
OUT
OUT
1.52
1.50
1.48
1.46
1.44
1.42
1.40
1.38
100
90
80
70
60
50
1.02
1.00
0.98
0.96
0.94
0.92
0.90
V
IN
= 8V
V
IN
= 12V
V
IN
= 20V
SKIP = REF
SKIP = V
CC
0.1
1
10
100
0
10
20
30
40
50
60
0
10
20
30
40
50
60
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
DUAL-PHASE EFFICIENCY vs. LOAD CURRENT
OUTPUT VOLTAGE vs. LOAD CURRENT
EFFICIENCY vs. LOAD CURRENT
(V
= 0.80V)
(V
= 0.80V)
(V
= 1.00V)
OUT
OUT
OUT
100
100
0.82
0.80
0.78
0.76
0.74
0.72
SKIP = REF
SUS = V
CC
V
IN
= 8V
V
= 8V
IN
90
80
70
60
90
80
70
60
V
IN
= 12V
V
= 12V
IN
V
IN
= 20V
V
IN
= 20V
SKIP = REF
SKIP = V
CC
50
50
0.1
1
10
100
0.1
1
10
100
0
10
20
30
40
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
SINGLE-PHASE EFFICIENCY
vs. LOAD CURRENT
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (FORCED-PWM MODE)
SWITCHING FREQUENCY
vs. LOAD CURRENT
(V
= 0.80V)
OUT
100
150
400
300
SKIP = GND
SKIP = V
CC
V
IN
= 8V
120
90
60
30
0
90
80
70
60
I + I
CC DD
FORCED-PWM (SKIP = V
SKIP MODE (SKIP = REF)
)
CC
200
100
0
V
IN
= 12V
V
IN
= 20V
1
I
IN
V
OUT
= 1V (NO LOAD)
50
0.1
10
100
0
5
10
15
20
25
30
0
10
20
LOAD CURRENT (A)
30
40
LOAD CURRENT (A)
INPUT VOLTAGE (V)
_______________________________________________________________________________________
9
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = 12V, V
= V
= 5V, SHDN = SKIP = V , D0–D4 set for 1.5V (SUS = GND), S0–S1 set
IN
CC
DD CC
for 1V (SUS = V ), OFS = GND, T = +25°C, unless otherwise specified.)
CC
A
OUTPUT OFFSET VOLTAGE
vs. OFS VOLTAGE
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (PULSE SKIPPING)
REFERENCE VOLTAGE
DISTRIBUTION
150
100
50
50
40
30
20
3.0
2.5
2.0
1.5
1.0
0.5
0
SAMPLE SIZE = 100
SKIP = REF
I + I
CC DD
0
-50
-100
-150
10
0
UNDEFINED
I
IN
REGION
0
0.5
1.0
1.5
2.0
1.990
1.995
2.005
2.010
0
5
10
15
20
25
30
2.000
OFS VOLTAGE (V)
REFERENCE VOLTAGE (V)
INPUT VOLTAGE (V)
CURRENT-BALANCE OFFSET
VOLTAGE DISTRIBUTION
CURRENT-LIMIT THRESHOLD
DISTRIBUTION
VOLTAGE-POSITIONING AMPLIFIER
GAIN AND PHASE vs. FREQUENCY
MAX1519 toc15
50
40
30
20
50
40
30
20
60
50
40
30
20
10
0
180
144
108
SAMPLE SIZE = 100
V
= 0.20V
ILIM
SAMPLE SIZE = 100
72
36
GAIN
0
-36
-10
-20
-30
-40
-72
PHASE
-108
10
0
10
0
-144
-180
10,000
0
10.0
CURRENT LIMIT (mV)
-2.50
-1.25
1.25
2.50
9.0
9.5
10.5
11.0
0.1
1
10
100
1000
OFFSET VOLTAGE (mV)
FREQUENCY (kHz)
INDUCTOR CURRENT DIFFERENCE
vs. LOAD CURRENT
VPS AMPLIFIER OFFSET VOLTAGE
vs. COMMON-MODE VOLTAGE
1.0
0.8
180
160
140
120
SKIP = REF
0.6
0.4
0.2
0
100
80
60
40
20
0
SKIP = V
CC
VPS AMPLIFIER
DISABLED
R
= 1mΩ
SENSE
10
0
20
30
40
50
0
1
2
3
4
5
LOAD CURRENT (A)
COMMON-MODE VOLTAGE (V)
10 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = 12V, V
= V
= 5V, SHDN = SKIP = V , D0–D4 set for 1.5V (SUS = GND), S0–S1 set
IN
CC
DD CC
for 1V (SUS = V ), OFS = GND, T = +25°C, unless otherwise specified.)
CC
A
SOFT-START
POWER-UP SEQUENCE
MAX1519 toc19
MAX1519 toc18
5V
5V
A
B
A
B
C
0V
1.5V
0V
2V
1V
0V
C
D
0V
5V
10A
0A
0V
0A
100µs/div
1ms/div
A. SHDN, 5V/div
A. SHDN, 5V/div
B. 1.5V OUTPUT, 1V/div
B. 1.5V OUTPUT, 1V/div
C. VROK, 5V/div
C. I , 10A/div
L1
D. I , 10A/div
L2
R
= 64.9kΩ
TIME
R
LOAD
= 75mΩ, R
= 64.9kΩ
TIME
1.50V LOAD TRANSIENT
(10A TO 50A LOAD)
SOFT-SHUTDOWN
MAX1519 toc21
MAX1519 toc20
5V
0V
50A
10A
A
B
A
B
1.5V
1.5V
0V
20A
10A
20A
0A
C
D
10A
0A
C
D
0A
20µs/div
200µs/div
A. LOAD CURRENT, (I
= 10A TO 50A), 50A/div
A. SHDN, 5V/div
LOAD
B. OUTPUT VOLTAGE (1.5V NO LOAD), 100mV/div
B. 1.5V OUTPUT, 1V/div
C. I , 10A/div
C. I , 10A/div
L1
L1
D. I , 10A/div
L2
D. I , 10A/div
L2
R
LOAD
= 75mΩ, R
= 64.9kΩ
TIME
______________________________________________________________________________________ 11
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = 12V, V
= V
= 5V, SHDN = SKIP = V , D0–D4 set for 1.5V (SUS = GND), S0–S1 set
IN
CC
DD CC
for 1V (SUS = V ), OFS = GND, T = +25°C, unless otherwise specified.)
CC
A
1.00V LOAD TRANSIENT
(10A TO 30A LOAD)
OFFSET TRANSITION
MAX1519 toc22
MAX1519 toc23
30A
10A
0.2V
0V
A
B
A
B
1.0V
10A
1.5V
0A
10A
C
D
5A
5A
C
D
0A
20µs/div
20µs/div
A. LOAD CURRENT, (I
= 10A TO 30A), 25A/div
A. V = 0 TO 200mV, 0.2V/div
OFS
OUT
LOAD
B. OUTPUT VOLTAGE (1.00V NO LOAD), 50mV/div
B. V
= 1.500V TO 1.475V, 20mV/div
C. I , 10A/div
C. I , 10A/div
L1
L1
D. I , 10A/div
L2
D. I , 10A/div
L2
10A LOAD
SUSPEND TRANSITION
(DUAL-PHASE PWM OPERATION)
SUSPEND TRANSITION
(SINGLE-PHASE SKIP OPERATION)
MAX1519 toc24
MAX1519 toc25
3.3V
0V
3.3V
0V
A
B
A
B
1.5V
1.0V
1.5V
1.0V
10A
0A
2.5A
2.5A
C
D
C
D
10A
0A
40µs/div
100µs/div
= 1.5V TO 1.0V, 0.5V/div
A. SUS, 5V/div
OUT
A. SUS, 5V/div
OUT
C. I , 10A/div
L1
B. V
= 1.5V TO 1.0V, 0.5V/div
B. V
C. I , 10A/div
L1
D. I , 10A/div
L2
D. I , 10A/div
L2
5A LOAD, SKIP = V , R
= 64.9kΩ
5A LOAD, C
= (4) 680µF, SKIP = SUS, R
= 64.9kΩ
TIME
CC TIME
OUT
12 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = 12V, V
= V
= 5V, SHDN = SKIP = V , D0–D4 set for 1.5V (SUS = GND), S0–S1 set
IN
CC
DD CC
for 1V (SUS = V ), OFS = GND, T = +25°C, unless otherwise specified.)
CC
A
SINGLE-PHASE SKIP TO DUAL-PHASE
DUAL-PHASE SKIP TO DUAL-PHASE
PWM TRANSITION
PWM TRANSITION
MAX1519 toc26
MAX1519 toc27
5V
2V
5V
A
B
A
B
1.5V
1.5V
0A
0A
C
D
0A
0A
C
D
20µs/div
20µs/div
A. SKIP = V TO GND, 5V/div
CC
B. 1.5V OUTPUT, 50mV/div
A. SKIP = V TO REF, 5V/div
CC
B. 1.5V OUTPUT, 50mV/div
C. I , 10A/div
L2
2A LOAD
L1
C. I , 10A/div
L2
2A LOAD
D. I , 10A/div
L1
D. I , 10A/div
100mV DAC CODE TRANSITION
400mV DAC CODE TRANSITION
MAX1519 toc28
MAX1519 toc29
3.3V
0V
3.3V
0V
A
B
A
B
1.5V
1.1V
1.5V
1.4V
5A
5A
5A
C
D
C
D
5A
40µs/div
A. D3, 5V/div
B. V = 1.50V TO 1.10V, 0.5V/div
20µs/div
A. D1, 5V/div
B. V = 1.50V TO 1.40V, 100mV/div
OUT
C. I , 10A/div
OUT
L1
C. I , 10A/div
D. I , 10A/div
L1
L2
10A LOAD
D. I , 10A/div
L2
10A LOAD
______________________________________________________________________________________ 13
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Pin Description
PIN
NAME
FUNCTION
Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A
150kΩ to 15kΩ resistor sets the clock from 100kHz to 1MHz, f = 500kHz × 30kΩ/R
1
TIME
.
TIME
SLEW
On-Time Selection Control Input. This four-level input sets the K-factor value used to determine the
2
3
TON
SUS
DH_ on-time (see the On-Time One-Shot TON section): GND = 550kHz, REF = 300kHz, OPEN =
200kHz, V
= 100kHz.
CC
Suspend Input. SUS is a three-level logic input. When the controller detects on-transition on SUS, the
controller slews the output voltage to the new voltage level determined by SUS, S0–S1, and D0–D4.
The controller blanks VROK during the transition and another 24 R
clock cycles after the new
TIME
DAC code is reached. Connect SUS as follows to select which multiplexer sets the nominal output
voltage:
3.3V or V (high) = suspend mode; S0–S1 low-range suspend code (Table 5),
CC
REF = suspend mode; S0–S1 high-range suspend code (Table 5),
GND = normal operation; D0–D4 VID DAC code (Table 4).
Suspend-Mode Voltage Select Inputs. S0–S1 are four-level digital inputs that select the suspend
mode VID code (Table 5) for the suspend mode multiplexer inputs. If SUS is high, the suspend mode
VID code is delivered to the DAC (see the Internal Multiplexers section), overriding any other voltage
setting (Figure 3).
4, 5
S0, S1
Shutdown Control Input. This input cannot withstand the battery voltage. Connect to V for normal
CC
operation. Connect to ground to put the IC into its 1µA (typ) shutdown state. During the transition from
normal operation to shutdown, the output voltage ramps down at 4 times the output-voltage slew rate
programmed by the TIME pin. In shutdown mode, DLM and DLS are forced to V to clamp the output to
DD
6
SHDN
ground. Forcing SH DN to 12V ~ 15V disables both overvoltage protection and undervoltage protection
circuits, disables overlap operation, and clears the fault latch. Do not connect SH DN to >15V.
Voltage-Divider Input for Offset Control. For 0 < V
< 0.8V, 0.125 times the voltage at OFS is
OFS
subtracted from the output. For 1.2V < V
is added to the output. Voltages in the range of 0.8V < V
disables the offset amplifier during suspend mode (SUS = REF or high).
< 2V, 0.125 times the difference between REF and OFS
OFS
7
8
OFS
REF
ILIM
< 1.2V are undefined. The controller
OFS
2V Reference Output. Bypass to GND with a 0.22µF or greater ceramic capacitor. The reference can
source 100µA for external loads. Loading REF degrades output voltage accuracy according to the
REF load regulation error.
Current-Limit Adjustment. The current-limit threshold defaults to 30mV if ILIM is tied to V . In
CC
adjustable mode, the current-limit threshold voltage is precisely 1/20 the voltage seen at ILIM over a
0.2V to 1.5V range. The logic threshold for switchover to the 30mV default value is approximately
9
V
- 1V.
CC
Analog Supply Voltage Input for PWM Core. Connect V
to the system supply voltage (4.5V to 5.5V)
CC
10
V
with a series 10Ω resistor. Bypass to GND with a 1µF or greater ceramic capacitor, as close to the IC
CC
as possible.
11
12
GND
CCV
Analog Ground. Connect the MAX1519/MAX1545’s exposed pad to analog ground.
Voltage Integrator Capacitor Connection. Connect a 47pF to 1000pF (47pF, typ) capacitor from CCV
to analog ground (GND) to set the integration time constant.
14 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Pin Description (continued)
PIN
NAME
FUNCTION
Ground Remote-Sense Input. Connect GNDS directly to the CPU ground-sense pin. GNDS internally
connects to an amplifier that adjusts the output voltage, compensating for voltage drops from the
regulator ground to the load ground.
13
GNDS
Current-Balance Compensation. Connect a 470pF capacitor between CCI and FB (see the Current-
Balance Compensation (CCI) section).
14
15
CCI
FB
Feedback Input. FB is internally connected to both the feedback input and the output of the voltage-
positioning op amp. See the Setting Voltage Positioning section to set the voltage-positioning gain.
Op Amp Inverting Input and Op Amp Disable Input. When using the internal op amp for additional
voltage-positioning gain, connect to the negative terminal of the current-sense resistor through a
16
17
OAIN-
resistor as described in the Setting Voltage Positioning section. Connect OAIN- to V to disable the
CC
op amp. The logic threshold to disable the op amp is approximately V
- 1V.
CC
Op Amp Noninverting Input. When using the internal op amp for additional voltage-positioning gain,
connect to the positive terminal of the current-sense resistor through a resistor as described in the
Setting Voltage Positioning section.
OAIN+
Pulse-Skipping Select Input. When pulse skipping, the controller blanks the VROK upper threshold:
3.3V or V (high) = Dual-phase forced-PWM operation,
CC
REF = Dual-phase pulse-skipping operation,
GND = Single-phase pulse-skipping operation.
18
19
SKIP
VID DAC Code Selection Output. Connect CODE to GND to select the desktop P4 code set, or
CODE
connect CODE to V
to select the mobile P4 code set (Table 4).
CC
Low-Voltage VID DAC Code Inputs. The D0–D4 inputs do not have internal pullups. These 1.0V logic
inputs are designed to interface directly with the CPU. In normal mode (Table 4, SUS = GND), the
output voltage is set by the VID code indicated by the logic-level voltages on D0–D4. In suspend
mode (Table 5, SUS = REF or high), the decoded state of the four-level S0–S1 inputs sets the output
voltage.
20–24
D4–D0
Open-Drain Power-Good Output. After output voltage transitions, except during power-up and power-
down, if OUT is in regulation, then VROK is high impedance. The controller blanks VROK whenever
the slew-rate control is active (output voltage transitions). VROK is forced low in shutdown. A pullup
resistor on VROK causes additional finite shutdown current. During power-up, VROK includes a 3ms
(min) delay after the output reaches the regulation voltage.
25
26
VROK
BSTM
Main Boost Flying Capacitor Connection. An optional resistor in series with BSTM allows the DHM
pullup current to be adjusted.
27
28
LXM
Main Inductor Connection. LXM is the internal lower supply rail for the DHM high-side gate driver.
Main High-Side Gate-Driver Output. Swings LXM to BSTM.
DHM
Main Low-Side Gate-Driver Output. DLM swings from PGND to V . DLM is forced high after the
DD
MAX1519/MAX1545 power down.
29
DLM
Supply Voltage Input for the DLM and DLS Gate Drivers. Connect to the system supply voltage (4.5V
30
V
to 5.5V). Bypass V
possible.
to PGND with a 2.2µF or greater ceramic capacitor as close to the IC as
DD
DD
______________________________________________________________________________________ 15
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Pin Description (continued)
PIN
NAME
FUNCTION
Power Ground. Ground connection for low-side gate drivers DLM and DLS.
31
PGND
Secondary Low-Side Gate-Driver Output. DLS swings from PGND to V . DLS is forced high after the
DD
MAX1519/MAX1545 power down.
32
33
34
DLS
DHS
LXS
Secondary High-Side Gate-Driver Output. Swings LXS to BSTS.
Secondary Inductor Connection. LXS is the internal lower supply rail for the DHS high-side gate
driver.
Secondary Boost Flying Capacitor Connection. An optional resistor in series with BSTS allows the
DHS pullup current to be adjusted.
35
36
BSTS
V+
Battery Voltage-Sense Connection. Used only for PWM one-shot timing. DH_ on-time is inversely
proportional to input voltage over a range of 4V to 28V.
37
38
39
40
CMP
CMN
CSN
CSP
Main Inductor Positive Current-Sense Input
Main Inductor Negative Current-Sense Input
Secondary Inductor Positive Current-Sense Input
Secondary Inductor Negative Current-Sense Input
loss, and RMS ripple current (see the Input Capacitor
Detailed Description
Dual 180° Out-of-Phase Operation
Selection section). As a result, the same performance
can be achieved with fewer or less expensive input
capacitors.
The two phases in the MAX1519/MAX1545 operate
180° out-of-phase (SKIP = REF or high) to minimize
input and output filtering requirements, reduce electro-
magnetic interference (EMI), and improve efficiency.
This effectively lowers component count—reducing
cost, board space, and component power require-
ments—making the MAX1519/MAX1545 ideal for high-
power, cost-sensitive applications.
Transient Overlap Operation
When a transient occurs, the response time of the con-
troller depends on how quickly it can slew the inductor
current. Multiphase controllers that remain 180° out-of-
phase when a transient occurs actually respond slower
than an equivalent single-phase controller. In order to
provide fast transient response, the MAX1519/
MAX1545 support a phase-overlap mode, which allows
the dual regulators to operate in-phase when heavy
load transients are detected, reducing the response
time. After either high-side MOSFET turns off and if the
output voltage does not exceed the regulation voltage
when the minimum off-time expires, the controller simul-
taneously turns on both high-side MOSFETs during the
next on-time cycle. This maximizes the total inductor-
current slew rate. The phases remain overlapped until
the output voltage exceeds the regulation voltage and
after the minimum off-time expires.
Typically, switching regulators provide transfer power
using only one phase instead of dividing the power
among several phases. In these applications, the input
capacitors must support high instantaneous current
requirements. The high-RMS ripple current can lower
efficiency due to I2R power loss associated with the input
capacitor’s effective series resistance (ESR). Therefore,
the system typically requires several low-ESR input
capacitors in parallel to minimize input voltage
ripple, reduce ESR-related power losses, and to meet
the necessary RMS ripple current rating.
With the MAX1519/MAX1545, the controller shares the
current between two phases that operate 180° out-of-
phase, so the high-side MOSFETs never turn on simul-
taneously during normal operation. The instantaneous
input current of either phase is effectively cut in half,
resulting in reduced input voltage ripple, ESR power
After the phase-overlap mode ends, the controller auto-
matically begins with the opposite phase. For example, if
the secondary phase provided the last on-time pulse
before overlap operation began, the controller starts
switching with the main phase when overlap operation
ends.
16 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Table 1. Component Selection for Standard Multiphase Applications*
MAX1519/MAX1545
MAX1519/MAX1545
2-PHASE DESKTOP P4
4- PHASE DESKTOP P4
DESIGNATION
Circuit of Figure 1
Circuit of Figure 12
Input Voltage Range
7V to 24V
7V to 24V
VID Output Voltage
1.5V
1.5V
(D4–D0)
(CODE = GND, D4–D0 = 01110)
(CODE = GND, D4–D0 = 01110)
Suspend Voltage
Not Used
Not Used
(SUS, S0–S1)
(SUS = GND)
(SUS = GND)
Maximum Load Current
60A
60A
Two phases
(1) MAX1519/MAX1545
Four phases
(1) MAX1519/MAX1545 + (2) MAX1980
Number of Phases (η
)
TOTAL
0.6µH
0.7µH Panasonic ETQP2H0R7BFA or
0.8µH Sumida CDEP105L-0R8
Inductor (per phase)
Panasonic ETQP1H0R6BFA
Switching Frequency
High-Side MOSFET
(N , per phase)
H
300kHz (TON = REF)
300kHz (TON = REF)
Siliconix (1) Si7886DP
International Rectifier (2) IRF6604
International Rectifier (1) IRF7811W or
Fairchild (1) FDS6694
Low-Side MOSFET
(N , per phase)
L
Siliconix (2) Si7442DP or
International Rectifier (2) IRF6603
Fairchild (2) FDS6688 or
Siliconix (1) Si7442DP
(6) 10µF, 25V
(6) 10µF, 25V
Total Input Capacitance (C
)
IN
Taiyo Yuden TMK432BJ106KM or
TDK C4532X5R1E106M
Taiyo Yuden TMK432BJ106KM or
TDK C4532X5R1E106M
Total Output Capacitance
(4) 680µF, 2.5V
(4) 680µF, 2.5V
(C
)
Sanyo 2R5TPD680M
Sanyo 2R5TPD680M
OUT
Current-Sense Resistor
(R , per phase)
1.0mΩ
1.5mΩ
Panasonic ERJM1WTJ1M0U
Panasonic ERJM1WTJ1M5U
SENSE
*Contact Intel for the Mobile P4 specifications and contact Maxim for a reference schematic.
troller pulls VROK low until at least 3ms after the
MAX1519/MAX1545 reach the target DAC code.
Power-Up Sequence
The MAX1519/MAX1545 are enabled when SHDN is
driven high (Figure 2). The reference powers up first.
Once the reference exceeds its undervoltage lockout
threshold, the PWM controller evaluates the DAC target
and starts switching.
Shutdown
When SHDN goes low, the MAX1519/MAX1545 enter
low-power shutdown mode. VROK is pulled low imme-
diately, and the output voltage ramps down to 0V in
25mV increments at 4 times the clock rate set by
For the MAX1519/MAX1545, the slew-rate controller
ramps up the output voltage in 25mV increments to the
proper operating voltage (see Tables 3 and 4) set by
either D0–D4 (SUS = GND) or S0–S1 (SUS = REF or
R
TIME
:
4
V
DAC
high). The ramp rate is set with the R
resistor (see
t
≤
TIME
SHDN
f
V
SLEW
LSB
the Output Voltage Transition Timing section). The con-
______________________________________________________________________________________ 17
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
5V BIAS
SUPPLY
C1
2.2µF
R10
10Ω
R11
BST
V
DD
100kΩ
V
DIODES
CC
U1
C2
1µF
MAX1519
MAX1545
INPUT*
V+
7V TO 24V
POWER-
GOOD
C
IN
BSTM
DHM
VROK
C
BST1
0.22µF
D0
D1
D2
D3
D4
R
DAC INPUTS
SENSE1
1.0mΩ
N
H1
C
OUT
L1
LXM
DLM
GND (DESKTOP P4)
SUSPEND INPUTS
CODE
S0
S1
N
L1
(FOUR-LEVEL LOGIC)
PGND
GND
R3
ON
1kΩ
SHDN
R2
1kΩ
1%
OFF
R
TIME
1%
R6
64.9kΩ
TIME
CMN
CMP
OAIN+
OAIN-
1.5kΩ
1%
C
47pF
CCV
CCV
OUTPUT
REF (300kHz)
C
R1
REF
0.22µF
TON
REF
1.5kΩ
1%
R8
100kΩ
1%
R4
1kΩ
1%
R9
FB
49.9kΩ
C
CCI
470pF
1%
R5
ILIM
OFS
1kΩ
CCI
CSP
CSN
1%
REF
C
IN
R28
182kΩ
1%
BSTS
C
BST2
C3
100pF
0.22µF
DHS
LXS
DLS
R
SENSE2
1.0mΩ
N
H2
L2
R27
20kΩ
1%
STP_CPU#
SKIP
C
OUT
N
L2
PWM
SKIP
SUS
GNDS
*LOWER INPUT VOLTAGES
REQUIRE ADDITIONAL
INPUT CAPACITANCE.
POWER GROUND
ANALOG GROUND
Figure 1. Standard Two-Phase Desktop P4 Application Circuit
18 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
SHDN
VID (D0–D4)
DO NOT CARE
SOFT-SHUTDOWN
SOFT-START
1LSB PER R CYCLE
1LSB PER 4 R
CYCLES
TIME
TIME
V
CORE
VROK
t
VROK(START)
3ms, TYP
Figure 2. Power-Up and Shutdown Sequence Timing Diagram
Table 2. Component Suppliers
MANUFACTURER
BI Technologies
PHONE
WEBSITE
www.bitechnologies.com
714-447-2345 (USA)
631-435-1110 (USA)
800-322-2645 (USA)
561-752-5000 (USA)
888-522-5372 (USA)
310-322-3331 (USA)
408-986-0424 (USA)
847-468-5624 (USA)
65-6281-3226 (Singapore)
203-268-6261 (USA)
408-982-9660 (USA)
www.centralsemi.com
www.coilcraft.com
www.coiltronics.com
www.fairchildsemi.com
www.irf.com
Central Semiconductor
Coilcraft
Coiltronics
Fairchild Semiconductor
International Rectifier
Kemet
www.kemet.com
www.panasonic.com
www.secc.co.jp
Panasonic
Sanyo
www.vishay.com
www.sumida.com
Siliconix (Vishay)
Sumida
03-3667-3408 (Japan)
408-573-4150 (USA)
www.t-yuden.com
Taiyo Yuden
847-803-6100 (USA)
www.component.tdk.com
www.tokoam.com
TDK
81-3-5201-7241 (Japan)
858-675-8013 (USA)
TOKO
where f
= 500kHz ✕ 30kΩ/R
, V is the DAC
This eliminates the need for the Schottky diode normally
connected between the output and ground to clamp the
negative output voltage excursion. When the DAC
reaches the 0V setting, DL_ goes high, DH_ goes low,
the reference turns off, and the supply current drops to
about 1µA. When a fault condition—output undervoltage
lockout, output overvoltage lockout (MAX1545), or ther-
mal shutdown—activates the shutdown sequence, the
controller sets the fault latch to prevent the controller from
restarting. To clear the fault latch and reactivate the con-
SLEW
TIME DAC
setting when the controller begins the shutdown
sequence, and V = 25mV is the DAC’s smallest volt-
LSB
age increment. Slowly discharging the output capacitors
by slewing the output over a long period of time
(4/f
) keeps the average negative inductor current
SLEW
low (damped response), thereby eliminating the nega-
tive output voltage excursion that occurs when the con-
troller discharges the output quickly by permanently
turning on the low-side MOSFET (underdamped
response).
troller, toggle SHDN or cycle V power below 1V.
CC
______________________________________________________________________________________ 19
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Table 3. Operating Mode Truth Table
OUTPUT
VOLTAGE
SHDN
SUS
x
SKIP
OFS
x
OPERATING MODE
Low-Power Shutdown Mode. DL_ is forced high, DH_ is
forced low, and the PWM controller is disabled. The supply
current drops to 1µA (typ).
GND
x
GND
D0–D4
(no offset)
Normal Operation. The no-load output voltage is determined by
the selected VID DAC code (CODE and D0–D4, Table 4).
V
V
GND
V
GND or REF
CC
CC
CC
Pulse-Skipping Operation. When SKIP is pulled low, the
MAX1519/MAX1545 immediately enter pulse-skipping
operation, allowing automatic PWM/PFM switchover under
light loads. The VROK upper threshold is blanked.
REF
or
GND
D0–D4
(no offset)
x
GND or REF
0 to 0.8V
or
1.2V to 2V
Deep-Sleep Mode. The no-load output voltage is determined
by the selected VID DAC code (CODE and D0–D4, Table 4),
plus the offset voltage set by OFS.
D0–D4
(plus offset)
V
V
GND
x
x
CC
CC
REF
or
high
Suspend Mode. The no-load output voltage is determined by
the selected suspend code (SUS, S0–S1, Table 5),
overriding all other active modes of operation.
SUS, S0–S1
(no offset)
x
x
Fault Mode. The fault latch has been set by either UVP, OVP
(MAX1545 only), or thermal shutdown. The controller
V
x
x
GND
CC
remains in FAULT mode until V
toggled.
power is cycled or SHDN
CC
a new output voltage level. Change D0–D4 together,
avoiding greater than 1µs skew between bits.
Otherwise, incorrect DAC readings can cause a partial
transition to the wrong voltage level followed by the
intended transition to the correct voltage level, length-
ening the overall transition time. The available DAC
codes and resulting output voltages are compatible
with desktop and mobile P4 (Table 4) specifications.
When SHDN goes high, the reference powers up. Once
the reference voltage exceeds its UVLO threshold, the
controller evaluates the DAC target and starts switching.
The slew-rate controller ramps up from 0V in 25mV
increments to the currently selected output-voltage set-
ting (see the Power-Up Sequence section). There is no
traditional soft-start (variable current-limit) circuitry, so
full output current is available immediately.
Four-Level Logic Inputs
TON and S0–S1 are four-level logic inputs. These
inputs help expand the functionality of the controller
without adding an excessive number of pins. The four-
level inputs are intended to be static inputs. When left
open, an internal resistive voltage-divider sets the input
voltage to approximately 3.5V. Therefore, connect the
Internal Multiplexers
The MAX1519/MAX1545 have a unique internal DAC
input multiplexer (muxes) that selects one of three differ-
ent DAC code settings for different processor states
(Figure 3). On startup, the MAX1519/MAX1545 select the
DAC code from the D0–D4 (SUS = GND) or S0–S1 (SUS
= REF or high) input decoders.
four-level logic inputs directly to V , REF, or GND
CC
DAC Inputs (CODE, D0–D4)
During normal forced-PWM operation (SUS = GND), the
DAC programs the output voltage using code and the
when selecting one of the other logic levels. See
Electrical Characteristics for exact logic level voltages.
Suspend Mode
When the processor enters low-power suspend mode, it
sets the regulator to a lower output voltage to reduce
power consumption. The MAX1519/MAX1545 include
D0–D4 inputs. Connect CODE to V
or GND for the
CC
mobile or desktop P4 setting, respectively. Do not leave
D0–D4 unconnected. D0–D4 can be changed while the
MAX1519/MAX1545 are active, initiating a transition to
20 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
D0–D4
DECODER
D0
D1
IN
D2
D3
D4
SUSPEND
MUX
OUT
0
1
CODE
SEL
S0–S1
DECODER
S0
S1
IN
DAC
OUT
OUT
SEL
SEL
SUS
2.5V
1.0V
SUS 3-LEVEL
DECODER
Figure 3. Internal Multiplexers Functional Diagram
independent suspend-mode output voltage codes set by
the four-level S0–S1 inputs and the three-level SUS input.
When the CPU suspends operation (SUS = REF or high),
the controller disables the offset amplifier and overrides
the 5-bit VID DAC code set by D0–D4 (normal operation).
The master controller slews the output to the selected
suspend-mode voltage. During the transition, the
MAX1519/MAX1545 blank VROK and the UVP fault pro-
ing input surge currents. This feature allows the circuit
designer to achieve nearly ideal transitions, guaranteeing
just-in-time arrival at the new output voltage level with the
lowest possible peak currents for a given output capaci-
tance.
At the beginning of an output voltage transition, the
MAX1519/MAX1545 blank the VROK output, preventing
them from changing states. VROK remains blanked dur-
ing the transition and is enabled 24 clock cycles after the
slew-rate controller has set the final DAC code value.
tection until 24 R
clock cycles after the slew-rate con-
TIME
troller reaches the suspend-mode voltage.
SUS is a three-level logic input: GND, REF, or high. This
expands the functionality of the controller without
adding an additional pin. This input is intended to be
driven by a dedicated open-drain output with the pullup
resistor connected either to REF (or a resistive-divider
The slew-rate clock frequency (set by resistor R
)
TIME
must be set fast enough to ensure that the transition is
completed within the maximum allotted time.
The slew-rate controller transitions the output voltage in
25mV steps during soft-start, soft-shutdown, and sus-
pend-mode transitions. The total time for a transition
from V ) or to a logic-level bias supply (3.3V or
CC
greater). When pulled up to REF, the MAX1519/
MAX1545 select the upper suspend voltage range.
When pulled high (2.7V or greater), the controller
selects the lower suspend voltage range. See Electrical
Characteristics for exact logic level voltages.
depends on R
, the voltage difference, and the
TIME
accuracy of the MAX1519/MAX1545s’ slew-rate clock,
and is not dependent on the total output capacitance.
The greater the output capacitance, the higher the
surge current required for the transition. The
MAX1519/MAX1545 automatically control the current to
the minimum level required to complete the transition in
the calculated time, as long as the surge current is less
Output Voltage Transition Timing
The MAX1519/MAX1545 are designed to perform mode
transitions in a controlled manner, automatically minimiz-
______________________________________________________________________________________ 21
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
SUS
1 LSB PER R
CYCLE
TIME
V
DAC
OUTPUT SET BY D0–D4
OUTPUT SET BY SUS AND S0–S1
t
t
= 24 CLKS
t
t
= 24 CLKS
SLEW
BLANK
SLEW
BLANK
TIME
CLOCK
VROK
VROK BLANKING
VROK BLANKING
Figure 4. Suspend Transition
than the current limit set by ILIM. The transition time is
given by:
an overvoltage fault. During normal forced-PWM opera-
tion (SKIP = high), the controller detects an OVP fault if
the output voltage exceeds the set DAC voltage by
more than 13% (min). During pulse-skipping operation
(SKIP = REF or GND), the controller detects an OVP
fault if the output voltage exceeds the fixed 2V (typ)
threshold. When the OVP circuit detects an overvoltage
fault, it immediately sets the fault latch, pulls VROK low,
and activates the shutdown sequence.
1
V
− V
NEW
OLD
t
≈
for V
rising
SLEW
OUT
f
V
SLEW
LSB
1
V
− V
OLD
NEW
t
≈
+2 for V
falling
SLEW
OUT
f
V
SLEW
LSB
where f
= 500kHz ✕ 30kΩ / R
, V
is the
OLD
SLEW
TIME
This action discharges the output filter capacitor and
forces the output to ground. If the condition that caused
the overvoltage (such as a shorted high-side MOSFET)
persists, the battery fuse blows. The controller remains
shut down until the fault latch is cleared by toggling
original DAC setting, V
is the new DAC setting, and
NEW
V
is the DAC’s smallest voltage increment. The
LSB
additional two clock cycles on the falling edge time are
due to internal synchronization delays. See TIME
Frequency Accuracy in the Electrical Characteristics for
SHDN or cycling the V power supply below 1V.
CC
f
limits.
SLEW
Overvoltage protection can be disabled through the “no-
fault” test mode (see the No-Fault Test Mode section).
The practical range of R
is 15kΩ to 150kΩ corre-
TIME
sponding to 1.0µs to 10µs per 25mV step. Although the
DAC takes discrete steps, the output filter makes the
transitions relatively smooth. The average inductor cur-
rent required to make an output voltage transition is:
Output Undervoltage Shutdown
The output UVP function is similar to foldback current
limiting, but employs a timer rather than a variable current
limit. If the MAX1519/MAX1545 output voltage is under
70% of the nominal value, the controller activates the
shutdown sequence and sets the fault latch.
I ≅ C
× V × f
LSB SLEW
L
OUT
Fault Protection
Output Overvoltage Protection
(MAX1545 Only)
Once the controller ramps down to the 0V DAC code
setting, it forces the DL_ low-side gate-driver high, and
pulls the DH_ high-side gate-driver low. Toggle SHDN
or cycle the V
power supply below 1V to clear the
CC
The overvoltage protection (OVP) circuit is designed to
protect the CPU against a shorted high-side MOSFET by
drawing high current and blowing the battery fuse. The
MAX1519/MAX1545 continuously monitor the output for
fault latch and reactivate the controller. UVP is ignored
during output voltage transitions and remains blanked
22 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Table 4. Output Voltage VID DAC Codes (SUS = GND)
CODE = V
CODE = GND
D1
CC
OUTPUT
VOLTAGE
(V)
OUTPUT
VOLTAGE
(V)
D4
D3
D2
D1
D0
D4
D3
D2
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.750
1.700
1.650
1.600
1.550
1.500
1.450
1.400
1.350
1.300
1.250
1.200
1.150
1.100
1.050
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
0.775
0.750
0.725
0.700
0.675
0.650
0.625
0.600
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.850
1.825
1.800
1.775
1.750
1.725
1.700
1.675
1.650
1.625
1.600
1.575
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.300
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
Shutdown
for an additional 24 clock cycles after the controller
reaches the final DAC code value.
Thermal-Fault Protection
The MAX1519/MAX1545 feature a thermal fault-protec-
tion circuit. When the junction temperature rises above
+160°C, a thermal sensor activates the fault latch and
activates the soft-shutdown sequence. Once the con-
UVP can be disabled through the “no-fault” test mode
(see the No-Fault Test Mode section).
______________________________________________________________________________________ 23
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Table 5. Suspend Mode DAC Codes
LOWER SUSPEND CODES
UPPER SUSPEND CODES
OUTPUT
VOLTAGE
(V)
OUTPUT
VOLTAGE
(V)
SUS*
S1
S0
SUS*
S1
S0
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
GND
GND
GND
GND
REF
GND
REF
0.675
0.700
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
GND
GND
GND
GND
REF
GND
REF
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
OPEN
OPEN
V
CC
V
CC
GND
REF
GND
REF
REF
REF
REF
OPEN
REF
OPEN
REF
V
CC
REF
V
CC
OPEN
OPEN
OPEN
OPEN
GND
REF
OPEN
OPEN
OPEN
OPEN
GND
REF
OPEN
OPEN
V
CC
V
CC
V
V
V
V
GND
REF
CC
CC
CC
CC
V
V
V
V
GND
REF
CC
CC
CC
CC
OPEN
OPEN
V
CC
V
CC
*Connect the three-level SUS input to a 2.7V or greater supply (3.3V or V ) for an input logic level high.
CC
troller ramps down to the 0V DAC code setting, it forces
the DL_ low-side gate-driver high, and pulls the DH_
high-side gate-driver low. Toggle SHDN or cycle the
supply is the notebook’s 95%-efficient 5V system sup-
ply. Keeping the bias supply external to the IC
improves efficiency and eliminates the cost associated
with the 5V linear regulator that would otherwise be
needed to supply the PWM circuit and gate drivers. If
stand-alone capability is needed, the 5V bias supply
can be generated with an external linear regulator.
V
power supply below 1V to clear the fault latch and
CC
reactivate the controller after the junction temperature
cools by 15°C.
Thermal shutdown can be disabled through the “no-fault”
test mode (see the No-Fault Test Mode section).
The 5V bias supply must provide VCC (PWM controller)
and VDD (gate-drive power), so the maximum current
drawn is:
No-Fault Test Mode
The latched-fault protection features and overlap mode
can complicate the process of debugging prototype
breadboards since there are (at most) a few milliseconds
in which to determine what went wrong. Therefore, a “no-
fault” test mode is provided to disable the fault protection
(overvoltage protection, undervoltage protection, and
thermal shutdown) and overlap mode. Additionally, the
test mode clears the fault latch if it has been set. The no-
fault test mode is entered by forcing 12V to 15V
on SHDN.
I
= I
+ f (Q
+ Q
)
BIAS
CC
SW G(LOW)
G(HIGH)
where ICC is provided in the Electrical Characteristics,
fSW is the switching frequency, and QG(LOW) and QG(HIGH)
are the MOSFET data sheet’s total gate-charge specifi-
cation limits at V
= 5V. V+ and V
can be tied
DD
GS
together if the input power source is a fixed 4.5V to 5.5V
supply. If the 5V bias supply is powered up prior to the
battery supply, the enable signal (SHDN going from low
to high) must be delayed until the battery voltage is pre-
sent to ensure startup.
Multiphase Quick-PWM
Free-Running, Constant On-Time PWM
Controller with Input Feed Forward
The Quick-PWM control architecture is a pseudo-fixed-
frequency, constant-on-time, current-mode regulator
5V Bias Supply (V
and V
)
CC
DD
The Quick-PWM controller requires an external 5V bias
supply in addition to the battery. Typically, this 5V bias
24 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
with input voltage feed forward (Figure 5). This archi-
Table 6. Approximate K-Factor Errors
tecture relies on the output filter capacitor’s ESR to act
as the current-sense resistor, so the output ripple volt-
age provides the PWM ramp signal. The control algo-
rithm is simple: the high-side switch on-time is
determined solely by a one-shot whose period is
inversely proportional to the input voltage, and directly
proportional to the output voltage or the difference
between the main and secondary inductor currents
(see the On-Time One-Shot (TON) section). Another
one-shot sets a minimum off-time. The on-time one-shot
triggers when the error comparator goes low, the induc-
tor current of the selected phase is below the valley current-
limit threshold, and the minimum off-time one-shot times out.
The controller maintains 180° out-of-phase operation by
alternately triggering the main and secondary phases after
the error comparator drops below the output voltage set
point.
MAX
FREQUENCY
SETTING
(kHz)
TON
CONNECTION
K-FACTOR
(µs)
K-FACTOR
ERROR
(%)
V
100
200
300
550
10
5
10
10
CC
Float
REF
3.3
1.8
10
GND
12.5
where Z
is the impedance at the CCI output. The
CCI
secondary on-time one-shot uses this integrated signal
(V ) to set the secondary high-side MOSFETs on-time.
CCI
When the main and secondary current-sense signals
(V
= V
- V
and V = V
- V
) become
CM
CMP
CMN
CS
CSP
CSM
unbalanced, the transconductance amplifiers adjust the
secondary on-time, which increases or decreases the
secondary inductor current until the current-sense
signals are properly balanced:
On-Time One-Shot (TON)
The core of each phase contains a fast, low-jitter,
adjustable one-shot that sets the high-side MOSFETs
on-time. The one-shot for the main phase varies the on-
time in response to the input and feedback voltages.
The main high-side switch on-time is inversely propor-
tional to the input voltage as measured by the V+ input,
V
+ 0.075V
CCI
t
=K
=K
ON(2ND)
V
IN
V
+ 0.075V
I
Z
FB
and proportional to the feedback voltage (V ):
FB
CCI CCI
+ K
V
V
IN
IN
K V + 0.075V
(
)
FB
= (Main On− Time) +
(Secondary Current Balance Correction)
t
ON(MAIN) =
V
IN
where K is set by the TON pin-strap connection (Table 6)
and 0.075V is an approximation to accommodate the
expected drop across the low-side MOSFET switch.
This algorithm results in a nearly constant switching
frequency and balanced inductor currents, despite the
lack of a fixed-frequency clock generator. The benefits of
a constant switching frequency are twofold: first, the
frequency can be selected to avoid noise-sensitive
regions such as the 455kHz IF band; second, the induc-
tor ripple-current operating point remains relatively con-
stant, resulting in easy design methodology and
predictable output voltage ripple. The on-time one-shots
have good accuracy at the operating points specified in
the Electrical Characteristics. On-times at operating
points far removed from the conditions specified in the
Electrical Characteristics can vary over a wider range. For
example, the 300kHz setting typically runs about 3%
slower with inputs much greater than 12V due to the very
short on-times required.
The one-shot for the secondary phase varies the on-time
in response to the input voltage and the difference
between the main and secondary inductor currents. Two
identical transconductance amplifiers integrate the differ-
ence between the master and slave current-sense sig-
nals. The summed output is internally connected to CCI,
allowing adjustment of the integration time constant with a
compensation network connected between CCI and FB.
The resulting compensation current and voltage are
determined by the following equations:
I
= G
V
- V
- G
Z
V
- V
(
)
(
)
CCI
M
CMP
CMN
M
CSP CSN
V
= V
I
CCI
FB + CCI CCI
______________________________________________________________________________________ 25
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
BSTS
DHS
LXS
CSN
SECONDARY PHASE
DRIVERS
CSP
ILIM
DLS
TRIG
CMP
Q
19R
Gm
Gm
ON-TIME
ONE-SHOT
CMN
CSN
R
CCI
MINIMUM
OFF-TIME
CMP
CMN
TRIG
Q
ONE-SHOT
CSP
FB
V+
V
CC
ON-TIME
ONE-SHOT
TON
REF
REF
(2.0V)
Q
TRIG
Q
Q
T
SHDN
GND
BSTM
DHM
LXM
MAIN PHASE
DRIVERS
R
S
Q
S
R
Q
CMP
CMN
CCV
Gm
1.5mV
V
DD
REF
1.0V
DLM
SKIP
FAULT
PGND
T
T = 1
T = 0
MAX1519
MAX1545
Gm
OFS
FB
INTERNAL MULTIPLEXERS, MODE
CONTROL, AND SLEW-RATE CONTROL
TIME
OAIN+
R-2R
DAC
Gm
OAIN-
GNDS
S[0:1] D[0:4] SUS
CODE
SKIP
Figure 5. Dual-Phase Quick-PWM Functional Diagram
26 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
On-times translate only roughly to switching frequencies.
With active current balancing, the current mismatch is
determined by the current-sense resistor values and the
offset voltage of the transconductance amplifiers:
The on-times guaranteed in the Electrical Characteristics
are influenced by switching delays in the external high-
side MOSFET. Resistive losses, including the inductor,
both MOSFETs, output capacitor ESR, and PC board
copper losses in the output and ground tend to raise the
switching frequency at higher output currents. Also, the
dead-time effect increases the effective on-time, reduc-
ing the switching frequency. It occurs only during forced-
PWM operation and dynamic output voltage transitions
when the inductor current reverses at light or negative
load currents. With reversed inductor current, the induc-
tor’s EMF causes LX to go high earlier than normal,
extending the on-time by a period equal to the DH-rising
dead time.
V
OS(IBAL)
I
= I
- I
=
OS(IBAL)
LM
LS
R
SENSE
where V
is the current-balance offset specifica-
OS(IBAL)
tion in the Electrical Characteristics.
The worst-case current mismatch occurs immediately
after a load transient due to inductor value mismatches
resulting in different di/dt for the two phases. The time it
takes the current-balance loop to correct the transient
imbalance depends on the mismatch between the
inductor values and switching frequency.
For loads above the critical conduction point, where the
dead-time effect is no longer a factor, the actual switch-
ing frequency (per phase) is:
Feedback Adjustment Amplifiers
Voltage-Positioning Amplifier
The multiphase Quick-PWM controllers include an inde-
pendent operational amplifier for adding gain to the volt-
age-positioning sense path. The voltage-positioning
gain allows the use of low-value current-sense resistors
in order to minimize power dissipation. This 3MHz gain-
bandwidth amplifier was designed with low offset volt-
age (70µV, typ) to meet the IMVP output accuracy
requirements.
V
+ V
DROP1
(
)
OUT
f
SW =
t
V
+ V
- V
(
)
ON
IN
DROP1 DROP2
where V
is the sum of the parasitic voltage drops in
DROP1
the inductor discharge path, including synchronous recti-
fier, inductor, and PC board resistances; V
is the
DROP2
sum of the parasitic voltage drops in the inductor charge
path, including high-side switch, inductor, and PC board
The inverting (OAIN-) and noninverting (OAIN+) inputs
are used to differentially sense the voltage across the
voltage-positioning sense resistor. The op amp’s output is
internally connected to the regulator’s feedback input
(FB). The op amp should be configured as a noninvert-
ing, differential amplifier, as shown in Figure 10. The
voltage-positioning slope is set by properly selecting the
feedback resistor connected from FB to OAIN- (see the
Setting Voltage Positioning section). For applications
using a slave controller, additional differential input
resistors (summing configuration) can be connected to
the slave’s voltage-positioning sense resistor. Summing
together both the master and slave current-sense signals
ensures that the voltage-positioning slope remains con-
stant when the slave controller is disabled.
resistances; and t
is the on-time as determined above.
ON
Current Balance
Without active current-balance circuitry, the current
matching between phases depends on the MOSFET’s
on-resistance (R
), thermal ballasting, on-/off-time
DS(ON)
matching, and inductance matching. For example, vari-
ation in the low-side MOSFET on-resistance (ignoring
thermal effects) results in a current mismatch that is
proportional to the on-resistance difference:
R
R
MAIN
I
- I
= I
1 -
MAIN
MAIN
2ND
However, mismatches between on-times, off-times, and
inductor values increase the worst-case current imbal-
ance, making it impossible to passively guarantee
accurate current balancing.
The controller also uses the amplifier for remote output
sensing (FBS) by summing the remote-sense voltage
into the positive terminal of the voltage-positioning
amplifier (Figure 10).
The multiphase Quick-PWM controller integrates the
difference between the current-sense voltages and
adjusts the on-time of the secondary phase to maintain
current balance. The current balance now relies on the
accuracy of the current-sense resistors instead of the
inaccurate, thermally sensitive on-resistance of the low-
side MOSFETs.
In applications that do not require voltage-positioning
gain, the amplifier can be disabled by connecting the
OAIN- pin directly to V . The disabled amplifier’s out-
CC
put becomes high impedance, guaranteeing that the
unused amplifier does not corrupt the FB input signal.
The logic threshold to disable the op amp is approxi-
mately V
- 1V.
CC
______________________________________________________________________________________ 27
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
SKIP
Table 7.
Settings*
SKIP
CONNECTION
MODE
OPERATION
The controller operates with a constant switching frequency, providing low-noise forced-PWM
operation. The controller disables the zero-crossing comparators, forcing the low-side gate-
drive waveform to constantly be the complement of the high-side gate-drive waveform.
High
(3.3V or V
Two-phase
forced-PWM
)
CC
The controller automatically switches over to PFM operation under light loads. The controller
keeps both phases active and uses the automatic pulse-skipping control
scheme—alternating between the primary and secondary phases with each cycle.
Two-phase
pulse skipping
REF
The controller automatically switches over to PFM operation under light loads. Only the main
phase is active. The secondary phase is disabled—DHS and DLS are pulled low so LXS is
high impedance.
One-phase
pulse skipping
GND
*Settings for a dual 180° out-of-phase controller.
Integrator Amplifier
Offset Amplifier
The multiphase Quick-PWM controllers include a third
amplifier used to add small offsets to the voltage-posi-
tioned load line. The offset amplifier is summed directly
with the feedback voltage, making the offset gain inde-
pendent of the DAC code. This amplifier has the ability
to offset the output by 100mV.
A feedback amplifier forces the DC average of the
feedback voltage to equal the VID DAC setting. This
transconductance amplifier integrates the feedback
voltage and provides a fine adjustment to the regulation
voltage (Figure 5), allowing accurate DC output voltage
regulation regardless of the output ripple voltage. The
feedback amplifier has the ability to shift the output
voltage. The differential input voltage range is at least
80mV total, including DC offset and AC ripple. The
integration time constant can be set easily with an
external compensation capacitor at the CCV pin. Use a
capacitor value of 47pF to 1000pF (47pF, typ).
The offset is adjusted using resistive voltage-dividers at
the OFS input. For inputs from 0 to 0.8V, the offset
amplifier adds a negative offset to the output that is
equal to 1/8 the voltage appearing at the selected OFS
input (V
= V
- 0.125 × V
). For inputs from
OFS
OUT
DAC
1.2V to 2V, the offset amplifier adds a positive
offset to the output that is equal to 1/8 the difference
between the reference voltage and the voltage appear-
Differential Remote Sense
The multiphase Quick-PWM controllers include differen-
tial remote-sense inputs to eliminate the effects of volt-
age drops down the PC board traces and through the
processor’s power pins. The remote output sense (FBS)
is accomplished by summing the remote-sense voltage
into the positive terminal of the voltage-positioning
amplifier (Figure 10). The controller includes a dedicat-
ed input and internal amplifier for the remote ground
sense. The GNDS amplifier adds an offset directly to the
feedback voltage, adjusting the output voltage to coun-
teract the voltage drop in the ground path. Together, the
ing at the selected OFS input (V
= V
+ 0.125 ×
DAC
OUT
(V
- V
)). With this scheme, the controller sup-
REF
OFS
ports both positive and negative offsets with a single
input. The piecewise linear transfer function is shown in
the Typical Operating Characteristics. The regions of
the transfer function below zero, above 2V, and
between 0.8V and 1.2V are undefined. OFS inputs are
disallowed in these regions, and the respective effects
on the output are not specified.
The controller disables the offset amplifier during
suspend mode (SUS = REF or high).
feedback sense resistor (R
) and GNDS input sum
FBS
the remote-sense voltages with the feedback signals
that set the voltage-positioned output, enabling true dif-
ferential remote sense of the processor voltage.
Forced-PWM Operation (Normal Mode)
During normal mode, when the CPU is actively running
(SKIP = high, Table 7), the Quick-PWM controller oper-
ates with the low-noise forced-PWM control scheme.
Forced-PWM operation disables the zero-crossing
comparator, forcing the low-side gate-drive waveform
to constantly be the complement of the high-side gate-
drive waveform. This keeps the switching frequency
fairly constant and allows the inductor current to
Connect the feedback sense resistor (R
) and
FBS
ground-sense input (GNDS) directly to the processor’s
core supply remote-sense outputs as shown in the
Standard Applications Circuit.
28 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
200
100
UNDEFINED
REGION
∆i
∆t
V
- V
BATT OUT
=
L
I
PEAK
0
-100
-200
I
= I
/2
LOAD PEAK
0.8
1.2
0
ON-TIME
TIME
0
0.5
1.0
OFS VOLTAGE (V)
1.5
2.0
Figure 6. Offset Voltage
Figure 7. Pulse-Skipping/Discontinuous Crossover Point
reverse under light loads, providing fast, accurate neg-
ative output voltage transitions by quickly discharging
the output capacitors.
I
Forced-PWM operation comes at a cost: the no-load 5V
bias supply current remains between 10mA to 60mA
per phase, depending on the external MOSFETs and
switching frequency. To maintain high efficiency under
light load conditions, the processor may switch the
controller to a low-power pulse-skipping control
scheme after entering suspend mode.
PEAK
I
LOAD
LIMIT
I
Low-Power Pulse Skipping
During pulse-skipping override mode (SKIP = REF or
GND, Table 7), the multiphase Quick-PWM controllers
use an automatic pulse-skipping control scheme. When
SKIP is pulled low, the controller uses the automatic
pulse-skipping control scheme, overriding forced-PWM
operation, and blanks the upper VROK threshold.
2 - LIR
2η
I
= I
LIMIT(VALLEY) LOAD(MAX)
( )
0
TIME
SKIP is a three-level logic input—GND, REF, or high.
This input is intended to be driven by a dedicated
open-drain output with the pullup resistor connected
Figure 8. “Valley” Current-Limit Threshold Point
switch on-time at the inductor current’s zero crossing
affects this switchover. The zero-crossing comparator
senses the inductor current across the current-sense
either to REF (or a resistive divider from V ) or to a
CC
logic-level high bias supply (3.3V or greater).
resistors. Once V _ - V _ drops below the zero-
When driven to GND, the multiphase Quick-PWM con-
troller disables the secondary phase (DLS = PGND and
DHS = LXS) and the primary phase uses the automatic
pulse-skipping control scheme. When pulled up to REF,
the controller keeps both phases active and uses the
automatic pulse-skipping control scheme—alternating
between the primary and secondary phases with each
cycle.
C P
C N
crossing comparator threshold (see the Electrical
Characteristics), the comparator forces DL low (Figure 5).
This mechanism causes the threshold between pulse-
skipping PFM and nonskipping PWM operation to coin-
cide with the boundary between continuous and
discontinuous inductor-current operation. The
PFM/PWM crossover occurs when the load current of
each phase is equal to 1/2 the peak-to-peak ripple cur-
rent, which is a function of the inductor value (Figure 7).
For a battery input range of 7V to 20V, this threshold is
relatively constant, with only a minor dependence on
Automatic Pulse-Skipping Switchover
In skip mode (SKIP = REF or GND), an inherent auto-
matic switchover to PFM takes place at light loads
(Figure 7). A comparator that truncates the low-side
______________________________________________________________________________________ 29
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
the input voltage due to the typically low duty cycles.
C
BYP
The total load current at the PFM/PWM crossover
V
DD
threshold (I ) is approximately:
LOAD(SKIP)
D
BST
(R )*
BST
BST
V
K
V -V
IN OUT
OUT
L
INPUT
(V
I
= η
LOAD(SKIP)
C
)
BST
IN
TOTAL
V
IN
DH
LX
N
H
where η
is the number of active phases, and K is
L
TOTAL
the on-time scale factor (Table 6).
V
DD
The switching waveforms may appear noisy and asyn-
chronous when light loading activates the pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Varying the inductor
value makes trade-offs between PFM noise and light-load
efficiency. Generally, low inductor values produce a
broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the coil
resistance remains fixed) and less output voltage ripple.
Penalties for using higher inductor values include larger
physical size and degraded load-transient response,
especially at low input voltage levels.
DL
N
L
(C )*
NL
PGND
(R )* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING
NODE RISE TIME.
(CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT
CAN CAUSE SHOOT-THROUGH CURRENTS.
BST
Figure 9. Optional Gate-Driver Circuitry
The current-limit threshold is adjusted with an external
resistive voltage-divider at ILIM. The current-limit
threshold voltage adjustment range is from 10mV to
75mV. In the adjustable mode, the current-limit thresh-
old voltage is precisely 1/20 the voltage seen at ILIM.
The threshold defaults to 30mV when ILIM is connected
Current-Limit Circuit
The current-limit circuit employs a unique “valley” cur-
rent-sensing algorithm that uses current-sense resistors
between the current-sense inputs (C_P to C_N) as the
current-sensing elements. If the current-sense signal of
the selected phase is above the current-limit threshold,
the PWM controller does not initiate a new cycle
(Figure 8) until the inductor current of the selected
phase drops below the valley current-limit threshold.
When either phase trips the current limit, both phases
are effectively current limited since the interleaved con-
troller does not initiate a cycle with either phase.
to V . The logic threshold for switchover to the 30mV
default value is approximately V
CC
- 1V.
CC
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signals seen by the current-sense inputs
(C_P, C_N).
MOSFET Gate Drivers (DH, DL)
The DH and DL drivers are optimized for driving mod-
erately sized, high-side and larger, low-side power
MOSFETs. This is consistent with the low-duty factor
seen in the notebook CPU environment, where a large
Since only the valley current is actively limited, the actual
peak current is greater than the current-limit threshold by
an amount equal to the inductor ripple current. Therefore,
the exact current-limit characteristic and maximum load
capability are a function of the current-sense resistance,
inductor value, and battery voltage. When combined with
the undervoltage protection circuit, this current-limit
method is effective in almost every circumstance.
V
- V
differential exists. An adaptive dead-time
OUT
IN
circuit monitors the DL output and prevents the high-
side FET from turning on until DL is fully off. There must
be a low-resistance, low-inductance path from the DL
driver to the MOSFET gate in order for the adaptive
dead-time circuit to work properly. Otherwise, the
sense circuitry in the Quick-PWM controller interprets
the MOSFET gate as “off” while there is actually charge
still left on the gate. Use very short, wide traces (50 mils
to 100 mils wide if the MOSFET is 1in from the device).
The dead time at the other edge (DH turning off) is
determined by a fixed 35ns internal delay.
There is also a negative current limit that prevents
excessive reverse inductor currents when V
is sink-
OUT
ing current. The negative current-limit threshold is set to
approximately 120% of the positive current limit, and
therefore tracks the positive current limit when ILIM is
adjusted. When a phase drops below the negative cur-
rent limit, the controller immediately activates an on-
time pulse—DL turns off, and DH turns on—allowing
the inductor current to remain above the negative cur-
rent threshold.
The internal pulldown transistor that drives DL low is
robust, with a 0.4Ω (typ) on-resistance. This helps pre-
vent DL from being pulled up due to capacitive cou-
30 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
pling from the drain to the gate of the low-side
MOSFETs when LX switches from ground to V
at the trigger input initiate a corresponding on-time
pulse (see the On-Time One-Shot section). If the V
voltage drops below 4.25V, it is assumed that there is
not enough supply voltage to make valid decisions. To
protect the output from overvoltage faults, the controller
activates the shutdown sequence.
.
IN
CC
Applications with high input voltages and long, induc-
tive DL traces may require additional gate-to-source
capacitance to ensure fast-rising LX edges do not pull
up the low-side MOSFET’s gate voltage, causing shoot-
through currents. The capacitive coupling between LX
and DL created by the MOSFET’s gate-to-drain capaci-
Multiphase Quick-PWM
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
tance (C
RSS
), gate-to-source capacitance (C
-
ISS
RSS
C
), and additional board parasitics should not
exceed the minimum threshold voltage:
C
C
RSS
V
< V
IN
GS(TH)
ISS
Lot-to-lot variation of the threshold voltage can cause
problems in marginal designs. Typically, adding a
4700pF between DL and power ground (C in Figure
NL
9), close to the low-side MOSFETs, greatly reduces
coupling. Do not exceed 22nF of total gate capacitance
to prevent excessive turn-off delays.
•
Input voltage range: The maximum value
(V ) must accommodate the worst-case high
IN(MAX)
AC adapter voltage. The minimum value (V
)
IN(MIN)
must account for the lowest input voltage after drops
due to connectors, fuses, and battery selector
switches. If there is a choice at all, lower input volt-
ages result in better efficiency.
Alternatively, shoot-through currents may be caused by
a combination of fast high-side MOSFETs and slow low-
side MOSFETs. If the turn-off delay time of the low-side
MOSFET is too long, the high-side MOSFETs can turn
on before the low-side MOSFETs have actually turned
off. Adding a resistor less than 5Ω in series with BST
slows down the high-side MOSFET turn-on time, elimi-
nating the shoot-through currents without degrading
•
Maximum load current: There are two values to
consider. The peak load current (I
) deter-
LOAD(MAX)
mines the instantaneous component stresses and fil-
tering requirements, and thus drives output capacitor
selection, inductor saturation rating, and the design
of the current-limit circuit. The continuous load cur-
rent (I
) determines the thermal stresses and
LOAD
the turn-off time (R
in Figure 9). Slowing down the
BST
thus drives the selection of input capacitors,
MOSFETs, and other critical heat-contributing com-
ponents. Modern notebook CPUs generally exhibit
high-side MOSFET also reduces the LX node rise time,
thereby reducing EMI and high-frequency coupling
responsible for switching noise.
I
= I
× 80%.
LOAD
LOAD(MAX)
Power-On Reset
For multiphase systems, each phase supports a
fraction of the load, depending on the current bal-
ancing. When properly balanced, the load current is
evenly distributed among each phase:
Power-on reset (POR) occurs when V
rises above
CC
approximately 2V, resetting the fault latch, activating
boot mode, and preparing the PWM for operation. V
CC
undervoltage lockout (UVLO) circuitry inhibits switch-
ing, and forces the DL gate driver high (to enforce out-
I
LOAD
I
=
put overvoltage protection). When V
rises above
LOAD(PHASE)
CC
η
4.25V, the DAC inputs are sampled and the output volt-
age begins to slew to the target voltage.
TOTAL
where η
is the total number of active phases.
TOTAL
For automatic startup, the battery voltage should be
present before V . If the Quick-PWM controller
CC
attempts to bring the output into regulation without the
battery voltage present, the fault latch trips. Toggle the
SHDN pin to reset the fault latch.
•
•
Switching frequency: This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage, due to MOSFET switching losses that
are proportional to frequency and V 2. The opti-
IN
mum frequency is also a moving target, due to rapid
improvements in MOSFET technology that are mak-
ing higher frequencies more practical.
Input Undervoltage Lockout
During startup, the V
UVLO circuitry forces the DL
CC
gate driver high and the DH gate driver low, inhibiting
switching until an adequate supply voltage is reached.
Inductor operating point: This choice provides
trade-offs between size vs. efficiency and transient
Once V
rises above 4.25V, valid transitions detected
CC
______________________________________________________________________________________ 31
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
response vs. output noise. Low-inductor values pro-
vide better transient response and smaller physical
size, but also result in lower efficiency and higher out-
put noise due to increased ripple current. The mini-
mum practical inductor value is one that causes the
circuit to operate at the edge of critical conduction
(where the inductor current just touches zero with
every cycle at maximum load). Inductor values lower
than this grant no further size-reduction benefit. The
optimum operating point is usually found between
20% and 50% ripple current.
can be calculated as:
2
(∆I
) L
LOAD(MAX)
V
≈
SOAR
2η
C
V
OUT OUT
TOTAL
where η
is the total number of active phases.
TOTAL
Setting the Current Limit
The minimum current-limit threshold must be high
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The valley
of the inductor current occurs at I
the ripple current; therefore:
minus half
LOAD(MAX)
Inductor Selection
The switching frequency and operating point (% ripple
current or LIR) determine the inductor value as follows:
I
LIR
2
LOAD(MAX)
I
>
1 −
LIMIT(LOW)
η
TOTAL
f
V
− V
V
V
IN
IN
OUT
OUT
L = η
where η
is the total number of active phases, and
TOTAL
I
LIR
TOTAL
SW LOAD(MAX)
I
equals the minimum current-limit threshold
LIMIT(LOW)
where η
is the total number of phases.
voltage divided by the current-sense resistor (R
).
SENSE
TOTAL
For the 30mV default setting, the minimum current-limit
threshold is 28mV.
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
Connect ILIM to V
for the default current-limit thresh-
CC
old (see the Electrical Characteristics). In adjustable
mode, the current-limit threshold is precisely 1/20 the
voltage seen at ILIM. For an adjustable threshold, con-
nect a resistive divider from REF to GND with ILIM con-
nected to the center tap. When adjusting the current
limit, use 1% tolerance resistors with approximately 10µA
of divider current to prevent a significant increase of
errors in the current-limit tolerance.
inductor current (I
):
PEAK
I
LIR
2
LOAD(MAX)
I
=
1 +
PEAK
η
TOTAL
Transient Response
The inductor ripple current impacts transient-response
performance, especially at low V - V differentials.
Output Capacitor Selection
The output filter capacitor must have low enough effec-
tive series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
IN
OUT
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output filter
capacitors by a sudden load step. The amount of output
sag is also a function of the maximum duty factor, which
can be calculated from the on-time and minimum off-
time. For a dual-phase controller, the worst-case output
sag voltage can be determined by:
In CPU V
converters and other applications where
CORE
the output is subject to large load transients, the output
capacitor’s size typically depends on how much ESR is
needed to prevent the output from dipping too low
under a load transient. Ignoring the sag due to finite
capacitance:
V
K
OUT
2
)
L(∆I
+ t
OFF(MIN)
LOAD(MAX)
V
IN
V
=
SAG
(V − 2V
)K
OUT
IN
VSTEP
2C
V
− 2t
OFF(MIN)
OUT OUT
RESR
≤
V
IN
∆ILOAD(MAX)
∆I
V
K
LOAD(MAX)
OUT
In non-CPU applications, the output capacitor’s size
often depends on how much ESR is needed to maintain
an acceptable level of output ripple voltage. The output
ripple voltage of a step-down controller equals the total
inductor ripple current multiplied by the output capaci-
tor’s ESR. When operating multiphase systems out-of-
+
+ t
OFF(MIN)
2C
V
IN
OUT
where t
is the minimum off-time (see the
Electrical Characteristics) and K is from Table 6.
OFF(MIN)
The amount of overshoot due to stored inductor energy
32 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
phase, the peak inductor currents of each phase are
For a standard 300kHz application, the ESR zero frequen-
cy must be well below 95kHz, preferably below 50kHz.
Tantalum, Sanyo POSCAP, and Panasonic SP capacitors
in widespread use at the time of publication have typical
ESR zero frequencies below 50kHz. For example, the
staggered, resulting in lower output ripple voltage by
reducing the total inductor ripple current. For 3- or 4-
phase operation, the maximum ESR to meet ripple
requirements is:
ESR needed to support a 30mV
ripple in a 40A design
P-P
is 30mV/(40A × 0.3) = 2.5mΩ. Four 330µF/2.5V Panasonic
SP (type XR) capacitors in parallel provide 2.5mΩ (max)
ESR. Their typical combined ESR results in a zero at
40kHz.
V
L
RIPPLE
R
ESR
≤
(2V − η
V
)t
− η V t
TOTAL OUT TRIG
IN
TOTAL OUT ON
where η
is the total number of active phases, t
Ceramic capacitors have a high ESR zero frequency,
but applications with significant voltage positioning can
take advantage of their size and low ESR. Do not put
high-value ceramic capacitors directly across the out-
put without verifying that the circuit contains enough
voltage positioning and series PC board resistance to
ensure stability. When only using ceramic output
ON
is the
TOTAL
is the calculated on-time per phase, and t
TRIG
trigger delay between the master’s DH rising edge and
the slave’s DH rising edge. The trigger delay must be
less than 1/(f
actual capacitance value required relates to the physi-
cal size needed to achieve low ESR, as well as to the
chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of polymer
types).
× η
) for stable operation. The
SW
TOTAL
capacitors, output overshoot (V
) typically deter-
SOAR
mines the minimum output capacitance requirement.
Their relatively low capacitance value can cause output
overshoot when stepping from full-load to no-load con-
ditions, unless a small inductor value is used (high
switching frequency) to minimize the energy transferred
from inductor to capacitor during load-step recovery.
The efficiency penalty for operating at 550kHz is about
5% when compared to the 300kHz circuit, primarily due
to the high-side MOSFET switching losses.
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
needed to prevent V
problems during load transients. Generally, once
enough capacitance is added to meet the overshoot
requirement, undershoot at the rising load edge is no
and V
from causing
SOAR
SAG
longer a problem (see the V
in the Transient Response section).
and V
equations
SOAR
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and feedback
loop instability. Double-pulsing occurs due to noise on
the output or because the ESR is so low that there is
not enough voltage ramp in the output voltage signal.
This “fools” the error comparator into triggering a new
cycle immediately after the minimum off-time period
has expired. Double-pulsing is more annoying than
harmful, resulting in nothing worse than increased out-
put ripple. However, it can indicate the possible pres-
ence of loop instability due to insufficient ESR. Loop
instability can result in oscillations at the output after
line or load steps. Such perturbations are usually
damped, but can cause the output voltage to rise
above or fall below the tolerance limits.
SAG
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching fre-
quency. The boundary of instability is given by the fol-
lowing equation:
fSW
π
fESR
≤
where:
1
fESR
=
2πREFFCOUT
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
and:
REFF = RESR + AVPSRSENSE + RPCB
is the total output capacitance, R
where C
is the
ESR
OUT
total equivalent-series resistance, R
is the cur-
SENSE
rent-sense resistance, A
gain, and R
is the voltage-positioning
VPS
is the parasitic board resistance
PCB
between the output capacitors and sense resistors.
______________________________________________________________________________________ 33
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
sized package (i.e., one or two SO-8s, DPAK, or
Input Capacitor Selection
D2PAK), and is reasonably priced. Ensure that the DL
gate driver can supply sufficient current to support the
gate charge and the current injected into the parasitic
gate-to-drain capacitor caused by the high-side MOSFET
turning on; otherwise, cross-conduction problems can
occur (see the MOSFET Gate Driver section).
The input capacitor must meet the ripple current
requirement (I
) imposed by the switching currents.
RMS
The multiphase Quick-PWM controllers operate out-of-
phase, while the Quick-PWM slave controllers provide
selectable out-of-phase or in-phase on-time triggering.
Out-of-phase operation reduces the RMS input current
by dividing the input current between several stag-
MOSFET Power Dissipation
gered stages. For duty cycles less than 100%/η
OUTPH
Worst-case conduction losses occur at the duty factor
per phase, the I
requirements may be determined
RMS
extremes. For the high-side MOSFET (N ), the worst-
H
by the following equation:
case power dissipation due to resistance occurs at the
minimum input voltage:
I
LOAD
I
=
η
V (V − ηOUTPH
OUT IN
V
OUT
)
RMS
OUTPH
η
V
IN
OUTPH
2
V
V
I
LOAD
OUT
PD (N RESISTIVE) =
R
DS(ON)
H
where η
is the total number of out-of-phase switch-
ing regulators. The worst-case RMS current requirement
η
OUTPH
IN
TOTAL
where η
is the total number of phases.
occurs when operating with V = 2η
V
RMS
. At this
IN
OUT
TOTAL
OUTPH
point, the above equation simplifies to I
= 0.5 ×
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
I
/η
.
LOAD
OUTPH
However, the R
required to stay within package
DS(ON)
For most applications, nontantalum chemistries (ceramic,
aluminum, or OS-CON™) are preferred due to their resis-
tance to inrush surge currents typical of systems with a
mechanical switch or connector in series with the input. If
the Quick-PWM controller is operated as the second
stage of a two-stage power-conversion system, tantalum
input capacitors are acceptable. In either configuration,
choose an input capacitor that exhibits less than 10°C
temperature rise at the RMS input current for optimal cir-
cuit longevity.
power dissipation often limits how small the MOSFETs
can be. Again, the optimum occurs when the switching
losses equal the conduction (R
) losses. High-
DS(ON)
side switching losses do not usually become an issue
until the input is greater than approximately 15V.
Calculating the power dissipation in high-side
MOSFETs (N ) due to switching losses is difficult since
H
it must allow for difficult quantifying factors that influ-
ence the turn-on and turn-off times. These factors
include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PC board
layout characteristics. The following switching-loss cal-
culation provides only a very rough estimate and is no
substitute for breadboard evaluation, preferably includ-
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (>20V) AC adapters. Low-cur-
rent applications usually require less attention.
ing verification using a thermocouple mounted on N :
H
The high-side MOSFET (N ) must be able to dissipate
H
the resistive losses plus the switching losses at both
C
I
f
I
LOAD
RSS SW
2
)
PD (N SWITCHING) = (V
V
and V
. Calculate both of these sums.
IN(MAX)
H
IN(MAX)
IN(MIN)
η
GATE
TOTAL
Ideally, the losses at V
should be roughly equal to
IN(MIN)
losses at V
losses at V
, with lower losses in between. If the
where C
GATE
is the reverse transfer capacitance of N and
H
IN(MAX)
IN(MIN)
RSS
are significantly higher than the losses
I
is the peak gate-drive source/sink current (1A, typ).
at V
, consider increasing the size of N (reducing
IN(MAX)
DS(ON)
H
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
R
but with higher C
). Conversely, if the losses
GATE
at V
are significantly higher than the losses at
IN(MAX)
voltages are applied, due to the squared term in the C
V
R
, consider reducing the size of N (increasing
IN(MIN)
H
2
× V
× f
switching-loss equation. If the high-side
SW
IN
to lower C
). If V does not vary over a wide
DS(ON)
GATE IN
MOSFET chosen for adequate R
at low battery
DS(ON)
range, the minimum power dissipation occurs where the
resistive losses equal the switching losses.
voltages becomes extraordinarily hot when biased from
, consider choosing another MOSFET with
V
IN(MAX)
lower parasitic capacitance.
Choose a low-side MOSFET that has the lowest possi-
ble on-resistance (R
), comes in a moderate-
DS(ON)
OS-CON is a trademark of Sanyo.
34 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
CMN
CMP
R
L1
SENSE
MAIN
PHASE
MAX1519
MAX1545
R
A
R
B
PC BOARD TRACE
RESISTANCE
OAIN+
R
FBS
CPU SENSE
POINT
ERROR
COMPARATOR
OAIN-
FB
PC BOARD TRACE
RESISTANCE
R
F
R
A
R
B
R
L2
SENSE
SECOND
PHASE
CSP
CSN
Figure 10. Voltage-Positioning Gain
For the low-side MOSFET (N ), the worst-case power
L
dissipation always occurs at maximum input voltage:
Boost Capacitors
) selected must be large
The boost capacitors (C
BST
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1µF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current appli-
cations driving large, high-side MOSFETs require boost
capacitors larger than 0.1µF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the high-
side MOSFET’s gates:
2
V
V
I
LOAD
OUT
PD (N RESISTIVE) = 1 −
R
DS(ON)
L
η
IN(MAX)
TOTAL
The worst-case for MOSFET power dissipation occurs
under heavy overloads that are greater than
I
but are not quite high enough to exceed
LOAD(MAX)
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you can “overdesign” the
circuit to tolerate:
∆I
N x QGATE
200mV
INDUCTOR
2
I
= η
= η
I
+
LOAD
VALLEY(MAX)
CBST =
TOTA
L
I
LIR
LOAD(MAX)
2
I
+
VALLEY(MAX)
where N is the number of high-side MOSFETs used for
TOTAL
one regulator, and Q is the gate charge specified
GATE
where I
is the maximum valley current
VALLEY(MAX)
in the MOSFET’s data sheet. For example, assume (2)
IRF7811W N-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a sin-
gle IRF7811W has a maximum gate charge of 24nC
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good size heatsink to handle the overload
power dissipation.
(V
= 5V). Using the above equation, the required
boost capacitance would be:
GS
Choose a Schottky diode (D ) with a forward voltage
L
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. As a gen-
eral rule, select a diode with a DC current rating equal
to 1/3 of the load current-per-phase. This diode is
optional and can be removed if efficiency is not critical.
2 x 24nC
200mV
CBST
=
= 0.24µF
Selecting the closest standard value, this example
requires a 0.22µF ceramic capacitor.
______________________________________________________________________________________ 35
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
η
for voltage-positioning feedback, and
is the total
Current-Balance Compensation (CCI)
The current-balance compensation capacitor (C
TOTAL
number of active phases. When the slave controller is
disabled, the current-sense summation maintains the
proper voltage-positioned slope. Select the positive input
)
CCI
integrates the difference between the main and sec-
ondary current-sense voltages. The internal compensa-
summing resistors so R
= R and R = R .
F A B
tion resistor (R
= 20kΩ) improves transient response
FBS
CCI
by increasing the phase margin. This allows the
dynamics of the current-balance loop to be optimized.
Excessively large capacitor values increase the inte-
gration time constant, resulting in larger current differ-
ences between the phases during transients.
Excessively small capacitor values allow the current
loop to respond cycle-by-cycle but can result in small
DC current variations between the phases. Likewise,
excessively large resistor values can also cause DC
current variations between the phases. Small resistor
values reduce the phase margin, resulting in marginal
stability in the current-balance loop. For most applica-
tions, a 470pF capacitor from CCI to the switching reg-
ulator’s output works well.
Minimum Input Voltage Requirements
and Dropout Performance
The nonadjustable minimum off-time one-shot and the
number of phases restrict the output voltage adjustable
range for continuous-conduction operation. For best
dropout performance, use the slower (200kHz) on-time
settings. When working with low input voltages, the
duty-factor limit must be calculated using worst-case
values for on- and off-times. Manufacturing tolerances
and internal propagation delays introduce an error to
the TON K-factor. This error is greater at higher fre-
quencies (Table 6). Also, keep in mind that transient
response performance of buck regulators operated too
close to dropout is poor, and bulk output capacitance
Connecting the compensation network to the output
must often be added (see the V
Design Procedure section).
equation in the
SAG
(V
) allows the controller to feed forward the output
OUT
voltage signal, especially during transients. To reduce
noise pickup in applications that have a widely distrib-
uted layout, it is sometimes helpful to connect the com-
pensation network to the quiet analog ground rather
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time (∆I
)
DOWN
as much as it ramps up during the on-time (∆I ). The
UP
ratio h = ∆I /∆I
is an indicator of the ability to
UP DOWN
than V
.
OUT
slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
Setting Voltage Positioning
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the
processor’s power dissipation. When the output is
loaded, an op amp (Figure 5) increases the signal fed
back to the Quick-PWM controller’s feedback input.
The adjustable amplification allows the use of standard,
current-sense resistor values, and significantly reduces
the power dissipated since smaller current-sense resis-
tors can be used. The load-transient response of this
control loop is extremely fast, yet well controlled, so the
amount of voltage change can be accurately confined
within the limits stipulated in the microprocessor power-
supply guidelines.
each switching cycle and V
greatly increases
SAG
unless additional output capacitance is used.
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows trade-offs between V , output
SAG
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
V
− V
+ V
FB
VPS DROP1
V
= η
OUTPH
IN(MIN)
h x t
VPS
OFF(MIN)
K
1 − η
OUTPH
The voltage-positioned circuit determines the load current
from the voltage across the current-sense resistors
+ V
− V
+ V
DROP2
DROP1
(R
= R
= R ) connected between the inductors
SENSE
CM CS
where η
is the total number of out-of-phase
and output capacitors, as shown in Figure 10. The volt-
age drop can be determined by the following equation:
OUTPH
switching regulators, V
is the voltage-positioning
VPS
DROP2
droop, V
and V
are the parasitic voltage
DROP1
V
= A
I R
drops in the discharge and charge paths (see the On-
VPS
A
VPS LOAD SENSE
Time One-Shot section), t
is from the Electrical
OFF(MIN)
η
R
F
SUM
Characteristics, and K is taken from Table 6. The
=
VPS
η
R
B
absolute minimum input voltage is calculated with h = 1.
TOTAL
η
where
is the number of phases summed together
SUM
36 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
If the calculated V
minimum input voltage, then reduce the operating fre-
quency or add output capacitance to obtain an accept-
is greater than the required
3) Each slave controller should also have a separate
analog ground. Return the appropriate noise-sen-
sitive slave components to this plane. Since the
reference in the master is sometimes connected
to the slave, it may be necessary to couple the
analog ground in the master to the analog ground
in the slave to prevent ground offsets. A low-value
(≤10Ω) resistor is sufficient to link the two grounds.
IN(MIN)
able V
calculate V
response.
. If operation near dropout is anticipated,
SAG
SAG
to be sure of adequate transient
Dropout design example:
= 1.4V
V
FB
4) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance caus-
es a measurable efficiency penalty.
K
= 3µs for f
= 300kHz
SW
MIN
t
= 400ns
OFF(MIN)
V
V
= 3mV/A × 30A = 90mV
VPS
= V
= 150mV (30A load)
DROP1
DROP2
h = 1.5 and ηOUTPH = 2
1.4V − 90mV + 150mV
1 − 2 x (0.4µs x 1.5/ 3.0µs
5) Keep the high-current, gate-driver traces (DL, DH,
LX, and BST) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
V
= 2 x
IN(MIN)
+ 150mV − 150mV + 90mV = 4.96V
Calculating again with h = 1 gives the absolute limit of
dropout:
6) C_P, C_N, OAIN+, and OAIN- connections for cur-
rent limiting and voltage positioning must be made
using Kelvin-sense connections to guarantee the
current-sense accuracy.
1.4V − 90mV + 150mV
1 − 2 x (0.4µs x 1.0/ 3.0µs
V
= 2 x
IN(MIN)
+ 150mV − 150mV + 90mV = 4.07V
7) When trade-offs in trace lengths must be made, it
is preferable to allow the inductor-charging path to
be made longer than the discharge path. For
example, it is better to allow some extra distance
between the input capacitors and the high-side
MOSFET than to allow distance between the
inductor and the low-side MOSFET or between the
inductor and the output filter capacitor.
Therefore, V must be greater than 4.1V, even with very
IN
large output capacitance, and a practical input voltage
with reasonable output capacitance would be 5V.
Applications Information
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 11). If possible, mount all of the power compo-
nents on the topside of the board with their ground ter-
minals flush against one another. Follow these
guidelines for good PC board layout:
8) Route high-speed switching nodes away from
sensitive analog areas (REF, CCV, CCI, FB, C_P,
C_N, etc). Make all pin-strap control input connec-
tions (SHDN, ILIM, SKIP, SUS, S_, TON) to analog
ground or V
rather than power ground or V
.
CC
DD
Layout Procedure
Place the power components first, with ground termi-
nals adjacent (low-side MOSFET source, C , C
1) Keep the high-current paths short, especially at
the ground terminals. This is essential for stable,
jitter-free operation.
,
OUT
IN
and D1 anode). If possible, make all these connections
on the top layer with wide, copper-filled areas:
2) Connect all analog grounds to a separate solid
copper plane, which connects to the GND pin of
1) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate traces must be short and
wide (50 mils to 100 mils wide if the MOSFET is
1in from the controller IC).
the Quick-PWM controller. This includes the V
CC
bypass capacitor, REF and GNDS bypass capaci-
tors, compensation (CC_) components, and the
resistive dividers connected to ILIM and OFS.
______________________________________________________________________________________ 37
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
2) Group the gate-drive components (BST diodes
and capacitors, V bypass capacitor) together
4) Connect the output power planes (V
and
CORE
system ground planes) directly to the output filter
capacitor positive and negative terminals with
multiple vias. Place the entire DC-to-DC converter
circuit as close to the CPU as is practical.
DD
near the controller IC.
3) Make the DC-to-DC controller ground connections
as shown in the Standard Application Circuits.
This diagram can be viewed as having four sepa-
rate ground planes: input/output ground, where all
the high-power components go; the power ground
Chip Information
TRANSISTOR COUNT: 11,015
plane, where the PGND pin and V
bypass
DD
capacitor go; the master’s analog ground plane,
where sensitive analog components, the master’s
PROCESS: BiCMOS
GND pin, and V
bypass capacitor go; and the
CC
slave’s analog ground plane, where the slave’s
GND pin and V bypass capacitor go. The mas-
CC
ter’s GND plane must meet the PGND plane only
at a single point directly beneath the IC. Similarly,
the slave’s GND plane must meet the PGND plane
only at a single point directly beneath the IC. The
respective master and slave ground planes
should connect to the high-power output ground
with a short metal trace from PGND to the source
of the low-side MOSFET (the middle of the star
ground). This point must also be very close to the
output capacitor ground terminal.
38 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
KELVIN SENSE VIAS UNDER
THE SENSE RESISTOR
(REFER TO EVALUATION KIT)
CPU
MAIN PHASE
SECONDARY PHASE
OUTPUT
R
R
SENSE
SENSE
INDUCTOR
INDUCTOR
POWER
GROUND
INPUT
POWER GROUND
(2ND LAYER)
PLACE CONTROLLER ON
VIAS TO POWER
GROUND
BACK SIDE WHEN POSSIBLE,
USING THE GROUND PLANE
TO SHIELD THE IC FROM EMI
CONNECT THE
EXPOSED PAD TO
ANALOG GND
CONNECT GND
AND PGND TO THE
CONTROLLER AT ONE POINT
ONLY AS SHOWN
POWER GROUND
(2ND LAYER)
VIAS TO ANALOG
GROUND
Figure 11. PC Board Layout Example
______________________________________________________________________________________ 39
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
5V BIAS
SUPPLY
C1
2.2µF
R10
10Ω
R11
BST
V
DD
100kΩ
V
DIODES
CC
U1
C2
1µF
MAX1519
MAX1545
INPUT*
V+
7V TO 24V
POWER-
GOOD
C
IN
BSTM
DHM
VROK
C
BST1
0.22µF
D0
D1
D2
D3
D4
R
DAC INPUTS
SENSE1
1.5mΩ
N
H1
C
OUT
L1
LXM
DLM
GND (DESKTOP P4)
SUSPEND INPUTS
CODE
S0
S1
N
L1
(FOUR-LEVEL LOGIC)
PGND
GND
R3
ON
1kΩ
SHDN
R2
1kΩ
1%
OFF
R
TIME
1%
R6
64.9kΩ
TIME
CMN
CMP
OAIN+
OAIN-
3.0kΩ
1%
C
47pF
CCV
CCV
OUTPUT
REF (300kHz)
C
R1
REF
0.22µF
TON
REF
3.0kΩ
1%
R8
100kΩ
1%
R4
1kΩ
1%
R9
FB
30.1kΩ
C
CCI
470pF
1%
R5
ILIM
OFS
1kΩ
CCI
CSP
CSN
1%
REF
C
IN
R28
182kΩ
1%
BSTS
C
BST2
C3
100pF
0.22µF
DHS
LXS
DLS
R
SENSE2
1.5mΩ
N
H2
L2
R27
20kΩ
1%
STP_CPU#
SKIP
C
OUT
N
L2
PWM
SKIP
SUS
GNDS
*LOWER INPUT VOLTAGES
REQUIRE ADDITIONAL
INPUT CAPACITANCE.
POWER GROUND
ANALOG GROUND
Figure 12a. Standard 4-Phase Desktop P4 Application Circuit (1st and 2nd Phases—MAX1519/MAX1545 Master)
40 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
5V BIAS
SUPPLY
C5
1µF
R12
10Ω
V
DD
V
CC
INPUT*
7V TO 24V
C6
D
BST3
C
IN
0.22µF
POL
V+
D1
1N4148
BST
DH
C
BST3
0.22µF
OUTPUT
COMP
N
N
H3
R
SENSE3
1.5mΩ
R
C
COMP1
20kΩ
COMP1
270pF
L3
OUTPUT
U2
LX
DL
C
OUT
R17
200kΩ
MAX1980
L3
REF
(MASTER)
ILIM
PGND
GND
C9
100pF
R18
49.9kΩ
R13
100Ω
CS+
CS-
FLOAT
(300kHz)
T
ON
R14
C7
100Ω
1000pF
LIMIT
DD
R15
100Ω
TRIG
CM+
CM-
C8
1000pF
R16
100Ω
CONNECT TO
MAX1519/MAX1545
(SEE FIGURE 12a)
CONNECT TO
MAX1519/MAX1545
(SEE FIGURE 12a)
POWER GROUND
*LOWER INPUT VOLTAGES
REQUIRE ADDITIONAL
INPUT CAPACITANCE.
ANALOG GROUND
(MASTER)
ANALOG GROUND
(SLAVE)
Figure 12b. Standard 4-Phase Desktop 4 Application Circuit (3rd Phase—MAX1980 Slave)
______________________________________________________________________________________ 41
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
5V BIAS
SUPPLY
C10
1µF
R19
10Ω
V
DD
V
CC
INPUT*
7V TO 24V
C11
D
BST4
C
IN
0.22µF
POL
V+
D2
1N4148
BST
DH
C
BST4
0.22µF
OUTPUT
COMP
N
N
H4
R
SENSE4
1.5mΩ
R
C
COMP2
20kΩ
COMP2
270pF
L4
OUTPUT
U3
LX
DL
C
OUT
R24
200kΩ
MAX1980
L4
REF
(MASTER)
ILIM
PGND
GND
C14
100pF
R25
49.9kΩ
R20
100Ω
CS+
CS-
FLOAT
(300kHz)
T
ON
R21
C12
100Ω
1000pF
LIMIT
DD
R22
100Ω
TRIG
CM+
CM-
C13
1000pF
R23
100Ω
CONNECT TO
MAX1519/MAX1545
(SEE FIGURE 12a)
CONNECT TO
MAX1519/MAX1545
(SEE FIGURE 12a)
POWER GROUND
*LOWER INPUT VOLTAGES
REQUIRE ADDITIONAL
INPUT CAPACITANCE.
ANALOG GROUND
(MASTER)
ANALOG GROUND
(SLAVE)
Figure 12c. Standard 4-Phase Desktop 4 Application Circuit (4th Phase—MAX1980 Slave)
42 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
C
L
b
D2/2
D/2
k
E/2
E2/2
(NE-1) X
e
C
L
E
E2
k
L
e
(ND-1) X
e
C
C
L
L
L
L
e
e
A
A1
A2
PACKAGE OUTLINE
36,40L QFN THIN, 6x6x0.8 mm
1
21-0141
C
2
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
D2 E2
PKG.
CODES
MIN. NOM. MAX. MIN. NOM. MAX.
3.60 3.70 3.80 3.60 3.70 3.80
4.00 4.10 4.20 4.00 4.10 4.20
T3666-1
T4066-1
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
PACKAGE OUTLINE
36, 40L QFN THIN, 6x6x0.8 mm
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
2
21-0141
C
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 43
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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