MAX1518 [MAXIM]
TFT-LCD DC-DC Converters with Operational Amplifiers; TFT -LCD DC-DC与运算放大器转换器
| 型号： | MAX1518 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | TFT-LCD DC-DC Converters with Operational Amplifiers |
| 文件： | 总26页 (文件大小：916K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3244; Rev 0; 4/04
TFT-LCD DC-DC Converters with
Operational Amplifiers
General Description
Features
The MAX1516/MAX1517/MAX1518 include a high-perfor-
mance step-up regulator, two linear-regulator controllers,
and high-current operational amplifiers for active-matrix
thin-film transistor (TFT) liquid-crystal displays (LCDs).
Also included is a logic-controlled, high-voltage switch
with adjustable delay.
♦ 2.6V to 5.5V Input Supply Range
♦ 1.2MHz Current-Mode Step-Up Regulator
Fast Transient Response to Pulsed Load
High-Accuracy Output Voltage (1.5%)
Built-In 14V, 2.4A, 0.16Ω N-Channel MOSFET
High Efficiency (90%)
The step-up DC-DC converter provides the regulated
supply voltage for the panel source driver ICs. The con-
verter is a high-frequency (1.2MHz) current-mode regu-
lator with an integrated 14V n-channel MOSFET that
allows the use of ultra-small inductors and ceramic
capacitors. It provides fast transient response to pulsed
loads while achieving efficiencies over 85%.
♦ Linear-Regulator Controllers for V
and V
GOFF
GON
♦ High-Performance Operational Amplifiers
±150mA Output Short-Circuit Current
13V/µs Slew Rate
12MHz, -3dB Bandwidth
Rail-to-Rail Inputs/Outputs
The gate-on and gate-off linear-regulator controllers
provide regulated TFT gate-on and gate-off supplies
using external charge pumps attached to the switching
node. The MAX1518 includes five high-performance
operational amplifiers, the MAX1517 includes three,
and the MAX1516 includes one operational amplifier.
These amplifiers are designed to drive the LCD back-
plane (VCOM) and/or the gamma-correction divider
string. The devices feature high output current
( 15ꢀmA), fast slew rate (1ꢁV/µs), wide bandwidth
(12MHz), and rail-to-rail inputs and outputs.
♦ Logic-Controlled, High-Voltage Switch with
Adjustable Delay
♦ Timer-Delay Fault Latch for All Regulator Outputs
♦ Thermal-Overload Protection
♦ 0.6mA Quiescent Current
Minimal Operating Circuit
V
CN
V
CP
The MAX1516/MAX1517/MAX1518 are available in ꢁ2-
pin thin QFN packages with a maximum thickness of
ꢀ.8mm for ultra-thin LCD panels.
V
IN
V
MAIN
LX
IN
FB
STEP-UP
CONTROLLER
Applications
Notebook Computer Displays
LCD Monitor Panels
PGND
AGND
COMP
V
V
CP
MAX1518
DRVP
FBP
Automotive Displays
GATE-ON
CONTROLLER
GON
Ordering Information
SRC
COM
DRN
DEL
CTL
PART
TEMP RANGE PIN-PACKAGE
SWITCH
CONTROL
V
V
MAX1516ETJ -4ꢀ°C to +1ꢀꢀ°C ꢁ2 Thin QFN 5mm x 5mm
MAX1517ETJ -4ꢀ°C to +1ꢀꢀ°C ꢁ2 Thin QFN 5mm x 5mm
MAX1518ETJ -4ꢀ°C to +1ꢀꢀ°C ꢁ2 Thin QFN 5mm x 5mm
CN
DRVN
FBN
GATE-OFF
CONTROLLER
GOFF
SUP
NEG1
OUT1
OP1
OP2
REF
REF
POS1
NEG2
NEG4
OUT2
POS2
OUT4
OP4
POS4
NEG5
OUT3
POS3
OUT5
POS5
OP3
OP5
BGND
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
TFT-LCD DC-DC Converters with
Operational Amplifiers
ABSOLUTE MAXIMUM RATINGS
IN, CTL to AGND......................................................-ꢀ.ꢁV to +6V
COM, DRN to AGND ................................-ꢀ.ꢁV to (V
+ ꢀ.ꢁV)
SRC
COMP, FB, FBP, FBN, DEL, REF to AGND ....-ꢀ.ꢁV to (V + ꢀ.ꢁV)
DRN to COM............................................................-ꢁꢀV to +ꢁꢀV
OUT_ Maximum Continuous Output Current.................... 75mA
LX Switch Maximum Continuous RMS Output Current.........1.6A
IN
PGND, BGND to AGND...................................................... ꢀ.ꢁV
LX to PGND ............................................................-ꢀ.ꢁV to +14V
SUP to AGND .........................................................-ꢀ.ꢁV to +14V
DRVP, SRC to AGND..............................................-ꢀ.ꢁV to +ꢁꢀV
Continuous Power Dissipation (T = +7ꢀ°C)
A
ꢁ2-Pin Thin QFN (derate 21.2mW/°C above +7ꢀ°C) ..17ꢀ2mW
Operating Temperature Range .........................-4ꢀ°C to +1ꢀꢀ°C
Junction Temperature......................................................+15ꢀ°C
Storage Temperature Range.............................-65°C to +15ꢀ°C
Lead Temperature (soldering, 1ꢀs) .................................+ꢁꢀꢀ°C
POS_, NEG_, OUT_ to AGND...................-ꢀ.ꢁV to (V
POS1 to NEG1, POS2 to NEG2, POSꢁ to NEGꢁ,
+ ꢀ.ꢁV)
SUP
POS4 to NEG4, POS5 to NEG5...............................-6V to +6V
DRVN to AGND...................................(V - ꢁꢀV) to (V + ꢀ.ꢁV)
IN
IN
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = ꢁV, V
IN
= 8V, PGND = AGND = BGND = ꢀ, I
= 25µA, T = 0°C to +85°C. Typical values are at T = +25°C, unless other-
SUP
REF
A
A
wise noted.)
PARAMETER
IN Supply Range
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
2.6
5.5
V
IN
IN Undervoltage-Lockout
Threshold
V
V
V
rising, typical hysteresis = 15ꢀmV
2.ꢁ
2.5
ꢀ.6
6
2.7
ꢀ.8
11
V
UVLO
IN
= V
= 1.4V, V
= ꢀ,
FB
FBP
FBN
LX not switching
IN Quiescent Current
I
mA
IN
V
= 1.1V, V
= 1.4V, V
= ꢀ,
FB
FBP
FBN
LX switching
Duration to Trigger Fault
Condition
55
ms
V
REF Output Voltage
-2µA < I
< 5ꢀµA, V = 2.6V to 5.5V
1.2ꢁ1
1.25ꢀ
+16ꢀ
15
1.269
REF
IN
Temperature rising
Hysteresis
Thermal Shutdown
°C
MAIN STEP-UP REGULATOR
Output Voltage Range
V
f
V
1ꢁ
V
kHz
%
MAIN
IN
Operating Frequency
1ꢀ2ꢀ
84
12ꢀꢀ
87
1ꢁ8ꢀ
9ꢀ
OSC
Oscillator Maximum Duty Cycle
T
T
= +25°C to +85°C
= ꢀ°C to +85°C
1.221
1.218
ꢀ.96
1.2ꢁꢁ
1.2ꢁꢁ
1.ꢀꢀ
-1.6
1.245
1.247
1.ꢀ4
A
A
FB Regulation Voltage
V
No load
V
FB
FB Fault Trip Level
FB Load Regulation
FB Line Regulation
FB Input Bias Current
FB Transconductance
FB Voltage Gain
V
falling
V
%
FB
ꢀ < I
< full load, transient only
MAIN
V
V
= 2.6V to 5.5V
= 1.4V
+ꢀ.ꢀ4
±ꢀ.15
+4ꢀ
%/V
nA
µS
IN
-4ꢀ
75
FB
∆I
= 5µA
15ꢀ
6ꢀꢀ
28ꢀ
COMP
FB to COMP
V/V
2
_______________________________________________________________________________________
TFT-LCD DC-DC Converters with
Operational Amplifiers
ELECTRICAL CHARACTERISTICS (continued)
(V = ꢁV, V
IN
= 8V, PGND = AGND = BGND = ꢀ, I
= 25µA, T = 0°C to +85°C. Typical values are at T = +25°C, unless other-
SUP
REF
A
A
wise noted.)
PARAMETER
LX On-Resistance
SYMBOL
CONDITIONS
MIN
TYP
16ꢀ
ꢀ.ꢀ2
ꢁ.ꢀ
MAX
25ꢀ
4ꢀ
UNITS
mΩ
µA
R
LX(ON)
LX Leakage Current
LX Current Limit
I
V
V
= 1ꢁV
LX
LX
FB
I
= 1V, duty cycle = 65%
2.5
ꢁ.ꢀ
ꢁ.5
A
LIM
Current-Sense
Transconductance
ꢁ.8
14
5
S
Soft-Start Period
t
ms
A
SS
Soft-Start Step Size
I
/ 8
LIM
OPERATIONAL AMPLIFIERS
SUP Supply Range
V
4.5
1ꢁ.ꢀ
4.8
ꢁ
V
SUP
MAX1518
MAX1517
MAX1516
ꢁ.2
Buffer configuration,
_ = 4V, no load
SUP Supply Current
Input Offset Voltage
I
mA
2
SUP
V
POS
ꢀ.7
1.1
(V
NEG
_, V
_, V
_)
V
/ 2,
POS
OUT
SUP
V
ꢀ
12
mV
OS
T
= +25°C
A
Input Bias Current
I
(V
_ , V
_, V
_)
V
SUP
/ 2
+1
±5ꢀ
nA
V
BIAS
NEG
POS
OUT
Input Common-Mode Range
Common-Mode Rejection Ratio
Open-Loop Gain
V
ꢀ
V
SUP
CM
CMRR
ꢀ ≤ (V
_, V
_) ≤ V
POS
45
dB
dB
NEG
SUP
125
V
-
-
V
V
-
-
SUP
15
SUP
ꢁ
I
I
_ = 1ꢀꢀµA
_ = 5mA
OUT
OUT
Output Voltage Swing, High
V
mV
OH
V
SUP
15ꢀ
SUP
8ꢀ
I
I
_ = -1ꢀꢀµA
_ = -5mA
2
15
OUT
OUT
Output Voltage Swing, Low
Short-Circuit Current
V
mV
mA
mA
OL
7ꢀ
15ꢀ
To V
/ 2, source or sink
5ꢀ
4ꢀ
15ꢀ
SUP
(V
_ , V _, V
POS
_)
V / 2,
SUP
NEG
OUT
Output Source and Sink Current
|∆V | < 1ꢀmV
OS
DC, 6V ≤ V
≤ 1ꢁV,
SUP
Power-Supply Rejection Ratio
PSRR
GBW
6ꢀ
dB
(V
NEG
_, V
_)
V
/2
SUP
POS
Slew Rate
1ꢁ
12
8
V/µs
MHz
MHz
-ꢁdB Bandwidth
Gain-Bandwidth Product
R = 1ꢀkΩ, C = 1ꢀpF, buffer configuration
L L
Buffer configuration
GATE-ON LINEAR-REGULATOR CONTROLLER
FBP Regulation Voltage
FBP Fault Trip Level
V
I
= 1ꢀꢀµA
falling
1.2ꢁ1
ꢀ.96
-5ꢀ
1.25ꢀ
1.ꢀꢀ
1.269
1.ꢀ4
+5ꢀ
V
V
FBP
DRVP
V
V
FBP
FBP
FBP Input Bias Current
I
= 1.4V
nA
FBP
FBP Effective Load-Regulation
Error (Transconductance)
V
= 1ꢀV, I
= 5ꢀµA to 1mA
-ꢀ.7
-1.5
%
DRVP
DRVP
_______________________________________________________________________________________
3
TFT-LCD DC-DC Converters with
Operational Amplifiers
ELECTRICAL CHARACTERISTICS (continued)
(V = ꢁV, V
IN
= 8V, PGND = AGND = BGND = ꢀ, I
= 25µA, T = 0°C to +85°C. Typical values are at T = +25°C, unless other-
SUP
REF
A
A
wise noted.)
PARAMETER
FBP Line (IN) Regulation Error
DRVP Sink Current
SYMBOL
CONDITIONS
MIN
TYP
1.5
5
MAX
UNITS
mV
I
= 1ꢀꢀµA, 2.6V < V < 5.5V
5
DRVP
IN
I
V
V
= 1.1V, V
= 1ꢀV
= 28V
1
mA
DRVP
FBP
FBP
DRVP
DRVP
DRVP Off-Leakage Current
Soft-Start Period
= 1.4V, V
ꢀ.ꢀ1
14
1ꢀ
µA
t
ms
SS
V
REF
128
/
Soft-Start Step Size
V
GATE-OFF LINEAR-REGUALTOR CONTROLLER
FBN Regulation Voltage
FBN Fault Trip Level
V
I
= 1ꢀꢀµA
rising
2ꢁ5
ꢁ7ꢀ
-5ꢀ
25ꢀ
42ꢀ
265
47ꢀ
+5ꢀ
mV
mV
nA
FBN
DRVN
V
V
FBN
FBN
FBN Input Bias Current
I
= ꢀ
FBN
FBN Effective Load-Regulation
Error (Transconductance)
V
= -1ꢀV, I
= 5ꢀµA to 1mA
DRVN
11
25
5
mV
DRVN
FBN Line (IN) Regulation Error
DRVN Source Current
DRVN Off-Leakage Current
Soft-Start Period
I
= ꢀ.1mA, 2.6V < V < 5.5V
+ꢀ.7
4
mV
mA
µA
DRVN
IN
I
V
V
= 5ꢀꢀmV, V = -1ꢀV
DRVN
1
DRVN
FBN
FBN
= ꢀV, V
= -25V
-ꢀ.ꢀ1
14
-1ꢀ
DRVN
t
ms
SS
V
REF
128
/
Soft-Start Step Size
V
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
DEL Capacitor Charge Current
DEL Turn-On Threshold
During startup, V
= 1V
4
5
6
µA
V
DEL
V
1.19
1.25
1.ꢁ1
TH(DEL)
DEL Discharge Switch On-
Resistance
During UVLO, V = 2.2V
2ꢀ
Ω
IN
CTL Input Low Voltage
V
V
= 2.6V to 5.5V
= 2.6V to 5.5V
ꢀ.6
+1
V
V
IN
IN
CTL Input High Voltage
2
CTL Input Leakage Current
CTL-to-SRC Propagation Delay
SRC Input Voltage Range
CTL = AGND or IN
-1
µA
ns
V
1ꢀꢀ
28
1ꢀꢀ
ꢁꢀ
V
V
= 1.5V, CTL = IN
5ꢀ
15
DEL
DEL
SRC Input Current
I
µA
Ω
SRC
= 1.5V, CTL = AGND
SRC to COM Switch On-
Resistance
R
V
V
V
= 1.5V, CTL = IN
= 1.5V, CTL = AGND
= 1.1V
6
12
7ꢀ
SRC(ON)
DRN(ON)
COM(ON)
DEL
DEL
DEL
DRN to COM Switch On-
Resistance
R
ꢁ5
Ω
COM to PGND Switch On-
Resistance
R
ꢁ5ꢀ
1ꢀꢀꢀ
18ꢀꢀ
Ω
4
_______________________________________________________________________________________
TFT-LCD DC-DC Converters with
Operational Amplifiers
ELECTRICAL CHARACTERISTICS
(V = ꢁV, V
= 8V, PGND = AGND = BGND = ꢀ, I
= 25µA, T = -40°C to +85°C, unless otherwise noted.) (Note 1)
REF A
IN
SUP
PARAMETER
IN Supply Range
SYMBOL
CONDITIONS
MIN
MAX
UNITS
V
2.6
5.5
V
IN
IN Undervoltage-Lockout
Threshold
V
V
V
rising, typical hysteresis = 15ꢀmV
2.265
2.715
ꢀ.8
V
UVLO
IN
= V
= 1.4V, V
= ꢀ,
FB
FBP
FBN
LX not switching
IN Quiescent Current
I
IN
mA
V
V
= 1.1V, V
= 1.4V, V
= ꢀ,
FB
FBP
FBN
11
LX switching
REF Output Voltage
-2µA < I
< 5ꢀµA, V = 2.6V to 5.5V
1.222
1.269
REF
IN
MAIN STEP-UP REGULATOR
Output Voltage Range
Operating Frequency
FB Regulation Voltage
FB Line Regulation
V
f
V
1ꢁ
1ꢁ8ꢀ
1.25ꢀ
±ꢀ.15
+4ꢀ
ꢁꢀꢀ
V
kHz
V
MAIN
IN
1ꢀ2ꢀ
OSC
V
No load
1.212
FB
V
V
= 2.6V to 5.5V
= 1.4V
%/V
nA
µS
mΩ
A
IN
FB Input Bias Current
FB Transconductance
LX On-Resistance
-4ꢀ
75
FB
∆I
= 5µA
COMP
R
25ꢀ
LX(ON)
LX Current Limit
I
V
= 1V, duty cycle = 65%
FB
2.5
4.5
ꢁ.5
LIM
OPERATIONAL AMPLIFIERS
SUP Supply Range
V
1ꢁ.ꢀ
4.8
ꢁ.ꢀ
1.1
12
V
SUP
MAX1518
MAX1517
MAX1516
Buffer configuration,
_ = 4V, no load
SUP Supply Current
I
mA
SUP
V
POS
Input Offset Voltage
V
(V
NEG
_, V
_, V
POS
_)
V
SUP
/ 2
mV
V
OS
OUT
Input Common-Mode Range
V
ꢀ
V
CM
SUP
V
-
SUP
15
I
I
_ = 1ꢀꢀµA
_ = 5mA
OUT
OUT
Output Voltage Swing, High
V
mV
OH
V
-
SUP
15ꢀ
I
I
_ = -1ꢀꢀµA
_ = -5mA
15
OUT
OUT
Output Voltage Swing, Low
Short-Circuit Current
V
mV
mA
mA
OL
15ꢀ
Source
Sink
5ꢀ
5ꢀ
To V
/ 2
SUP
(V
_ , V _, V
POS
_)
V / 2,
SUP
NEG
OUT
Output Source and Sink Current
4ꢀ
|∆V | < 1ꢀmV
OS
GATE-ON LINEAR-REGULATOR CONTROLLER
FBP Regulation Voltage
V
I
= 1ꢀꢀµA
DRVP
1.218
1.269
V
FBP
_______________________________________________________________________________________
5
TFT-LCD DC-DC Converters with
Operational Amplifiers
ELECTRICAL CHARACTERISTICS (continued)
(V = ꢁV, V
IN
= 8V, PGND = AGND = BGND = ꢀ, I
= 25µA, T = -40°C to +85°C, unless otherwise noted.) (Note 1)
REF A
SUP
PARAMETER
SYMBOL
CONDITIONS
= 5ꢀµA to 1mA
DRVP
MIN
MAX
UNITS
FBP Effective Load-Regulation
Error (Transconductance)
V
= 1ꢀV, I
-2
%
DRVP
FBP Line (IN) Regulation Error
DRVP Sink Current
I
= 1ꢀꢀµA, 2.6V < V < 5.5V
5
mV
mA
DRVP
IN
I
V
= 1.1V, V = 1ꢀV
DRVP
1
DRVP
FBP
GATE-OFF LINEAR-REGULATOR CONTROLLER
FBN Regulation Voltage
V
I
= 1ꢀꢀµA
= -1ꢀV, I
2ꢁ5
265
25
5
mV
mV
FBN
DRVN
FBN Effective Load-Regulation
Error (Transconductance)
V
= 5ꢀµA to 1mA
DRVN
DRVN
FBN Line (IN) Regulation Error
DRVN Source Current
I
= ꢀ.1mA, 2.6V < V < 5.5V
mV
mA
DRVN
IN
I
V
= 5ꢀꢀmV, V = -1ꢀV
DRVN
1
DRVN
FBN
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
DEL Capacitor Charge Current
DEL Turn-On Threshold
CTL Input Low Voltage
During startup, V
= 1V
4
6
µA
V
DEL
V
1.19
1.ꢁ1
ꢀ.6
TH(DEL)
V
V
= 2.6V to 5.5V
V
IN
IN
CTL Input High Voltage
SRC Input Voltage Range
= 2.6V to 5.5V
2
V
28
1ꢀꢀ
ꢁꢀ
V
V
V
= 1.5V, CTL = IN
DEL
DEL
SRC Input Current
I
µA
Ω
SRC
= 1.5V, CTL = AGND
SRC to COM Switch On-
Resistance
R
V
V
V
= 1.5V, CTL = IN
12
7ꢀ
SRC(ON)
DRN(ON)
COM(ON)
DEL
DEL
DEL
DRN to COM Switch On-
Resistance
R
= 1.5V, CTL = AGND
= 1.1V
Ω
COM to PGND Switch On-
Resistance
R
ꢁ5ꢀ
18ꢀꢀ
Ω
Note 1: Specifications to -4ꢀ°C are guaranteed by design, not production tested.
6
_______________________________________________________________________________________
TFT-LCD DC-DC Converters with
Operational Amplifiers
Typical Operating Characteristics
(Circuit of Figure 1. V = 5V, V
IN
= 1ꢁV, V
= 24V, V
= -8V, V
= V
= V
= V
= V
= 6.5V, T = +25°C
MAIN
GON
GOFF
OUT1
OUT2
OUTꢁ
OUT4
OUT5 A
unless otherwise noted.)
STEP-UP SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SWITCHING FREQUENCY
vs. INPUT VOLTAGE
STEP-UP EFFICIENCY
vs. LOAD CURRENT
10
1.4
1.3
1.2
1.1
1.0
100
90
80
70
60
50
40
30
NO LOAD, SUP DISCONNECTED,
R1 = 95.3kΩ, R2 = 10.2kΩ
V
= 5.0V
IN
8
6
4
2
0
V
= 3.3V
IN
CURRENT INTO INDUCTOR
CURRENT INTO IN PIN
V
= 13V
1000
OUT
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1
10
100
SUPPLY VOLTAGE (V)
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
STEP-UP REGULATOR SOFT-START
(HEAVY LOAD)
STEP-UP REGULATOR PULSED
LOAD-TRANSIENT RESPONSE
MAX1516 toc05
MAX1516 toc04
A
0V
A
200mA
B
0V
13V
B
C
0A
C
0A
10µs/div
A: LOAD CURRENT, 1A/div
B: V , 200mV/div, AC-COUPLED
2ms/div
A: V , 5V/div
IN
B: V
, 5V/div
MAIN
MAIN
C: INDUCTOR CURRENT, 1A/div
C: INDUCTOR CURRENT, 1A/div
_______________________________________________________________________________________
7
TFT-LCD DC-DC Converters with
Operational Amplifiers
Typical Operating Characteristics (continued)
(Circuit of Figure 1. V = 5V, V
IN
= 1ꢁV, V
= 24V, V
= -8V, V
= V
= V
= V
= V
= 6.5V, T = +25°C
MAIN
GON
GOFF
OUT1
OUT2
OUTꢁ
OUT4
OUT5 A
unless otherwise noted.)
TIMER DELAY LATCH
RESPONSE TO OVERLOAD
REF VOLTAGE LOAD REGULATION
GATE-ON REGULATOR LINE REGULATION
MAX1516 toc06
1.253
0.2
0
A
1.252
1.251
1.250
1.249
1.248
1.247
0V
-0.2
-0.4
-0.6
-0.8
-1.0
B
V
= 23.5V
= 20mA
GON
GON
55ms
I
0A
0
10
20
30
40
50
23
24
25
26
27
28
29
30
10ms/div
, 5V/div
LOAD CURRENT (µA)
INPUT VOLTAGE (V)
A: V
MAIN
B: INDUCTOR CURRENT, 1A/div
GATE-ON REGULATOR LOAD REGULATION
GATE-OFF REGULATOR LINE REGULATION
GATE-OFF REGULATOR LOAD REGULATION
0
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
1.00
0.75
0.50
0.25
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
V
I
= -8V
= 50mA
GOFF
GOFF
-0.25
0
5
10
15
20
-16
-14
-12
INPUT VOLTAGE (V)
-10
-8
0
10
20
30
40
50
LOAD CURRENT (mA)
LOAD CURRENT (mA)
8
_______________________________________________________________________________________
TFT-LCD DC-DC Converters with
Operational Amplifiers
Typical Operating Characteristics (continued)
(Circuit of Figure 1. V = 5V, V
IN
= 1ꢁV, V
= 24V, V
= -8V, V
= V
= V
= V
= V
= 6.5V, T = +25°C
MAIN
GON
GOFF
OUT1
OUT2
OUTꢁ
OUT4
OUT5 A
unless otherwise noted.)
OPERATIONAL-AMPLIFIER
MAX1518 OPERATIONAL-AMPLIFIER
SUPPLY CURRENT vs. SUPPLY VOLTAGE
RAIL-TO-RAIL INPUT/OUTPUT
POWER-UP SEQUENCE
MAX1516 toc14
MAX1516 toc12
6
5
4
3
2
1
0
V
= 6V
SUP
A
0V
A
B
0V
B
0V
0V
C
NO-LOAD
BUFFER CONFIGURATION
D
V
TO V
= V / 2
POS1
POS5
SUP
0V
0V
40µs/div
4ms/div
4.5
6.0
6.5
7.0
7.5
8.0
8.5
A: INPUT SIGNAL, 2V/div
B: OUTPUT SIGNAL, 2V/div
A: V
, 10V/div
SUPPLY VOLTAGE (V)
MAIN
SRC
B: V , 20V/div
C: V
, 10V/div
GOFF
D: V , 20V/div
GON
OPERATIONAL-AMPLIFIER
OPERATIONAL-AMPLIFIER
SMALL-SIGNAL STEP RESPONSE
OPERATIONAL-AMPLIFIER
LOAD-TRANSIENT RESPONSE
LARGE-SIGNAL STEP RESPONSE
MAX1516 toc16
MAX1516 toc17
MAX1516 toc15
V
= 6V
SUP
A
A
0V
A
0V
0V
+50mA
B
0
B
B
-50mA
0V
0V
1µs/div
A: INPUT SIGNAL, 2V/div
B: OUTPUT SIGNAL, 2V/div
400ns/div
400ns/div
A: INPUT SIGNAL, 100mV/div
B: OUTPUT SIGNAL, 100mV/div
A: OUTPUT VOLTAGE, 1V/div, AC-COUPLED
B: OUTPUT CURRENT, 50mA/div
_______________________________________________________________________________________
9
TFT-LCD DC-DC Converters with
Operational Amplifiers
Pin Description
NAME
PIN
1
FUNCTION
MAX1516 MAX1517 MAX1518
Switch Input. Source of the internal high-voltage p-channel MOSFET. Bypass SRC to
PGND with a minimum ꢀ.1µF capacitor close to the pins.
SRC
REF
SRC
REF
SRC
REF
Reference Bypass Terminal. Bypass REF to AGND with a minimum of ꢀ.22µF close to
the pins.
2
Analog Ground for Step-Up Regulator and Linear Regulators. Connect to power
ground (PGND) underneath the IC.
ꢁ
AGND
AGND
AGND
Power Ground. PGND is the source of the main step-up n-channel power MOSFET.
Connect PGND to the input-capacitor ground terminals through a short, wide PC board
trace. Connect to analog ground (AGND) underneath the IC.
4
PGND
PGND
PGND
5
6
7
OUT1
NEG1
POS1
OUT1
NEG1
POS1
OUT1
NEG1
POS1
Operational-Amplifier 1 Output
Operational-Amplifier 1 Inverting Input
Operational-Amplifier 1 Noninverting Input
Operational-Amplifier 2 Output for the MAX1518 and MAX1517. Not Internally
Connected for the MAX1516.
8
N.C.
N.C.
I. C.
OUT2
NEG2
POS2
BGND
N.C.
OUT2
NEG2
POS2
BGND
POSꢁ
OUTꢁ
SUP
Operational-Amplifier 2 Inverting Input for the MAX1518 and MAX1517. Not Internally
Connected for the MAX1516.
9
Operational-Amplifier 2 Noninverting Input for the MAX1518 and MAX1517. Internally
Connected for the MAX1516. Connect this pin to GND for the MAX1516.
1ꢀ
11
12
1ꢁ
14
15
16
17
18
19
Analog Ground for Operational Amplifiers. Connect to power ground (PGND)
underneath the IC.
BGND
N.C.
N.C.
SUP
N.C.
N.C.
N.C.
I. C.
Operational-Amplifier ꢁ Noninverting Input for the MAX1518. Not Internally Connected
for the MAX1517 and MAX1516.
Operational-Amplifier ꢁ Output. Not Internally Connected for the MAX1517 and
MAX1516.
N.C.
Operational-Amplifier Power Input. Positive supply rail for the operational amplifiers.
SUP
Typically connected to V
. Bypass SUP to BGND with a ꢀ.1µF capacitor.
MAIN
Operational-Amplifier 4 Noninverting Input for the MAX1518. Operational-Amplifier ꢁ
Noninverting Input for the MAX1517. Not Internally Connected for the MAX1516.
POSꢁ
NEGꢁ
OUTꢁ
I. C.
POS4
NEG4
OUT4
POS5
NEG5
Operational-Amplifier 4 Inverting Input for the MAX1518. Operational-Amplifier ꢁ
Inverting Input for the MAX1517. Not Internally Connected for the MAX1516.
Operational-Amplifier 4 Output for the MAX1518. Operational-Amplifier ꢁ Output for the
MAX1517. Not Internally Connected for the MAX1516.
Operational-Amplifier 5 Noninverting Input for the MAX1518. Internally Connected for
the MAX1517 and MAX1516. Connect this pin to GND for the MAX1517 and MAX1516.
Operational-Amplifier 5 Inverting Input. Not Internally Connected for the MAX1517 and
MAX1516.
N.C.
N.C.
10 ______________________________________________________________________________________
TFT-LCD DC-DC Converters with
Operational Amplifiers
Pin Description (continued)
NAME
PIN
FUNCTION
MAX1516 MAX1517 MAX1518
Operational-Amplifier 5 Output. Not Internally Connected for the MAX1517 and
MAX1516.
2ꢀ
N.C.
N.C.
OUT5
N-Channel Power MOSFET Drain and Switching Node. Connect the inductor and
Schottky diode to LX and minimize the trace area for lowest EMI.
21
22
LX
IN
LX
IN
LX
IN
Supply Voltage Input. IN can range from 2.6V to 5.5V.
Step-Up Regulator Feedback Input. Regulates to 1.2ꢁ6V (nominal). Connect a resistive
voltage-divider from the output (V
divider within 5mm of FB.
) to FB to analog ground (AGND). Place the
2ꢁ
24
FB
FB
FB
MAIN
Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RC from
COMP to AGND. See the Loop Compensation section for component selection
guidelines.
COMP
COMP
COMP
Gate-On Linear-Regulator Feedback Input. FBP regulates to 1.25V (nominal). Connect
FBP to the center of a resistive voltage-divider between the regulator output and AGND
to set the gate-on linear-regulator output voltage. Place the resistive voltage-divider
close to the pin.
25
26
27
FBP
DRVP
FBN
FBP
DRVP
FBN
FBP
DRVP
FBN
Gate-On Linear-Regulator Base Drive. Open drain of an internal n-channel MOSFET.
Connect DRVP to the base of an external pnp pass transistor. See the Pass-Transistor
Selection section.
Gate-Off Linear-Regulator Feedback Input. FBN regulates to 25ꢀmV (nominal).
Connect FBN to the center of a resistive voltage-divider between the regulator output
and REF to set the gate-off linear-regulator output voltage. Place the resistive voltage-
divider close to the pin.
Gate-Off Linear-Regulator Base Drive. Open drain of an internal p-channel MOSFET.
Connect DRVN to the base of an external npn pass transistor. See the Pass-Transistor
Selection section.
28
29
DRVN
DEL
DRVN
DEL
DRVN
DEL
High-Voltage Switch Delay Input. Connect a capacitor from DEL to AGND to set the
high-voltage switch startup delay.
High-Voltage Switch Control Input. When CTL is high, the high-voltage switch between
COM and SRC is on and the high-voltage switch between COM and DRN is off. When
CTL is low, the high-voltage switch between COM and SRC is off and the high-voltage
switch between COM and DRN is on. CTL is inhibited by the undervoltage lockout and
when the voltage on DEL is less than 1.25V.
ꢁꢀ
CTL
CTL
CTL
Switch Input. Drain of the internal high-voltage back-to-back p-channel MOSFETs
connected to COM.
ꢁ1
ꢁ2
DRN
DRN
DRN
Internal High-Voltage MOSFET Switch Common Terminal. Do not allow the voltage on
COM
COM
COM
COM to exceed V
.
SRC
______________________________________________________________________________________ 11
TFT-LCD DC-DC Converters with
Operational Amplifiers
Typical Operating Circuit
Table 1. Component List
The MAX1518 Typical Operating Circuit (Figure 1) is a
complete power-supply system for TFT LCDs. The cir-
cuit generates a +1ꢁV source-driver supply and +24V
and -8V gate-driver supplies. The input voltage range
for the IC is from +2.6V to +5.5V. The listed load cur-
rents in Figure 1 are available from a +4.5V to +5.5V
supply. Table 1 lists some recommended components,
and Table 2 lists the contact information of component
suppliers.
DESIGNATION
DESCRIPTION
22µF, 6.ꢁV X5R ceramic capacitor (121ꢀ)
TDK Cꢁ225X5RꢀJ227M
C1
22µF, 16V X5R ceramic capacitor (1812)
TDK C45ꢁ2X5X1C226M
C2
D1
ꢁA, ꢁꢀV Schottky diode (M-flat)
Toshiba CMSꢀ2
2ꢀꢀmA, 1ꢀꢀV, dual ultra-fast diodes (SOT2ꢁ)
Fairchild MMBD4148SE
Detailed Description
D2, Dꢁ
L1
The MAX1516/MAX1517/MAX1518 contain a high-
performance step-up switching regulator, two low-cost
linear-regulator controllers, multiple high-current opera-
tional amplifiers, and startup timing and level-shifting
functionality useful for active-matrix TFT LCDs. Figure 2
shows the MAX1518 Functional Diagram.
ꢁ.ꢀµH, ꢁA inductor
Sumida CDRH6D28-ꢁRꢀ
2ꢀꢀmA, 4ꢀV pnp bipolar transistor (SOT2ꢁ)
Fairchild MMBTꢁ9ꢀ6
Q1
2ꢀꢀmA, 4ꢀV npn bipolar transistor (SOT2ꢁ)
Fairchild MMBTꢁ9ꢀ4
Q2
Main Step-Up Regulator
The main step-up regulator employs a current-mode,
fixed-frequency PWM architecture to maximize loop
bandwidth and provide fast transient response to
pulsed loads typical of TFT-LCD panel source drivers.
The 1.2MHz switching frequency allows the use of low-
profile inductors and ceramic capacitors to minimize
the thickness of LCD panel designs. The integrated
high-efficiency MOSFET and the IC’s built-in digital
soft-start functions reduce the number of external com-
ponents required while controlling inrush currents. The
Figure ꢁ shows the Functional Diagram of the step-up
regulator. An error amplifier compares the signal at FB
to 1.2ꢁ6V and changes the COMP output. The voltage
at COMP sets the peak inductor current. As the load
varies, the error amplifier sources or sinks current to the
COMP output accordingly to produce the inductor peak
current necessary to service the load. To maintain sta-
bility at high duty cycles, a slope-compensation signal
is summed with the current-sense signal.
output voltage can be set from V to 1ꢁV with an exter-
IN
On the rising edge of the internal clock, the controller
sets a flip-flop, turning on the n-channel MOSFET and
applying the input voltage across the inductor. The cur-
rent through the inductor ramps up linearly, storing
energy in its magnetic field. Once the sum of the cur-
rent-feedback signal and the slope compensation
exceeds the COMP voltage, the controller resets the
flip-flop and turns off the MOSFET. Since the inductor
current is continuous, a transverse potential develops
across the inductor that turns on the diode (D1). The
voltage across the inductor then becomes the differ-
ence between the output voltage and the input voltage.
nal resistive voltage-divider. To generate an output volt-
age greater than 1ꢁV, an external cascoded MOSFET
is needed. See the Generating Output Voltages > 13V
section in the Design Procedures.
The regulator controls the output voltage and the power
delivered to the output by modulating the duty cycle (D)
of the internal power MOSFET in each switching cycle.
The duty cycle of the MOSFET is approximated by:
V
− V
IN
MAIN
D ≈
V
MAIN
Table 2. Component Suppliers
SUPPLIER
PHONE
FAX
WEBSITE
www.fairchildsemi.com
Fairchild
4ꢀ8-822-2ꢀꢀꢀ
847-545-67ꢀꢀ
847-8ꢀꢁ-61ꢀꢀ
949-455-2ꢀꢀꢀ
4ꢀ8-822-21ꢀ2
847-545-672ꢀ
847-ꢁ9ꢀ-44ꢀ5
949-859-ꢁ96ꢁ
Sumida
TDK
www.sumida.com
www.component.tdk.com
www.toshiba.com/taec
Toshiba
12 ______________________________________________________________________________________
TFT-LCD DC-DC Converters with
Operational Amplifiers
LX
L1
3.0µH
D1
V
V
IN
4.5V TO 5.5V
MAIN
13V/500mA
C2
22µF
C1
22µF
R10
10Ω
R1
95.3kΩ
1%
LX
IN
FB
C18
LX
R1
10.2kΩ
1%
0.1µF
0.1µF
180kΩ
AGND
PGND
COMP
220µF
0.1µF
D2
LX
0.1µF
MAX1518
6.8kΩ
6.8kΩ
DRVP
FBP
Q1
0.1µF
D3
R4
192kΩ
1%
DRVN
FBN
Q2
R7
332kΩ
1%
R5
V
GOFF
-8V/50mA
0.47µF
10.0kΩ
1%
0.22µF
R8
40.2kΩ
1%
SRC
COM
DRN
REF
DEL
V
GON
0.22µF
24V/20mA
CTL
SUP
0.033µF
0.1µF
BGND
NEG1
OUT1
NEG2
POS1
POS2
POS3
POS4
POS5
OUT2
OUT3
TO VCOM
BACKPLANE
NEG4
OUT4
NEG5
OUT5
Figure 1. Typical Operating Circuit
______________________________________________________________________________________ 13
TFT-LCD DC-DC Converters with
Operational Amplifiers
V
V
CP
CN
V
V
MAIN
IN
LX
IN
FB
STEP-UP
CONTROLLER
PGND
AGND
COMP
V
V
CP
MAX1518
DRVP
FBP
GATE-ON
CONTROLLER
GON
SRC
COM
DRN
DEL
CTL
SWITCH
CONTROL
V
V
CN
DRVN
FBN
GATE-OFF
CONTROLLER
GOFF
SUP
NEG1
OUT1
OP1
OP2
REF
REF
POS1
NEG2
NEG4
OUT2
POS2
OUT4
OP4
POS4
NEG5
OUT3
POS3
OUT5
POS5
OP3
OP5
BGND
Figure 2. MAX1518 Functional Diagram
14 ______________________________________________________________________________________
TFT-LCD DC-DC Converters with
Operational Amplifiers
LX
RESET DOMINANT
CLOCK
S
PGND
R
Q
ILIM
COMPARATOR
SOFT-
START
V
LIMIT
SLOPE COMP
PWM
COMPARATOR
CURRENT
SENSE
Σ
OSCILLATOR
FAULT
COMPARATOR
TO FAULT LATCH
ERROR AMP
1.0V
FB
1.236V
COMP
Figure 3. Step-Up Regulator Functional Diagram
This discharge condition forces the current through the
inductor to ramp back down, transferring the energy
stored in the magnetic field to the output capacitor and
the load. The MOSFET remains off for the rest of the
clock cycle.
REG P is typically used to provide the TFT-LCD gate
drivers’ gate-on voltage. Use a charge pump with as
many stages as necessary to obtain a voltage exceed-
ing the required gate-on voltage (see the Selecting the
Number of Charge-Pump Stages section). Note the
voltage rating of the DRVP is 28V. If the charge-pump
output voltage can exceed 28V, an external cascode
npn transistor should be added as shown in Figure 4.
Alternately, the linear regulator can control an interme-
diate charge-pump stage while regulating the final
charge-pump output (Figure 5).
Gate-On Linear-Regulator Controller, REG P
The gate-on linear-regulator controller (REG P) is an
analog gain block with an open-drain n-channel output.
It drives an external pnp pass transistor with a 6.8kΩ
base-to-emitter resistor (Figure 1). Its guaranteed base-
drive sink current is at least 1mA. The regulator including
Q1 in Figure 1 uses a ꢀ.47µF ceramic output capacitor
and is designed to deliver 2ꢀmA at 24V. Other output
voltages and currents are possible with the proper pass
transistor and output capacitor. See the Pass-Transistor
Selection and Stability Requirements sections.
REG P is enabled after the REF voltage exceeds 1.ꢀV.
Each time it is enabled, the controller goes through a
soft-start routine that ramps up its internal reference
DAC in 128 steps.
______________________________________________________________________________________ 15
TFT-LCD DC-DC Converters with
Operational Amplifiers
LX
FROM CHARGE-PUMP
0.1µF
V
OUTPUT
MAIN
V
MAIN
13V
0.1µF
PNP PASS
TRANSISTOR
DRVP
NPN CASCODE
TRANSISTOR
6.8kΩ
V
GON
DRVP
Q1
V
GON
35V
MAX1516
MAX1517
MAX1518
MAX1516
MAX1517
MAX1518
0.47µF
0.22µF
267kΩ
1%
FBP
FBP
10.0kΩ
1%
Figure 5. The linear regulator controls the intermediate charge-
pump stage.
Figure 4. Using Cascoded npn for Charge-Pump Output
Voltages >28V
Short-Circuit Current Limit
The operational amplifiers limit short-circuit current to
approximately ±15ꢀmA if the output is directly shorted to
SUP or to BGND. If the short-circuit condition persists, the
junction temperature of the IC rises until it reaches the
thermal-shutdown threshold (+16ꢀ°C typ). Once the junc-
tion temperature reaches the thermal-shutdown threshold,
an internal thermal sensor immediately sets the thermal
fault latch, shutting off all the IC’s outputs. The device
remains inactive until the input voltage is cycled.
Gate-Off Linear-Regulator Controller, REG N
The gate-off linear-regulator controller (REG N) is an
analog gain block with an open-drain p-channel output.
It drives an external npn pass transistor with a 6.8kΩ
base-to-emitter resistor (Figure 1). Its guaranteed base-
drive source current is at least 1mA. The regulator
including Q2 in Figure 1 uses a ꢀ.47µF ceramic output
capacitor and is designed to deliver 5ꢀmA at -8V. Other
output voltages and currents are possible with the proper
pass transistor and output capacitor (see the Pass-
Transistor Selection and Stability Requirements sections).
Driving Pure Capacitive Load
The operational amplifiers are typically used to drive
the LCD backplane (VCOM) or the gamma-correction
divider string. The LCD backplane consists of a distrib-
uted series capacitance and resistance, a load that can
be easily driven by the operational amplifier. However,
if the operational amplifier is used in an application with
a pure capacitive load, steps must be taken to ensure
stable operation.
REG N is typically used to provide the TFT-LCD gate
drivers’ gate-off voltage. A negative voltage can be
produced using a charge-pump circuit as shown in
Figure 1. REG N is enabled after the voltage on REF
exceeds 1.ꢀV. Each time it is enabled, the control goes
through a soft-start routine that ramps down its internal
reference DAC from V
to 25ꢀmV in 128 steps.
REF
Operational Amplifiers
As the operational amplifier’s capacitive load increases,
the amplifier’s bandwidth decreases and gain peaking
increases. A 5Ω to 5ꢀΩ small resistor placed between
OUT_ and the capacitive load reduces peaking but also
reduces the gain. An alternative method of reducing
peaking is to place a series RC network (snubber) in par-
allel with the capacitive load. The RC network does not
continuously load the output or reduce the gain. Typical
values of the resistor are between 1ꢀꢀΩ and 2ꢀꢀΩ, and
the typical value of the capacitor is 1ꢀnF.
The MAX1518 has five operational amplifiers, the
MAX1517 has three operational amplifiers, and the
MAX1516 has one operational amplifier. The operational
amplifiers are typically used to drive the LCD backplane
(VCOM) or the gamma-correction divider string. They
feature ±15ꢀmA output short-circuit current, 1ꢁV/µs slew
rate, and 12MHz bandwidth. The rail-to-rail input and
output capability maximizes system flexibility.
16 ______________________________________________________________________________________
TFT-LCD DC-DC Converters with
Operational Amplifiers
Undervoltage Lockout (UVLO)
The undervoltage-lockout (UVLO) circuit compares the
input voltage at IN with the UVLO threshold (2.5V rising,
2.ꢁ5V falling, typ) to ensure the input voltage is high
enough for reliable operation. The 15ꢀmV (typ) hysteresis
prevents supply transients from causing a restart. Once
the input voltage exceeds the UVLO rising threshold,
startup begins. When the input voltage falls below the
UVLO falling threshold, the controller turns off the main
step-up regulator, turns off the linear-regulator outputs,
and disables the switch control block; the operational-
amplifier outputs are high impedance.
V
V
V
V
IN
2.5V
REF
MAIN
GON
1.05V
Reference Voltage (REF)
The reference output is nominally 1.25V and can
source at least 5ꢀµA (see the Typical Operating
Characteristics). Bypass REF with a ꢀ.22µF ceramic
capacitor connected between REF and AGND.
V
GOFF
V
DEL
12ms
1.25V
SWITCH
CONTROL
ENABLED
INPUT SOFT- SOFT-
VOLTAGE START START
OK BEGINS ENDS
Power-Up Sequence and Soft-Start
Once the voltage on IN exceeds approximately 1.7V,
the reference turns on. With a ꢀ.22µF REF bypass
capacitor, the reference reaches its regulation voltage
of 1.25V in approximately 1ms. When the reference
voltage exceeds 1.ꢀV, the ICs enable the main step-up
regulator, the gate-on linear-regulator controller, and
the gate-off linear-regulator controller simultaneously.
Figure 6. Power-Up Sequence
1.25V (typ), the switch-control block is enabled as
shown in Figure 6. After the switch-control block is
enabled, COM can be connected to SRC or DRN
through the internal p-channel switches, depending
upon the state of CTL. Before startup and when IN is
The IC employs soft-start for each regulator to minimize
inrush current and voltage overshoot and to ensure a
well-defined startup behavior. During the soft-start, the
main step-up regulator directly limits the peak inductor
current. The current-limit level is increased through the
soft-start period from ꢀ up to the full current-limit value
in eight equal current steps (ILIM / 8). The maximum
load current is available after the output voltage reach-
es regulation (which terminates soft-start), or after the
soft-start timer expires. Both linear-regulator controllers
use a 7-bit soft-start DAC. For the gate-on linear regula-
tor, the DAC output is stepped in 128 steps from zero
up to the reference voltage. For the gate-off linear regu-
lator, the DAC output steps from the reference down to
25ꢀmV in 128 steps. The soft-start duration is 14ms
(typ) for all three regulators.
less than V
, DEL is internally connected to AGND
DEL
UVLO
to discharge C
. Select C
to set the delay time
DEL
using the following equation:
5µA
1.25V
C
=DELAY_TIME×
DEL
Switch-Control Block
The switch-control input (CTL) is not activated until all
four of the following conditions are satisfied: the input
voltage exceeds V
, the soft-start routine of all the
UVLO
regulators is complete, there is no fault condition
detected, and V exceeds its turn-on threshold. As
DEL
shown in Figure 7, COM is pulled down to PGND
through a 1kΩ resistor when the switch control is not
activated. Once activated and if CTL is high, the 5Ω
internal p-channel switch (Q1) between COM and SRC
turns on and the ꢁꢀΩ p-channel switch (Q2) between
DRN and COM turns off. If CTL is low, Q1 turns off and
Q2 turns on.
A capacitor (C ) from DEL to AGND determines the
DEL
switch-control-block startup delay. After the input volt-
age exceeds the UVLO threshold (2.5V typ) and the
soft-start routine for each regulator is complete and
there is no fault detected, a 5µA current source starts
charging C
. Once the capacitor voltage exceeds
DEL
______________________________________________________________________________________ 17
TFT-LCD DC-DC Converters with
Operational Amplifiers
IN
MAX1516
MAX1517
MAX1518
5µA
2.5V
FB OK
FBP OK
FBN OK
SRC
Q1
DEL
REF
COM
1kΩ
CTL
Q2
Q3
DRN
Figure 7. Switch-Control Block
Fault Protection
Thermal-Overload Protection
Thermal-overload protection prevents excessive power
dissipation from overheating the MAX1516/MAX1517/
During steady-state operation, if the output of the main
regulator or any of the linear-regulator outputs does not
exceed its respective fault-detection threshold, the
MAX1516/MAX1517/MAX1518 activate an internal fault
timer. If any condition or combination of conditions indi-
cates a continuous fault for the fault-timer duration
(55ms typ), the MAX1516/MAX1517/MAX1518 set the
fault latch to shut down all the outputs except the refer-
ence. Once the fault condition is removed, cycle the
input voltage (below the UVLO falling threshold) to
clear the fault latch and reactivate the device. The fault-
detection circuit is disabled during the soft-start time.
MAX1518. When the junction temperature exceeds T =
J
+16ꢀ°C, a thermal sensor immediately activates the
fault protection, which shuts down all outputs except
the reference, allowing the device to cool down. Once
the device cools down by approximately 15°C, cycle
the input voltage (below the UVLO falling threshold) to
clear the fault latch and reactivate the device.
The thermal-overload protection protects the controller
in the event of fault conditions. For continuous opera-
tion, do not exceed the absolute maximum junction
temperature rating of T = +15ꢀ°C.
J
18 ______________________________________________________________________________________
TFT-LCD DC-DC Converters with
Operational Amplifiers
Design Procedure
Main Step-Up Regulator
2
η
V
V
− V
× f
IN
MAIN IN
TYP
L =
V
I
LIR
MAIN MAIN(MAX) OSC
Inductor Selection
The minimum inductance value, peak current rating,
and series resistance are factors to consider when
selecting the inductor. These factors influence the con-
verter’s efficiency, maximum output load capability,
transient-response time, and output voltage ripple. Size
and cost are also important factors to consider.
Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input cur-
rent at the minimum input voltage (V
) using con-
IN(MIN)
servation of energy and the expected efficiency at that
operating point (η ) taken from the appropriate curve
MIN
in the Typical Operating Characteristics:
The maximum output current, input voltage, output volt-
age, and switching frequency determine the inductor
value. Very high inductance values minimize the cur-
rent ripple and therefore reduce the peak current,
which decreases core losses in the inductor and I2R®
losses in the entire power path. However, large induc-
tor values also require more energy storage and more
turns of wire, which increases size and can increase
I2R losses in the inductor. Low inductance values
decrease the size but increase the current ripple and
peak current. Finding the best inductor involves choos-
ing the best compromise between circuit efficiency,
inductor size, and cost.
I
× V
MAIN(MAX)
MAIN
I
=
IN(DC,MAX)
V
× η
MIN
IN(MIN)
Calculate the ripple current at that operating point and
the peak current required for the inductor:
V
×(V
− V
)
IN(MIN)
MAIN
IN(MIN)
I
=
RIPPLE
L × V
× f
MAIN OSC
I
RIPPLE
I
=I
+
PEAK IN(DC,MAX)
2
The inductor’s saturation current rating and the
MAX1516/MAX1517/MAX1518s’ LX current limit (I
The equations used here include a constant LIR, which
is the ratio of the inductor peak-to-peak ripple current
to the average DC inductor current at the full load cur-
rent. The best trade-off between inductor size and cir-
cuit efficiency for step-up regulators generally has an
LIR between ꢀ.ꢁ and ꢀ.5. However, depending on the
AC characteristics of the inductor core material and
ratio of inductor resistance to other power-path resis-
tances, the best LIR can shift up or down. If the induc-
tor resistance is relatively high, more ripple can be
accepted to reduce the number of turns required and
increase the wire diameter. If the inductor resistance is
relatively low, increasing inductance to lower the peak
current can decrease losses throughout the power
path. If extremely thin high-resistance inductors are
used, as is common for LCD-panel applications, the
best LIR can increase to between ꢀ.5 and 1.ꢀ.
)
LIM
should exceed I
, and the inductor’s DC current
PEAK
rating should exceed I
choose an inductor with less than ꢀ.1Ω series resistance.
. For good efficiency,
IN(DC,MAX)
Considering the Typical Operating Circuit, the maximum
load current (I ) is 5ꢀꢀmA with a 1ꢁV output and
MAIN(MAX)
a typical input voltage of 5V. Choosing an LIR of ꢀ.5 and
estimating efficiency of 85% at this operating point:
2
5V
1ꢁV
1ꢁV − 5V
ꢀ.5A ×1.2MHz ꢀ.5
ꢀ.85
L =
≈ ꢁ.ꢁµH
Using the circuit’s minimum input voltage (4.5V) and
estimating efficiency of 8ꢀ% at that operating point:
ꢀ.5A ×1ꢁV
4.5V × ꢀ.8
I
=
≈1.8A
Once a physical inductor is chosen, higher and lower
values of the inductor should be evaluated for efficien-
cy improvements in typical operating regions.
IN(DC,MAX)
The ripple current and the peak current are:
Calculate the approximate inductor value using the typ-
4.5V ×(1ꢁV − 4.5V)
ꢁ.ꢁµH×1ꢁV ×1.2MHz
ical input voltage (V ), the maximum output current
IN
I
=
≈ ꢀ.74A
RIPPLE
(I
), the expected efficiency (η
) taken from
TYP
MAIN(MAX)
an appropriate curve in the Typical Operating
Characteristics section, and an estimate of LIR based
on the above discussion:
ꢀ.74A
2
I
=1.8A +
≈ 2.2A
PEAK
I2R is a registered trademark of Instruments for Research and
Industry, Inc.
______________________________________________________________________________________ 19
TFT-LCD DC-DC Converters with
Operational Amplifiers
Output-Capacitor Selection
The total output voltage ripple has two components: the
capacitive ripple caused by the charging and discharg-
ing of the output capacitance, and the ohmic ripple due
to the capacitor’s equivalent series resistance (ESR).
where V , the step-up regulator’s feedback set point,
FB
is 1.2ꢁ6V. Place R1 and R2 close to the IC.
Generating Output Voltages >13V
The maximum output voltage of the step-up regulator is
1ꢁV, which is limited by the absolute maximum rating of
the internal power MOSFET. To achieve higher output
voltages, an external n-channel MOSFET can be cascod-
ed with the internal FET (Figure 8). Since the gate of the
external FET is biased from the input supply, use a logic-
level FET to ensure that the FET is fully enhanced at the
minimum input voltage. The current rating of the FET
needs to be higher than the IC’s internal current limit.
V
= V
+ V
RIPPLE
RIPPLE(C) RIPPLE(ESR)
I
C
V
V
− V
MAIN
MAIN IN
V
≈
, and
RIPPLE(C)
f
OUT
MAIN OSC
V
≈I
R
RIPPLE(ESR) PEAK ESR(COUT)
where I
is the peak inductor current (see the
PEAK
Inductor Selection section). For ceramic capacitors, the
Loop Compensation
output voltage ripple is typically dominated by
Choose R
to set the high-frequency integrator
COMP
V
. The voltage rating and temperature charac-
RIPPLE(C)
gain for fast transient response. Choose C
the integrator zero to maintain loop stability.
to set
COMP
teristics of the output capacitor must also be considered.
Input-Capacitor Selection
The input capacitor (C ) reduces the current peaks
For low-ESR output capacitors, use the following equa-
tions to obtain stable performance and good transient
response:
IN
drawn from the input supply and reduces noise injec-
tion into the IC. A 22µF ceramic capacitor is used in the
Typical Applications Circuit (Figure 1) because of the
high source impedance seen in typical lab setups.
Actual applications usually have much lower source
impedance since the step-up regulator often runs
directly from the output of another regulated supply.
ꢁ15× V × V
×C
OUT
IN
OUT
R
≈
≈
COMP
L ×I
MAIN(MAX)
V
×C
OUT
OUT
C
COMP
1ꢀ×I
×R
MAIN(MAX)
COMP
Typically, C can be reduced below the values used in
IN
the Typical Applications Circuit. Ensure a low-noise
To further optimize transient response, vary R
in
COMP
supply at IN by using adequate C . Alternately,
IN
2ꢀ% steps and C
in 5ꢀ% steps while observing
COMP
greater voltage variation can be tolerated on C if IN is
IN
transient-response waveforms.
decoupled from C using an RC lowpass filter (see
IN
Charge Pumps
R1ꢀ and C18 in Figure 1).
Selecting the Number of Charge-Pump Stages
For highest efficiency, always choose the lowest num-
ber of charge-pump stages that meet the output
requirement. Figures 9 and 1ꢀ show the positive and
negative charge-pump output voltages for a given
Rectifier Diode
The MAX1516/MAX1517/MAX1518s’ high switching fre-
quency demands a high-speed rectifier. Schottky
diodes are recommended for most applications
because of their fast recovery time and low forward
voltage. In general, a 2A Schottky diode complements
the internal MOSFET well.
V
for one-, two-, and three-stage charge pumps.
MAIN
The number of positive charge-pump stages is given by:
Output-Voltage Selection
The output voltage of the main step-up regulator can be
adjusted by connecting a resistive voltage-divider from
V
+ V
− V
−2× V
D
GON
DROPOUT MAIN
n
=
POS
V
MAIN
the output (V
) to AGND with the center tap connect-
MAIN
where n
is the number of positive charge-pump
is the gate-on linear-regulator REG P out-
is the main step-up regulator output, V is
POS
GON
MAIN
ed to FB (see Figure 1). Select R2 in the 1ꢀkΩ to 5ꢀkΩ
range. Calculate R1 with the following equation:
stages, V
put, V
D
the forward-voltage drop of the charge-pump diode,
V
V
MAIN
and V
is the dropout margin for the linear reg-
= ꢀ.ꢁV.
DROPOUT
DROPOUT
ulator. Use V
R1=R2×
−1
FB
20 ______________________________________________________________________________________
TFT-LCD DC-DC Converters with
Operational Amplifiers
nitely has a negligible effect on output-current capabili-
ty because the internal switch resistance and the diode
impedance place a lower limit on the source imped-
ance. A ꢀ.1µF ceramic capacitor works well in most
low-current applications. The flying capacitor’s voltage
rating must exceed the following:
V
>13V
MAIN
V
IN
LX
FB
V
> n× V
MAIN
CX
STEP-UP
CONTROLLER
where n is the stage number in which the flying capaci-
tor appears, and V is the output voltage of the
PGND
MAIN
main step-up regulator.
MAX1516
Charge-Pump Output Capacitor
Increasing the output capacitance or decreasing the
ESR reduces the output ripple voltage and the peak-to-
peak transient voltage. With ceramic capacitors, the
output voltage ripple is dominated by the capacitance
value. Use the following equation to approximate the
required capacitor value:
MAX1517
MAX1518
Figure 8. Operation with Output Voltages >13V Using
Cascoded MOSFET
The number of negative charge-pump stages is given by:
I
LOAD_CP
C
≥
OUT_CP
−V
+ V
DROPOUT
GOFF
V
2f
V
OSC RIPPLE_CP
n
=
NEG
−2× V
MAIN
D
where C
pump, I
pump, and V
output ripple.
is the output capacitor of the charge
is the load current of the charge
RIPPLE_CP
OUT_CP
LOAD_CP
where n
stages, V
output, V
is the number of negative charge-pump
is the gate-off linear-regulator REG N
NEG
GOFF
is the peak-to-peak value of the
is the main step-up regulator output, V
MAIN
D
is the forward-voltage drop of the charge-pump diode,
and V is the dropout margin for the linear reg-
Charge-Pump Rectifier Diodes
DROPOUT
ulator. Use V
Use low-cost silicon switching diodes with a current rat-
ing equal to or greater than two times the average
charge-pump input current. If it helps avoid an extra
stage, some or all of the diodes can be replaced with
Schottky diodes with an equivalent current rating.
= ꢀ.ꢁV.
DROPOUT
The above equations are derived based on the
assumption that the first stage of the positive charge
pump is connected to V
and the first stage of the
MAIN
negative charge pump is connected to ground.
Sometimes fractional stages are more desirable for bet-
ter efficiency. This can be done by connecting the first
Linear-Regulator Controllers
Output-Voltage Selection
Adjust the gate-on linear-regulator (REG P) output volt-
age by connecting a resistive voltage-divider from the
REG P output to AGND with the center tap connected
to FBP (Figure 1). Select the lower resistor of the divider
R5 in the range of 1ꢀkΩ to ꢁꢀkΩ. Calculate the upper
resistor R4 with the following equation:
stage to V or another available supply. If the first
IN
charge-pump stage is powered from V , then the
IN
above equations become:
V
+ V
+ V
GON
DROPOUT IN
n
=
=
POS
V
−2× V
D
MAIN
−V
+ V
+ V
GOFF
DROPOUT IN
n
NEG
V
V
GON
V
−2× V
D
MAIN
R4 =R5×
−1
FBP
Flying Capacitors
Increasing the flying-capacitor (C ) value lowers the
where V
= 1.25V (typ).
FBP
X
effective source impedance and increases the output-
current capability. Increasing the capacitance indefi-
______________________________________________________________________________________ 21
TFT-LCD DC-DC Converters with
Operational Amplifiers
POSITIVE CHARGE-PUMP
NEGATIVE CHARGE-PUMP
OUTPUT VOLTAGE vs. V
OUTPUT VOLTAGE vs. V
MAIN
MAIN
60
50
40
30
20
10
0
-0
-5
1-STAGE
CHARGE PUMP
3-STAGE CHARGE PUMP
V
= 0.3V TO 1V
D
-10
-15
-20
-25
-30
-35
-40
-45
2-STAGE CHARGE PUMP
2-STAGE
CHARGE PUMP
3-STAGE
CHARGE PUMP
1-STAGE CHARGE PUMP
V
= 0.3V TO 1V
D
2
4
6
8
10
12
14
2
4
6
8
10
12
14
V
(V)
V
(V)
MAIN
MAIN
Figure 10. Negative Charge-Pump Output Voltage vs. V
Figure 9. Positive Charge-Pump Output Voltage vs. V
MAIN
MAIN
Adjust the gate-off linear-regulator REG N output volt-
age by connecting a resistive voltage-divider from
GOFF
(Figure 1). Select R8 in the range of 2ꢀkΩ to 5ꢀkΩ.
Calculate R7 with the following equation:
Therefore, transistors with current gain over 1ꢀꢀ at the
maximum output current can be difficult to stabilize and
are not recommended unless the high gain is needed to
meet the load-current requirements.
V
to REF with the center tap connected to FBN
The transistor’s saturation voltage at the maximum out-
put current determines the minimum input-to-output
voltage differential that the linear regulator can support.
Also, the package’s power dissipation limits the usable
maximum input-to-output voltage differential. The maxi-
mum power-dissipation capability of the transistor’s
package and mounting must exceed the actual power
dissipated in the device. The power dissipated equals
V
V
− V
GOFF
FBN
R7 =R8×
− V
REF
FBN
where V
= 25ꢀmV, V
= 1.25V. Note that REF can
FBN
REF
only source up to 5ꢀµA; using a resistor less than 2ꢀkΩ
for R8 results in higher bias current than REF can supply.
the maximum load current (I
) multiplied
LOAD(MAX)_LR
by the maximum input-to-output voltage differential:
Pass-Transistor Selection
The pass transistor must meet specifications for current
gain (h ), input capacitance, collector-emitter saturation
FE
voltage and power dissipation. The transistor’s current
gain limits the guaranteed maximum output current to:
P =I ×(V − V
)
OUT_LR
LOAD(MAX)_LR
IN(MAX)_LR
where V
linear regulator, and V
the linear regulator.
is the maximum input voltage of the
IN(MAX)_LR
_
is the output voltage of
OUT LR
V
BE
I
= I
−
×h
FE(MIN)
LOAD(MAX)
DRV
R
BE
Stability Requirements
The MAX1516/MAX1517/MAX1518 linear-regulator con-
trollers use an internal transconductance amplifier to
drive an external pass transistor. The transconductance
amplifier, the pass transistor, the base-emitter resistor,
and the output capacitor determine the loop stability.
The following applies to both linear-regulator controllers
in the MAX1516/MAX1517/MAX1518.
where I
is the minimum guaranteed base-drive cur-
DRV
rent, V is the transistor’s base-to-emitter forward volt-
BE
age drop, and R
is the pullup resistor connected
BE
between the transistor’s base and emitter. Furthermore,
the transistor’s current gain increases the linear regula-
tor’s DC loop gain (see the Stability Requirements sec-
tion), so excessive gain destabilizes the output.
22 ______________________________________________________________________________________
TFT-LCD DC-DC Converters with
Operational Amplifiers
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base cur-
rent. The total DC loop gain is approximately:
g
is the transconductance of the pass transistor,
m
and f is the transition frequency. Both parameters
T
can be found in the transistor’s data sheet. Because
R
is much greater than R , the above equation
IN
BE
can be simplified:
1ꢀ
V
T
I
×h
BIAS FE
A
≅
× 1+
× V
REF
V_LR
I
LOAD_LR
1
f
=
POLE_IN
2π ×C ×R
IN
IN
where V is 26mV at room temperature, and I
is the
T
BIAS
BE
current through the base-to-emitter resistor (R ). For
Substituting for C and R yields:
IN
IN
the MAX1516/MAX1517/MAX1518, the bias currents for
both the gate-on and gate-off linear-regulator controllers
are ꢀ.1mA. Therefore, the base-to-emitter resistor for
both linear regulators should be chosen to set ꢀ.1mA
bias current:
f
T
f
=
POLE_IN
h
FE
4) Next, calculate the pole set by the linear regula-
tor’s feedback resistance and the capacitance
between FB_ and AGND (including stray capaci-
tance):
V
ꢀ.7V
BE
R
=
=
≈ 6.8kΩ
BE
ꢀ.1mA ꢀ.1mA
The output capacitor and the load resistance create the
dominant pole in the system. However, the internal
amplifier delay, pass transistor’s input capacitance,
and the stray capacitance at the feedback node create
additional poles in the system, and the output capaci-
tor’s ESR generates a zero. For proper operation, use
the following equations to verify the linear regulator is
properly compensated:
1
f
=
POLE_FB
2π ×C ×(R
||R
)
FB
UPPER
LOWER
where C
is the capacitance between FB_ and
FB
AGND, R
is the upper resistor of the linear
UPPER
regulator’s feedback divider, and R
lower resistor of the divider.
is the
LOWER
1) First, determine the dominant pole set by the linear
regulator’s output capacitor and the load resistor:
5) Next, calculate the zero caused by the output
capacitor’s ESR:
I
LOAD(MAX)_LR
f
=
POLE_LR
1
2π ×C
× V
OUT_LR
OUT_LR
f
=
POLE_ESR
2π ×C
×R
ESR
OUT_LR
The unity-gain crossover of the linear regulator is:
= A
where R
OUT_LR
is the equivalent series resistance of
ESR
.
f
♦ f
V_LR POLE_LR
CROSSOVER
C
2) The pole created by the internal amplifier delay is
approximately 1MHz:
To ensure stability, choose C
large enough so
OUT_LR
the crossover occurs well before the poles and zero
calculated in steps 2 to 5. The poles in steps ꢁ and 4
generally occur at several megahertz, and using
ceramic capacitors ensures the ESR zero occurs at
several megahertz as well. Placing the crossover below
5ꢀꢀkHz is sufficient to avoid the amplifier-delay pole
and generally works well, unless unusual component
choices or extra capacitances move one of the other
poles or the zero below 1MHz.
f
= 1MHz
POLE_AMP
ꢁ) Next, calculate the pole set by the transistor’s
input capacitance, the transistor’s input resistance,
and the base-to-emitter pullup resistor:
1
f
=
POLE_IN
2π ×C ×(R ||R )
IN
BE
IN
g
2πf
h
FE
m
where C
=
, R
=
,
IN
IN
g
T
m
______________________________________________________________________________________ 23
TFT-LCD DC-DC Converters with
Operational Amplifiers
to the inductor, to the IC’s LX pin, out of PGND, and
Applications Information
to the input capacitor’s negative terminal. The high-
current output loop is from the positive terminal of
the input capacitor to the inductor, to the output
diode (D1), and to the positive terminal of the output
capacitors, reconnecting between the output capac-
itor and input capacitor ground terminals. Connect
these loop components with short, wide connec-
tions. Avoid using vias in the high-current paths. If
vias are unavoidable, use many vias in parallel to
reduce resistance and inductance.
Power Dissipation
An IC’s maximum power dissipation depends on the
thermal resistance from the die to the ambient environ-
ment and the ambient temperature. The thermal resis-
tance depends on the IC package, PC board copper
area, other thermal mass, and airflow.
The MAX1516/MAX1517/MAX1518, with their exposed
backside pad soldered to 1in2 of PC board copper,
can dissipate about 1.7W into +7ꢀ°C still air. More PC
board copper, cooler ambient air, and more airflow
increase the possible dissipation, while less copper or
warmer air decreases the IC’s dissipation capability.
The major components of power dissipation are the
power dissipated in the step-up regulator and the
power dissipated by the operational amplifiers.
• Create a power-ground island (PGND) consisting of
the input and output capacitor grounds, PGND pin,
and any charge-pump components. Connect all of
these together with short, wide traces or a small
ground plane. Maximizing the width of the power-
ground traces improves efficiency and reduces out-
put voltage ripple and noise spikes. Create an
analog ground plane (AGND) consisting of the
AGND pin, all the feedback-divider ground connec-
tions, the operational-amplifier divider ground con-
nections, the COMP and DEL capacitor ground
connections, and the device’s exposed backside
pad. Connect the AGND and PGND islands by con-
necting the PGND pin directly to the exposed back-
side pad. Make no other connections between these
separate ground planes.
Step-Up Regulator
The largest portions of power dissipation in the step-up
regulator are the internal MOSFET, the inductor, and the
output diode. If the step-up regulator has 9ꢀ% efficiency,
about ꢁ% to 5% of the power is lost in the internal
MOSFET, about ꢁ% to 4% in the inductor, and about 1%
in the output diode. The remaining 1% to ꢁ% is distrib-
uted among the input and output capacitors and the PC
board traces. If the input power is about 5W, the power
lost in the internal MOSFET is about 15ꢀmW to 25ꢀmW.
• Place all feedback voltage-divider resistors as close
to their respective feedback pins as possible. The
divider’s center trace should be kept short. Placing
the resistors far away causes their FB traces to
become antennas that can pick up switching noise.
Take care to avoid running any feedback trace near
LX or the switching nodes in the charge pumps.
Operational Amplifier
The power dissipated in the operational amplifiers
depends on their output current, the output voltage,
and the supply voltage:
PD
PD
=I
×(V
− V
)
SOURCE OUT_(SOURCE)
SUP
OUT_
• Place the IN pin and REF pin bypass capacitors as
close to the device as possible. The ground connec-
tion of the IN bypass capacitor should be connected
directly to the AGND pin with a wide trace.
=I
× V
OUT_
SINK OUT_(SINK)
where I
is the output current sourced by
OUT_(SOURCE)
the operational amplifier, and I
is the output
OUT_(SINK)
current that the operational amplifier sinks.
• Minimize the length and maximize the width of the
traces between the output capacitors and the load
for best transient responses.
In a typical case where the supply voltage is 1ꢁV and
the output voltage is 6V with an output source current
of ꢁꢀmA, the power dissipated is 18ꢀmV.
• Minimize the size of the LX node while keeping it
wide and short. Keep the LX node away from feed-
back nodes (FB, FBP, and FBN) and analog ground.
Use DC traces to shield if necessary.
PC Board Layout and Grounding
Careful PC board layout is important for proper opera-
tion. Use the following guidelines for good PC board
layout:
Refer to the MAX1518 evaluation kit for an example of
proper PC board layout.
• Minimize the area of high-current loops by placing
the inductor, the output diode, and the output
capacitors near the input capacitors and near the
LX and PGND pins. The high-current input loop
goes from the positive terminal of the input capacitor
Chip Information
TRANSISTOR COUNT: 46ꢀ8
PROCESS: BiCMOS
24 ______________________________________________________________________________________
TFT-LCD DC-DC Converters with
Operational Amplifiers
Pin Configurations
TOP VIEW
32 31 30 29 28 27 26 25
SRC
REF
1
2
3
4
5
6
7
8
24 COMP
23 FB
AGND
PGND
OUT1
NEG1
POS1
N.C.
22 IN
21 LX
MAX1516
20 N.C.
19 N.C.
18 I.C.
17 N.C.
9
10 11 12 13 14 15 16
THIN QFN
5mm x 5mm
N.C. = NOT INTERNALLY CONNECTED
I.C. = INTERNALLY CONNECTED
TOP VIEW
TOP VIEW
32 31 30 29 28 27 26 25
32 31 30 29 28 27 26 25
SRC
REF
1
2
3
4
5
6
7
8
24 COMP
23 FB
SRC
REF
1
2
3
4
5
6
7
8
24 COMP
23 FB
AGND
PGND
OUT1
NEG1
POS1
OUT2
22 IN
AGND
PGND
OUT1
NEG1
POS1
OUT2
22 IN
21 LX
21 LX
MAX1517
MAX1518
20 N.C.
19 N.C.
18 I.C.
17 OUT3
20 OUT5
19 NEG5
18 POS5
17 OUT4
9
10 11 12 13 14 15 16
9
10 11 12 13 14 15 16
THIN QFN
5mm x 5mm
THIN QFN
5mm x 5mm
N.C. = NOT INTERNALLY CONNECTED
I.C. = INTERNALLY CONNECTED
______________________________________________________________________________________ 25
TFT-LCD DC-DC Converters with
Operational Amplifiers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
0.15
C A
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
PIN # 1
I.D.
0.15
C
B
PIN # 1 I.D.
0.35x45∞
E/2
E2/2
C
(NE-1) X
e
L
E2
E
k
L
DETAIL A
e
(ND-1) X
e
DETAIL B
e
L
C
L
C
L
L1
L
L
e
e
0.10
C
A
0.08
C
C
A1 A3
PACKAGE OUTLINE
16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm
1
E
21-0140
2
COMMON DIMENSIONS
20L 5x5 28L 5x5
EXPOSED PAD VARIATIONS
DOWN
BONDS
ALLOWED
PKG.
D2
E2
16L 5x5
32L 5x5
40L 5x5
PKG.
CODES
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
MIN. NOM. MAX. MIN. NOM. MAX.
T1655-1 3.00 3.10 3.20 3.00 3.10 3.20
NO
A
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80
T1655-2 3.00 3.10 3.20 3.00 3.10 3.20 YES
NO
T2055-3 3.00 3.10 3.20 3.00 3.10 3.20 YES
A1
-
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.05
0.20 REF.
T2055-2 3.00 3.10 3.20 3.00 3.10 3.20
A3
b
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
NO
T2055-4 3.00 3.10 3.20 3.00 3.10 3.20
D
E
T2855-1 3.15 3.25 3.35 3.15 3.25 3.35
T2855-2 2.60 2.70 2.80 2.60 2.70 2.80
NO
NO
e
0.80 BSC.
0.25
0.65 BSC.
0.25
0.50 BSC.
0.25
0.50 BSC.
0.25
0.40 BSC.
T2855-3 3.15 3.25 3.35 3.15 3.25 3.35 YES
k
-
-
-
-
-
-
-
-
0.25 0.35 0.45
YES
NO
T2855-4 2.60 2.70 2.80 2.60 2.70 2.80
T2855-5 2.60 2.70 2.80 2.60 2.70 2.80
T2855-6 3.15 3.25 3.35 3.15 3.25 3.35
L
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60
L1
-
-
-
-
-
-
-
-
-
-
-
-
0.30 0.40 0.50
NO
N
ND
16
4
4
20
5
5
28
7
7
32
8
8
40
10
10
2.80
3.20
T2855-7 2.60 2.70
T3255-2
T3255-3 3.00 3.10
2.60 2.70 2.80 YES
NO
3.00 3.10 3.20 YES
NO
3.00 3.10
3.00 3.10 3.20
NE
3.20
WHHB
WHHC
WHHD-1
WHHD-2
-
JEDEC
T3255-4 3.00 3.10 3.20 3.00 3.10 3.20
T4055-1 3.20 3.30 3.40 3.20 3.30 3.40 YES
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,
T2855-3 AND T2855-6.
PACKAGE OUTLINE
16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
2
E
21-0140
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2ꢀꢀ4 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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