MAX15158AATJ_技术文档

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

General Description

Beneﬁts and Features

● Wide Operating Range

MAX15158/MAX15158A is a high-voltage multiphase

boost controller designed to support up to two MOSFET

drivers and four external MOSFETs in single-phase

or dual-phase boost/inverting-buck-boost configurations.

Two devices can be stacked up for quad-phase operation.

The output voltage of MAX15158 can be dynamically

set through the 1V to 2.2V reference input (REFIN) for

modular design support. For MAX15158A the REFIN pin

is removed, and the internal 2.0V reference voltage is

selected by default.

• 8V to 76V Input Voltage Range for Booost

Conﬁguration and -8V to -76V Input Voltage Range

for Inverting-Buck-Boost Conﬁguration

• 3.3V to 60V Output Voltage Range on the Top of

Input Voltage

• 120kHz to 1MHz Switching Frequency Range

• -40°C to +125°C Temperature Range

• Single/Dual/Quad-Phase Operation

• Active Phase Current Balance Control

● Integration Reduces Design Footprint

• Internal LDO for Bias Supply Generation

• Multiphase Multiple Controller Synchronization and

Interleave

The switching frequency is controlled either through

an external resistor setting the internal oscillator or by

synchronizing the regulator to an external clock. The

device is designed to support 120kHz to 1MHz switching

frequencies. The controller has a dedicated enable/input

undervoltage-lockout (EN/UVLO) pin to configure for flexible

power sequencing.

• Output Voltage Sense Level Shifter

● Robust Fault Protection Improves Quality and

Reliability

• Adjustable Input Undervoltage Lockout

• Adjustable Cycle-by-Cycle Peak Current Limit

and Fast Overcurrent Protection

• Selectable Feedback Overvoltage Protection

• Thermal Shutdown

MAX15158/MAX15158A has a dedicated RAMP pin to

adjust internal slope compensation. The device features

adjustable overcurrent protection. The device incorporates

current sense amplifiers to accurately measure the current

of each phase across external sense resistors to

implement accurate phase current sharing. The control-

ler is also protected against output overvoltage, input

undervoltage and thermal shutdown.

● Flexible and Simple System Design

• Adjustable Slope Compensation

• Low-Side MOSFET Gate Monitoring for Accurate

Current Sensing

The device is available in 5mm x 5mm, 32-pin TQFN

package and supports -40°C to 125°C junction temperature

range.

• Discontinuous-Conduction-Mode Operation is

Supported when Using a Diode in Place of the

High-Side MOSFET

Applications

● Communication

● Industrial

● Small 5mm x 5mm TQFN package, 0.5mm pitch

Ordering Information appears at end of data sheet.

● Automotive

● Multiphase Boost

19-100365; Rev 2; 11/19

MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Typical Application Circuit

V

= -8V TO -65V

IN-

3.3V TO 60V

OUTPUT

MAX15158 /

MAX15158A

V

IN-

EN/UVLO

DH1

DL1

RAMP

V

IN-

MOSFET

DRIVER

V

IN-

DRV

6V TO 14V BIAS W.R.T. V

IN-

DLFB1

REFIN

(NC)

1V TO 2.2V DAC W.R.T. V

SYSTEM CLK

IN-

POWER STAGE

CURRENT SENSE

FREQ/CLK

CSP1

CSN1

COMP

V

IN-

V

IN-

V

IN-

V

IN-

V

IN-

OPEN-DRAIN POWER GOOD

PGOOD

DH2

DL2

MOSFET

DRIVER

SYNC

CSIO_

MULTIPHASE SUPPORT / SYNCHRONIZATION

DLFB2

SS

POWER STAGE

CURRENT SENSE

V

IN-

CSP2

CSN2

BIAS

V

IN-

ILIM

OVP

OUTN

OUTP

FB

GND

V

IN-

V

IN-

Maxim Integrated

│ 2

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Absolute Maximum Ratings

OUTP, OUTN to GND............................................-0.3V to +80V

CSP_, CSN_ to GND ...........................................-0.3V to +0.3V

CSP_ to CSN_ .....................................................-0.3V to +0.3V

CSION, CSIOP to GND..........................-0.3V to (V

Maximum Current out of BIAS .........................................100mA

Operating Temperature Range......................... -40°C to +125°C

+ 0.3V)

BIAS

DH_, DL_ to GND ................................ -0.3V to (V

DLFB_ to GND........................................ -0.3V to (V

+ 0.3V)

Continuous Power Dissipation (T = +70°C)

BIAS

A

TQFN (derate 34.5mW/°C above +70°C)......................2.76W

Junction Temperature......................................................+150°C

Storage Temperature Range............................ -40°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow).......................................+240°C

DRV

DRV to GND..........................................................-0.3V to +16V

BIAS to GND...........................................................-0.3V to +6V

DRV to BIAS..........................................................-0.3V to +16V

FB, PGOOD, REFIN to GND ..................................-0.3V to +6V

EN/UVLO, FREQ/CLK to GND ...............................-0.3V to +6V

COMP, SS, ILIM, OVP, RAMP,

SYNC to GND.....................................-0.3V to (V

+ 0.3V)

BIAS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Package Information

PACKAGE TYPE: 32-PIN TQFN

Package Code

T3255+6

21-0140

90-0603

Outline Number

Land Pattern Number

THERMAL RESISTANCE, FOUR-LAYER BOARD

Junction to Ambient (θ

)

29°C/W

1.7°C/W

JA

Junction to Case (θ

)

JC

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,

“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing

pertains to the package regardless of RoHS status.

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.

For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Maxim Integrated

│ 3

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Electrical Characteristics

(V

= 9V, V

= 1.2V, REFIN = BIAS (MAX15158), C

= 2.2μF, C = 10nF, R

= 100kΩ (600kHz), T = T = -40°C to +125°C,

DRV

EN/UVLO

BIAS

SS

FREQ

A

J

unless otherwise noted.) (Note 1)

PARAMETER

INPUT SUPPLIES

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DRV Operating Range

V

8.5

14

V

mA

μA

V

DRV

Device Switching, 2 phases, 10pF load

DH_ and DL_

DRV Quiescent Current

DRV Shutdown Current

I

10.0

15.4

DRV

EN = GND

10

19

V

rising

falling

8.00

7.90

8.27

8.16

8.41

8.31

DRV Undervoltage-Lockout

Threshold

DRV

V

DRV(UVLO)

DRV

BIAS LINEAR REGULATOR

BIAS LDO Output

Voltage

V

I

= 5mA

4.66

4.75

4.81

V

mA

V

BIAS

BIAS LDO Current Limit

30

56

90

V

rising

4.10

4.00

4.24

4.19

4.40

4.32

BIAS Undervoltage-Lockout

Threshold

BIAS

V

BIAS(UVLO)

falling

BIAS

CONTROLLER ENABLE

V

rising

falling

0.98

0.88

1.00

0.90

1.03

0.93

EN/UVLO Adjustable Undervolt-

age-Lockout Threshold

UVLO

V

UVLO

EN/UVLO Input

Leakage Current

I

V

= 0V to V

-1

+1

μA

UVLO

BIAS

FEEDBACK VOLTAGE LEVEL SHIFTER (OUTP, OUTN)

OUTP Current Range

OUTN Bias Current

I

OUTP = OUTN > 8V

OUTN = OUTP = BIAS

0.05

3.000

375

10

mA

μA

OUTP

I

220

4

OUTN

OUTP Leakage Current

OUTN Leakage Current

3

10

Minimum OUTN voltage for HV FB

operations

7.0

6.8

8

7.2

7.0

7.4

7.2

76

OUTN Undervoltage-Lockout

Threshold

OUTN

UVLO

V

OUTN UVLO hysteresis

HV FB Voltage-Buffer Operat-

ing Range

V

OUTP,

V

OUTN

CONTROL LOOP

FB Regulation Threshold (Pre-

set Mode)

V

REFIN = BIAS (MAX15158)

1.97

2.00

2.02

FB

FB-to-REFIN Offset Voltage (Track-

ing Mode)

V

– V

, V = 1V to 2V

REFIN

-9

1

+9

mV

V

FB

REFIN

REFIN Input Voltage Range

V

(Note 2)

2.2

REFIN

Maxim Integrated

│ 4

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Electrical Characteristics (continued)

(V

= 9V, V

= 1.2V, REFIN = BIAS (MAX15158), C

= 2.2μF, C = 10nF, R

= 100kΩ (600kHz), T = T = -40°C to +125°C,

DRV

EN/UVLO

BIAS

SS

FREQ

A

J

unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

100mV hysteresis (typ)

V = 0V to 2V;

FB

MIN

TYP

MAX

UNITS

Preset Mode REFIN Threshold

Rising

2.30

2.36

V

FB Input Leakage

Current

I

-1

+1

μA

FB

OUTP = OUTN = BIAS

REFIN Input Leakage Current

I

V

= 0.4V to 2.2V

REFIN

CSP_

CSP_-to-CSN_ Differential Volt-

age Range

D

V

- V

-200

+200

mV

VCS_

CSN_

Current-Sense

Common-Mode Voltage Range

V

,

CSP_

With respect to GND (Note 3)

-300

-1

+300

+1

mV

V/V

μA

V

CSN_

CSP_, CSN_ Current-Sense

Ampliﬁer Gain

A

8.3

1.1

CS_

CSP_ , CSN_ Input Leakage

Current

I

V

, V

= ±200 mV with respect

CSP__,

CSP_ CSN_

I

to AGND

CSN_

Error-Ampliﬁer Transconduc-

tance

G

mS

mV

MEA

Ramp Pin Amplitude Adjustable

Range

V

120

375

RAMP

Internal Slope Compensation

V

= 0.3V

= 0V

1.9

V/V

RAMP

Ramp Voltage to V

Ratio

RAMP

RAMP Bias Current

I

9.4

10.0

10.6

305

μA

RAMP

SWITCHING FREQUENCY

Preset PWM Switching

Frequency

f

R

= OPEN

293

300

kHz

SW

FREQ/CLK

R

= 20kΩ

105

135

550

115

150

600

125

165

650

FREQ

Adjustable PWM

Switching Frequency

= 25kΩ

= 100kΩ (R

< 120 kΩ)

FREQ

PWM Switching

frequency range

FREQ/CLK externally applied

120

1000

kHz

FREQ/CLK Frequency Detec-

tion Range

f

0.48

4.00

1.85

MHz

CLK

Logic-high (rising)

Logic-low (falling)

1.80

1.6

FREQ/CLK Logic Level

V

CLK

1.5

FREQ/CLK Input Bias Current

I

V

= GND

-10.7

-10.0

-9.3

μA

CLK

FREQ/CLK

FREQ/CLK to PWM Switching

Frequency Ratio

f

/ f

1/2/4 Phases Operation

4

kHz/kHz

CLK SW

Maxim Integrated

│ 5

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Electrical Characteristics (continued)

(V

= 9V, V

= 1.2V, REFIN = BIAS (MAX15158), C

= 2.2μF, C = 10nF, R

= 100kΩ (600kHz), T = T = -40°C to +125°C,

DRV

EN/UVLO

BIAS

SS

FREQ

A

J

unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

QUAD-PHASE CLOCK SYNC

Logic high (rising)

Logic low (falling)

= 0V to 4.6V, internal 5MΩ

1.58

1.17

1.95

SYNC Logic Threshold

V

SYNC

0.90

-2

V

SYNC

SYNC Input Leakage Current

SYNC Frequency Range

I

f

+2

μA

SYNC

pulldown

200

2000

kHz

Logic-high, I

= 10mA

V

- 0.4

SOURCE

BIAS

SYNC Output Voltage Level

V

SYNC

Logic-low, I

= 10mA

0.4

SINK

OUTPUT FAULT PROTECTION

CSP_ to CSN_ Minimum

Threshold for Cycle-by-Cycle

Positive Peak Current Limit

V

= 0V

17

94

20

23

mV

ILIM

CSP_ to CSN_ Maximum

Threshold for Cycle-by-Cycle

Positive Peak Current Limit

> 1.25V

100

106

ILIM

CSP_ to CSN_ Minimum

Threshold for Cycle-by-Cycle

Negative Overcurrent

Protection

V

-80

mV

ILIM

CSP_ to CSN_ Maximum

Threshold for Cycle-by-Cycle

Negative Overcurrent

Protection

= 0V

-16

26

ILIM

CSP_ to CSN_ Minimum

Threshold for Fast Positive

Overcurrent Protection

V

= 0V

21

31

mV

ILIM

CSP_ to CSN_ Maximum

Threshold for Fast Positive

Overcurrent Protection

> 1.25V

121

133

145

ILIM

ILIM Source Current

9.4

-15

10.0

10.6

+ 15

µA

%

CSP_-to-CSN_ Cycle-by-Cycle

Positive Peak Current Limit

Threshold Accuracy

0.25V < V

< 0.95V

ILIM

V

= 500mV

-6

+6

%

ILIM

CSP_-to-CSN_ Negative

Overcurrent Protection

Threshold Accuracy

V

= 500mV

-20

+20

%

Maxim Integrated

│ 6

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Electrical Characteristics (continued)

(V

= 9V, V

= 1.2V, REFIN = BIAS (MAX15158), C

= 2.2μF, C = 10nF, R

= 100kΩ (600kHz), T = T = -40°C to +125°C,

DRV

EN/UVLO

BIAS

SS

FREQ

A

J

unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

= 500mV

MIN

TYP

MAX

UNITS

V

to |CSP_ - CSN_|

Cycle-by-Cycle Positive Peak

ILIM

V

10

V/V

ILIM

Current Limit Threshold Ratio

Minimum REFIN and SS

Voltage for Valid FB OV Fault

SS > 1V

Measured with respect to target voltage

1.00

8.5

1.02

10.0

1.04

12.0

V

FB Overvoltage Default

Threshold (Preset Mode)

FB OV

(REFIN = BIAS for MAX15158), V

falling, 3% hysteresis

%

FB

Measured with respect to target voltage

(V = 1V for MAX15158), V falling,

FB Overvoltage Threshold

(Tracking Mode)

8.5

9.4

10

11

%

REFIN

FB

3% hysteresis

OVP Selector Output Source

Current

Resistor connected to GND

10.0

12

10.6

µA

EN/UVLO falling to SS falling

μs

Cumulative cycle-by-cycle peak current

limit or negative overcurrent protection

events for hiccup

Fault Propagation

Delay

32

Events

PWM CLK

Cycles

FB OV

128

PWM CLK

Cycles

Hiccup Timeout Duration

PGOOD Threshold

32,768

1.88

PGOOD rising (REFIN = BIAS for

MAX15158)

1.83

1.77

1.93

1.87

V

PGOOD falling (REFIN = BIAS for

MAX15158)

1.82

PGOOD Falling and Rising

Delay

PWM CLK

Cycles

64

20

PGOOD Output Low Voltage

PGOOD Leakage Current

Thermal Shutdown

V

I

= 3mA

SINK

40

1

mV

μA

°C

PGOOD

I

FB = REFIN for MAX15158, V

= 5V

PGOOD

T

15°C hysteresis

165

SHDN

Maxim Integrated

│ 7

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Electrical Characteristics (continued)

(V

= 9V, V

= 1.2V, REFIN = BIAS (MAX15158), C

= 2.2μF, C = 10nF, R

= 100kΩ (600kHz), T = T = -40°C to +125°C,

DRV

EN/UVLO

BIAS

SS

FREQ

A

J

unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SOFT-START (SS)

SS Ampliﬁer

Transconductance

G

0.2

mS

μA

Ω

M(SS)

Source

Sink

4.75

-5.8

5.00

-5.0

5.25

-4.2

SS Current Capability

I

SS

SS Pulldown

Resistance

R

Discharge

SS rising

4.3

SS

55

45

SS Undervoltage-

Lockout Threshold

V

mV

UVLO(SS)

SS falling (drivers disabled)

PWM Output

Logic-high, I

= 10mA

V

- 0.5

SOURCE

BIAS

DH_, DL_ Output

Voltage Level

V

, V

V

DH_ DL_

Logic-low, I

= 10mA

0.2

SINK

DLFB_ Leakage Current

DLFB_ Logic Threshold

I

V

= 9V

-1

+1

μA

LK

DLFB_

Logic high (rising)

Logic low (falling)

0.75

0.45

0.80

0.50

0.85

0.55

V

DLFB

CURRENT SHARING (MULTIPHASE APPLICATIONS ONLY)

CSIO_ Output Common-Mode

Voltage

V

With respect to AGND

1.24

4.2

V

CSION

CSIO_ Differential Input

Resistance

R

kΩ

CSIO_

Note 1: Limits are 100% tested at T = +25°C. Limits over the operating temperature range and relevant supply-voltage range are

A

guaranteed by design and characterization.

Note 2: For MAX15158, operating REFIN below 1V is not recommended due to disabled FB overvoltage-fault protection.

Note 3: Guaranteed by design, not production tested.

Maxim Integrated

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Typical Operating Characteristics

(T = -40°C to +125°C, V = -48V, unless otherwise noted. See the Standard Application Circuits.)

A

IN-

EFFICIENCY vs. LOAD CURRENT

LOAD REGULATION

LINE REGULATION

toc01

toc02

toc03

98

12.060

12.055

12.050

12.045

12.040

12.035

12.030

12.040

12.038

12.036

12.034

12.032

12.030

96

94

92

90

88

86

84

82

Vout=5V

V_OUT= 5V

Vout=9V

V_OUT= 9V

Vout=12V

V_OUT= 12V

VoVut=14=.51V4.5V

OUT

V_OUT= 12V

I_LOAD= 1A

VoVut=35=V35V

OUT

V_OUT= 12V

20

VoVut=55=V55V

OUT

0

5

10

15

20

25

0

5

10

15

25

-60 -55 -50 -45 -40 -35 -30 -25

INPUT VOLTAGE (V)

LOAD CURRENT (A)

STARTUP WAVEFORM WITH

PREBIASED OUTPUT VOLTAGE

STARTUP WAVEFORM

EN/UVLO RISING

STARTUP WAVEFORM

LX_ SWITCHING

toc06

toc04

toc05

5V/div

1V/div

V_EN/UVLO

V_PGOOD

5V/div

V_OUT

1V/div

V_OUT

V_SS

V_LX1

V_LX2

V_SS

1V/div

V_OUT

V_SS

50V/div

V_LX1

V_LX2

5ms/div

DYNAMIC REFIN RAMP RESPONSE

17.5V TO 35V OUTPUT

SHUT-DOWN WAVEFORM

EN/UVLO FALLING

SHUT-DOWN WAVEFORM

LX_ SWITCHING

toc09

toc07

toc08

V_OUT

V_EN/UVLO

10V/div

5V/div

V_OUT

V_PGOOD

V_OUT

V_REFIN

1V/div

V_SS

5V/div

1V/div

V_SS

5V/div

1V/div

50V/div

V_LX1

V_PGOOD

5V/div

V_LX2

5ms/div

10ms/div

Maxim Integrated

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Typical Operating Characteristics (continued)

(T = -40°C to +125°C, V = -48V, unless otherwise noted. See the Standard Application Circuits.)

A

IN-

DYNAMIC REFIN STEP RESPONSE

17.5V TO 35V OUTPUT

LOAD TRANSIENT WAVEFORM

35V OUTPUT WITH 10A LOAD STEP

CLOCK SYNCHRONIZATION

toc12

toc10

toc11

V_OUT

V_REFIN

V_SS

V_CLK

10V/div

1V/div

2V/div

V_OUT

500mV/div

10A/div

V_LX1

50V/div

I_LOAD

V_PGOOD

5V/div

V_LX2

10ms/div

2ms/div

2µs/div

BODE PLOT

12V OUTPUT WITH 25A LOAD

BODE PLOT

12V OUTPUT WITH 0A LOAD

toc14

toc13

100

200

160

120

80

100

80

200

80

60

160

120

80

60

40

20

40

20

40

0

-20

-40

-60

-80

-40

-80

-120

-160

-200

-20

-40

-60

-80

-100

-40

-80

-120

-160

-200

-100

1

10

100

1

10

100

FREQUENCY (kHz)

AUTO-RETRY AFTER

OVERCURRENT FAULT

OUTPUT OVERCURRENT WAVEFORM

toc16

toc15

5V/div

V_OUT

5V/div

I_LOAD

50A/div

2V/div

50A/div

V_SS

V_PGOOD

5V/div

V_PGOOD

50V/div

V_LX

200µs/div

50ms/div

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Pin Conﬁguration

24 23 22 21 20 19 18 17

NC

REFIN

FB

COMP

SS

OVP

ILIM

RAMP

NC

FB

COMP

SS

OVP

ILIM

RAMP

DLFB1

DL1

DH1

CSP1

CSN1

CSN2

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

DLFB1

DL1

DH1

CSP1

CSN1

CSN2

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

TOP VIEW

5mm x 5mm

TQFN

TOP VIEW

5mm x 5mm

TQFN

EP

CSP2

DLFB2

CSP2

DLFB2

1

2

3

4

5

6

7

8

1 2 3 4 5 6 7 8

+

MAX15158

MAX15158A

T3255-6

Pin Description

NAME

FUNCTION

Logic Output for Low-Side MOSFET Gate Driver for the Second Phase. Connect DL2 to the second phase

external MOSFET driver low-side input pin.

1

DL2

Logic Output for High-Side MOSFET Gate Driver for the Second Phase. Connect DH2 to the second phase

external MOSFET driver high-side input pin.

2

3

DH2

Multiphase Synchronization Pin. For single IC operation, leave this pin unconnected. Tie this pin together

when two MAX15158/MAX15158A ICs are stacked-up in master/slave operation mode.

SYNC

Frequency Selection/Clock Synchronization Input. MAX15158/MAX15158A supports switching frequencies

from 120kHz to 1MHz. Set the switching frequency by either selecting the appropriate external resistor to use

the internal oscillator frequency, or by synchronizing the regulator to an external system clock (see Table 2).

Leave the FREQ/CLK pin unconnected to select the preset 300kHz switching frequency or place a resistor

FREQ/

CLK

4

between FREQ/CLK and GND to set the following: f

= (R

/100k) x 600kHz

SW

FREQ

5

6

GND

Analog Ground.

Negative Input of Master/Slave Current-Sense Signal. MAX15158/MAX15158A uses a differential current-

sense signal to ensure proper startup and current-balance behavior in applications where two MAX15158/

MAX15158A ICs are stacked up in master/slave operation mode.

CSION

Positive Input of Master/Slave Current-Sense Signal. MAX15158/MAX15158A uses a differential current-

sense signal to ensure proper startup and current-balance behavior in applications where two MAX15158/

MAX15158A ICs are stacked up in master/slave operation mode.

7

8

CSIOP

Open-Drain Power Good Output. MAX15158/MAX15158A pulls PGOOD low when the output voltage

exceeds the OVP threshold, or drops below the output UVP threshold, during soft-start and shutdown

(EN/UVLO pulled low). The PGOOD output goes high-impedance when the controller completes soft-start

and remains in regulation.

PGOOD

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Pin Description (continued)

NAME

FUNCTION

Slope Compensation Input. A resistor connected from RAMP to GND programs the amount of slope

compensation. See the Adjustable Slope Compensation (RAMP) section.

9

RAMP

CSP_-CSN_ Cycle-by-Cycle/Hiccup Current Limit Threshold Selector. Connect a resistor from ILIM to GND

to select the protection value.

10

11

12

ILIM

OVP

SS

Program Pin. Connect a resistor from OVP to GND to conﬁgure FB overvoltage protection, single-phase or

dual-phase selection and FB level shifter selection (see Table 1).

Soft-Start Control. The capacitance (C ) between SS to GND sets the startup period. An internal

SS

pulldown MOSFET holds SS low until the controller begins the startup sequence.

Compensation Ampliﬁer Output. COMP is the output of the internal transconductance error ampliﬁer.

Connect a type II compensation network as shown in the Typical Application Circuit (See the Compensation

Design Guidelines section).

13

COMP

Feedback Input. When the FB level shifter is enabled, connect a resistor from FB to GND; when the FB

level shifter is disabled, connect FB to the center of a resistive divider between the output and GND. For

MAX15158A, FB regulates to the preset 2.0V reference voltage. For MAX15158, FB tracks the REFIN

voltage (REFIN between 0.4V and 2.2V) or regulates to the preset 2.0V reference voltage by connecting

REFIN to BIAS. Operation between 0.4V < REFIN < 1V is possible but the FB OVP is disabled. When two

MAX15158/MAX15158A ICs are stacked-up in master/slave operation mode, connect FB of the slave to

BIAS.

14

FB

External Reference Input of MAX15158. REFIN sets the feedback regulation voltage when supplied with a volt-

age between 0.4V and 2.2V. Connect REFIN pin to BIAS to select internal 2.0V reference voltage. Operation

between 0.4V < REFIN < 1V is possible but the FB OV and UV fault functions are disabled.

REFIN

15

Not Connected. For MAX15158A, this pin is NC (Not Connected), where the controller selects internal 2.0V

reference voltage.

NC

16,

19–20

Not Connected

Positive Differential Output Voltage Sense Input. MAX15158/MAX15158A can operate in inverting

buck-boost mode and sense output voltage differentially using its internal FB level shifter. Connect a sense

resistor between OUTP and positive node of output as shown in the Typical Application Circuit. OUTP must

be shorted to OUTN and BIAS if the internal FB level shifter is disabled.

17

OUTP

Negative Differential Output Voltage Sense Input. MAX15158/MAX15158A can operate in inverting

buck-boost mode and sense output voltage differentially using its internal FB level shifter. Connect OUTN to

the negative node of output as shown in the Typical Application Circuit. Connect OUTN to OUTP and BIAS if

the internal FB level shifter is disabled.

18

21

OUTN

BIAS

4.75V Linear Regulator Output and Controller Bias Supply. Bypass to GND with a 2.2µF or greater ceramic

capacitor.

Enable Control / Adjustable Undervoltage Lockout Input for Startup/Shutdown Power Sequencing. This

pin has two voltage thresholds with hysteresis. The lower threshold (0.7V rising / 0.55V falling) determines

whether the BIAS regulator is enabled/disabled. The higher threshold (1V rising / 0.9V falling) initiates soft-

start / soft-shutdown and enables switching. Connect EN/UVLO to the center of a resistor divider between

the input and GND to adjust the undervoltage lockout voltage level as shown in the Typical Application

Circuit.

22

EN/UVLO

23

24

GND

DRV

Analog Ground.

Supply Voltage Input. Provide a 8.5V to 14V supply for internal bias generation.

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Pin Description (continued)

NAME

FUNCTION

External MOSFET Status Feedback Pin for the First Phase. Connect DLFB1 to the center of a resistor di-

vider between the gate of the low-side MOSFET of the ﬁrst phase and GND. See the MOSFET Gate Control

section.

25

DLFB1

Logic Output for Low-Side MOSFET Gate Driver for the First Phase. Connect DL1 to the ﬁrst phase external

MOSFET driver low-side input pin.

26

27

DL1

DH1

Logic Output for High-Side MOSFET Gate Driver for the First Phase. Connect DH1 to the ﬁrst phase

external MOSFET driver high-side input pin.

Positive Low-Side Differential Current-Sense Input for the First Phase. MAX15158/MAX15158A uses the

differential current-sense signal in the current-mode control loop, and multiphase current sharing.

Connect CSP1 to the "MOSFET side" of the current-sense resistor.

28

29

30

31

32

CSP1

CSN1

CSN2

CSP2

DLFB2

Negative Low-Side Differential Current-Sense Input for the First Phase. MAX15158/MAX15158A uses

the differential current-sense signal in the current-mode control loop, and multiphase current sharing.

Connect CSN1 to the "ground side" of the current-sense resistor.

Negative Low-Side Differential Current-Sense Input for the Second Phase. MAX15158/MAX15158A uses

the differential current-sense signal in the current-mode control loop, and multiphase current sharing.

Connect CSN2 to the "ground side" of the current-sense resistor.

Positive Low-Side Differential Current-Sense Input for the Second Phase. MAX15158/MAX15158A uses

the differential current-sense signal in the current-mode control loop, and multiphase current sharing.

Connect CSP2 to the "MOSFET side" of the current-sense resistor.

External MOSFET Status Feedback Pin for the Second Phase. Connect DLFB2 to the center of a resistor

divider between the gate of the low-side MOSFET of the second phase and GND. See the MOSFET Gate

Control section.

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Block Diagram

CSP2

CSN2

IB2

CSIOP

CSION

2R

CURRENT

BALANCE

R

MAX15158

CSP1

CSN1

1.23V

IB1

ILIM2

IB1

ILIM2

ILIM1

DH1

DL1

ILIM

GENERATOR

CSP1

CSN1

CMP1

DLFB1

PWM

CONTROL

LOGIC

DH2

CLOCK

DISTRIBUTION

AND SLOPE

CLK

UP

FREQ/CLK

SYNC

DL2

CLK

REF

COMPENSATION

DLFB2

IB2

RAMP

GENERATOR

CMP2

OUTP

OUTN

CSP2

CSN2

FEEDBACK LEVEL SHIFT

FB

ILIM1

COMP

OVP

FB

1V

PGOOD

COMPARATORS

OVP

THRESHOLD

ILIM1

ILIM2

50mV

REFIN

0.7V

RISING

2.3V

EN/UVLO

STARTUP

AND FAULT

LOGIC

DRV

BIAS

DRV UVLO

SS

2V REF

BIAS UVLO

RESTA RT

2V

40mV

HICCUP

RESET

PGOOD

THERMAL

SHUTDOW N

BIAS SUPPLIES

GND

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Block Diagram (continued)

CSP2

CSN2

IB2

CSIOP

2R

CURRENT

BALANCE

R

MAX15158A

CSION

CSP1

CSN1

1.23V

IB1

ILIM2

IB1

DH1

DL1

ILIM2

ILIM1

ILIM

GENERATOR

CMP1

CSP1

CSN1

DLFB1

PWM

CONTROL

LOGIC

DH2

CLK

UP

CLOCK

DISTRIBUTION

AND SLOPE

FREQ/CLK

SYNC

DL2

CLK

REF

DLFB2

COMPENSATION

IB2

RAMP

GENERATOR

CMP2

OUTP

OUTN

CSP2

CSN2

FEEDBACK LEVEL SHIFT

FB

ILIM1

COMP

OVP

FB

1V

PGOOD

COMPARATORS

OVP

THRESHOLD

ILIM1

ILIM2

0.7V

RISING

EN/UVLO

STARTUP

AND FAULT

LOGIC

DRV

BIAS

DRV UVLO

BIAS UVLO

SS

2V REF

RESTA RT

HICCUP

2V

40mV

PGOOD

THERMAL

SHUTDOW N

BIAS SUPPLIES

GND

RESET

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

FB level shifter to differentially sense the output voltage.

The internal FB level shifter can be enabled or disabled

by connecting a resistor from the OVP pin to GND (See

Overvoltage Protection (OVP) section). When the internal FB

level shifter is enabled, connect OUTN to the ground node

of the output capacitor and OUTP to the output terminal

Detailed Description

MAX15158/MAX15158A is a high-voltage multiphase

boost controller designed to support up to two MOSFET

drivers and four external MOSFETs in single-phase

or dual-phase boost/inverting-buck-boost configurations.

Two devices can be stacked up for quad-phase operation.

When configured as inverting-buck-boost converter, the

controller has an internal high-voltage FB level shifter to

differentially sense the output voltage. The output voltage

of MAX15158 can be dynamically set through the 1V to

2.2V reference input (REFIN) for modular design sup-

port. For MAX15158A the REFIN pin is removed, and the

internal 2.0V reference voltage is selected by default.

using a resistor R

. FB is connected to GND (V

)

IN-

FB1

using a resistor R . The output voltage is set by these

FB2

two resistors:

V

= (R

/R

) x V

OUT

FB1 FB2 REF

For MAX15158, V

can be externally supplied with a

REF

voltage between 1V and 2.2V on the REFIN pin. By con-

necting the REFIN pin to BIAS, the default internal 2.0V

The switching frequency is controlled either through

an external resistor setting the internal oscillator or by

synchronizing the regulator to an external clock. The

device is designed to support 120kHz to 1MHz switch-

ing frequencies. When two devices are stacked up

as master-slave for quad-phase operation, the SYNC

pin of two devices are connected to ensure the clock

synchronization and phase interleaving. The controller

has a dedicated enable/input undervoltage-lockout (EN/

UVLO) pin to configure for flexible power sequencing.

reference voltage is selected. For MAX15158A, V

=

REF

2.0V and cannot be externally controlled. When the FB

level shifter is enabled, the OUTN pin has a UVLO threshold

that controls the power sequencing. If the voltage on

OUTN falls below 7.0V (typ), the controller disables the

drivers (all driver outputs are pulled low) and discharges

the SS capacitor through a 4.3Ω pulldown MOSFET.

V

OUT

MAX15158/MAX15158A has a dedicated RAMP pin to

adjust internal slope compensation. The device features

adjustable overcurrent protection. The device incorpo-

rates current sense amplifiers to accurately measure the

current of each phase across external sense resistors to

implement accurate phase current sharing. The controller

is also protected against output overvoltage, input under-

voltage and thermal shutdown.

R

FB1

MAX15158 /

MAX15158A

OUTP

OUTN

High Voltage Internal FB Level Shifter

FB

MAX15158/MAX15158A can support both boost and

inverting-buck-boost applications. When configured

in inverting-buck-boost operation, the GND pin of the

device must be connected to the negative input voltage

R

FB2

GND

terminal (V ), so that the ground of the IC is different

IN-

V

IN-

than the ground of output capacitor and load. Output

voltage cannot be controlled using a simple resistor

divider. MAX15158/MAX15158A has a dedicated internal

Figure 1. Using Internal FB Level Shifter

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

For inverting-buck-boost applications where V is higher

IN

differential voltage across CSP_ and CSN_ does not

exceed the cycle-by-cycle peak current limit threshold

(see the Overcurrent Protection (OCP) section). The

differential voltage across CSP_ and CSN_ is amplified 8

times by a current sense amplifier. A high-frequency RC

noise filter is suggested across the sense resistor. The RC

time constant should not exceed 30ns.

than 76V, MAX15158/MAX15158A can still be used but

an external level shifter is required. The internal FB level

shifter must be disabled. Pin OUTP and OUTN must be

tied to BIAS. An example of using external FB level shifter

is shown in Figure 2. Two matched PNP transistors are

used. The output voltage is given by:

V

OUT

= (1 + R

/R

) x V

The error between the output voltage feedback (V

)

FB

FB1 FB2

REF

and reference voltage (V ) is fed to the input of

SS

When operating in boost mode, the internal FB level shifter

is disabled. Pin OUTP and OUTN must be tied to BIAS,

and the FB pin must be connected to the center of a resis-

tor divider from output to GND as shown in Figure 3. When

the resistor divider is used, the output voltage is given by:

an error amplifier. The output of the error amplifier

(COMP) is required to connect to a type-II compensation

network for control loop stability (see the Compensation

Design Guidelines section). A slope compensation ramp

generator is also used. The slope of the compensation

ramp can be adjusted by connecting a resistor between

RAMP and GND (see the Adjustable Slope Compensation

(RAMP) section).

V

OUT

= (1 + R

/R

) x V

FB1 FB2 REF

Peak-Current-Mode Control Loop

The controller relies on a fixed-frequency, peak-current-

mode architecture to regulate the output. A detailed

block diagram of the control loop is shown in Figure 4.

A sense resistor is required between the source of the

low-side MOSFET and GND for current sensing. The

sense resistor should be selected so that the maximum

The controller drives on the low-side MOSFET (DL_

driven high) on each rising clock edge. When the PWM

comparator detects that the sum of the current-sense

amplifier output (V

), the slope compensation ramp

CS_

and the phase current imbalance signal exceeds the

COMP voltage, the controller pulls DL_ low and drives

DH_ high.

V

OUT

V

OUT

R

FB1

MAX15158 /

MAX15158A

MAX15158 /

MAX15158A

BIAS

OUTP

OUTN

OUTP

OUTN

DISABLE INTERNAL

FB LEVEL SHIFTER

DISABLE INTERNAL

FB LEVEL SHIFTER

FB

R

FB2

R

FB2

GND

R

FB1

V

IN-

V

IN-

Figure 2. Using External FB Level Shifter

Figure 3. Using External FB Resistor Divider

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

V

OUT

*

HIGH-

V

IN

MAX15158 /

MAX15158A

SIDE

MOSFET

I

RAMP

CLOCK

L

RAMP

DH_

DL_

RAMP

GENERATOR

LOW-

SIDE

MOSFET

PHASE CURRENT

IMBALANCE

R

V

= 1.9 × I

× R

RAMP

SLOPE

RAMP RAMP

PWM

CONTROL

LOGIC

GND

CSP_

CSN_

∑

V

CS_

= 8.3 × (V

- V

)

CSP_

CSN_

R

SENSE

PWM

COMPARATOR

ERROR

AMPLIFIER

FB

SS

GND

C

COMP

R

CCOMP

COMP

GND

TYPE-II COMPENSATION

C

PAR

*FOR BOOST APPLICATIONS V

IS REFERRED TO GND; FOR INVERTING-BUCK-BOOST

OUT

APPLICATIONS V

IS REFERRED TO V

IN

OUT

Figure 4. Peak-Current-Mode Control Loop

For stable operation, it is required that the bandwidth

of control loop (BW) is sufficiently lower than f and

Compensation Design Guidelines

RHP

MAX15158/MAX15158A utilizes a fixed-frequency, peak

current-mode control scheme to provide easy compensation

and fast transient response. It is by nature for boost or

inverting-buck-boost converters to have a right half plane

(RHP) zero in their small signal control-to-output transfer

function. For boost converters, the location of RHP zero

is calculated by:

switching frequency (f ).

SW

BW ≤ Minimum(f

/7, f /10)

SW

RHP

A type-II compensation network is required to be

connected between COMP and GND (R , C

COMP

and C

in Figure 4) to provide sufficient phase margin

PAR

and gain margin to the control loop. The value of the

compensation network can be selected by:

2

f

= V

x (1 - D) / (2 x π x I

x L)

RHP

OUT

OUT(MAX)

where:

R

= 16 x π x BW x R

x C

x V

/

COMP

SENSE

MEA

OUT

]

OUT

[N x (1 - D) x G

x V

REF

I

= Maximum load current per phase

OUT(MAX)

C

= 5/(π x R

x BW)

COMP

D = Duty cycle = 1 - V /V

IN OUT

C

= 1/(2 x π x R

x f

)

PAR

COMP

SW

L = Value of the inductor

where,

For inverting-buck-boost converters, the location of RHP

zero is calculated by:

R

C

= Value of the sense resistor

SENSE

2

f

= V

x (1 - D) / (2 x π x I

x L x D)

= Value of the output capacitor

RHP

OUT

OUT(MAX)

OUT

where:

D = Duty cycle = V

N = Number of phases

= Error Amplifier Transconductance (1.1mS, typ)

/(|V | + V

)

G

OUT

IN

OUT

MEA

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

and discharges the SS capacitor through an internal

4.3Ω discharge MOSFET, placing the regulator into a

high-impedance output state, so the output capacitance

passively discharges through the load current.The BIAS

linear regulator and internal reference power up only

when DRV exceeds its undervoltage-lockout threshold

and EN/UVLO is driven high.

Adjustable Slope Compensation (RAMP)

When MAX15158/MAX15158A operates at a duty cycle

greater than 50%, additional slope compensation is

required to ensure stability and prevent subharmonic

oscillations that occurs naturally in peak-current-mode

controlled converters operating in continuous-conduction-

mode (CCM). MAX15158/MAX15158A provides RAMP

input to select the internal slope compensation ramp

within a range of 230mV ~ 730mV. It is recommended

that discontinuous-conduction-mode (DCM) designs also

use this minimum amount of slope compensation to

provide better noise immunity and jitter-free operation.

EN/UVLO and Soft-Start/Shutdown

The EN/UVLO pin allows the input voltage operating

range to be externally adjusted for power-sequence

control. Connect EN/UVLO to the center of a resistor

divider between the input and GND to adjust the under-

voltage lockout voltage level as shown in the Typical

Application Circuit. In the case where the DRV voltage

threshold of the external MOSFET driver is higher than

the undervoltage lockout threshold of the DRV pin, the

EN/UVLO pin should also be pulled to GND before the

external MOSFET driver is enabled. The EN/UVLO pin

has two levels of thresholds with hysteresis. At power-

up, once the voltage of the EN/UVLO pin is higher than

0.7V (typ) and DRV voltage is higher than its UVLO

threshold, the internal 4.75V BIAS regulator is enabled.

Once the voltage of EN/UVLO is higher than 1V (typ),

and the internal reference stabilizes, the controller starts

the initialization period where the OVP pin configuration

is checked. During this initialization period, the control-

ler pulls SS low through a 4.3Ω discharge MOSFET. As

long as initialization is complete, the controller starts the

soft-start sequence by charging the SS capacitor with a

constant 5μA current source until the SS voltage reaches

either the preset 2.0V target voltage (MAX15158A or

MAX15158 with REFIN connected to BIAS), or the exter-

As shown in Figure 4, by connecting a resistor (R

between RAMP and GND, the amplitude of the slope

compensation ramp is calculated as:

)

RAMP

V

= 1.9 x V

= 1.9 x I

x R

SLOPE

RAMP

RAMP RAMP

where I

is the current sourced from RAMP to GND

RAMP

(10μA typ)

To guarantee stable and jitter-free operation, it is

suggested to select the RAMP resistor that:

R

≥ 5 x (V

- V

)

RAMP

x R

OUT(MAX)

IN(MIN)

/(I

x f

x L)

SENSE RAMP

SW

where:

V

= Maximum output voltage referred to GND

OUT(MAX)

V

= Minimum input voltage referred to GND

= Value of the sense resistor

IN(MIN)

R

f

SENSE

= Switching frequency

SW

L = Value of the inductor

DRV Supply and Bias Regulator (BIAS)

nally driven REFIN voltage (MAX15158, V

= 1V to

REFIN

2.2V). The drivers start switching once SS exceeds 50mV

and the controller detects that FB voltage is below the

SS voltage. The controller enables the overvoltage fault-

protection circuitry when SS exceeds 1V.

The controller requires an external 8.5V to 14V DRV supply.

The DRV supply powers the internal linear regulator that

generates a regulated 4.75V bias supply to power the

internal analog and digital control circuitry as shown in

the Block Diagram. Bypass the BIAS pin with a 2.2μF

or greater ceramic capacitor to maintain noise immunity

and stability. The BIAS regulator provides up to 50mA of

load current and the controller requires up to 5mA, so the

remaining load capability can be used to support pullup

resistors.

At power-down, once the voltage of EN/UVLO is below

0.9V (typ), the controller pulls PGOOD low and initiates the

soft-shutdown sequence by discharging the SS capacitor

with a constant 5μA current load. Since the output voltage

tracks the SS voltage, the regulator actively discharges

the output capacitors. Once the SS and FB voltage

reaches 40mV, the controller stops switching and enters

a low-power shutdown state. The device does not restart

until the soft-shutdown sequence has completed. During

the soft-shutdown cycle, the overvoltage fault protec-

tion remains active until the SS voltage falls below 1V. If

the voltage of EN/UVLO is below 0.55V (typ) after soft-

shutdown is complete, the 4.75V BIAS regulator is then

disabled (see Figure 5).

The controller has an undervoltage-lockout threshold on

DRV. The undervoltage-protection circuits inhibit switching

until DRV rises above 8.196V (typ).

If DRV drops below its undervoltage threshold, the con-

troller determines that there is insufficient supply voltage

to make valid control decisions. To protect the regulator

and the output, the controller immediately pulls PGOOD

low, disables the drivers (all driver outputs pulled low),

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

DRV

1V

0.9V

0.7V

0.55V

EN/UVLO

t

DELAY

BIAS

50mV

SS

40mV

t

INIT

PWM

PGOOD

Figure 5. Soft-Start and Shutdown Sequence with EN/UVLO

The cycle-by-cycle peak current limit threshold is set by a

resistor at ILIM pin. A 10μA source current flows into the

resistor and generates a voltage level. This voltage level

is internally scaled by a factor of 0.10 to set cycle-by-cycle

peak current limit threshold. The minimum and maximum

settable current limit levels are 20mV and 100mV. The

cycle-by-cycle peak current limit level is given by:

Overcurrent Protection (OCP)

A current-sense resistor (R40 and R41 in the Standard

Application Circuits) is connected between the source of

the low-side MOSFET and GND. MAX15158/MAX15158A

detects the current-sense signal (CSP_ to CSN_) and

compares it with the cycle-by-cycle peak current limit

threshold during low-side on-time. When the current

exceeds the cycle-by-cycle peak current limit threshold,

the device turns off the low-side MOSFET and turns on

the high-side MOSFET to allow the inductor current to

be discharged until the end of that switching cycle. Each

phase has an independent up-down counter to accumulate

the number of consecutive peak current limit events. If

the counter exceeds 32, the device disables the drivers

(all driver outputs are pulled low) and discharges the SS

capacitor. After 32,768 clock cycles, the device automatically

attempts to restart using the soft-start sequence.

V

OCP

= 0.10 x 10μA x R

ILIM

The maximum peak inductor current is set by both V

OCP

and the current-sense resistor (R

).

SENSE

I

= V

/R

PEAK(MAX)

OCP SENSE

The device also has a negative overcurrent protection

(NOCP) threshold which is -83% of the cycle-by-cycle

peak current limit threshold. When the low-side MOSFET

is turned on and the inductor current is below the NOCP

threshold, the device will command to keep the low-side

MOSFET on to allow the inductor current to be charged

by the input voltage, until the inductor current is above

the NOCP threshold. Each phase has an independent

up-down counter to accumulate the number of consecutive

NOCP events. If the counter exceeds 32, the device

disables the drivers (all driver outputs are pulled low) and

discharges the SS capacitor. After 32,768 clock cycles,

the device automatically attempts to restart using the

soft-start sequence.

There is a secondary fast positive overcurrent protection

(FPOCP) threshold, which is 33% higher than the cycle-

by-cycle peak current limit threshold. If the inductor peak

current exists the FPOCP threshold for two cycles, the

device disables the drivers (all driver outputs are pulled

low) and discharges the SS capacitor. After 32,768 clock

cycles, the device automatically attempts to restart using

the soft-start sequence.

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Overvoltage Protection (OVP)

Thermal Shutdown (TSHDN)

MAX15158/MAX15158A has an OVP comparator to

monitor the FB voltage. The device can be configured

to disable OVP or select OVP threshold of 110% by

connecting a resistor from the OVP pin to GND. FB OVP

is also disabled when the voltage on the SS pin is below

1V. Once OVP is enabled, the drivers start switching, and

voltage on the SS pin is higher than 1V, the FB overvoltage

comparator trips if the feedback voltage exceeds the SS

voltage by 110% for more than 128 PWM clock cycles. If

the overvoltage comparator is triggered, the controller pulls

PGOOD low, discharges the SS capacitor and disables

the drivers. The controller immediately restarts once the

fault condition has been removed. When OVP is disabled,

the PGOOD will remain high when FB voltage is higher

than the reference voltage.

The controller features a thermal fault-protection circuit.

When the junction temperature rises above +165°C,

the internal thermal sensor triggers the fault protection,

disables the drivers, and discharges the SS capacitor.

The controller remains disabled until the junction

temperature cools by 15°C. Once the device has cooled

down the controller automatically restarts using the

soft-start sequence.

Switching Frequency (FREQ/CLK)

The controller supports 120kHz to 1MHz switching

frequencies. Leave FREQ/CLK unconnected to select

the preset 300kHz switching frequency. To adjust the

switching frequency, either place an external resistor from

FREQ/CLK to AGND, or drive FREQ/CLK with an external

system clock (see Table 2). The resistively programmable

switching frequency is determined by:

The resistor from OVP pin to GND is also used to enable

or disable the FB level shifter and select single or dual

phase operation. Refer to the Table 1.

Table 1. FB OVP Settings, Phase and FB Level Shifter Configuration

OVP PIN VOLTAGE (V)

0.10 ± 0.05

R

FB OVP THRESHOLD

110%

FB LEVEL SHIFTER

DISABLED

ENABLED

PHASE CONFIGURATION

OVP

GND

33kΩ

0.33 ± 0.05

DISABLED

110%

Dual-phase or

quad-phase operations

0.68 ± 0.05

68kΩ

ENABLED

1.00 ± 0.05

1.33 ± 0.05

1.69 ± 0.05

2.05 ± 0.05

2.53 ± 0.05

100kΩ

133kΩ

169kΩ

205kΩ

OPEN

DISABLED

110%

DISABLED

ENABLED

Single-phase operation

DISABLED

110%

DISABLED

Table 2. Phase and Master/Slave Configurations

NUMBER OF

NUMBER OF PHASES

FB OF SLAVE

CONNECTED TO BIAS

CLK FREQUENCY

MAX15158/MAX15158A

1

2

4

1

2

N/A

Yes

4 x f

SW

Maxim Integrated

│ 21

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

f

= (R

/100kΩ) x 600kHz

MAX15158/MAX15158A must be used with external

MOSFET drivers to drive power MOSFETs for typical

high-voltage applications. The device has dedicated

DLFB_ pins to detect the gate voltage of the low-side

MOSFETs to ensure no-shoot-through between the high-

and low-side MOSFETs due to the mismatch delays

caused by the external MOSFET driver. The DLFB_ pins

have a rising threshold of 0.8V (typ) and falling threshold

of 0.5V (typ). A resistor divider can be used from the gate

of the low-side MOSFET to DLFB_ pins to match the

MOSFET gate threshold voltage and the DLFB_ threshold

(see the Standard Application Circuits), to allow robust

operation with a wide range of MOSFETs while minimizing

dead-time power losses.

SW

FREQ

Phase and Master/Slave Conﬁgurations

MAX15158/MAX15158A can be configured in single-

phase, dual-phase or quad-phase operation modes.

When supporting quad-phase operation, two MAX15158/

MAX15158A ICs are used as master and slave. The

controller identifies the number of phases by the resistor

at the OVP pin. This identification is used to determine

how the controller responds to the multiphase clock signal

generated by the primary phase.

For proper synchronization between two devices, connect

the SYNC, SS, COMP, CSIOP and CSION of the master

and slave devices. The FB, REFIN, OUTP and OUTN of

the slave device are connected to its BIAS pin (see the

Standard Application Circuits).

Inductor Selection

A larger inductor value results in reduced inductor ripple

current, leading to a reduced inductor core loss. However,

a larger inductor value results in either a larger physical

size or a higher series resistance (DCR) and a lower

saturation current rating. Typically, inductor value is

The two phases of the same device are interleaved 180°.

When two MAX15158/MAX15158A ICs are stacked up,

there is a 90° phase shift between master and slave

(Figure 6).

chosen to have current ripple (ΔI ) around 50% of

average inductor current. The average inductor current is

can be calculated by:

L

Multiphase Current Balance

MAX15158/MAX15158A monitors the low side MOSFET

current of each phase for active phase current balancing in

multiphase operations. The current imbalance is applied

to the cycle-by-cycle current sensing circuitry as a feed-

back, helping regulating so that load current is evenly

shared between the two phases (see the Block Diagram).

I

= I

/[(1 – D) x N]

L(AVE)

LOAD(MAX)

where:

N = Number of phases

The inductor can be chosen with the following formula:

L = D x V /(f x ΔI )

In quad phase operation, the device uses the differential

CSIO_ connections to communicate the average per-chip

current between master and slave. The current-mode

master and slave devices regulate their current so that all

four phases share the load current equally.

IN SW

L

Output Capacitor Selection

The output capacitors are selected to improve stability,

output voltage ripple and load transient performance. To

MOSFET Gate Control

meet output voltage ripple (V

output capacitor can be selected by:

) requirement, the

RIPPLE

C

= I x D/(N x f

x V

)

OUT(RIPPLE)

LOAD(MAX)

SW

RIPPLE

For some applications it is desired to limit output voltage

overshoot and undershoot during load transient. To meet

the load transient requirement, the output capacitor can

be selected by:

CLK

MASTER

PHASE 1

C

= ΔI

/(3 x BW x ΔV

)

OUT(TRANSIENT)

LOAD

OUT

MASTER

PHASE 2

where:

ΔI

SLAVE

PHASE 3

= Load current step,

LOAD

BW = The control loop bandwidth (see Compensation

Design Guidelines),

SLAVE

PHASE 4

ΔV

= The desired output voltage overshoot or undershoot.

OUT

Figure 6. Quad Phase Synchronization (Master/Slave)

Maxim Integrated

│ 22

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

The final output capacitance should be selected as:

For high power applications, it is suggested to use

planes for the power traces V , V

, and GND. It is

OUT

IN

C

≥ Maximum (C

, C

)

OUT

OUT(RIPPLE) OUT(TRANSIENT)

important to have enough vias connecting the power

planes in different layers. The signal and power grounds

must be seperated. All the power components, including

input and output capacitors, MOSFETs, sense resistor

and MOSFET driver should be connected to the power

ground. MAX15158/MAX15158A and its peripheral RC

components must be connected to the signal ground. It

is suggested to have an island of signal ground in the

closest internal layer underneath the controller. Multiple

vias can be used to connect the signal ground island to

the exposed pad of the controller and the ground nodes of

the noise sensitive signal (COMP, SS, REFIN, FB, etc.).

Signal ground should be tied to power ground through a

short trace or 0Ω resistor, close to the power ground node

of the sense resistor and input capacitors.

Input Capacitor Selection

The input capacitors are selected to help reduce input

voltage ripple (V ). For boost converters, the

IN_RIPPLE

input current is continuous. Neglecting ESR and ESL of

the input capacitor, the input capacitor can be selected by:

C

= ΔI /(8 x N x f

x V

)

IN

L

SW

IN_RIPPLE

For inverting-buck-boost converters, the input current is

discontinuous. The input capacitor can be selected by:

C

= I

x D/(N x f

x V

).

IN

LOAD(MAX)

SW

IN_RIPPLE

PCB Layout Guidelines

PCB layout can dramatically affect the performance of the

power converter. A poorly designed board can degrade

efficiency, thermal performance, noise control, and even

control-loop stability. At higher switching frequencies, lay-

out issues are especially critical.

When the FB level shifter is used, the OUTP/OUTN

sense lines must be routed differentially directly from the

load points. The current sense lines from sense resistor

to CSP_ and CSN_ should also be routed differentially.

When the controller is configured to multiphase operation,

the current sense lines of different phases should be kept

apart to avoid signal coupling. Keep all sense lines and

other noise sensitive signals (CSIO_, COMP, SS, REFIN,

FB, etc.) away from the noisy traces (SW, BST, gate

drives, FREQ/CLK, SYNC, etc.).

As a general guideline, the input capacitors, inductor,

MOSFETs, sense resistor and output capacitors should

be placed close together to minimize the high frequency

current path. The MOSFET driver should be placed close

to the MOSFETs and the switching node (SW) to keep

the gate drive, BST and SW traces short. MAX15158/

MAX15158A should keep some distance from the high

dv/dt SW, BST, and gate drive traces. The peripheral RC

components should be placed as close to the controller as

possible. Priority should be given to the pins that are

sensitive to noise (COMP, SS, REFIN, FB, etc.). It is

suggested to place both differential-mode and common-

mode filters between the CSP_ pin, CSN_ pin, and sense

resistor (see the Standard Application Circuits).

Maxim Integrated

│ 23

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Standard Application Circuits

Dual-Phase Inverting Buck-Boost Converter

C1, C2... C16

16x 1210 4.7µF X7R 100V

V

= -8V TO -65V

IN-

R19 200kΩ

C29 47nF

C31 to C40

10x 1210 10µF

X7R 63V

OUT

17.5V TO 38.5V

V

IN-

V

IN-

OUTP

EN/UVLO

DRV

R14

35kΩ

R20 30kΩ

OUTN

FB

V

IN-

DRV

8V TO 14V

W.R.T. V

DRV

8V TO 14V W.R.T. V

R24 2kΩ

C39 1µF

IN-

V

IN-

MAX15158

ILIM

C21 0.1µF

V

DD

IN-

BST

DH

IN_H

DH1

N1 150V NFET

R17 55kΩ

R18 33kΩ

BSC110N15NS5

OVP

L1 10µH

SER2915H-103KL

MAX15013

HS

V

IN-

BIAS

C40 2.2µF

IN_L

DL1

N2 150V NFET

BSC110N15NS5

DL

R8 100kΩ

GND

V

IN-

R53 3kΩ

R54 1kΩ

V

IN-

PGOOD

REFIN

DLFB1

R32 10kΩ

REFIN

1V TO 2.2V

C25 1nF

V

IN-

C32 10nF

W.R.T. V

R6 10Ω

C17 1nF

IN-

V

IN-

CSP1

CSN1

R40

3mΩ 1%

IN-

C41 to C50

10x 1210 10µF X7R 63V

COMP

SS

R7 10Ω

C26 1nF

R22 6.2kΩ

C36 100pF

C33 47nF

V

IN-

V

IN-

C35 68nF

DRV

IN-

8V TO 14V W.R.T. V

IN_H

C23 0.1µF

V

DD

BST

DH

V

IN-

CLK

FREQ/CLK DH2

N3 150V NFET

BSC110N15NS5

R16 41.2kΩ

L2 10µH

SER2915H-103KL

MAX15013

R21 39.2kΩ

RAMP

DL2

GND

HS

DL

IN_L

N4 150V NFET

BSC110N15NS5

GND

EP

R55 3kΩ

V

IN-

V

IN-

DLFB2

CSIOP

R56 1kΩ

CSIOP

CSION

V

C25 1nF

IN-

V

R36 10Ω

C18 1nF

IN-

CSION

CSP2

R41

3mΩ 1%

SYNCCLK

SYNC

CSN2

R37 10Ω

MULTIPHASE SIGNALS

C28 1nF

V

IN-

V

IN-

Maxim Integrated

│ 24

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Standard Application Circuits (continued)

Single-Phase Boost Converter

C1, C2... C16

16x 1210 4.7µF X7R 50V

V

= 8V TO 24V

IN

R19 200kΩ

C29 47nF

C31 to C40

10x 1210 10µF

X7R 63V

OUT 48V

EN/UVLO

R20 30kΩ

DRV

8V TO 14V

DRV

C39 1µF

DRV 8V TO 14V

MAX15158A

C21 0.1µF

V

DD

BST

DH

ILIM

DH1

IN_H

R17 55kΩ

N1 80V NFET

OVP

BSC030N08NS5

R18 220kΩ

L1 4.7µH

MAX15013

HS

DL

SER2915H-472KL

BIAS

DL1

C40 2.2µF

IN_L

N2 80V NFET

BSC030N08NS5

R8 100kΩ

GND

R53 3kΩ

R54 1kΩ

PGOOD

DLFB1

C25 1nF

R6 10Ω

CSP1

R40

3mΩ 1%

C17 1nF

R7 10Ω

CSN1

COMP

R22 6.2kΩ

C36 100pF

C33 47nF

SS

C26 1nF

C35 68nF

R14

46kΩ

FB

CLK

FREQ/CLK

R24 2kΩ

R16 41.2kΩ

DH2

DL2

R21 39.2kΩ

RAMP

DLFB2

GND

EP

CSP2

CSN2

CSIOP

CSION

SYNCCLK

CSIOP

CSION

SYNC

V

BIAS

OUTP

OUTN

MULTIPHASE SIGNALS

Maxim Integrated

│ 25

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Standard Application Circuits (continued)

Quad Phase Interconnects (Inverting Buck-Boost Converter)

EN

CLK

U1_MASTER

U2-SLAVE

-48V

SYNC

COMP

SYNC

COMP

DAC

REFIN

-48V

-48V -48V

-48V

OUTPUT

-48V

POWER STAGE

-48V

POWER STAGE

-48V

POWER STAGE

Maxim Integrated

│ 26

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Ordering Information

PART NUMBER

TEMP RANGE

-40°C to +125°C

PIN-PACKAGE

32 TQFN-EP*

MAX15158ATJ+

MAX15158ATJ+T

MAX15158AATJ+

MAX15158AATJ+T

+ Denotes a lead(Pb)-free/RoHS-complian package.

T = Tape and reel.

*EP = Exposed pad.

Maxim Integrated

│ 27

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MAX15158/MAX15158A

High-Voltage Multiphase Boost Controller

Revision History

REVISION REVISION

PAGES

DESCRIPTION

CHANGED

NUMBER

DATE

0

6/18

Initial release

—

Updated Electrical Characteristics table, Block Diagrams, OVP section, added

Inductor Selection section, and update Ordering Information table

4, 6, 7, 13, 14,

16, 17, 19, 21, 25

1

2

9/18

Updated General Description, Beneﬁts and Features sections, Electrical

Characteristics, Pin Description, Block Diagrams, and Detailed Description

1, 4–7, 10, 11,

13–20

11/19

For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and speciﬁcations without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

©

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

2019 Maxim Integrated Products, Inc.

│ 28


型号：	MAX15158AATJ
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	High-Voltage Multiphase Boost Controller
文件：	总28页 (文件大小：857K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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