MAX149 [MAXIM]
+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs; + 2.7V至+ 5.25V ，低功耗， 8通道，串行10位ADC
| 型号： | MAX149 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs |
| 文件： | 总24页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0464; Rev 2; 5/98
+2.7V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
8/MAX149
Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
The MAX148/MAX149 10-bit data-acquisition systems
c omb ine a n 8-c ha nne l multip le xe r, hig h-b a nd wid th
track/hold, and serial interface with high conversion
speed and low power consumption. They operate from a
single +2.7V to +5.25V supply, and sample to 133ksps.
Both devices’ analog inputs are software configurable for
unipolar/bipolar and single-ended/differential operation.
♦ 8-Channel Single-Ended or 4-Channel
Differential Inputs
♦ Single-Supply Operation: +2.7V to +5.25V
♦ Internal 2.5V Reference (MAX149)
♦ Low Power: 1.2mA (133ksps, 3V supply)
54µA (1ksps, 3V supply)
The 4-wire serial interface connects directly to SPI™/
QSPI™ and MICROWIRE™ devices without external
logic. A serial-strobe output allows direct connection to
TMS320-family digital signal processors. The MAX148/
MAX149 use either the internal clock or an external serial-
interface clock to perform successive-approximation
analog-to-digital conversions.
1µA (power-down mode)
♦ SPI/QSPI/MICROWIRE/TMS320-Compatible
4-Wire Serial Interface
♦ Software-Configurable Unipolar or Bipolar Inputs
♦ 20-Pin DIP/SSOP Packages
The MAX149 has an internal 2.5V reference, while the
MAX148 requires an external reference. Both parts have
a re fe re nc e -b uffe r a mp lifie r with a ± 1.5% volta g e -
adjustment range.
Ord e rin g In fo rm a t io n
These devices provide a hard-wired SHDN pin and a
s oftwa re -s e le c ta b le p owe r-d own, a nd c a n b e p ro-
grammed to automatically shut down at the end of a con-
version. Accessing the serial interface automatically
powers up the MAX148/MAX149, and the quick turn-on
time allows them to be shut down between all conver-
sions. This technique can cut supply current to under
60µA at reduced sampling rates.
INL
(LSB)
PART†
TEMP. RANGE PIN-PACKAGE
MAX148ACPP
MAX148BCPP
MAX148ACAP
MAX148BCAP
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
20 Plastic DIP
20 Plastic DIP
20 SSOP
±1/2
±1
±1/2
±1
20 SSOP
Ordering Information continued at end of data sheet.
Contact factory for availability of alternate surface-mount
packages.
†
The MAX148/MAX149 are available in a 20-pin DIP and a
20-pin SSOP.
For 4-c ha nne l ve rs ions of the s e d e vic e s , s e e the
MAX1248/MAX1249 data sheet.
__________Typ ic a l Op e ra t in g Circ u it
________________________Ap p lic a t io n s
+3V
Portable Data Logging
Medical Instruments
Pen Digitizers
Data Acquisition
V
V
CH0
DD
DD
0.1µF
0V TO
+2.5V
ANALOG
INPUTS
DGND
Battery-Powered Instruments
Process Control
MAX149
CH7
AGND
COM
CPU
I/O
VREF
CS
4.7µF
SCLK
SCK (SK)
MOSI (SO)
MISO (SI)
DIN
DOUT
REFADJ
0.01µF
SSTRB
SHDN
V
SS
Pin Configuration appears at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
ABSOLUTE MAXIMUM RATINGS
V
to AGND, DGND................................................. -0.3V to 6V
SSOP (derate 8.00mW/°C above +70°C) ................... 640mW
CERDIP (derate 11.11mW/°C above +70°C).............. 889mW
Operating Temperature Ranges
DD
AGND to DGND...................................................... -0.3V to 0.3V
CH0–CH7, COM to AGND, DGND ............ -0.3V to (V + 0.3V)
DD
VREF, REFADJ to AGND ........................... -0.3V to (V + 0.3V)
Digital Inputs to DGND .............................................. -0.3V to 6V
MAX148_C_P/MAX149_C_P .............................. 0°C to +70°C
MAX148_E_P/MAX149_E_P............................ -40°C to +85°C
MAX148_MJP/MAX149_MJP ........................ -55°C to +125°C
Storage Temperature Range ............................ -60°C to +150°C
Lead Temperature (soldering, 10sec) ............................ +300°C
DD
Digital Outputs to DGND ........................... -0.3V to (V + 0.3V)
DD
Digital Output Sink Current .................................................25mA
Continuous Power Dissipation (T = +70°C)
A
Plastic DIP (derate 11.11mW/°C above +70°C) ......... 889mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
V
= +2.7V to +5.25V; COM = 0V; f
= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
8/MAX149
DD
SCLK
MAX149—4.7µF capacitor at VREF pin; MAX148—external reference, VREF = 2.500 V applied to VREF pin; T = T
to T
; unless
A
MIN
MAX
otherwise noted.)
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
10
Bits
MAX14_A
MAX14_B
±0.5
LSB
±1.0
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
INL
DNL
No missing codes over temperature
±1
±1
±2
±1
±2
LSB
MAX14_A
MAX14_B
MAX14_A
MAX14_B
±0.15
±0.15
LSB
Gain Error (Note 3)
LSB
ppm/°C
LSB
Gain Temperature Coefficient
±0.25
±0.05
Channel-to-Channel Offset
Matching
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)
Signal-to-Noise + Distortion Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Small-Signal Bandwidth
SINAD
THD
66
-70
70
dB
dB
Up to the 5th harmonic
SFDR
dB
65kHz, 2.500V (Note 4)
p-p
-75
2.25
1.0
dB
-3dB rolloff
MHz
MHz
Full-Power Bandwidth
CONVERSION RATE
5.5
35
6
7.5
65
Internal clock, SHDN = FLOAT
Conversion Time (Note 5)
t
µs
Internal clock, SHDN = V
CONV
DD
External clock = 2MHz, 12 clocks/conversion
Track/Hold Acquisition Time
Aperture Delay
t
1.5
µs
ns
ps
ACQ
30
Aperture Jitter
<50
2
_______________________________________________________________________________________
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
8/MAX149
ELECTRICAL CHARACTERISTICS (continued)
V
= +2.7V to +5.25V; COM = 0V; f
= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
DD
SCLK
MAX149—4.7µF capacitor at VREF pin; MAX148—external reference, VREF = 2.500 V applied to VREF pin; T = T
to T
; unless
A
MIN
MAX
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
CONVERSION RATE (continued)
1.8
SHDN = FLOAT
SHDN = V
Internal Clock Frequency
MHz
0.225
DD
0.1
0
2.0
External Clock Frequency
MHz
2.0
Data transfer only
ANALOG/COM INPUTS
Unipolar, COM = 0V
0 to VREF
Input Voltage Range, Single-
Ended and Differential (Note 6)
V
Bipolar, COM = VREF / 2
±VREF / 2
±1
Multiplexer Leakage Current
Input Capacitance
On/off leakage current, V
= 0V or V
±0.01
16
µA
pF
CH_
DD
INTERNAL REFERENCE (MAX149 only, reference buffer enabled)
VREF Output Voltage
T
= +25°C (Note 7)
2.470
2.500
2.530
30
V
mA
A
VREF Short-Circuit Current
VREF Temperature Coefficient
Load Regulation (Note 8)
MAX149
±30
ppm/°C
mV
0mA to 0.2mA output load
Internal compensation mode
External compensation mode
0.35
0
Capacitive Bypass at VREF
µF
4.7
Capacitive Bypass at REFADJ
REFADJ Adjustment Range
0.01
µF
%
±1.5
EXTERNAL REFERENCE AT VREF (Buffer disabled)
VREF Input Voltage Range
(Note 9)
V
50mV
+
DD
V
1.0
18
VREF Input Current
VREF = 2.500V
100
25
150
µA
kΩ
µA
VREF Input Resistance
Shutdown VREF Input Current
0.01
10
V
0.5
-
DD
REFADJ Buffer-Disable Threshold
EXTERNAL REFERENCE AT REFADJ
Capacitive Bypass at VREF
V
Internal compensation mode
External compensation mode
MAX149
0
µF
V/V
µA
4.7
2.06
2.00
Reference Buffer Gain
REFADJ Input Current
MAX148
MAX149
±50
±10
MAX148
_______________________________________________________________________________________
3
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
V
= +2.7V to +5.25V; COM = 0V; f
= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
DD
SCLK
MAX149—4.7µF capacitor at VREF pin; MAX148—external reference, VREF = 2.500 V applied to VREF pin; T = T
to T
; unless
A
MIN
MAX
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
V
≤ 3.6V
2.0
3.0
DD
V
IH
V
DIN, SCLK, CS Input High Voltage
V
DD
> 3.6V
V
0.8
V
V
DIN, SCLK, CS Input Low Voltage
DIN, SCLK, CS Input Hysteresis
DIN, SCLK, CS Input Leakage
DIN, SCLK, CS Input Capacitance
SHDN Input High Voltage
SHDN Input Mid Voltage
IL
V
HYST
0.2
I
IN
V
= 0V or V
DD
±0.01
±1
15
µA
pF
V
IN
C
(Note 10)
IN
V
SH
V
- 0.4
DD
1
V
SM
1.1
V
DD
- 1.1
0.4
V
V
SL
V
SHDN Input Low Voltage
I
±4.0
µA
V
SHDN Input Current
SHDN = 0V or V
SHDN = FLOAT
S
DD
V
FLT
V
DD
/ 2
SHDN Voltage, Floating
SHDN Maximum Allowed
Leakage, Mid Input
±100
nA
SHDN = FLOAT
DIGITAL OUTPUTS (DOUT, SSTRB)
I
= 5mA
0.4
0.8
SINK
Output Voltage Low
V
OL
V
I
= 16mA
SINK
Output Voltage High
V
OH
I
= 0.5mA
V - 0.5
DD
V
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
I
±0.01
±10
15
µA
pF
CS = V
L
DD
C
CS = V (Note 10)
OUT
DD
V
DD
2.70
5.25
3.0
2.0
15
V
V
= 5.25V
= 3.6V
= 5.25V
= 3.6V
1.6
1.2
3.5
1.2
30
DD
Operating mode,
full-scale input (Note 11)
mA
V
DD
I
DD
Positive Supply Current
V
DD
Full power-down
V
DD
10
µA
I
Fast power-down (MAX149)
70
DD
Full-scale input, external reference = 2.500V,
= 2.7V to 5.25V
Supply Rejection (Note 12)
PSR
±0.3
mV
V
DD
4
_______________________________________________________________________________________
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
8/MAX149
TIMING CHARACTERISTICS
(V = +2.7V to +5.25V, T = T
to T
, unless otherwise noted.)
DD
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
1.5
100
0
TYP
MAX UNITS
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
t
µs
ns
ns
ACQ
t
DS
t
DH
MAX14_ _C/E
MAX14_ _M
20
200
ns
SCLK Fall to Output Data Valid
t
Figure 1
DO
20
240
t
Figure 1
Figure 2
240
240
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
DV
t
TR
t
100
0
CSS
CSH
t
SCLK Pulse Width High
SCLK Pulse Width Low
t
200
200
CH
t
CL
SCLK Fall to SSTRB
t
Figure 1
240
240
240
SSTRB
t
External clock mode only, Figure 1
External clock mode only, Figure 2
Internal clock mode only (Note 7)
CS Fall to SSTRB Output Enable
CS Rise to SSTRB Output Disable
SSTRB Rise to SCLK Rise
SDV
t
STR
t
0
SCK
Note 1: Tested at V = 2.7V; COM = 0V; unipolar single-ended input mode.
DD
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX149—internal reference, offset nulled; MAX148—external reference (VREF = +2.500V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to V
.
DD
Note 7: Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 10: Guaranteed by design. Not subject to production testing.
Note 11: The MAX148 typically draws 400µA less than the values shown.
Note 12: Measured as V (2.7V) - V (5.25V) .
FS
FS
|
|
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = 3.0V, VREF = 2.500V, f
= 2.0MHz, C
= 20pF, T = +25°C, unless otherwise noted.)
A
DD
SCLK
LOAD
INTEGRAL NONLINEARITY
vs. CODE
INTEGRAL NONLINEARITY
vs. TEMPERATURE
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
0.125
0.125
0.100
0.075
0.050
0.025
V
DD
= 2.7V
0.10
0.05
0
0.100
0.075
0.050
MAX149
MAX148
MAX149
MAX148
60
-0.05
-0.10
0.025
0
0
-60
-20
20
100
140
0
256
512
768
1024
2.25 2.75 3.25 3.75 4.25 4.75 5.25
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
CODE
_______________________________________________________________________________________
5
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = 3.0V, VREF = 2.500V, f
= 2.0MHz, C
= 20pF, T = +25°C, unless otherwise noted.)
A
DD
SCLK
LOAD
MAX149
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
2.5020
2.00
1.75
1.50
1.25
1.00
0.75
0.50
3.0
R = ∞
CODE = 1010101000
L
FULL POWER-DOWN
C
= 50pF
LOAD
2.5015
2.5010
2.5005
2.5000
2.4995
2.4990
2.5
2.0
MAX149
1.5
1.0
0.5
0
C
= 20pF
LOAD
8/MAX149
MAX148
2.25 2.75 3.25 3.75 4.25 4.75 5.25
2.25 2.75 3.25 3.75 4.25 4.75 5.25
2.25 2.75 3.25 3.75 4.25 4.75 5.25
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT
vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
2.0
1.3
MAX149
1.2
1.6
1.2
0.8
0.4
1.1
1.0
MAX148
0.9
R
LOAD
= ∞
CODE = 1010101000
-60 -20 20
TEMPERATURE (°C)
0
0.8
-60
-20
20
60
100
140
60
100
140
TEMPERATURE (°C)
MAX149
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.501
V
DD
= 5.25V
2.500
2.499
V
DD
= 3.6V
V
DD
= 2.7V
2.498
2.497
2.496
2.495
2.494
-60
-20
20
60
100
140
TEMPERATURE (°C)
6
_______________________________________________________________________________________
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
8/MAX149
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
1–8
CH0–CH7
Sampling Analog Inputs
Ground reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.
9
COM
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX148/MAX149 down; otherwise, they are
fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation mode.
Letting SHDN float puts the reference-buffer amplifier in external compensation mode.
10
SHDN
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode (MAX149 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
11
VREF
REFADJ to V
.
DD
12
13
14
15
REFADJ
AGND
DGND
DOUT
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to V
.
DD
Analog Ground
Digital Ground
Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX148/MAX149 begin the
A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance when CS is high (external clock
mode).
16
SSTRB
17
18
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
CS
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
19
20
SCLK
V
DD
Positive Supply Voltage
V
DD
V
DD
6k
6k
DOUT
DOUT
DOUT
DOUT
C
50pF
C
LOAD
50pF
C
50pF
C
50pF
LOAD
LOAD
LOAD
6k
6k
DGND
DGND
DGND
a) High-Z to V and V to V
OH
DGND
b) High-Z to V and V to V
OL
OH
OL
OL
OH
a) V to High-Z
b) V to High-Z
OL
OH
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
_______________________________________________________________________________________
7
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
acquisition interval, the T/H switch opens, retaining
charge on C as a sample of the signal at IN+.
_______________De t a ile d De s c rip t io n
HOLD
The MAX148/MAX149 a na log -to-d ig ita l c onve rte rs
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 10-bit digital output. A flexible seri-
al interface provides easy interface to microprocessors
(µPs ). Fig ure 3 is a b loc k d ia g ra m of the MAX148/
MAX149.
The conversion interval begins with the input multiplexer
switching C from the positive input (IN+) to the
HOLD
negative input (IN-). In single-ended mode, IN- is simply
COM. This unbalances node ZERO at the comparator’s
input. The capacitive DAC adjusts during the remainder
of the conversion cycle to restore node ZERO to 0V
within the limits of 10-bit resolution. This action is equiv-
P s e u d o -Diffe re n t ia l In p u t
The sampling architecture of the ADC’s analog com-
p a ra tor is illus tra te d in the e q uiva le nt inp ut c irc uit
(Fig ure 4). In s ing le -e nd e d mod e , IN+ is inte rna lly
switched to CH0–CH7, and IN- is switched to COM. In
differential mode, IN+ and IN- are selected from the fol-
lowing p a irs : CH0/CH1, CH2/CH3, CH4/CH5, a nd
CH6/CH7. Configure the channels with Tables 2 and 3.
alent to transferring a 16pF x [(VIN+) - (V -)] charge
IN
from C
to the binary-weighted capacitive DAC,
HOLD
which in turn forms a digital representation of the analog
input signal.
Tra c k /Ho ld
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN- connects to the “-” input, and the
difference of |IN+ - IN-| is sampled. At the end of the
conversion, the positive input connects back to IN+,
8/MAX149
In differential mode, IN- and IN+ are internally switched
to e ithe r of the a na log inp uts . This c onfig ura tion is
pseudo-differential to the effect that only the signal at IN+
is sampled. The return side (IN-) must remain stable within
±0.5LSB (±0.1LSB for best results) with respect to AGND
during a conversion. To accomplish this, connect a 0.1µF
capacitor from IN- (the selected analog input) to AGND.
During the acquisition interval, the channel selected
and C
charges to the input signal.
HOLD
as the positive input (IN+) charges capacitor C
.
HOLD
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
The acquisition interval spans three SCLK cycles and
ends on the falling SCLK edge after the last bit of the
input control word has been entered. At the end of the
18
CS
19
SCLK
CAPACITIVE DAC
VREF
INPUT
SHIFT
INT
17
10
DIN
CLOCK
REGISTER
CONTROL
LOGIC
COMPARATOR
INPUT
C
SHDN
HOLD
MUX
ZERO
–
+
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
1
15
16
CH0
OUTPUT
SHIFT
DOUT
2
3
16pF
CH1
CH2
REGISTER
SSTRB
R
IN
ANALOG
INPUT
MUX
4
5
6
7
8
9k
T/H
CH3
CH4
C
SWITCH
CLOCK
HOLD
IN
10+2-BIT
SAR
ADC
CH5
CH6
TRACK
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
OUT
20
14
T/H
SWITCH
REF
V
DD
CH7
9
A ≈ 2.06*
COM
+1.21V
DGND
AGND
20k
REFERENCE
(MAX149)
13
12
11
REFADJ
VREF
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
MAX148
MAX149
+2.500V
*A ≈ 2.00 (MAX148)
Figure 4. Equivalent Input Circuit
Figure 3. Block Diagram
8
_______________________________________________________________________________________
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
8/MAX149
OSCILLOSCOPE
V
DD
+3V
0.1µF
DGND
SCLK
AGND
COM
CS
MAX148
MAX149
0V TO
+2.500V
ANALOG
INPUT
SSTRB
DOUT*
CH7
0.01µF
SCLK
DIN
+3V
2MHz
OSCILLATOR
+3V
2.5V
REFADJ
VREF
+3V
CH1
CH2
CH3
CH4
V
OUT
DOUT
SSTRB
C1
0.1µF
1000pF
MAX872
COMP
SHDN
N.C.
OPTIONAL FOR MAX149,
REQUIRED FOR MAX148
* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
Figure 5. Quick-Look Circuit
allowed between conversions. The acquisition time,
An a lo g In p u t P ro t e c t io n
Internal protection diodes, which clamp the analog input
to V and AGND, allow the channel input pins to swing
t
, is the maximum time the device takes to acquire
ACQ
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
DD
from AGND - 0.3V to V
+ 0.3V without d a ma g e .
DD
However, for accurate conversions near full scale, the
inputs must not exceed V by more than 50mV or be
lower than AGND by 50mV.
DD
t
= 7 x (R + R ) x 16pF
S IN
ACQ
where R = 9kΩ, R = the source impedance of the
input signal, and t
that source impedances below 4kΩ do not significantly
affect the ADC’s AC performance.
IN
S
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.
is never less than 1.5µs. Note
ACQ
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with the
inp ut s ourc e imp e d a nc e , limiting the ADC’s s ig na l
bandwidth.
Qu ic k Lo o k
To quickly evaluate the MAX148/MAX149’s analog perfor-
mance, use the circuit of Figure 5. The MAX148/MAX149
require a control byte to be written to DIN before each
conversion. Tying DIN to +3V feeds in control bytes of
$FF (HEX), which trigger single-ended unipolar conver-
sions on CH7 in external clock mode without powering
down between conversions. In external clock mode, the
SSTRB output pulses high for one clock period before
the most significant bit of the conversion result is shift-
ed out of DOUT. Varying the analog input to CH7 will
alter the sequence of bits from DOUT. A total of 15
clock cycles is required per conversion. All transitions
of the SSTRB and DOUT outputs occur on the falling
edge of SCLK.
In p u t Ba n d w id t h
The ADC’s inp ut tra c king c irc uitry ha s a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
ra te b y us ing und e rs a mp ling te c hniq ue s . To a void
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
_______________________________________________________________________________________
9
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
Table 1. Control-Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
BIT
NAME
DESCRIPTION
7(MSB)
START
The first logic “1” bit after CS goes low defines the beginning of the control byte.
6
5
4
SEL2
SEL1
SEL0
These three bits select which of the eight channels are used for the conversion (Tables 2 and 3).
3
UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF/2 to +VREF/2.
2
SGL/DIF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
8/MAX149
1
PD1
PD0
Selects clock and power-down modes.
0(LSB)
PD1
PD0
Mode
0
0
1
1
0
1
0
1
Full power-down
Fast power-down (MAX149 only)
Internal clock mode
External clock mode
DIF
Table 2. Channel Selection in Single-Ended Mode (SGL/
= 1)
SEL2
0
SEL1
0
SEL0
0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
+
–
1
0
1
0
1
0
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
+
–
–
–
–
–
–
–
+
+
+
+
+
+
registers: set CPOL = 0 and CPHA = 0. MICROWIRE,
SPI, and QSPI all transmit a byte and receive a byte at
the same time. Using the Typical Operating Circuit, the
simplest software interface requires only three 8-bit
transfers to perform a conversion (one 8-bit transfer to
configure the ADC, and two more 8-bit transfers to clock
out the conversion result). See Figure 20 for MAX148/
MAX149 QSPI connections.
Ho w t o S t a rt a Co n ve rs io n
Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX148/MAX149’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 1 shows the control-byte format.
The MAX148/MAX149 a re c omp a tib le with SPI/
QSPI and MICROWIRE devices. For SPI, select the cor-
rect clock polarity and sampling edge in the SPI control
10 ______________________________________________________________________________________
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
8/MAX149
DIF
Table 3. Channel Selection in Differential Mode (SGL/
= 0)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+
–
+
–
+
–
+
–
–
–
+
–
+
–
+
+
CS
t
ACQ
SCLK
1
4
8
12
16
20
24
UNI/
BIP
SGL/
DIF
SEL2 SEL1 SEL0
PD1 PD0
DIN
SSTRB
DOUT
START
RB2
B6
RB3
RB1
FILLED WITH
ZEROS
B9
MSB
B0
LSB
B8
B7
B5
B4
B3
B2
B1
S1
S0
ACQUISITION
1.5µs
CONVERSION
A/D STATE
IDLE
IDLE
(f
SCLK
= 2MHz)
Figure 6. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with f
≤ 2MHz)
SCLK
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with one leading zero, two sub-LSB bits, and three trail-
ing zeros. The total conversion time is a function of the
serial-clock frequency and the amount of idle time
between 8-bit transfers. To avoid excessive T/H droop,
make sure the total conversion time does not exceed
120µs.
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull
Digital Output
In unipolar input mode, the output is straight binary
(Figure 17). For bipolar input mode, the output is twos
complement (Figure 18). Data is clocked out at the
falling edge of SCLK in MSB-first format.
CS low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.
Clo c k Mo d e s
The MAX148/MAX149 ma y us e e ithe r a n e xte rna l
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the e xte rna l c loc k s hifts d a ta in a nd out of the
5) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.
6) Pull CS high.
______________________________________________________________________________________ 11
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
• • •
CS
t
t
CH
t
CSH
CSS
t
t
CL
CSH
SCLK
• • •
t
DS
t
DH
DIN
• • •
t
DV
t
DO
t
TR
8/MAX149
DOUT
• • •
Figure 7. Detailed Serial-Interface Timing
CS
• • •
• • •
t
t
STR
SDV
SSTRB
• • •
• • •
t
t
SSTRB
SSTRB
SCLK
• • • •
• • • •
PD0 CLOCKED IN
Figure 8. External Clock Mode SSTRB Detailed Timing
MAX148/MAX149. The T/H acquires the input signal as
the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 7–10 show the timing characteris-
tics common to both modes.
state when CS goes high; after the next CS falling edge,
SSTRB outputs a logic low. Figure 8 shows the SSTRB
timing in external clock mode.
The conversion must complete in some minimum time,
or d roop on the s a mp le -a nd -hold c a p a c itors ma y
degrade conversion results. Use internal clock mode if
the serial-clock frequency is less than 100kHz, or if
serial-clock interruptions could cause the conversion
interval to exceed 120µs.
External Clock
In external clock mode, the external clock not only shifts
data in and out, but it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock
period after the last bit of the control byte. Succes-
sive-approximation bit decisions are made and appear
at DOUT on each of the next 12 SCLK falling edges
(Figure 6). SSTRB and DOUT go into a high-impedance
Internal Clock
In internal clock mode, the MAX148/MAX149 generate
their own conversion clocks internally. This frees the µP
12 ______________________________________________________________________________________
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
8/MAX149
CS
SCLK
DIN
1
4
8
18
24
2
3
5
6
7
9
10
11
12
19
20
21
22
23
UNI/ SGL/
BIP DIF
SEL2 SEL1 SEL0
PD1 PD0
START
SSTRB
t
CONV
FILLED WITH
ZEROS
B9
MSB
B0
LSB
DOUT
B8
B7
S1
S0
ACQUISITION
CONVERSION
A/D STATE
1.5µs
IDLE
IDLE
7.5µs MAX
(f
SCLK
= 2MHz) (SHDN = FLOAT)
Figure 9. Internal Clock Mode Timing
CS
t
CONV
t
CSS
t
t
SCK
CSH
SSTRB
SCLK
t
SSTRB
t
DO
PD0 CLOCK IN
DOUT
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 10. Internal Clock Mode SSTRB Detailed Timing
from the burden of running the SAR conversion clock
and allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0MHz
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5µs (SHDN = FLOAT),
during which time SCLK should remain low for best
noise performance.
Pulling CS high prevents data from being clocked into
the MAX148/MAX149 and three-states DOUT, but it
does not adversely affect an internal clock mode con-
version already in progress. When internal clock mode
is s e le c te d , SSTRB d oe s not g o into a hig h-
impedance state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX148/MAX149 at clock rates exceeding 2.0MHz if
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the c onve rs ion a t DOUT, followe d b y the
remaining bits in MSB-first format (Figure 9). CS does
not need to be held low once a conversion is started.
the minimum acquisition time (t
) is kept above 1.5µs.
ACQ
Da t a Fra m in g
The falling edge of CS does not start a conversion.
The first logic high clocked into DIN is interpreted as a
start bit and defines the first bit of the control byte. A
conversion starts on SCLK’s falling edge, after the eighth
______________________________________________________________________________________ 13
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
Table 4. Typical Power-Up Delay Times
REFERENCE-
VREF
CAPACITOR
(µF)
POWER-UP
DELAY
(µs)
MAXIMUM
SAMPLING RATE
(ksps)
REFERENCE
BUFFER
BUFFER
COMPENSATION
MODE
POWER-DOWN
MODE
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Internal
Internal
External
External
—
—
—
Fast
Full
Fast
Full
Fast
Full
5
26
300
26
4.7
4.7
—
See Figure 14c
133
133
133
133
See Figure 14c
2
2
—
—
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as follows:
Re fe re n c e -Bu ffe r Co m p e n s a t io n
In addition to its shutdown function, SHDN selects inter-
na l or e xte rna l c omp e ns a tion. The c omp e ns a tion
affects both power-up time and maximum conversion
speed. The100kHz minimum clock rate is limited by
droop on the sample-and-hold and is independent of
the compensation used.
8/MAX149
The first high bit clocked into DIN with CS low any
time the converter is idle; e.g., after V is applied.
DD
OR
The first high bit clocked into DIN after bit 3 of a con-
version in progress is clocked onto the DOUT pin.
Floa t SHDN to s e le c t e xte rna l c omp e ns a tion. The
Typical Operating Circuit uses a 4.7µF capacitor at
VREF. A 4.7µF value ensures reference-buffer stability
and allows converter operation at the 2MHz full clock
spe e d . Exte rna l c ompe nsa tion inc re a se s powe r-up
time (see the Choosing Power-Down Mode section and
Table 4).
If CS is toggled before the current conversion is com-
plete, the next high bit clocked into DIN is recognized as
a start bit; the current conversion is terminated, and a
new one is started.
The fastest the MAX148/MAX149 can run with CS held
low between conversions is 15 clocks per conversion.
Figure 11a shows the serial-interface timing necessary to
perform a conversion every 15 SCLK cycles in external
clock mode. If CS is tied low and SCLK is continuous,
guarantee a start bit by first clocking in 16 zeros.
Pull SHDN hig h to s e le c t inte rna l c omp e ns a tion.
Internal compensation requires no external capacitor at
VREF and allows for the shortest power-up times. The
maximum clock rate is 2MHz in internal clock mode
and 400kHz in external clock mode.
Most microcontrollers (µCs) require that conversions
occur in multiples of 8 SCLK clocks; 16 clocks per con-
version is typically the fastest that a µC can drive the
MAX148/MAX149. Fig ure 11b s hows the s e ria l-
interface timing necessary to perform a conversion every
16 SCLK cycles in external clock mode.
Ch o o s in g P o w e r-Do w n Mo d e
You can save power by placing the converter in a low-
current shutdown state between conversions. Select full
power-down mode or fast power-down mode via bits 1
and 0 of the DIN control byte with SHDN high or floating
(Tables 1 and 5). In both software power-down modes,
the serial interface remains operational, but the ADC
does not convert. Pull SHDN low at any time to shut
down the converter completely. SHDN overrides bits 1
and 0 of the control byte.
__________ Ap p lic a t io n s In fo rm a t io n
P o w e r-On Re s e t
When power is first applied, and if SHDN is not pulled
low, inte rna l p owe r-on re s e t c irc uitry a c tiva te s the
MAX148/MAX149 in internal clock mode, ready to con-
vert with SSTRB = high. After the power supplies stabi-
lize, the internal reset time is 10µs, and no conversions
should be performed during this phase. SSTRB is high
on power-up and, if CS is low, the first logical 1 on DIN
is interpreted as a start bit. Until a conversion takes
place, DOUT shifts out zeros. (Also see Table 4.)
Full power-down mode turns off all chip functions that
draw quiescent current, reducing supply current to 2µA
(typ ). Fa s t p owe r-d own mod e turns off a ll c irc uitry
except the bandgap reference. With fast power-down
mode, the supply current is 30µA. Power-up time can be
shortened to 5µs in internal compensation mode.
Table 4 shows how the choice of reference-buffer com-
pensation and power-down mode affects both power-up
14 ______________________________________________________________________________________
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
8/MAX149
CS
1
8
15
1
8
15 1
SCLK
DIN
S
CONTROL BYTE 2
S
CONTROL BYTE 0
S
CONTROL BYTE 1
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 1
DOUT
SSTRB
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
• • •
• • •
• • •
• • •
CS
1
8
16
1
8
16
SCLK
DIN
S
CONTROL BYTE 0
S
CONTROL BYTE 1
DOUT
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 0
B9 B8 B7 B6
CONVERSION RESULT 1
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
CLOCK
MODE
EXTERNAL
EXTERNAL
SHDN
SETS SOFTWARE
POWER-DOWN
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
DIN
S X X X X X 1 1
S X X X X X 0 0
S X X X X X 1 1
DOUT
MODE
VALID
DATA
INVALID
DATA
10 + 2 DATA BITS
POWERED UP
10 + 2 DATA BITS
HARDWARE
POWER-
DOWN
POWERED UP
SOFTWARE
POWERED UP
POWER-DOWN
Figure 12a. Timing Diagram Power-Down Modes, External Clock
delay and maximum sample rate. In external compensa-
tion mode, power-up time is 20ms with a 4.7µF compen-
sation capacitor when the capacitor is initially fully
discharged. From fast power-down, start-up time can be
eliminated by using low-leakage capacitors that do not
discharge more than 1/2LSB while shut down. In power-
down, leakage currents at VREF cause droop on the ref-
erence bypass capacitor. Figures 12a and 12b show
the various power-down sequences in both external and
internal clock modes.
______________________________________________________________________________________ 15
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
CLOCK
MODE
INTERNAL
SETS
POWER-DOWN
SETS INTERNAL
CLOCK MODE
DIN
S X X X X X 1 0
S X X X X X 0 0
S
DOUT
DATA VALID
DATA VALID
SSTRB
MODE
CONVERSION
CONVERSION
POWER-DOWN
POWERED UP
POWERED UP
8/MAX149
Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
Table 5. Software Power-Down
and Clock Mode
Table 6. Hard-Wired Power-Down
and Internal Clock Frequency
REFERENCE-
BUFFER
COMPENSATION FREQUENCY
INTERNAL
CLOCK
PD1
PD0
DEVICE MODE
Full Power-Down
Fast Power-Down
DEVICE
MODE
SHDN
STATE
0
0
0
1
1
Floating
0
Enabled
Enabled
Internal
External
N/A
225kHz
1.8MHz
N/A
1
1
0
1
Internal Clock
External Clock
Power-Down
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
(USING FULLPD)
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
WITH EXTERNAL REFERENCE
100
10,000
1000
100
10
VREF = V = 3.0V
DD
R
= ∞
LOAD
R
LOAD
= ∞
CODE = 1010101000
CODE = 1010101000
8 CHANNELS
8 CHANNELS
10
1 CHANNEL
1 CHANNEL
1
0.1
1
0.01
0.1
1
10 100 1k 10k 100k 1M
CONVERSION RATE (Hz)
0.1
1
10
100
1k
CONVERSION RATE (Hz)
Figure 13. Average Supply Current vs. Conversion Rate with
External Reference
Figure 14a. MAX149 Supply Current vs. Conversion Rate,
FULLPD
16 ______________________________________________________________________________________
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
8/MAX149
results may be clocked out after the MAX148/MAX149
enter a software power-down.
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
The first logical 1 on DIN is interpreted as a start bit
a nd p owe rs up the MAX148/MAX149. Following
the start bit, the data input word or control byte also
determines clock mode and power-down states. For
example, if the DIN word contains PD1 = 1, then the
c hip re ma ins p owe re d up . If PD0 = PD1 = 0, a
power-down resumes after one conversion.
(USING FASTPD)
10,000
1000
100
R
= ∞
LOAD
CODE = 1010101000
8 CHANNELS
1 CHANNEL
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down (Table 6). Unlike software power-down
mode, the conversion is not completed; it stops coin-
cidentally with SHDN being brought low. SHDN also
controls the clock frequency in internal clock mode.
Letting SHDN float sets the internal clock frequency to
1.8MHz. When returning to normal operation with SHDN
10
1
0.1
1
10 100 1k 10k 100k 1M
CONVERSION RATE (Hz)
floating, there is a t delay of approximately 2MΩ x C ,
RC
L
where C is the capacitive loading on the SHDN pin.
L
Figure 14b. MAX149 Supply Current vs. Conversion Rate,
FASTPD
Pulling SHDN high sets internal clock frequency to
225kHz. This feature eases the settling-time requirement
for the reference voltage. With an external reference, the
MAX148/MAX149 can be considered fully powered up
within 2µs of actively pulling SHDN high.
TYPICAL REFERENCE-BUFFER POWER-UP
DELAY vs. TIME IN SHUTDOWN
P o w e r-Do w n S e q u e n c in g
The MAX148/MAX149 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. Figures 13, 14a, and 14b show
the average supply current as a function of the sam-
pling rate. The following discussion illustrates the vari-
ous power-down sequences.
2.0
1.5
1.0
Lowest Power at up to 500
Conversions/Channel/Second
The following examples show two different power-down
sequences. Other combinations of clock rates, compen-
sation modes, and power-down modes may give lowest
power consumption in other applications.
0.5
0
0.001
0.01
0.1
1
10
Figure 14a depicts the MAX149 power consumption for
one or eight channel conversions utilizing full power-
down mode and internal-reference compensation. A
0.01µF bypass capacitor at REFADJ forms an RC filter
with the internal 20kΩ reference resistor with a 0.2ms
time constant. To achieve full 10-bit accuracy, 8 time
c ons ta nts or 1.6ms a re re q uire d a fte r p owe r-up .
Waiting this 1.6ms in FASTPD mode instead of in full
power-up can reduce power consumption by a factor
of 10 or more. This is achieved by using the sequence
shown in Figure 15.
TIME IN SHUTDOWN (sec)
Figure 14c. Typical Reference-Buffer Power-Up Delay vs. Time
in Shutdown
Software Power-Down
Software power-down is activated using bits PD1 and PD0
of the control byte. As shown in Table 5, PD1 and PD0
also specify the clock mode. When software shutdown is
asserted, the ADC operates in the last specified clock
mode until the conversion is complete. Then the ADC
powers down into a low quiescent-current state. In internal
clock mode, the interface remains active and conversion
______________________________________________________________________________________ 17
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
COMPLETE CONVERSION SEQUENCE
1.6ms WAIT
0 1
(ZEROS)
CH1
CH7
(ZEROS)
DIN
1
0 0
FULLPD
1.21V
1
1
1 1
1
0 0
FULLPD
1
0 1
FASTPD
FASTPD
NOPD
REFADJ
VREF
0V
2.50V
0V
τ = RC = 20kΩ x C
REFADJ
t
≈ 75µs
BUFFEN
Figure 15. MAX149 FULLPD/FASTPD Power-Up Sequence
8/MAX149
+3.3V
24k
OUTPUT CODE
FULL-SCALE
TRANSITION
MAX149
11 . . . 111
11 . . . 110
510k
100k
REFADJ
12
11 . . . 101
0.01µF
FS = VREF + COM
ZS = COM
Figure 16. MAX149 Reference-Adjust Circuit
VREF
1024
1LSB =
00 . . . 011
00 . . . 010
Lowest Power at Higher Throughputs
Fig ure 14b s hows the p owe r c ons ump tion with
external-reference compensation in fast power-down,
with one and eight channels converted. The external
4.7µF c omp e ns a tion re q uire s a 75µs wa it a fte r
p owe r-up with one d ummy c onve rs ion. This g ra p h
shows fast multi-channel conversion with the lowest
power consumption possible. Full power-down mode
may provide increased power savings in applications
where the MAX148/MAX149 are inactive for long peri-
ods of time, but where intermittent bursts of high-speed
conversions are required.
00 . . . 001
00 . . . 000
0
1
2
3
FS
(COM)
FS - 3/2LSB
INPUT VOLTAGE (LSB)
Figure 17. Unipolar Transfer Function, Full Scale (FS) = VREF
+ COM, Zero Scale (ZS) = COM
Internal Reference (MAX149)
The MAX149’s full-scale range with the internal refer-
ence is 2.5V with unipolar inputs and ±1.25V with bipo-
lar inputs. The internal reference voltage is adjustable
to ±1.5% with the circuit in Figure 16.
In t e rn a l a n d Ex t e rn a l Re fe re n c e s
The MAX149 can be used with an internal or external
reference voltage, whereas an external reference is
required for the MAX148. An external reference can be
connected directly at VREF or at the REFADJ pin.
External Reference
With both the MAX149 and MAX148, an external refer-
ence can be placed at either the input (REFADJ) or the
output (VREF) of the internal reference-buffer amplifier.
The REFADJ input impedance is typically 20kΩ for the
MAX149, and higher than 100kΩ for the MAX148. At
An inte rna l b uffe r is d e s ig ne d to p rovid e 2.5V a t
VREF for b oth the MAX149 a nd the MAX148. The
MAX149’s internally trimmed 1.21V reference is buf-
fered with a 2.06 gain. The MAX148’s REFADJ pin is
also buffered with a 2.00 gain to scale an external 1.25V
reference at REFADJ to 2.5V at VREF.
18 ______________________________________________________________________________________
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
8/MAX149
Table 7. Full Scale and Zero Scale
UNIPOLAR MODE
BIPOLAR MODE
Positive
Zero
Negative
Full Scale
Full Scale
Zero Scale
COM
Full Scale
Scale
VREF / 2
+ COM
-VREF / 2
+ COM
VREF + COM
COM
OUTPUT CODE
VREF
2
FS
=
+ COM
+ COM
SUPPLIES
011 . . . 111
011 . . . 110
ZS = COM
+3V
+3V
GND
-VREF
2
-FS =
000 . . . 010
000 . . . 001
000 . . . 000
VREF
1024
1LSB =
R* = 10Ω
111 . . . 111
111 . . . 110
111 . . . 101
V
DD
AGND
COM DGND
+3V DGND
DIGITAL
CIRCUITRY
100 . . . 001
100 . . . 000
MAX148
MAX149
COM*
INPUT VOLTAGE (LSB)
- FS
+FS - 1LSB
*OPTIONAL
≤
*COM VREF / 2
Figure 18. Bipolar Transfer Function, Full Scale (FS) =
VREF / 2 + COM, Zero Scale (ZS) = COM
Figure 19. Power-Supply Grounding Connection
VREF, the DC input resistance is a minimum of 18kΩ.
During conversion, an external reference at VREF must
deliver up to 350µA DC load current and have 10Ω or
less output impedance. If the reference has a higher
output impedance or is noisy, bypass it close to the
VREF pin with a 4.7µF capacitor.
Tra n s fe r Fu n c t io n
Table 7 shows the full-scale voltage ranges for unipolar
and bipolar modes.
The external reference must have a temperature coeffi-
cient of 20ppm/°C or less to achieve accuracy to within
1LSB over the 0°C to +70°C commercial temperature
range.
Using the REFADJ input makes buffering the external
reference unnecessary. To use the direct VREF input,
Figure 17 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 18 shows the bipolar
input/output transfer function. Code transitions occur
ha lfwa y b e twe e n s uc c e s s ive -inte g e r LSB va lue s .
Output coding is binary, with 1LSB = 2.44mV (2.500V /
1024) for unip ola r op e ra tion, a nd 1LSB = 2.44mV
[(2.500V / 2 - -2.500V / 2) / 1024] for bipolar operation.
disable the internal buffer by tying REFADJ to V . In
DD
power-down, the input bias current to REFADJ is typi-
cally 25µA (MAX149) with REFADJ tied to V . Pull
DD
REFADJ to AGND to minimize the input bias current in
power-down.
______________________________________________________________________________________ 19
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
+3V
+3V
0.1µF
1µF
(POWER SUPPLIES)
1
2
20
19
18
17
16
15
14
13
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SHDN
V
DD
SCK
SCLK
CS
PCS0
3
4
MOSI
MC683XX
ANALOG
INPUTS
DIN
MAX148
MAX149
5
6
SSTRB
DOUT
DGND
AGND
MISO
7
8/MAX149
8
9
REFADJ 12
11
(GND)
10
VREF
0.1µF
+2.5V
Figure 20. MAX148/MAX149 QSPI Connections, External Reference
La yo u t , Gro u n d in g , a n d Byp a s s in g
For b e s t p e rforma nc e , us e p rinte d c irc uit b oa rd s .
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
XF
CLKX
CLKR
DX
CS
SCLK
Figure 19 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at AGND, separate from the logic
ground. Connect all other analog grounds and DGND
to the star ground. No other digital system ground
should be connected to this ground. For lowest-noise
operation, the ground return to the star ground’s power
s up p ly s hould b e low imp e d a nc e a nd a s s hort a s
possible.
TMS320LC3x
MAX148
MAX149
DIN
DR
DOUT
SSTRB
FSR
High-frequency noise in the V
power supply may
DD
affect the high-speed comparator in the ADC. Bypass
the s up p ly to the s ta r g round with 0.1µF a nd 1µF
capacitors close to pin 20 of the MAX148/MAX149.
Minimize capacitor lead lengths for best supply-noise
rejection. If the power supply is very noisy, a 10Ω resis-
tor can be connected as a lowpass filter (Figure 19).
Figure 21. MAX148/MAX149-to-TMS320 Serial Interface
20 ______________________________________________________________________________________
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
8/MAX149
CS
SCLK
DIN
START
SEL2
SEL1
SEL0
UNI/BIP SGL/DIF
PD1
PD0
HIGH
IMPEDANCE
SSTRB
HIGH
IMPEDANCE
DOUT
MSB
B8
S1
S0
Figure 22. TMS320 Serial-Interface Timing Diagram
Hig h -S p e e d Dig it a l In t e rfa c in g w it h QS P I
The MAX148/MAX149 can interface with QSPI using
2) The MAX148/MAX149’s CS pin is driven low by the
TMS320’s XF_ I/O port to enable data to be clocked
into the MAX148/MAX149’s DIN.
the circuit in Figure 20 (f
= 2.0MHz, CPOL = 0,
SCLK
CPHA = 0). This QSPI circuit can be programmed to do a
conversion on each of the eight channels. The result is
stored in memory without taxing the CPU, since QSPI
incorporates its own microsequencer.
3) An 8-bit word (1XXXXX11) should be written to the
MAX148/MAX149 to initiate a conversion and place
the device into external clock mode. Refer to Table
1 to select the proper XXXXX bit values for your
specific application.
The MAX148/MAX149 are QSPI compatible up to the
maximum external clock frequency of 2MHz.
4) The MAX148/MAX149’s SSTRB output is monitored
via the TMS320’s FSR input. A falling edge on the
SSTRB output indicates that the conversion is in
progress and data is ready to be received from the
MAX148/MAX149.
TMS 3 2 0 LC3 x In t e rfa c e
Figure 21 shows an application circuit to interface the
MAX148/MAX149 to the TMS320 in external clock mode.
The timing diagram for this interface circuit is shown in
Figure 22.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits rep-
resent the 10 + 2-bit conversion result followed by
4 trailing bits, which should be ignored.
Use the following steps to initiate a conversion in the
MAX148/MAX149 and to read the results:
1) The TMS320 s hould b e c onfig ure d with CLKX
(transmit clock) as an active-high output clock and
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR on the TMS320 are
tied together with the MAX148/MAX149’s SCLK
input.
6) Pull CS high to disable the MAX148/MAX149 until
the next conversion is initiated.
______________________________________________________________________________________ 21
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
Ord e rin g In fo rm a t io n (c o n t in u e d )
__________________P in Co n fig u ra t io n
INL
(LSB)
PART†
TEMP. RANGE
PIN-PACKAGE
TOP VIEW
MAX148AEPP -40°C to +85°C
MAX148BEPP -40°C to +85°C
MAX148AEAP -40°C to +85°C
MAX148BEAP -40°C to +85°C
20 Plastic DIP
20 Plastic DIP
20 SSOP
±1/2
±1
CH0
CH1
1
2
V
DD
20
19 SCLK
±1/2
±1
3
CS
CH2
18
17
20 SSOP
MAX148
MAX149
CH3
4
DIN
MAX148AMJP -55°C to +125°C 20 CERDIP*
MAX148BMJP -55°C to +125°C 20 CERDIP*
±1/2
±1
5
CH4
16 SSTRB
15 DOUT
CH5
6
MAX149ACPP
MAX149BCPP
MAX149ACAP
MAX149BCAP
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
20 Plastic DIP
20 Plastic DIP
20 SSOP
±1/2
±1
CH6
14
13
12
11
DGND
7
±1/2
±1
8
CH7
AGND
20 SSOP
REFADJ
9
COM
SHDN
8/MAX149
MAX149AEPP -40°C to +85°C
MAX149BEPP -40°C to +85°C
MAX149AEAP -40°C to +85°C
MAX149BEAP -40°C to +85°C
20 Plastic DIP
20 Plastic DIP
20 SSOP
±1/2
±1
VREF
10
±1/2
±1
DIP/SSOP
20 SSOP
MAX149AMJP -55°C to +125°C 20 CERDIP*
MAX149BMJP -55°C to +125°C 20 CERDIP*
±1/2
±1
†
Contact factory for availability of alternate surface-mount
packages.
* Contact factory for availability of CERDIP package, and for
processing to MIL-STD-883B.
___________________Ch ip In fo rm a t io n
TRANSISTOR COUNT: 2554
22 ______________________________________________________________________________________
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
8/MAX149
________________________________________________________P a c k a g e In fo rm a t io n
______________________________________________________________________________________ 23
+2 .7 V to +5.25V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
___________________________________________P a c k a g e In fo rm a t io n (c o n t in u e d )
8/MAX149
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1998 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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