MAX1490EACPG [MAXIM]
15kV ESD-Protected, Isolated RS-485/RS-422; 15kV ESD保护，隔离型RS - 485 / RS - 422
| 型号： | MAX1490EACPG |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 15kV ESD-Protected, Isolated RS-485/RS-422 |
| 文件： | 总19页 (文件大小：1664K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1940; Rev 0; 4/01
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
_________________General Description
____________________________Features
ꢀ Isolated Data Interface, Guaranteed to 1260V
The MAX1480EA/MAX1480EC/MAX1490EA/MAX1490EB
are complete, electrically isolated, RS-485/RS-422 data
communications interface solutions in a hybrid microcir-
cuit. The RS-485/RS-422 I/O pins are protected against
15ꢀk electrostatic discharge ꢁESꢂD shocꢀs, ꢃithout
latchup. Transceivers, optocouplers, and a transformer
provide a complete interface in a standard ꢂIP pacꢀage.
A single +5k supply on the logic side poꢃers both sides
of the interface.
RMS
(1min)
ꢀ
15kV ESD Protection on I/O Pins
ꢀ Slew-Rate Limited for Errorless Data
Transmission (MAX1480EC/MAX1490EB)
ꢀ High-Speed, Isolated, 2.5Mbps RS-485/RS-422
Interface (MAX1480EA/MAX1490EA)
ꢀ Full-Duplex Data Communication
(MAX1490EA/MAX1490EB)
The MAX1480EC/MAX1490EB feature reduced-sleꢃ-rate
drivers that minimize EMI and reduce reflections caused
by improperly terminated cables, alloꢃing error-free data
transmission at data rates up to 160ꢀbps. The
MAX1480EA/MAX1490EA driver sleꢃ rate is not limited,
alloꢃing transmission rates up to 2.5Mbps. The
MAX1480EA/MAX1480EC are designed for half-duplex
communication, ꢃhile the MAX1490EA/MAX1490EB fea-
ture full-duplex communication.
ꢀ Single +5V Supply
ꢀ Current Limiting and Thermal Shutdown for
Driver Overload Protection
ꢀ Standard 0.6in DIP Packages
28-Pin DIP (MAX1480EA/MAX1480EC)
24-Pin DIP (MAX1490EA/MAX1490EB)
_______________Ordering Information
ꢂrivers are short-circuit current limited and protected
against excessive poꢃer dissipation by thermal shut-
doꢃn circuitry that places the driver outputs into a high-
impedance state. The receiver input has a fail-safe
feature that guarantees a ꢀnoꢃn output ꢁRO loꢃ for the
MAX1480EA/MAX1480EC, RO high for the MAX1490EA/
MAX1490EBD if the input is open circuit.
†
PART
TEMP. RANGE
PIN-PACKAGE
MAX1480EACPI
MAX1480EAEPI
0°C to +70°C
28 Wide Plastic ꢂIP*
28 Wide Plastic ꢂIP*
-40°C to +85°C
Ordering Information continued at end of data sheet.
†
Data rate for A parts is up to 2.5Mbps. Data rate for C parts is
up to 250kbps.
The MAX1480EA/MAX1480EC/MAX1490EA/MAX1490EB
*See Reliability section at end of data sheet.
ꢃithstand 1260k
ꢁ1minD or 1520k
ꢁ1sD. Their iso-
RMS
RMS
lated outputs meet all RS-485/RS-422 specifications. The
MAX1480EA/MAX1480EC are available in a 28-pin ꢂIP
pacꢀage, and the MAX1490EA/MAX1490EB are available
in a 24-pin ꢂIP pacꢀage.
-in Configurations
TOP VIEW
V
.
CC1
CC2
1
2
3
4
5
AC1
24
MAX1490EA/
MAX1490EB
V
23 AC2
________________________Applications
Isolated RS-485/RS-422 ꢂata Interface
Transceivers for EMI-Sensitive Applications
Industrial-Control Local Area Netꢃorꢀs
Automatic Test Equipment
22
21
20
19
18
17
D1
D2
ISO V
CC1
ISO RO DRV
GND1
FS
A
B
Z
Y
6
HkAC/Building Control Netꢃorꢀs
Telecom
SD
7
8
V
V
CC3
DI
9
16 ISO COM1
ISO DI DRV
10
11
12
15
14
CC4
RO
ISO V
CC2
GND2
13 ISO RO LED
ISOLATION BARRIER
DIP
Pin Configurations continued at end of data sheet.
Selector Guide appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
ABSOLUTE MAXIMUM RATINGS
With Respect to GNꢂ_
Supply koltage ꢁk
LEꢂ Forꢃard Current ꢁꢂI, ꢂE, ISO RO LEꢂD ......................50mA
D..........................................-0.3k to +6k
Continuous Poꢃer ꢂissipation ꢁT = +70°CD
CC_
A
Control Input koltage ꢁSꢂ, FSD..............-0.3k to ꢁk
Receiver Output koltage ꢁRO, ROD.......-0.3k to ꢁk
Output Sꢃitch koltage ꢁꢂ1, ꢂ2D.......................................+12k
With Respect to ISO COM_
+ 0.3kD
+ 0.3kD
24-Pin Plastic ꢂIP ꢁderate 8.7mW°C above +70°CD ....696mW
28-Pin Plastic ꢂIP ꢁderate 9.09mW/°C above +70°CD .727mW
Operating Temperature Ranges
MAX1480E_CPI/MAX1490E_CPI ........................0°C to +70°C
MAX1480E_EPI/MAX1490E_EPI......................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature ꢁsoldering, 10sD .................................+300°C
CC_
CC_
Control Input koltage ꢁISO ꢂE_D....-0.3k to ꢁISO k
ꢂriver Input koltage ꢁISO ꢂI_D .......-0.3k to ꢁISO k
+ 0.3kD
+ 0.3kD
+ 0.3kD
CC_
CC_
Receiver Output koltage ꢁISO RO_D ..-0.3k to ꢁISO k
CC_
ꢂriver Output koltage ꢁA, B, Y, ZD ......................-8k to +12.5k
Receiver Input koltage ꢁA, BD.............................-8k to +12.5k
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
ꢁk
= +5k 10ꢄ, k = k
, T = T
to T
, unless otherꢃise noted. Typical values are at k = +5k and T = +25°C.D
CC_ A
CC_
FS
CC_
A
MIN
MAX
ꢁNotes 1, 2D
PARAMETER
SYMBOL
CONDITIONS
or open
MIN
TYP
MAX UNITS
f
k
= 0
535
725
85
145
55
120
130
180
65
SWL
FS
Sꢃitch Frequency
ꢀHz
f
FS = k
CC_
SWH
R = ∞
120
MAX1480EA,
ꢂE´ = k or open
L
R = 54Ω
CC_
L
R = ∞
120
MAX1480EC,
ꢂE´ = k or open
L
R = 54Ω
CC_
L
Operating Supply Current
I
mA
CC
R = ∞
180
L
MAX1490EA
MAX1490EB
R = 54Ω
L
R = ∞
125
L
R = 54Ω
L
130
Shutdoꢃn Supply Current
ꢁNote 3D
I
Sꢂ = k
0.2
µA
SHꢂN
CC_
k
k
High
Loꢃ
2.4
2.4
SꢂH
Shutdoꢃn Input Threshold
k
0.8
SꢂL
Shutdoꢃn Input Leaꢀage
Current
10
pA
k
k
High
Loꢃ
FSH
FS Input Threshold
k
0.8
FSL
FS Input Pullup Current
FS Input Leaꢀage Current
Input High koltage
FS loꢃ
50
µA
pA
k
FS high
10
k
k
CC
- 0.4
ꢂE´, ꢂI´, Figures 1 and 2
ꢂE´, ꢂI´, Figures 1 and 2
IH
Input Loꢃ koltage
k
0.4
k
IL
Isolation koltage
k
R
T
A
T
A
T
A
= +25°C, 1min ꢁNote 4D
1260
100
k
RMS
ISO
ISO
Isolation Resistance
Isolation Capacitance
= +25°C, k
= 50kꢂC
10,000
10
MΩ
pF
ISO
C
= +25°C, f = 1MHz
ISO
ꢂifferential ꢂriver Output
ꢁNo LoadD
k
8
5
k
Oꢂ1
R = 50Ω ꢁRS-422D
R = 27Ω ꢁRS-485D, Figure 4
2
1.5
ꢂifferential ꢂriver Output
ꢁꢃith LoadD
k
Oꢂ2
k
2
_______________________________________________________________________________________
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
ELECTRICAL CHARACTERISTICS (continued)
ꢁk
= +5k 10ꢄ, k = k
, T = T
A
to T
, unless otherꢃise noted. Typical values are at k
= +5k and T = +25°C.D
CC_ A
CC_
FS
CC_
MIN
MAX
ꢁNotes 1, 2D
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Change in Magnitude of
ꢂriver Output koltage for
Complementary Output States
ꢂifferential
0.3
k
0.3
∆k
R = 27Ω or 50Ω, Figure 4
R = 27Ω or 50Ω, Figure 4
Oꢂ
Common mode
ꢂriver Common-Mode Output
k
OC
4
k
MAX1490EA/
MAX1490EB
1.0
k
= +12k
= -7k
IN
MAX1480EA/
MAX1480EC
0.25
0.8
ꢂE´ = 0,
= 0 or +5.5k
Input Current ꢁA, BD
ISO I
mA
IN
k
CC_
MAX1490EA/
MAX1490EB
k
IN
MAX1480EA/
MAX1480EC
0.2
ꢁMAX1480E_D
ꢁMAX1490E_D
48
12
Receiver Input Resistance
R
-7k ≤ k
-7k ≤ k
≤ +12k
≤ +12k
ꢀΩ
IN
CM
Receiver ꢂifferential Threshold
Receiver Input Hysteresis
k
TH
-0.2
0.2
k
CM
∆k
k
CM
= 0
70
mk
k
TH
Receiver Output Loꢃ koltage
Receiver Output High Current
ꢂriver Short-Circuit Current
k
OL
Using resistor values listed in Tables 1 and 2
= 5.5k
0.4
I
k
OUT
250
µA
mA
OH
ISO I
-7k ≤ k ≤ 12k ꢁNote 5D
100
15
OSꢂ
O
A, B, Y, and Z pins, tested using Human Body
Model, Figures 1 and 2
ESꢂ Protection
ISO I
ꢀk
OSꢂ
SWITCHING CHARACTERISTICS—MAX1480EA/MAX1490EA
ꢁk
= +5k 10ꢄ, k = k
, T = T
A
to T
, unless otherꢃise noted. Typical values are at k = +5k and T = +25°C.D
MAX CC_ A
CC_
FS
CC_
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
90
MAX UNITS
t
t
275
ns
PLH
PHL
ꢂriver Input to Output
Propagation ꢂelay
Figures 5 and 7, R
= 54Ω,
ꢂIFF
C
L1
= C = 100pF
L2
60
275
ꢂriver Output Sꢀeꢃ
t
Figures 5 and 7, R
Figures 5 and 7, R
= 54Ω, C = C = 100pF
30
100
50
ns
ns
SKEW
ꢂIFF
L1
L2
ꢂriver Rise or Fall Time
t
t
= 54Ω, C = C = 100pF
15
R, F
ꢂIFF
L1
L2
ꢂriver Enable to Output High
ꢁMAX1480EA OnlyD
t
Figures 6 and 8, C = 100pF, S2 closed
1.0
1.0
0.5
0.5
1.8
1.8
1.8
1.8
µs
µs
µs
µs
ns
ZH
L
ꢂriver Enable to Output Loꢃ
ꢁMAX1480EA OnlyD
t
Figures 6 and 8, C = 100pF, S1 closed
L
ZL
LZ
HZ
ꢂriver ꢂisable Time from Loꢃ
ꢁMAX1480EA OnlyD
t
Figures 6 and 8, C = 15pF, S1 closed
L
ꢂriver ꢂisable Time from High
ꢁMAX1480EA OnlyD
t
Figures 6 and 8, C = 15pF, S2 closed
L
t
120
90
225
225
PLH
Receiver Input to Output
Propagation ꢂelay
Figures 5 and 10, R
= 54Ω, C = C = 100pF
L1 L2
ꢂIFF
t
PHL
_______________________________________________________________________________________
3
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
SWITCHING CHARACTERISTICS—MAX1480EA/MAX1490EA (continued)
ꢁk
= +5k 10ꢄ, k = k
, T = T
A
to T
, unless otherꢃise noted. Typical values are at k = +5k and T = +25°C.D
MAX CC_ A
CC_
FS
CC_
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
|t
- t
| ꢂifferential
PLH PHL
t
Figures 5 and 10, R
= 54Ω, C = C = 100pF
30
150
ns
SKꢂ
MAX
ꢂIFF
L1
L2
Receiver Sꢀeꢃ
Maximum ꢂata Rate
Time to Shutdoꢃn
Shutdoꢃn to ꢂriver Output High
Shutdoꢃn to ꢂriver Output Loꢃ
f
t
, t
, t
≤ 25ꢄ of data period
2.5
Mbps
µs
µs
SKEW SKꢂ PHL
t
100
3
3
SHꢂN
t
t
Figures 6 and 9, C = 100pF, S2 closed
15
15
ZHꢁSHꢂND
ZHꢁSHꢂND
L
Figures 6 and 9, C = 100pF, S1 closed
µs
L
SWITCHING CHARACTERISTICS—MAX1480EC/MAX1490EB
ꢁk
= +5k 10ꢄ, k = k
, T = T
A
to T
, unless otherꢃise noted. Typical values are at k = +5k and T = +25°C.D
MAX CC_ A
CC_
FS
CC_
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
1.4
1.1
MAX UNITS
t
t
Figures 5 and 7, R
= 54Ω, C = C = 100pF
3.0
3.0
ꢂriver Input to Output
Propagation ꢂelay
PLH
ꢂIFF
ꢂIFF
ꢂIFF
ꢂIFF
L1
L2
µs
Figures 5 and 7, R
Figures 5 and 7, R
Figures 5 and 7, R
= 54Ω, C = C = 100pF
= 54Ω, C = C = 100pF
= 54Ω, C = C = 100pF
L1 L2
PHL
L1
L2
ꢂriver Output Sꢀeꢃ
t
300
1.0
1200
2.0
ns
µs
SKEW
L1
L2
ꢂriver Rise or Fall Time
t
t
R, F
ꢂriver Enable to Output High
ꢁMAX1480EC OnlyD
t
Figures 6 and 8, C = 100pF, S2 closed
1.4
1.4
2.0
1.7
4.5
4.5
4.5
4.5
µs
µs
µs
µs
µs
ns
ZH
L
ꢂriver Enable to Output Loꢃ
ꢁMAX1480EC OnlyD
t
Figures 6 and 8, C = 100pF, S1 closed
L
ZL
LZ
HZ
ꢂriver ꢂisable Time from Loꢃ
ꢁMAX1480EC OnlyD
t
Figures 6 and 8, C = 15pF, S1 closed
L
ꢂriver ꢂisable Time from High
ꢁMAX1480EC OnlyD
t
Figures 6 and 8, C = 15pF, S2 closed
L
t
0.9
1.1
3.0
3.0
Receiver Input to Output
Propagation ꢂelay
PLH
Figures 5 and 10, R
Figures 5 and 10, R
= 54Ω, C = C = 100pF
L1 L2
ꢂIFF
t
PHL
|t
- t
| ꢂifferential
PLH PHL
t
= 54Ω, C = C = 100pF
200
SKꢂ
ꢂIFF
L1
L2
Receiver Sꢀeꢃ
Maximum ꢂata Rate
f
t
, t
≤ 25ꢄ of data period
160
ꢀbps
µs
MAX
SKEW SKꢂ
Time to Shutdoꢃn
t
100
3
SHꢂN
Shutdoꢃn to ꢂriver Output High
Shutdoꢃn to ꢂriver Output Loꢃ
t
Figures 6 and 9, C = 100pF, S2 closed
15
15
µs
ZHꢁSHꢂND
L
t
Figures 6 and 9, C = 100pF, S1 closed
3
µs
ZLꢁSHꢂND
L
Note 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to logic-
side ground ꢁGNꢂ_D, unless otherꢃise specified.
Note 2: For ꢂE´ and ꢂI´ pin descriptions, see Detailed Block Diagram and Typical Application Circuit ꢁFigure 1 for MAX1480EA/
MAX1480EC, Figure 2 for MAX1490EA/MAX1490EBD.
Note 3: Shutdoꢃn supply current is the current at k
and k
ꢃhen shutdoꢃn is enabled.
CC1
CC2
Note 4: Limit guaranteed by applying 1520k
for 1s. Test voltage is applied betꢃeen all pins on one side of the pacꢀage to all
RMS
pins on the other side of the pacꢀage, e.g., betꢃeen pins 1–14 and pins 15–28 on the 28-pin pacꢀage.
Note 5: Applies to peaꢀ current ꢁsee Typical Operating CharacteristicsD. Although the MAX1480EA/MAX1480EC and
MAX1490EA/MAX1490EB provide electrical isolation betꢃeen logic ground and signal paths, they do not provide isolation
betꢃeen external shields and the signal paths ꢁsee Isolated Common Connection sectionD.
4
_______________________________________________________________________________________
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
__________________________________________Typical Operating Characteristics
ꢁk
= +5k, k = k
, Figures 1 and 2, T = +25°C, unless otherꢃise noted.D
CC_
A
CC_
FS
RECEIVER OUTPUT HIGH VOLTAGE
vs. TEMPERATURE
OUTPUT CURRENT vs.
RECEIVER OUTPUT LOW VOLTAGE
OUTPUT CURRENT vs.
RECEIVER OUTPUT HIGH VOLTAGE
-30
-25
5.00
4.75
4.50
4.25
4.00
3.75
3.50
80
MEASURED AT ISO RO DRV
MEASURED AT ISO RO DRV
MEASURED AT ISO RO DRV
I
= 8mA
RO
70
60
50
40
30
20
-20
-15
-10
-5
0
3.25
3.00
10
0
-40
-20
0
20
40
60
80
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT LOW VOLTAGE (V)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT HIGH VOLTAGE (V)
TEMPERATURE (°C)
RECEIVER OUTPUT LOW VOLTAGE
vs. TEMPERATURE
OUTPUT CURRENT vs.
DRIVER OUTPUT LOW VOLTAGE
OUTPUT CURRENT vs.
DRIVER OUTPUT HIGH VOLTAGE
180
160
140
120
100
80
0.8
0.7
0.6
0.5
0.4
0.3
0.2
-100
-90
MEASURED AT ISO RO DRV
I
RO
= 8mA
-80
-70
-60
-50
-40
-30
-20
60
40
20
0
0.1
0
-10
0
-40
-20
0
20
40
60
80
0
1
2
3
4
5
6
7
8
9
10 11 12
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
TEMPERATURE (°C)
OUTPUT LOW VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
SHUTDOWN CURRENT
vs. TEMPERATURE
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs. TEMPERATURE
DRIVER OUTPUT CURRENT
vs. DIFFERENTIAL OUTPUT VOLTAGE
3.0
2.9
0.40
0.35
0.30
0.25
0.20
0.15
0.10
80
70
60
50
40
30
20
SD = V , DI´ = V
DI´ = HIGH OR OPEN
CC_
CC_
DI´ = HIGH OR OPEN
R = 54Ω
L
DE´= V (MAX1480EC ONLY)
CC_
MEASURED AT V AND V
2.8
2.7
2.6
CC1
CC2
2.5
2.4
2.3
2.2
0.05
0
10
0
2.1
2.0
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DIFFERENTIAL OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
____________________________Typical Operating Characteristics (continued)
ꢁk
= +5k, k = k
, Figures 1 and 2, T = +25°C, unless otherꢃise noted.D
CC_
A
CC_
FS
MAX1480EA
SUPPLY CURRENT vs. TEMPERATURE
MAX1480EC
SUPPLY CURRENT vs. TEMPERATURE
MAX1490EA
SUPPLY CURRENT vs. TEMPERATURE
160
140
120
110
100
90
200
180
160
R = 54Ω
L
V
= +5.5V
= +5V
R = 54Ω
CC
R = 54Ω
L
L
V
= +5.5V
= +5V
V
= +5.5V
CC
CC
V
V
CC
CC
V
= +5V
CC
120
100
80
V
= +4.5V
CC
V
= +4.5V
CC
V
= +4.5V
CC
80
DE´ = V
CC
DE´ = V
CC
R = ∞
L
70
140
120
100
80
60
V
= +5.5V
CC
60
R = ∞
L
V
= +5.5V
V
= +5V
CC
CC
R = ∞
L
50
V
= +5V
40
CC
V
= +5V
V
= +5.5V
CC
CC
40
30
20
V
CC
= +4.5V
20
0
V
= +4.5V
80
V
= +4.5V
CC
60
CC
-40
-20
0
20
40
60
80
-40
-20
0
20
40
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX1490EB
SUPPLY CURRENT vs. TEMPERATURE
150
140
130
120
110
100
90
V
= +5.5V
CC
V
= +5V
CC
V
= +4.5V
CC
R = 54Ω
L
V
= +5.5V
CC
80
V
= +5V
CC
R = ∞
L
70
60
50
V
= +4.5V
CC
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
MAX1480EA/MAX1490EA
MAX1480EA/MAX1490EA
RECEIVER t
RECEIVER t
PLH
PHL
MAX1480E/90E toc15
MAX1480E/90E toc14
RECEIVER
INPUT B
1V/div
RECEIVER
INPUT A
1V/div
RECEIVER
INPUT A
1V/div
RECEIVER
INPUT B
1V/div
RO
RO
2V/div
2V/div
20ns/div
20ns/div
V
= 5.0V, DE´= V
CC_
V
= 5.0V, DE´= V
CC_
CC_
CC_
6
_______________________________________________________________________________________
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
_____________________________Typical Operating Characteristics (continued)
ꢁk
= +5k, k = k
, k = 0, ꢂE´ toggled 0 to 5k at 5ꢀHz, Figures 1 and 2, T = +25°C, unless otherꢃise noted.D
CC_
FS
CC_ ꢂI´
A
MAX1480EC/MAX1490EB
MAX1480EC/MAX1490EB
RECEIVER t
PHL
RECEIVER t
PLH
MAX1480E/90E toc16
MAX1480E/90E toc17
RECEIVER
INPUT A
1V/div
RECEIVER
INPUT A
1V/div
RECEIVER
INPUT B
1V/div
RECEIVER
INPUT B
1V/div
RO
RO
2V/div
2V/div
200ns/div
500ns/div
´
´
MAX1480EC
DRIVER ENABLE TIME
MAX1480EC
DRIVER DISABLE TIME
DRIVER
OUTPUT B
2V/div
DRIVER
OUTPUT B
2V/div
DE´
2V/div
DE´
2V/div
500ns/div
500ns/div
V
= 5.0V, DI´= 0V
V
= 5.0V, DI´ = 0V
CC
MAX1480EA/MAX1490EA
POWER-UP DELAY TO DRIVER OUTPUTS VALID
DRIVER
OUTPUT B
(Z FOR MAX1490)
2V/div
SD
2V/div
1µs/div
V
V
= 0
DI´
= 5V TO 0 AT 1kHz
SD
_______________________________________________________________________________________
7
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
________________________________________________________________-in Description
PIN
NAME
FUNCTION
MAX1480EA/
MAX1480EC
MAX1490EA/
MAX1490EB
1, 2, 8, 10
1, 2, 8, 10
k
–k
Logic-Side ꢁNonisolated SideD +5k Supply koltages
Internal Connections. Leave these pins unconnected.
Logic-Side Ground. Connect to GNꢂ2 ꢁpin 12D.
CC1 CC4
3, 4
5
3, 4
5
ꢂ1, ꢂ2
GNꢂ1
Frequency Select Input. If FS = k
or is open, sꢃitch frequency is high; if FS
CC_
6
7
6
7
FS
= GNꢂ, sꢃitch frequency is loꢃ. For optimal performance and minimal supply
current, connect FS to k or leave unconnected.
CC_
Shutdoꢃn Input. Ground for normal operation. When high, the poꢃer oscillator is
disabled.
Sꢂ
ꢂriver Input. With ꢂE´ high ꢁMAX1480EA/MAX1480EC onlyD, a loꢃ on ꢂI´ forces
output A loꢃ and output B high. Similarly, a high on ꢂI´ forces output A high and
output B loꢃ. ꢂrives internal LEꢂ cathode through a resistor ꢁsee Table 1 for
MAX1480EA/MAX1480EC, Table 2 for MAX1490EA/MAX1490EBD.
9
9
ꢂI
ꢂriver-Enable Input. The driver outputs, A and B, are enabled by bringing ꢂE´
high. The driver outputs are high impedance ꢃhen ꢂE´ is loꢃ. If the driver out-
puts are enabled, the device functions as a line driver. While the driver outputs
are high impedance, the device functions as a line receiver. ꢂrives internal
LEꢂ cathode through a resistor ꢁTable 1D.
11
—
ꢂE
Receiver Output. If A > B by 200mk, RO is high; if A < B by 200mk, RO is loꢃ.
—
12
13
11
12
—
RO
Open collector; must have pullup to k
ꢁTable 2D.
CC
GNꢂ2
Logic-Side Ground. Connect to GNꢂ1 ꢁpin 5D.
Receiver Output. If A > B by 200mk, RO is loꢃ; if A < B by 200mk, RO is high.
RO
Open collector; must have pullup to k
ꢁTable 1D.
CC
14
—
k
CC5
Logic-Side ꢁNonisolated SideD +5k Supply koltage
Isolated Receiver Output LEꢂ. Internal LEꢂ anode in MAX1480EA/MAX1480EC and
LEꢂ cathode in MAX1490EA/MAX1490EB. Connect to ISO RO ꢂRk through a resis-
tor ꢁTable 1 for MAX1480EA/MAX1480EC; Table 2 for MAX1490EA/MAX1490EBD.
15
16
13
—
ISO RO LEꢂ
ISO COM2
Isolated Common. Connect to ISO COM1 ꢁpin 20D.
Isolated ꢂriver-Enable ꢂrive. The driver outputs, A and B, are enabled by bringing
ꢂE´ high. The driver outputs are high impedance ꢃhen ꢂE´ is loꢃ. If the driver
outputs are enabled, the device functions as a line driver. While the driver outputs
are high impedance, the device functions as a line receiver. Open-collector out-
put; must have pullup to ISO kCC_ and be connected to ISO ꢂE IN for normal
operation ꢁTable 1D.
17
—
ISO ꢂE ꢂRk
Isolated Supply koltage. Connect to ISO k
MAX1480EC, or pin 22 for MAX1490EA/MAX1490EBD.
ꢁpin 26 for MAX1480EA/
CC1
18
19
20
14
15
16
ISO k
CC2
Isolated ꢂriver-Input ꢂrive. With ꢂE´ high ꢁMAX1480EA/MAX1480EC onlyD, a loꢃ on
ꢂI´ forces output A loꢃ and output B high. Similarly, a high on ꢂI´ forces output A
high and output B loꢃ. Connect to ISO ꢂI IN ꢁon the MAX1480EA/MAX1480EC onlyD
for normal operation. Open-collector output; connect a pullup resistor to ISO k
ꢁTable 1 for MAX1480EA/MAX1480EC, Table 2 for MAX1490EA/MAX1490EBD.
ISO ꢂI ꢂRk
ISO COM1
CC_
Isolated Common. For MAX1480EA/MAX1480EC, connect to ISO COM2 ꢁpin
16D ꢁFigures 1 and 2D.
8
_______________________________________________________________________________________
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
___________________________________________________-in Description (continued)
PIN
NAME
FUNCTION
MAX1480EA/
MAX1480EC
MAX1490EA/
MAX1490EB
—
—
—
—
21
22
23
17
18
19
20
—
—
—
Y
Noninverting ꢂriver Output
Inverting ꢂriver Output
Inverting Receiver Input
Noninverting Receiver Input
Isolated ꢂriver-Enable Input. Connect to ISO ꢂE ꢂRk for normal operation.
Isolated ꢂriver Input. Connect to ISO ꢂI ꢂRk for normal operation.
Noninverting ꢂriver Output and Noninverting Receiver Input
Z
B
A
ISO ꢂE IN
ISO ꢂI IN
A
Isolated Receiver-Output ꢂrive. Connect to ISO RO LEꢂ through a resistor ꢁsee
Table 1 for MAX1480EA/MAX1480EC, Table 2 for MAX1490EA/MAX1490EBD.
24
21
ISO RO ꢂRk
25
26
—
22
B
ISO k
Inverting ꢂriver Output and Inverting Receiver Input
Isolated Supply koltage Source
CC1
27, 28
23, 24
AC2, AC1
Internal Connections. Leave these pins unconnected.
Note: For DE´ and DI´ pin descriptions, see Detailed Block Diagram and Typical Application Circuit (Figure 1 for MAX1480EA/
MAX1480EC, Figure 2 for MAX1490EA/MAX1490EB).
ꢂrivers are short-circuit current limited and are protect-
Detailed Description
ed against excessive poꢃer dissipation by thermal
The MAX1480EA/MAX1480EC/MAX1490EA/MAX1490EB
shutdoꢃn circuitry that puts the driver outputs into a
are complete, electrically isolated, RS-485/RS-422 data-
high-impedance state. The receiver input has a fail-safe
communications interface solutions. Transceivers, opto-
feature that guarantees a logic-high RO ꢁlogic-loꢃ ROD
couplers, a poꢃer driver, and a transformer in one
output if the input is open circuit.
standard 28-pin ꢂIP pacꢀage ꢁ24-pin pacꢀage for the
On the MAX1480EA/MAX1480EC, the driver outputs are
enabled by bringing ꢂE´ high. ꢂriver-enable time is typi-
cally 1.0µs. Alloꢃ time for the devices to be
enabled before sending data ꢁsee Typical Operating
CharacteristicsD. When enabled, driver outputs function
as line drivers. ꢂriver outputs are high impedance ꢃhen
ꢂE´ is loꢃ. When outputs are high impedance, they func-
tion as line receivers.
MAX1490EA/MAX1490EBD provide a complete inter-
face. Signals and poꢃer are internally transported
across the isolation barrier ꢁFigures 1, 2D. Poꢃer is
transferred from the logic side ꢁnonisolated sideD to the
isolated side of the barrier through a center-tapped
transformer. Signals cross the barrier through high-
speed optocouplers. A single +5k supply on the logic
side poꢃers both sides of the interface. The
MAX1480EA/MAX1480EC offer half-duplex communica-
tions ꢃhile the MAX1490EA/MAX1490EB feature full-
duplex communication. The functional input/output
relationships are shoꢃn in Tables 3 through 6.
The MAX1480EA/MAX1480EC/MAX1490EA/MAX1490EB
ꢃithstand 1260k
ꢁ1minD or 1520k
ꢁ1sD. The logic
RMS
RMS
inputs can be driven from TTL/CMOS logic ꢃith a series
resistor, and the received data output can directly drive
TTL or CMOS-logic families ꢃith only a resistive pullup.
The MAX1480EC/MAX1490EB feature reduced-sleꢃ-rate
drivers that minimize EMI and reduce reflections caused
by improperly terminated cables, alloꢃing error-free
transmission at data rates up to 160ꢀbps. The
MAX1480EA/MAX1490EA driver sleꢃ rate is not limited,
alloꢃing transmission rates up to 2.5Mbps.
Lowꢂ-ower ꢁhutdown Mode
The Sꢂ pin shuts doꢃn the oscillator on the internal poꢃer
driver. With the primary side in shutdoꢃn, no poꢃer is
transferred across the isolation barrier. The ꢂI and ꢂE
optocouplers, hoꢃever, still consume current if the drive
signals on the nonsolated side are loꢃ. Therefore, leave
ꢂI´ and ꢂE´ high or floating ꢃhen in shutdoꢃn mode.
Under these conditions, the MAX1480EC/MAX1490EB
supply current is reduced to as loꢃ as 0.2µA.
The MAX1480EC/MAX1490EB shutdoꢃn feature reduces
supply current to as loꢃ as 0.2µA by using the Sꢂ pin ꢁsee
Low-Power Shutdown Mode sectionD.
_______________________________________________________________________________________
9
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
V
CC3
ISO V
CC1
D1
D2
MAX845E
Q
MAX1480EA: MAX1487E
MAX1480EC: MAX487E
N
OSC
1.07MHz/
1.45MHz
T
F/F
FS
B
A
ISO DI IN
D
Q
N
ISO DE IN
ISO RO DRV
R
GND1
RE
SD
ISO COM1
EXTERNAL RS-485/RS-422 WIRING
TERMINATING RESISTOR
(ONE RESISTOR ON EACH END)
MAX1480EA
MAX1480EC
V
V
V
CC1
IN
+5V
AC1 (MAKE NO CONNECTION)
AC2 (MAKE NO CONNECTION)
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TWISTED PAIR
CC2
TO OTHER TRANSCEIVERS
C1
C2
ISO V
CC1
R
R
22µF
0.1µF
L
3
D1
D2
B
B
4
SHIELD (OPTIONAL)
GND1
ISO RO DRV
A
5
A
TWISTED PAIR
TO OTHER TRANSCEIVERS
MAX1487E
MAX487E
FS
MAX845E
6
SD
ISO DI IN
R6*
SH
7
L
74HC86
OR EQUIVALENT
V
V
CC3
DI
ISO DE IN
8
R1*
R4*
SHIELD (OPTIONAL)
DI
DRIVER INPUT
ISO COM1
ISO DI DRV
9
DI´
CC4
DE
10
11
12
13
14
R2*
R3*
R5*
NOTE: RESISTOR R7 PROTECTS
THE MAX1480EA FROM TRANSIENT
CURRENTS BETWEEN SHIELD AND
TRANSMISSION LINES.
DE
DRIVER ENABLE
ISO V
CC2
DE´
R7
100Ω
GND2
ISO DE DRV
ISO COM2
ISO RO LED
RECEIVER OUTPUT
RO
RO
V
CC5
LOGIC GROUND
ISOLATION BARRIER
ISOLATED COMMON
*SEE TABLE 1.
270pF
4kV
Figure 1. MAX1480EA/MAX1480EC Detailed Block Diagram and Application Circuit
Table 1. Pullup and LED Drive Resistors for Figure 1
PART
MAX1480EA
MAX1480EC
R1 (Ω)
200
R2 (Ω)
200
R3 (Ω)
1000
R4 (Ω)
R5 (Ω)
1000
R6 (Ω)
200
4300
3000
200
200
3000
3000
200
The high-speed optocouplers on the MAX1480EA/
MAX1480EC/MAX1490EA consume an additional 10mA
couplers. In normal operating mode, the sꢃitch carries
only the optocoupler currents, so an on-resistance of sev-
eral ohms does not significantly degrade efficiency.
through k
ꢁk
for the MAX1490EAD. Therefore, to
CC5 CC4
completely shut doꢃn these devices, use an external P-
channel MOSFET as shoꢃn in Figure 3. In normal opera-
tion, Sꢂ is loꢃ, turning the MOSFET on and thereby
providing poꢃer to all the k
pins. When Sꢂ is pulled
CC
high, the poꢃer oscillator is disabled and the sꢃitch is
turned off, disconnecting poꢃer from the ꢂI and ꢂE opto-
10 ______________________________________________________________________________________
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
V
CC3
D1
D2
MAX845
Q
N
OSC
1.07MHz/
1.45MHz
A
T
F/F
R
FS
ISO RO DRV
ISO DI DRV
B
Z
Q
N
MAX1490EA: MAX490E
MAX1490EB: MAX488E
D
Y
SD
GND1
MAX1490EA/
MAX1490EB
EXTERNAL RS-485/RS-422 WIRING
V
IN
+5V
V
V
TERMINATING RESISTOR
(ONE RESISTOR ON EACH END)
CC1
CC2
AC1 (MAKE NO CONNECTION)
AC2 (MAKE NO CONNECTION)
1
2
24
23
22
21
20
19
18
17
16
15
14
13
C1
C2
0.1µF
22µF
TWISTED PAIR
TO OTHER TRANSCEIVERS
ISO V
CC1
D1
D2
3
ISO RO DRV
4
R
L
R
L
GND1
A
B
Z
Y
A
B
5
SHIELD (OPTIONAL)
FS
6
TWISTED PAIR
TO OTHER TRANSCEIVERS
Z
SD
7
R
L
74HC86
OR EQUIVALENT
V
Y
CC3
8
R
L
R1*
R5, 100Ω
R6, 100Ω
SH1
DI
DRIVER INPUT
ISO COM1
ISO DI DRV
DI
9
R4*
V
DI´
SHIELD (OPTIONAL)
CC4
SH2
10
11
12
R2*
RECEIVER OUTPUT
ISO V
CC2
R0
RO
R3*
ISO RO LED
GND2
NOTE: RESISTORS R5 AND R6 PROTECT
THE MAX1490EA/MAX1490EB FROM
TRANSIENT CURRENTS BETWEEN SHIELD AND
TRANSMISSION LINES.
ISOLATION BARRIER
ISOLATED COMMON
*SEE TABLE 2.
LOGIC GROUND
270 pF
4kV
Figure 2. MAX1490EA/MAX1490EB Detailed Block Diagram and Typical Application Circuit
Table 2. Pullup and LED Drive Resistors for Figure 2
PART
MAX1490EA
MAX1490EB
R1 (Ω)
200
R2 (Ω)
1000
R3 (Ω)
R4 (Ω)
1000
330
330
200
3000
3000
MAX1480EC/MAX1490EB transmitting the same signal.
The high-frequency harmonics have much loꢃer ampli-
tudes, and therefore the potential for EMI is significantly
reduced.
MAX1480EC/MAX1490EB:
Reduced EMI and Reflections
The MAX1480EC/MAX1490EB are sleꢃ-rate-limited,
minimizing EMI and reducing reflections caused by
improperly terminated cables. Figure 11 shoꢃs both
the driver output ꢃaveform of a MAX1480EA/
MAX1490EA transmitting a 150ꢀHz signal and the
Fourier analysis of that ꢃaveform. High-frequency har-
monics ꢃith large amplitudes are evident. Figure 12
shoꢃs the same information for the sleꢃ-rate-limited
Driver Output -rotection
There are tꢃo mechanisms to prevent excessive output
current and poꢃer dissipation caused by faults or by
bus contention. A foldbacꢀ current limit on the output
stage provides immediate protection against short cir-
______________________________________________________________________________________ 11
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
MAX1480EA
V
V
CC1
CC2
D1
V
AC1
AC2
ISO V
B
IN
+5V
1
2
28
27
26
25
24
23
22
21
3
CC1
D2
4
GND1
FS
ISO RO DRV
5
Si9433DY
P
A
6
MAX845
MAX1487E
SD
ISO DI IN
ISO DE IN
7
SHUTDOWN
DI´
V
CC3
8
R1
R2
DI
CC4
DE
ISO COM1
ISO DI DRV
9
20
19
18
17
V
10
11
12
13
14
ISO V
CC2
DE´
GND2
RO
ISO DE DRV
ISO COM2
ISO RO LED
R3
16
15
RO
V
CC5
ISOLATION BARRIER
GND
Figure 3. MAX1480EA Low-Power Shutdown Mode
Test Circuits
ISOLATION BARRIER
ISOLATION BARRIER
ISOLATION BARRIER
(DE´)
( ) ARE FOR
THE MAX1480EA/MAX1480EC.
C
L1
R
R
DIFF
D
R
RO (RO)*
V
V
D
DI´
ID
OD
* OPTOCOUPLER
R
C
V
L2
OC
OUTPUTS. SEE FIGURES 1
AND 2 FOR DETAILED BLOCK
DIAGRAM AND TYPICAL
APPLICATION CIRCUIT.
Figure 4. Driver DC Test Load
Figure 5. Driver/Receiver Timing Test Circuit
12 ______________________________________________________________________________________
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
____________________________________________________Test Circuits (continued)
ISO V
_
CC
S1
S2
500Ω
OUTPUT
UNDER TEST
C
L
Figure 6. Driver Timing Test Load
ꢁwitching Waveforms
V
CC_
- 0.4V
2
V
- 0.4V
CC_
2
V
-0.4V
0
CC_
V
- 0.4V
0
CC_
V
- 0.4V
V
CC_
- 0.4V
CC_
2
2
DE´
DI´
t
t
PHL
PLH
1/2 V
O
t
t
LZ
ZL
B
A
A, B
V
O
2.3V
V
V
+ 0.5V
- 0.5V
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
OL
V
OL
1/2 V
O
V
= V (A) - V (B)
DIFF
A, B
V
O
0
V
DIFF
90%
90%
2.3V
t
OH
10%
10%
0
-V
O
t
R
t
F
t
ZH
HZ
t
t - t
SKEW = PLH PHL
Figure 7. Driver Propagation Delays and Transition Times
Figure 8. Driver Enable and Disable Times
INPUT
V
ID
ID
2.4V
0
0
-V
SD
0.8V
1.6V
1.6V
V - V
A
B
MAX1490EA/MAX1490EB
OUTPUT
t
t
SHDN
ZL(SHDN)
A, B
RO V
OH
t
t
PHL
2.3V
V
V
+ 0.5V
- 0.5V
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
OL
1.5V
t
1.5V
V
OL
V
OL
PLH
A, B
V
OH
2.3V
OH
MAX1480EA/MAX1480EC
1.5V
RO
0
1.5V
V
OUTPUT
OL
t
t
SHDN
ZH(SHDN)
t
PHL
PLH
t
= t
t
SKEW
PLH - PHL
Figure 10. Receiver Propagation Delays
______________________________________________________________________________________ 13
Figure 9. Times to/from Shutdown
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
cuits over the entire common-mode range ꢁsee Typical
_____________________Function Tables
Operating CharacteristicsD. In addition, a thermal shut-
doꢃn circuit forces the driver outputs into a high-im
pedance state if the die temperature rises excessively.
HalfꢂDuplex Devices
(MAX1480EA/MAX1480EC)
-ropagation Delay ꢁ5ew
Propagation delay sꢀeꢃ is the difference betꢃeen the
Table 3. Transmitting
loꢃ-to-high and high-to-loꢃ propagation delay. Small
INPUTS*
OUTPUTS
driver/receiver sꢀeꢃ times help reduce EMI and reflec-
tions by maintaining balanced differential signals.
B
0
1
A
DE´
1
DI´
1
1
0
1
0
0
X
High-Z
High-Z
X = Don’t care; High-Z = High impedance
Table 4. Receiving
INPUTS*
OUTPUT
(RO)
V
- V
B
DE´
0
A
≥ +0.2k
≤ -0.2k
Open
0
1
0
10dB/div
0
0
0
5MHz
FullꢂDuplex Devices
(MAX1490EA/MAX1490EB)
500kHz/div
Figure 11. Driver Output Waveform and FFT Plot of
MAX1480EA/MAX1490EA Transmitting a 150kHz Signal
Table 5. Transmitting
OUTPUTS
INPUT*
Z
Y
1
0
(DI´)
1
0
1
0
* For DE´ and DI´ pin descriptions, see Detailed Block Diagram
and Typical Application Circuit (Figure 1 for MAX1480EA/
MAX1480EC, Figure 2 for MAX1490EA/MAX1490EB).
10dB/div
Table 6. Receiving
0
5MHz
OUTPUT
(RO)
INPUT
(V - V )
500kHz/div
A
B
≥ +0.2k
≤ -0.2k
Open
1
0
1
Figure 12. Driver Output Waveform and FFT Plot of
MAX1480EC/ MAX1490EB Transmitting a 150kHz Signal
14 ______________________________________________________________________________________
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
Human Body Model
___________Applications Information
Figure 13 shoꢃs the Human Body Model, and Figure 14
These E versions of the MAX1480EA/MAX1480EC/
shoꢃs the current ꢃaveform it generates ꢃhen dis-
1490EA/MAX1490EB provide extra protection against
charged into loꢃ impedance. This model consists of a
ESꢂ. The rugged MAX1480EA/MAX1480EC/MAX1490EA/
100pF capacitor charged to the ESꢂ voltage of interest,
MAX1490EB are intended for harsh environments ꢃhere
ꢃhich is then discharged into the test device through a
high-speed communication is important. These devices
1.5ꢀΩ resistor.
eliminate the need for transient suppressor diodes or the
use of discrete protection components. The standard
ꢁnon-ED MAX1480A/MAX1480C/MAX1490A/MAX1490B
are recommended for applications ꢃhere cost is critical.
Machine Model
The Machine Model for ESꢂ tests all pins using a 200pF
storage capacitor and zero discharge resistance. Its
objective is to simulate the stress caused by contact that
occurs ꢃith handling and assembly during manufactur-
ing. All pins require this protection during manufactur-
ing—not just inputs and outputs. Therefore, after PC
board assembly, the Machine Model is less relevant to
I/O ports.
1ꢀ5k EꢁD -rotection
As ꢃith all Maxim devices, ESꢂ-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
The driver outputs and receiver inputs have extra protec-
tion against static electricity. Maxim’s engineers devel-
oped state-of-the-art structures to protect these pins
against ESꢂ of 15ꢀk ꢃithout damage. The ESꢂ struc-
tures ꢃithstand high ESꢂ in all states: normal operation,
shutdoꢃn, and poꢃered doꢃn. After an ESꢂ event,
Maxim’s MAX1480EA/MAX1480EC/MAX1490EA/
MAX1490EB ꢀeep ꢃorꢀing ꢃithout latchup. An isolation
capacitor of 270pF 4ꢀk should be placed betꢃeen ISO
COM and logic ground for optional performance against
an ESꢂ pulse ꢃith respect to logic ground.
The MAX1480EA/MAX1480EC are designed for bidirec-
tional data communications on multipoint bus-transmis-
sion lines. The MAX1490EA/MAX1490EB are designed
for full-duplex bidirectional communications that are pri-
marily point-to-point. Figures 15 and 16 shoꢃ half-duplex
and full-duplex typical netꢃorꢀ application circuits,
respectively. To minimize reflections, terminate the line at
both ends ꢃith its characteristic impedance, and ꢀeep
stub lengths off the main line as short as possible. The
sleꢃ-rate-limited MAX1480EC/MAX1490EB are more tol-
erant of imperfect termination and stubs off the main line.
ESꢂ protection can be tested in various ꢃays; the trans-
mitter outputs and receiver inputs of this product family
are characterized for protection to 15ꢀk using the
Human Body Model.
Layout Considerations
The MAX1480EA/MAX1480EC/MAX1490EA/MAX1490EB
pinouts enable optimal PC board layout by minimizing
interconnect lengths and crossovers:
EꢁD Test Conditions
The 15ꢀk ESꢂ test specifications apply only to the A, B,
Y, and Z I/O pins. The test surge may be referenced to
either the ISO COM or to the nonisolated GNꢂ ꢁFigures 1
and 2D.
• For maximum isolation, the “isolation barrier” should
not be breached except by the MAX1480EA/
R
1MΩ
1500Ω
RD
C
I 100%
P
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
90%
DISCHARGE
RESISTANCE
CHARGE-CURRENT
LIMIT RESISTOR
AMPERES
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
36.8%
C
STORAGE
CAPACITOR
s
100pF
10%
0
SOURCE
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 13. Human Body ESD Test Model
______________________________________________________________________________________ 15
Figure 14. Human Body Current Waveform
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
TERMINATING RESISTOR
(ONE RESISTOR ON EACH END)
B
DI
D
120Ω
DE
RO
A
A
B
A
B
R
100Ω
RE
R
R
RE
RE
D
D
RO DE
DI
RO DE
DI
TERMINATING RESISTOR
MAX1480EA/
MAX1480EC
V
IN
+5V
(ONE RESISTOR ON EACH END)
V
V
CC1
AC1 (MAKE NO CONNECTION)
AC2 (MAKE NO CONNECTION)
1
2
3
4
5
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC2
C1
22µF
C2
0.1µF
ISO V
CC1
D1
D2
B
B
GND1
ISO RO DRV
A
120Ω
A
MAX487E
MAX845E
FS
6
MAX1487E
R6
SD
ISO DI IN
ISO DE IN
ISO COM1
ISO DI DRV
SH
7
74HC86
OR EQUIVALENT
R4
R5
SHIELD
(OPTIONAL)
V
V
CC3
DI
8
R1
DI
DRIVER INPUT
NOTE: RESISTOR R7 PROTECTS
THE MAX1480EA/MAX1480EC
FROM TRANSIENT CURRENTS
BETWEEN SHIELD AND
9
CC4
DE
10
11
12
13
14
R2
R3
DE
DRIVER ENABLE
ISO V
CC2
TRANSMISSION LINES.
R7
100Ω
GND2
ISO DE DRV
ISO COM2
ISO RO LED
RECEIVER OUTPUT
RO
RO
V
CC5
LOGIC GROUND ISOLATION BARRIER
ISOLATED COMMON
270pF
4kV
Figure 15. Typical Half-Duplex RS-485/RS-422 Network
16 ______________________________________________________________________________________
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
MAX1490EA/
MAX1490EB
V
IN
+5V
V
V
CC1
AC1 (MAKE NO CONNECTION)
AC2 (MAKE NO CONNECTION)
1
2
24
23
22
21
20
19
18
17
16
15
14
13
C1
C2
CC2
22µF
0.1µF
ISO V
CC1
D1
D2
3
Y
120Ω
ISO RO DRV
4
D
R
DI
120Ω
Z
GND1
A
A
B
Z
Y
5
SHIELD (OPTIONAL)
B
FS
6
SD
Z
7
120Ω
74HC86
B
V
CC3
Y
8
OR EQUIVALENT
120Ω
RO
R1
R5, 100Ω
DI
ISO COM1
DI
SH1
9
A
R4
SHIELD (OPTIONAL)
DI´
V
ISO DI DRV
SH2
CC4
10
11
12
R2
DRIVER INPUT
ISO V
CC2
RO
R6, 100Ω
RO
NOTE: RESISTORS R5 AND R6 PROTECT
THE MAX1490EA/MAX1490EB FROM TRANSIENT
CURRENTS BETWEEN SHIELD AND
TRANSMISSION LINES.
R3
RECEIVER OUTPUT
ISO RO LED
GND2
ISOLATED COMMON
ISOLATION BARRIER
LOGIC GROUND
270pF
4kV
Figure 16. Typical Full-Duplex RS-485/RS-422 Network
MAX1480EC/MAX1490EA/MAX1490EB. Connections
and components from one side should not be locat-
ed near those of the other side.
resistor values shoꢃn in Tables 1 and 2 are recommend-
ed ꢃhen the 74HC86 gate or equivalent is used. These
values may need to be adjusted if a driving gate ꢃith dis-
similar series resistance is used.
• A shield trace connected to the ground on each side
of the barrier can help intercept capacitive currents
that might otherꢃise couple into the signal path. In a
double-sided or multilayer board, these shield traces
should be present on all conductor layers.
All pullup resistors are based on optocoupler specifica-
tions in order to optimize the devices’ data-transfer rates.
Isolated Common Connection
The isolated common may be completely floating ꢃith
respect to the logic ground and the effective netꢃorꢀ
ground. The receiver input resistors cause the isolated
common voltage to go to the mean voltage of the receiver
inputs. If using shielded cable, connect the isolated com-
mon to the shield through a 100Ω resistor. In the case of
the MAX1490EA/MAX1490EB, each shield should have its
oꢃn 100Ω resistor ꢁFigures 1, 2, 15, and 16D.
• Try to maximize the ꢃidth of the isolation barrier
ꢃherever possible; a clear space of at least 0.25
inches betꢃeen ground and isolated common is
suggested.
-ullup and LED Drive Resistors
The MAX1480EA/MAX1480EC/MAX1490EA/MAX1490EB
are specified and characterized using the resistor val-
ues shoꢃn in Tables 1 and 2. Altering the recommend-
ed values can degrade performance.
DoubleꢂIsolated Rꢁꢂ48ꢀ Repeater
The RS-422/RS-485 standard is specified for cable
lengths up to 4000 feet. When approaching or exceeding
the specified maximum cable length, a ground-potential
difference of several tens of volts can easily develop.
This difference can be either ꢂC, AC, at poꢃer-line fre-
quency, or any imaginable noise or impulse ꢃaveform. It
is typically very loꢃ impedance so that if a connection
betꢃeen the tꢃo grounds is attempted, very large cur-
DI and DE are intended to be driven through a series
current-limiting resistor. Directly grounding these
pins destroys the device.
The ꢂI and ꢂE ꢁMAX1480EA/MAX1480EC onlyD inputs
are the cathodes of LEꢂs ꢃhose anodes are connected
to the supply. These points are best driven by a CMOS-
logic gate ꢃith a series resistor to limit the current. The
______________________________________________________________________________________ 17
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
rents may floꢃ. These currents are by their nature unsta-
ble and unpredictable. In addition, they may cause noise
to be injected into sensitive instrumentation and, in
severe cases, might actually cause physical damage to
such equipment.
corrupted by the collisions that inevitably occur ꢃith a
party-line system. With the repeater of Figure 17, there
might be transmitters up to 8000 feet apart. That repre-
sents more than 8µs ꢁassuming 1ns/foot of delayD in
ꢃhich tꢃo nodes could be transmitting simultaneously.
Figure 17 shoꢃs a half-duplex ꢁ2-ꢃireD, bidirectional,
party-line repeater system that prevents interference
and/or damage from ground-potential differences. Tꢃo
MAX1480EA/MAX1480EC isolated RS-485 transceivers
are used to isolate each of the netꢃorꢀ segments from
the electrical environment of the repeater. The
MAX1480EA/MAX1480EC also regenerate bus signals
that may have been degraded by line attenuation or dis-
persion.
The circuit in Figure 17 can be used either directly as
shoꢃn, ꢃith the sleꢃ-rate-limited MAX1480EC, for data
transfer rates up to 160ꢀbps, or ꢃith the MAX1480EA for
data rates up to 2.5Mbps ꢁsee Table 1 for pullup and
LEꢂ resistor values ꢃhen using the MAX1480EAD. If dual-
port isolation is not needed, one of the MAX1480EC
devices can be replaced by a MAX487E for 250ꢀbps
applications.
Reliability
In the idle state, both transmitters are disabled, ꢃhile all
receivers in the system are enabled. If any device on the
system has information for any other device, it starts
sending its data onto the bus. Each data transmission on
the bus retriggers the one-shot, ꢀeeping the sending
transmitter enabled until there are no more transmis-
sions. All receivers receive all data; if this is undesirable,
the protocol must alloꢃ for an address field so receivers
can ignore data not directed to them.
These products contain transformers, optocouplers, and
capacitors, in addition to several monolithic ICs and
diodes. As such, the reliability expectations more closely
represent those of discrete optocouplers rather than the
more robust characteristics of monolithic silicon ICs. The
reliability testing programs for these multicomponent
devices may be vieꢃed on the Maxim ꢃebsite
ꢁꢃꢃꢃ.maxim-ic.comD under Technical Support,
Technical Reference, Multichip Products.
Each node must refrain from transmitting ꢃhen data
already exists on the bus, and must resend data that is
+5V
+5V
NETWORK SEGMENT B
2 8 10 14
NETWORK SEGMENT A
2 8 10 14
13
3kΩ
200Ω
A
B
23
25
23
25
A
1
2
9
B
26
26
3kΩ
74HC04
MAX1480EC
MAX1480EC
3kΩ
3kΩ
200Ω
4
3
13
11
9
3kΩ
19
22
17
21
19
22
17
21
3kΩ
DRIVER
ENABLE
B > A
DRIVER
ENABLE
A > B
200Ω
200Ω
11
24
24
200Ω
200Ω
15
15
5
7 12
5
7 12
+5V
+5V
51kΩ 1000pF
51kΩ 1000pF
16 15 14
7
6
5
2
B
Q
Q
10
B
Q
13
4
74HC123
74HC123
Q 12
1 A
9
A
CLR
3
CLR
11
Figure 17. Double-Isolated RS-485 Repeater
18 ______________________________________________________________________________________
1ꢀ5k EꢁDꢂ-rotected, Isolated Rꢁꢂ48ꢀ/Rꢁꢂ422
Data Interfaces
Ordering Information (continued)
-in Configurations (continued)
†
PART
TEMP. RANGE PIN-PACKAGE
MAX1480ECCPI
MAX1480ECEPI
MAX1490EACPG
0°C to +70°C
-40°C to +85°C
0°C to +70°C
28 Wide Plastic ꢂIP
28 Wide Plastic ꢂIP
24 Wide Plastic ꢂIP
24 Wide Plastic ꢂIP
24 Wide Plastic ꢂIP
24 Wide Plastic ꢂIP
MAX1480EA/
MAX1480EC
TOP VIEW
MAX1490EAEPG -40°C to +85°C
MAX1490EBCPG
0°C to +70°C
MAX1490EBEPG -40°C to +85°C
V
CC1
CC2
D1
1
2
3
4
5
AC1
28
V
27 AC2
†
ISO V
26
25
Data rate for A parts is up to 2500kbps. Data rate for C parts is
up to 250kbps.
CC1
B
D2
GND1
FS
24 ISO RO DRV
MAX845
MAX487E
MAX1487E
23
22
A
6
7
8
9
ISO DI IN
SD
V
CC3
DI
21 ISO DE IN
ꢁelector Guide
ISO COM1
ISO DI DRV
20
19
V
CC4 10
DE 11
HALF/
FULL
DUPLEX
DATA
RATE
(Mbps)
SLEW-
RATE
LIMITED
PART
18 ISO V
CC2
ISO DE DRV
GND2 12
17
16 ISO COM2
ISO RO LED
MAX1480EA
MAX1480EC
MAX1490EA
MAX1490EB
Half
Half
Full
Full
2.5
0.25
2.5
No
Yes
No
RO
13
14
V
CC5
15
ISOLATION BARRIER
0.25
Yes
DIP
This device is constructed using a unique set of packaging
techniques that impose a limit on the thermal profile the device
can be exposed to during board-level solder attach and
rework. Maxim recommends the use of the solder profiles rec-
ommended in the industry-standard specification, JEDEC
020A, paragraph 7.6, Table 3 for IR/VPR and Convection
Reflow processes. Preheating, per this standard, is required.
Hand or wave soldering is not recommended.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated -roducts, 120 ꢁan Gabriel Drive, ꢁunnyvale, CA 94086 (408) 737ꢂ7600___________________ 19
© 2001 Maxim Integrated Products
Printed USA
is a registered trademarꢀ of Maxim Integrated Products.
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