MAX1473_V01 [MAXIM]
315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range;
| 型号： | MAX1473_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range |
| 文件： | 总16页 (文件大小：1472K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
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MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
General Description
Features
The MAX1473 fully integrated low-power CMOS
superheterodyne receiver is ideal for receiving amplitude-
shift-keyed (ASK) data in the 300MHz to 450MHz frequency
range. Its signal range is from -114dBm to 0dBm. With few
external components and a low-current power-down mode,
it is ideal for cost- and power-sensitive applications typical
in the automotive and consumer markets. The chip consists
of a low-noise amplifier (LNA), a fully differential image-
rejection mixer, an on-chip phase-locked-loop (PLL) with
integrated voltage-controlled oscillator (VCO), a 10.7MHz IF
limiting amplifier stage with received-signal-strength indicator
(RSSI), and analog baseband data-recovery circuitry. The
MAX1473 also has a discrete one-step automatic gain
control (AGC) that drops the LNA gain by 35dB when the RF
input signal is greater than -57dBm.
● Optimized for 315MHz or 433MHz ISM Band
● Operates from Single 3.3V or 5.0V Supplies
● High Dynamic Range with On-Chip AGC
● Selectable Image-Rejection Center Frequency
● Selectable x64 or x32 f /f
Ratio
LO XTAL
● Low 5.2mA Operating Supply Current
● < 2.5μA Low-Current, Power-Down Mode for Efficient
Power Cycling
● 250μs Startup Time
● Built-In 50dB RF Image Rejection
● Receive Sensitivity of -114dBm
Ordering Information
The MAX1473 is available in 28-pin TSSOP and 32-pin
thin QFN packages. Both versions are specified for the
extended (-40°C to +85°C) temperature range.
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 TSSOP
MAX1473EUI+
MAX1473ETJ+
Applications
32 Thin QFN-EP*
● Automotive Remote
Keyless Entry
● Security Systems
● Home Automation
● Local Telemetry
Systems
+ Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
● Garage Door Openers
● Remote Controls
● Wireless Sensors
Functional Diagram and Typical Application Circuit appear
at end of data sheet.
Pin Configurations
TOP VIEW
+
XTAL1
1
2
3
4
5
6
7
8
9
28 XTAL2
AVDD
LNAIN
27 PWRDN
26 PDOUT
25 DATAOUT
+
LNASRC
AGND
N.C.
AGND
1
2
3
4
5
6
7
8
24 DATAOUT
23
24
V
DD5
V
DD5
MAX1473
LNAOUT
AVDD
23 DSP
LNAOUT
AVDD
22 DSP
21 N.C.
20 DFFB
19 OPP
18 DSN
17 DFO
22 DFFB
21 OPP
MAX1473
MIXIN1
MIXIN2
MIXIN1
MIXIN2
AGND
20 DSN
AGND 10
IRSEL 11
MIXOUT 12
DGND 13
DVDD 14
19 DFO
18 IFIN2
17 IFIN1
16 XTALSEL
15 AGCDIS
IRSEL
TSSOP
THIN QFN
19-2748; Rev 7; 1/19
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Absolute Maximum Ratings
V
to AGND .....................................................-0.3V to +6.0V
Continuous Power Dissipation (T = +70°C)
A
DD5
AVDD to AGND ....................................................-0.3V to +4.0V
DVDD to DGND....................................................-0.3V to +4.0V
AGND to DGND ...................................................-0.1V to +0.1V
IRSEL, DATAOUT, XTALSEL, AGCDIS,
28-Pin TSSOP (derate 12.8mW/°C above +70°C).1025.6mW
32-Pin Thin QFN (derate 21.3mW/°C
above +70°C) .........................................................1702.1mW
Operating Temperature Ranges
PWRDN to AGND................................... -0.3V to (V
+ 0.3V)
+ 0.3V)
MAX1473E__ ..................................................... -40°C to +85°C
Storage Temperature Range............................ -60°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
Soldering Temperature (reflow).......................................+260°C
DD5
All Other Pins to AGND..........................-0.3V to (AV
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics (3.3V Operation)
(Typical Application Circuit, AV
= DV
= V
= 3.0V to 3.6V, no RF signal applied, T = -40°C to +85°C, unless otherwise noted.
DD
DD
DD5 A
Typical values are at V
= 3.3V and T = +25°C.) (Note 1)
DD
A
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
3.3V nominal supply
MIN
TYP
3.3
5.2
5.8
1.6
2.5
MAX
3.6
UNITS
V
3.0
V
DD
f
f
f
f
= 315MHz
= 433MHz
= 315MHz
= 433MHz
6.23
6.88
RF
RF
RF
RF
Supply Current
I
V
= V
mA
µA
DD
PWRDN
DD5
V
V
= 0V,
PWRDN
Shutdown Supply Current
I
PWRDN
= 0V
XTALSEL
5.3
0.4
Input Voltage Low
V
V
V
IL
IH
IH
Input Voltage High
Input Logic Current High
V
AV
- 0.4
- 0.4
DD
I
10
µA
f
f
f
= 433MHz, V
= 375MHz, V
= 315MHz, V
= AV
DD
AV
RF
RF
RF
IRSEL
DD
Image Reject Select (Note 2)
= AV /2
DD
1.1
AV
- 1.5
V
IRSEL
IRSEL
DD
= 0V
0.4
0.4
DATAOUT Voltage Output Low
DATAOUT Voltage Output High
V
V
V
OL
R = 5kΩ
L
V
V
- 0.4
OH
DD5
Maxim Integrated
│ 2
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MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Electrical Characteristics (5V Operation)
(Typical Application Circuit, V
= 4.5V to 5.5V, AV
= DV
= ~3.2V, no RF signal applied, T = -40°C to +85°C, unless otherwise
DD5
DD
DD A
noted. Typical values are at V
= 5.0V and T = +25°C.) (Note 1)
A
DD
PARAMETER
SYMBOL
CONDITIONS
5.0V nominal supply
MIN
TYP
5.0
5.2
5.7
2.3
2.8
MAX
5.5
UNITS
Supply Voltage
V
4.5
V
DD
f
f
f
f
= 315MHz
= 433MHz
= 315MHz
= 433MHz
6.04
6.76
RF
RF
RF
RF
Supply Current
I
mA
µA
V
= V
DD5
DD
PWRDN
V
= 0V,
PWRDN
Shutdown Supply Current
I
PWRDN
VXTALSEL = 0V
6.2
0.4
Input Voltage Low
V
V
V
IL
IH
IH
Input Voltage High
Input Logic Current High
V
AV
- 0.4
- 0.4
DD
I
10
µA
f
f
f
= 433MHz, V
= 375MHz, V
= 315MHz, V
= AV
DD
AV
RF
RF
RF
IRSEL
IRSEL
IRSEL
DD
Image Reject Select (Note 2)
= AV /2
DD
1.1
AV
- 1.5
V
DD
= 0V
0.4
0.4
DATAOUT Voltage Output Low
DATAOUT Voltage Output High
V
V
V
OL
R = 5kΩ
L
V
V
- 0.4
OH
DD5
AC Electrical Characteristics
(Typical Application Circuit, AV
= DV
= V
= 3.0V to 3.6V, all RF inputs are referenced to 50Ω, f
= 315MHz, T = -40°C to
RF A
DD
DD
DD5
+85°C, unless otherwise noted. Typical values are at V
= 3.3V and T = +25°C.) (Note 1).
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL CHARACTERISTICS
Time for valid signal detection after
= V
Startup Time
t
250
µs
ON
V
PWRDN
OH
Receiver Input Frequency
Maximum Receiver Input Level
Sensitivity (Note 3)
f
300
450
MHz
dBm
dBm
dB
RF
P
Modulation depth > 18dB
Peak power level
0
-114
8
RFIN_MAX
P
RFIN_MIN
AGC Hysteresis
LNA gain from low to high
150
ms
LNA IN HIGH-GAIN MODE
Power Gain
16
dB
f
f
f
= 433MHz
= 375MHz
= 315MHz
1 - j3.4
1 - j3.9
1 - j4.7
-22
RF
RF
RF
Input Impedance (Note 4)
Z
Normalized to 50Ω
IN_LNA
1dB Compression Point
P1dB
dBm
dBm
LNA
Input-Referred 3rd-Order Intercept
IIP3
-12
LNA
Maxim Integrated
│ 3
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MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
AC Electrical Characteristics (continued)
(Typical Application Circuit, AV
= DV
= V
= 3.0V to 3.6V, all RF inputs are referenced to 50Ω, f
= 315MHz, T = -40°C to
RF A
DD
DD
DD5
+85°C, unless otherwise noted. Typical values are at V
= 3.3V and T = +25°C.) (Note 1).
DD
A
PARAMETER
LO Signal Feedthrough to Antenna
Noise Figure
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
dBm
dB
-80
2
NF
LNA
LNA IN LOW-GAIN MODE
f
f
f
= 433MHz
= 375MHz
= 315MHz
1 - j3.4
1 - j3.9
1 - j4.7
-10
RF
RF
RF
Input Impedance (Note 4)
Z
Normalized to 50Ω
IN_LNA
1dB Compression Point
Input-Referred 3rd-Order Intercept
LO Signal Feedthrough to Antenna
Noise Figure
P1dB
dBm
dBm
dBm
dB
LNA
IIP3
-7
LNA
-80
NF
2
LNA
Power Gain
0
dB
Voltage Gain Reduction
MIXER
AGC enabled (depends on tank Q)
35
dB
Input-Referred 3rd-Order Intercept
Output Impedance
IIP3
-18
330
16
dBm
Ω
MIX
Z
OUT_MIX
Noise Figure
NF
dB
MIX
f
f
f
= 433MHz, V
= 375MHz, V
= 315MHz, V
= AV
DD
42
RF
RF
RF
IRSEL
IRSEL
IRSEL
Image Rejection
(not Including LNA Tank)
= AV /2
DD
44
dB
dB
= 0V
44
Conversion Gain
330Ω IF filter load
13
INTERMEDIATE FREQUENCY (IF)
Input Impedance
Z
330
10.7
20
Ω
IN_IF
Operating Frequency
3dB Bandwidth
f
Bandpass response
MHz
MHz
dB
IF
RSSI Linearity
±0.5
80
RSSI Dynamic Range
dB
P
P
< -120dBm
1.15
2.35
14.2
1.45
2.05
RFIN
RSSI Level
V
mV/dB
V
> 0dBm, AGC enabled
RFIN
RSSI Gain
LNA gain from low to high
LNA gain from high to low
AGC Threshold
Maxim Integrated
│ 4
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MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
AC Electrical Characteristics (continued)
(Typical Application Circuit, AV
= DV
= V
= 3.0V to 3.6V, all RF inputs are referenced to 50Ω, f
= 315MHz, T = -40°C to
RF A
DD
DD
DD5
+85°C, unless otherwise noted. Typical values are at V
= 3.3V and T = +25°C.) (Note 1).
DD
A
PARAMETER
DATA FILTER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum Bandwidth
DATA SLICER
BW
100
100
kHz
DF
Comparator Bandwidth
Output High Voltage
Output Low Voltage
CRYSTAL OSCILLATOR
BW
kHz
V
CMP
V
DD5
0
V
V
V
V
V
= 0V
= AV
= 0V
= AV
6.6128
13.2256
4.7547
9.5094
50
XTALSEL
XTALSEL
XTALSEL
XTALSEL
f
f
= 433MHz
MHz
MHz
RF
RF
DD
DD
Crystal Frequency (Note 5)
f
XTAL
= 315MHz
Crystal Tolerance
Input Capacitance
ppm
pF
From each pin to ground
6.2
Recommended Crystal Load
Capacitance
C
C
3
pF
pF
LOAD
LOAD
Maximum Crystal Load
Capacitance
10
Note 1: Note 1: 100% tested at T = +25°C. Guaranteed by design and characterization over temperature.
A
Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image rejection setting is desired. A 1nF
capacitor is recommended in noisy environments.
Note 3: BER = 2 x 10-3, Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz.
Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance includes the 15nH inductive degeneration con-
nected from the LNA source to ground. The equivalent input circuit is 50Ω in series with 2.2pF.
Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (f - 10.7MHz)/64 for
RF
XTALSEL = 0V, and (f - 10.7MHz)/32 for XTALSEL = AV
.
RF
DD
Maxim Integrated
│ 5
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MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Typical Operating Characteristics
(Typical Application Circuit, V
= 3.3V, f = 315MHz, T = +25°C, unless otherwise noted.)
RF A
DD
SUPPLY CURRENT
SUPPLY CURRENT
BIT-ERROR RATE
vs. SUPPLY VOLTAGE
vs. RF FREQUENCY
vs. AVERAGE RF INPUT POWER
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ꢋꢌꢍꢍꢎꢏ ꢐꢑꢎꢒꢁꢓꢔ ꢕꢐꢖ
ꢌꢍ ꢍꢌꢎꢏꢐꢎꢑꢒꢓ ꢔꢀꢕꢖꢗ
ꢋꢑꢒꢓꢋꢔꢒ ꢕꢖꢗꢘꢙ ꢗꢚꢛꢒꢓ ꢜꢝꢞꢟꢠ
RSSI AND DELTA
vs. IF INPUT POWER
RSSI vs. RF INPUT POWER
SENSITIVITY vs. TEMPERATURE
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IMAGE REJECTION
vs. RF FREQUENCY
IMAGE REJECTION
vs. TEMPERATURE
SYSTEM GAIN vs. FREQUENCY
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ꢌꢍ ꢍꢌꢎꢏꢐꢎꢑꢒꢓ ꢔꢀꢕꢖꢗ
ꢌꢍꢀꢎꢍꢏꢁꢌꢐꢏꢍ ꢑꢒꢓꢔ
Maxim Integrated
│ 6
www.maximintegrated.com
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Typical Operating Characteristics (continued)
(Typical Application Circuit, V
= 3.3V, f = 315MHz, T = +25°C, unless otherwise noted.)
DD
RF
A
NORMALIZED IF GAIN
vs. IF FREQUENCY
S11 MAGNITUDE-LOG PLOT OF RFIN
S11 SMITH PLOT OF RFIN
ꢀꢁꢂꢃꢄꢅꢆ ꢇꢈꢉꢃꢊ
ꢀ
ꢆꢝ
ꢟꢝ
ꢋꢌꢌꢀꢍꢎ
ꢃꢝ
ꢃ
ꢁꢀ
ꢝ
ꢢꢃꢝ
ꢢꢟꢝ
ꢢꢆꢝ
ꢢꢄꢝ
ꢢꢡꢝ
ꢢꢠꢝ
ꢢꢅꢝ
ꢃꢌꢌꢀꢍꢎ
ꢁꢄꢃ
ꢁꢄꢀ
ꢆꢃꢡꢀꢓꢔ
ꢢꢆꢄꢚꢛ
ꢁꢂꢃ
ꢄ
ꢄꢃ
ꢄꢃꢃ
ꢃꢝ ꢃꢝꢜ ꢟꢝꢞ ꢆꢝꢅ ꢄꢝꢠ ꢡꢝꢡ ꢠꢝꢄ ꢅꢝꢆ ꢞꢝꢟ ꢜꢝꢃ ꢃꢝꢝꢝ
ꢊꢋ ꢋꢊꢌꢍꢎꢌꢏꢐꢑ ꢒꢀꢓꢔꢕ
ꢎꢏ ꢏꢐꢑꢒꢓꢑꢔꢕꢖ ꢗꢅꢘꢙꢚ
REGULATOR VOLTAGE
vs. REGULATOR CURRENT
PHASE NOISE
vs. OFFSET FREQUENCY
PHASE NOISE
vs. OFFSET FREQUENCY
ꢆꢙꢃ
ꢓ
ꢓ
ꢦ
ꢧ ꢖꢐꢔꢌꢍꢎ
ꢦ
ꢧ ꢕꢖꢖꢌꢍꢎ
ꢅꢁ
ꢅꢁ
ꢒꢗꢓ
ꢒꢗꢓ
ꢆꢙꢝ
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ꢘꢙꢛ
ꢘꢙꢅ
ꢘꢙꢚ
ꢘꢙꢗ
ꢠꢄꢝꢟꢑ
ꢞꢘꢗꢟꢑ
ꢒꢕꢓ
ꢒꢡꢓ
ꢒꢕꢓ
ꢒꢡꢓ
ꢞꢛꢗꢟꢑ
ꢞꢃꢝꢗꢟꢑ
ꢒꢠꢓ
ꢒꢠꢓ
ꢒꢐꢓꢓ
ꢒꢐꢓꢓ
ꢒꢐꢗꢓ
ꢒꢐꢕꢓ
ꢒꢐꢗꢓ
ꢒꢐꢕꢓ
ꢖ
ꢢ ꢗꢙꢝꢖ
ꢡꢡ
ꢗ
ꢃꢗ
ꢘꢗ
ꢆꢗ
ꢄꢗ
ꢐꢑꢃꢒꢓꢔ ꢐꢑꢃꢒꢓꢕ ꢐꢑꢃꢒꢓꢖ ꢐꢑꢃꢒꢓꢗ ꢐꢑꢃꢒꢓꢐ ꢐꢑꢃꢘꢓꢓ ꢐꢑꢃꢘꢓꢐ
ꢐꢑꢃꢒꢓꢔ ꢐꢑꢃꢒꢓꢕ ꢐꢑꢃꢒꢓꢖ ꢐꢑꢃꢒꢓꢗ ꢐꢑꢃꢒꢓꢐ ꢐꢑꢃꢘꢓꢓ ꢐꢑꢃꢘꢓꢐ
ꢊꢋꢌꢍꢎꢁꢏꢐꢊ ꢑꢍꢊꢊꢋꢒꢏ ꢓꢔꢁꢕ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎꢏ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎꢏ
Maxim Integrated
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MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Pin Description
PIN
NAME
FUNCTION
TSSOP TQFN
1
29
XTAL1
1st Crystal Input. (See the Phase-Locked Loop section.)
Positive Analog Supply Voltage. For +5V operation, pin 2 (TSSOP package) is the output of an on-
chip +3.2V low-dropout regulator and should be bypassed to AGND with a 0.1µF capacitor as close
as possible to the pin. Pin 7 must be externally connected to the supply from pin 2 and bypassed to
AGND with a 0.01µF capacitor as close as possible to the pin (see the Voltage Regulator section and
the Typical Application Circuit).
2, 7
4, 30
AVDD
3
4
5
6
31
32
2
LNAIN
LNASRC
AGND
Low-Noise Amplifier Input. (See the Low-Noise Amplifier section.)
Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground to set
LNA input impedance. (See the Low-Noise Amplifier section.)
Analog Ground
Low-Noise Amplifier Output. Connect to mixer through an LC tank filter. (See the Low-Noise Amplifier
section.)
3
LNAOUT
8
9
5
6
7
MIXIN1 1st Differential Mixer Input. Connect through a 100pF capacitor to LC tank filter from LNAOUT.
MIXIN2 2nd Differential Mixer Input. Connect through a 100pF capacitor to AV side of the LC tank.
DD
10
AGND
Analog Ground
Image Rejection Select Pin. Set V
= 0V to center image rejection at 315MHz. Leave IRSEL
IRSEL
11
8
IRSEL
unconnected to center image rejection at 375MHz. Set V
= AV to center image rejection at 433MHz.
DD
IRSEL
Input logic level based on AV , ~3.2V supply.
DD
12
13
9
MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
10
DGND
Digital Ground
Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a 0.01µF
capacitor as close as possible to the pin (see the Typical Application Circuit).
14
15
16
11
12
14
DVDD
AGCDIS AGC Control Pin. Pull high to disable AGC. Input logic level based on V
voltage.
DD5
Crystal Divider Ratio Select Pin. Drive XTALSEL low to select divider ratio of 64, or drive XTALSEL
high to select divider ratio of 32. Input logic level based on AV , ~3.2V supply.
DD
1st Differential Intermediate Frequency Limiter Amplifier Input. Decouple to AGND with a 1500pF
capacitor.
XTALSEL
IFIN1
17
18
15
16
2nd Differential Intermediate Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz
bandpass filter.
IFIN2
19
20
21
22
23
17
18
19
20
22
DFO
DSN
OPP
DFFB
DSP
Data Filter Output
Negative Data Slicer Input
Noninverting Op-Amp Input for the Sallen-Key Data Filter
Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
Positive Data Slicer Input
+5V Supply Voltage. Bypass to AGND with a 0.01µF capacitor as close as possible to the pin. For
24
23
V
+5V operation, V
is the input to an on-chip voltage regulator whose +3.2V output appears at the
DD5
DD5
pin 2 AVDD pin. (See the Voltage Regulator section and the Typical Application Circuit.)
25
26
24
26
DATAOUT Digital Baseband Data Output. Output logic level based on V
PDOUT Peak Detector Output
voltage.
DD5
Power-Down Select Input. Drive this pin with a logic high to power on the IC.
27
27
28
PWRDN
Input logic level based on V
voltage.
DD5
28
—
—
XTAL2
N.C.
EP
2nd Crystal Input
1, 13,
21, 25
No Connection
—
Exposed Pad (TQFN Only). Connect EP to GND.
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MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
The LC tank filter connected to LNAOUT comprises L3
and C2 (see the Typical Application Circuit). Select L3 and
C2 to resonate at the desired RF input frequency. The
resonant frequency is given by:
Detailed Description
The MAX1473 CMOS superheterodyne receiver and a few
external components provide the complete receive chain
from the antenna to the digital output data. Depending on
signal power and component selection, data rates as high
as 100kbps can be achieved. The MAX1473 is designed
to receive binary ASK data modulated in the 300MHz
to 450MHz frequency range. ASK modulation uses a
difference in amplitude of the carrier to represent logic 0
and logic 1 data.
1
f =
2π
L
C
TOTAL × TOTAL
where:
L
= L3 + L
PARASITICS
TOTAL
C
= C2 + C
PARASITICS
TOTAL
Voltage Regulator
For operation with a single +3.0V to +3.6V supply voltage,
connect AVDD, DVDD, and V
L
and C
include inductance and
PARASITICS
PARASITICS
capacitance of the PCB traces, package pins, mixer input
impedance, LNA output impedance, etc. These parasitics
at high frequencies cannot be ignored, and can have a
dramatic effect on the tank filter center frequency. Lab
experimentation should be done to optimize the center
frequency of the tank.
to the supply voltage.
DD5
For operation with a single +4.5V to +5.5V supply voltage,
connect V to the supply voltage. An on-chip voltage
DD5
regulator drives one of the AVDD pins to approximately
+3.2V. For proper operation, DVDD and both the AVDD
pins must be connected together. Bypass V
, DVDD,
DD5
and the pin 7 AVDD pin to AGND with 0.01μF capacitors,
and the pin 2 AVDD pin to AGND with a 0.1μF capacitor,
all placed as close as possible to the pins.
Mixer
A unique feature of the MAX1473 is the integrated image
rejection of the mixer. This device eliminates the need
for a costly front-end SAW filter for most applications.
Advantages of not using a SAW filter are increased
sensitivity, simplified antenna matching, less board space,
and lower cost.
Low-Noise Amplifier
The LNA is an NMOS cascode amplifier with off-chip
inductive degeneration that achieves approximately 16dB
of power gain with a 2.0dB noise figure and an IIP3 of
-12dBm. The gain and noise figure are dependent on both
the antenna matching network at the LNA input and the LC
tank network between the LNA output and the mixer inputs.
The mixer cell is a pair of double balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz IF from a low-side injected LO (i.e., f
= f
LO
RF
- f ). The image-rejection circuit then combines these
IF
The off-chip inductive degeneration is achieved by
connecting an inductor from LNASRC to AGND. This
inductor sets the real part of the input impedance at
LNAIN, allowing for a more flexible input impedance
match, such as a typical PCB trace antenna. A nominal
value for this inductor with a 50Ω input impedance is
15nH, but is affected by PCB trace. See the Typical
Operating Characteristics for the relationship between the
inductance and the LNA input impedance.
signals to achieve a minimum 45dB of image rejection
over the full temperature range. Low-side injection is
required due to the on-chip image rejection architecture.
The IF output is driven by a source-follower biased to
create a driving impedance of 330Ω; this provides a good
match to the off-chip 330Ω ceramic IF filter. The voltage
conversion gain is approximately 13dB when the mixer is
driving a 330Ω load.
The IRSEL pin is a logic input that selects one of the three
The AGC circuit monitors the RSSI output. When the
RSSI output reaches 2.05V, which corresponds to an RF
input level of approximately -57dBm, the AGC switches
on the LNA gain reduction resistor. The resistor reduces
the LNA gain by 35dB, thereby reducing the RSSI output
by about 500mV. The LNA resumes high-gain mode when
the RSSI level drops back below 1.45V (approximately
-65dBm at RF input) for 150ms. The AGC has a hysteresis
of ~8dB. With the AGC function, the MAX1473 can reliably
produce an ASK output for RF input levels up to 0dBm
with a modulation depth of 18dB.
possible image-rejection frequencies. The input logic level
is based on the AV , supply voltage generated by the
DD
on-chip voltage regulator (~3.2V). When V
= 0V, the
IRSEL
image rejection is tuned to 315MHz. V
= AV /2
IRSEL
DD
tunes the image rejection to 375MHz, and when V
=
IRSEL
AV , the image rejection is tuned to 433MHz. The IRSEL
DD
pin is internally set to AV /2 (image rejection at 375MHz)
DD
when it is left unconnected, thereby eliminating the need
for an external AV /2 voltage.
DD
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MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
causing the receiver to be tuned to 315.1MHz rather than
315.0MHz, an error of about 100kHz, or 320ppm.
Phase-Locked Loop
The PLL block contains a phase detector, charge pump/
integrated loop filter, VCO, asynchronous 64x clock
divider, and crystal oscillator driver. Besides the crystal,
this PLL does not require any external components.
The VCO generates a low-side local oscillator (LO). The
relationship between the RF, IF, and crystal reference
frequencies is given by:
In actuality, the oscillator pulls every crystal. The crystal’s
natural frequency is really below its specified frequency,
but when loaded with the specified load capacitance, the
crystal is pulled and oscillates at its specified frequency.
This pulling is already accounted for in the specification of
the load capacitance.
f
= (f - f )/(32 x M)
RF IF
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
XTAL
where:
M = 1 (V
= AV ) or 2 (V
= 0V)
XTALSEL
DD
XTALSEL
C
1
1
m
6
To allow the smallest possible IF bandwidth (for best
sensitivity), the tolerance of the reference must be
minimized.
f
=
-
× 10
p
2
C
C
C
C
case + spec
case + load
where:
f is the amount the crystal frequency pulled in ppm.
Intermediate Frequency/RSSI
p
The IF section presents a differential 330Ω load to
provide matching for the off-chip ceramic filter. The six
internal AC-coupled limiting amplifiers produce an overall
gain of approximately 65dB, with a bandpass filter-type
response centered near the 10.7MHz IF frequency with
a 3dB bandwidth of approximately 11.5MHz. The RSSI
circuit demodulates the IF by producing a DC output
proportional to the log of the IF signal level, with a slope
of approximately 14.2mV/dB (see the Typical Operating
Characteristics).
C
C
C
C
is the motional capacitance of the crystal.
m
is the case capacitance.
case
spec
load
is the specified load capacitance.
is the actual load capacitance.
When the crystal is loaded as specified, i.e., C
=
load
C
, the frequency pulling equals zero.
spec
Data Filter
The data filter is implemented as a 2nd-order lowpass
Sallen-Key filter. The pole locations are set by the
combination of two on-chip resistors and two external
capacitors. Adjusting the value of the external capacitors
changes the corner frequency to optimize for different
data rates. The corner frequency should be set to
approximately 1.5 times the fastest expected data rate
from the transmitter. Keeping the corner frequency near
the data rate rejects any noise at higher frequencies,
resulting in an increase in receiver sensitivity.
The AGC circuit monitors the RSSI output. When the
RSSI output reaches 2.05V, which corresponds to an RF
input level of approximately -57dBm, the AGC switches
on the LNA gain reduction resistor. The resistor reduces
the LNA gain by 35dB, thereby reducing the RSSI output
by about 500mV. The LNA resumes high-gain mode when
the RSSI level drops back below 1.45V (approximately
-65dBm at RF input) for 150ms. The AGC has a hysteresis
of ~8dB. With the AGC function, the MAX1473 can reliably
produce an ASK output for RF input levels up to 0dBm
with modulation depth of 18dB.
The configuration shown in Figure 1 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband and
a rolloff rate of 40dB/decade for the two-pole filter. The
Bessel filter has a linear phase response, which works well
for filtering digital data. To calculate the value of C7 and
C6, use the following equations along with the coefficients
in Table 1:
Applications Information
Crystal Oscillator
The XTAL oscillator in the MAX1473 is designed to
present a capacitance of approximately 3pF between the
XTAL1 and XTAL2. If a crystal designed to oscillate with
a different load capacitance is used, the crystal is pulled
away from its stated operating frequency, introducing an
error in the reference frequency. Crystals designed to
operate with higher differential load capacitance always
pull the reference frequency higher. For example, a
4.7547MHz crystal designed to operate with a 10pF load
capacitance oscillates at 4.7563MHz with the MAX1473,
Table 1. Coefficents to Calculate C7 and C6
FILTER TYPE
Butterworth (Q = 0.707)
Bessel (Q = 0.577)
a
b
1.414
1.3617
1.000
0.618
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MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Data Slicer
b
C7 =
C6 =
The purpose of the data slicer is to take the analog
output of the data filter and convert it to a digital signal.
This is achieved by using a comparator and comparing
the analog input to a threshold voltage. The output logic
a 100k π f
(
)( )
(
)
c
a
4 100k π f
( ) ( )
( )
c
level is based on V
voltage supply. One input is
DD5
supplied by the data filter output. Both comparator inputs
are accessible off chip to allow for different methods of
generating the slicing threshold, which is applied to the
second comparator input.
where f is the desired 3dB corner frequency.
C
For example, choose a Butterworth filter response with a
corner frequency of 5kHz:
1.000
The suggested data slicer configuration uses a resistor
(R1) connected between DSN and DSP with a capacitor
(C8) from DSN to DGND (Figure 2). This configuration
averages the analog output of the filter and sets the
threshold to approximately 50% of that amplitude. With
this configuration, the threshold automatically adjusts as
the analog signal varies, minimizing the possibility for
errors in the digital data. The sizes of R1 and C8 affect
how fast the threshold tracks to the analog amplitude. Be
sure to keep the corner frequency of the RC circuit much
lower than the lowest expected data rate.
C7 =
≈ 450pF
1.414 100kΩ 3.14 5kHz
)( )( )(
(
)
Choosing standard capacitor values changes C7 to 470pF
and C6 to 220pF, as shown in the Typical Application
Circuit.
MAX1473
Note that a long string of zeros or 1s can cause the
threshold to drift. This configuration works best if a coding
scheme, such as Manchester coding, which has an equal
number of zeros and 1s, is used.
ꢀꢁꢁꢂ
ꢀ
ꢀ
ꢃꢄꢅ
ꢃꢄꢈ
ꢅꢆꢆꢇΩ
ꢅꢆꢆꢇΩ
To prevent continuous toggling of DATAOUT in the
absence of an RF signal due to noise, hysteresis can be
added to the data slicer as shown in Figure 3.
ꢈꢈ
ꢃꢄꢄꢎ
ꢅꢋ
ꢃꢄꢌ
ꢈꢅ
ꢌꢍꢍ
ꢉꢏ
ꢉꢊ
For further information on Data Slicer options, please refer
to Maxim Application Note 3671, Data Slicing Techniques
Figure 1. Sallen-Key Lowpass Data Filter
MAX1473
ꢀꢁꢂꢁ
ꢃꢄꢅꢆꢇꢈ
MAX1473
ꢀꢁꢂꢁ
ꢃꢄꢅꢆꢇꢈ
ꢊꢍ
ꢊꢔ
ꢀꢃꢑ
ꢌꢒ
ꢀꢓꢎ
ꢊꢉ
ꢀꢃꢐ
ꢀꢁꢂꢁꢎꢏꢂ
ꢈꢌ
ꢈꢊ
ꢈꢋ
ꢈꢉ
ꢊꢋ
ꢊꢎ
ꢀꢃꢏ
ꢊꢒ
ꢀꢃꢓ
ꢉꢐ
ꢀꢑꢌ
ꢀꢁꢂꢁꢌꢍꢂ
ꢆꢕ
ꢋꢎꢐꢂꢅꢎꢑꢁꢄ
ꢈꢉ
ꢆꢔ
Figure 2. Generating Data Slicer Threshold
Figure 3. Generating Data Slicer Hysteresis
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MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
for UHF ASK Receivers.
Peak Detector
MAX1473
The peak detector output (PDOUT), in conjunction with
an external RC filter, creates a DC output voltage equal
to the peak value of the data signal. The resistor provides
a path for the capacitor to discharge, allowing the peak
detector to dynamically follow peak changes of the data
filter output voltage. For faster receiver startup, the circuit
shown in Figure 4 can be used.
ꢀꢁꢂꢁ
ꢃꢄꢅꢆꢇꢈ
ꢉꢊ
ꢉꢕ
ꢐꢑ
ꢉꢓ
ꢉꢎ
ꢀꢁꢂꢁꢌꢍꢂ
ꢀꢃꢔ
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ꢔꢀꢌꢍꢂ
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Layout Considerations
ꢉꢊꢋΩ
A properly designed PCB is an essential part of any RF/
microwave circuit. On high-frequency inputs and outputs,
use controlled-impedance lines and keep them as short
as possible to minimize losses and radiation. At high
frequencies, trace lengths that are on the order of λ/10 or
longer act as antennas.
ꢖꢗꢘꢒ
Keepingthetracesshortalsoreducesparasiticinductance.
Generally, 1in of a PCB trace adds about 20nH of parasitic
inductance. The parasitic inductance can have a dramatic
effect on the effective inductance of a passive component.
For example, a 0.5in trace connecting a 100nH inductor
adds an extra 10nH of inductance or 10%.
Figure 4. Using PDOUT for Faster Startup
Control Interface Considerations
When operating the MAX1473 with a +4.5V to +5.5V
supply voltage, the PWRDN and AGCDIS pins may be
driven by a microcontroller with either 3V or 5V interface
logic levels. When operating the MAX1473 with a +3.0V
to +3.6V supply, the microcontroller must produce logic
To reduce the parasitic inductance, use wider traces and
a solid ground or power plane below the signal traces.
Also, use low-inductance connections to ground on all
GND pins, and place decoupling capacitors close to all
power-supply pins.
levels which conform to the V and V specifications in
IH
IL
the DC Electrical Characteristics Table for the MAX1473.
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MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Table 2. Component Values for Typical Application Circuit
COMPONENT
VALUE FOR f = 433MHz
VALUE FOR f = 315MHz
DESCRIPTION
RF
RF
C1
C2
100pF
2.7pF
100pF
4.7pF
5%
±0.1pF
C3
100pF
100pF
5%
C4
100pF
100pF
5%
C5
1500pF
220pF
1500pF
220pF
10%
C6
5%
C7
470pF
470pF
5%
C8
0.47µF
220pF
0.47µF
220pF
20%
C9
10%
C10
C11
C12
C13
C14
C15
L1
0.01µF
0.1µF
0.01µF
0.1µF
20%
20%
15pF
15pF
Depends on XTAL
15pF
15pF
Depends on XTAL
0.01µF
0.01µF
56nH
0.01µF
0.01µF
120nH
20%
20%
5% or better**
L2
15nH
15nH
5% or better**
L3
15nH
27nH
5% or better**
R1
5.1kΩ
5.1kΩ
5%
R2
Open
Open
—
R3
Short
Short
—
X1(÷64)
X1 (÷32)
Y1
6.6128MHz*
13.2256MHz*
10.7MHz ceramic filter
4.7547MHz*
9.5094MHz*
10.7MHz ceramic filter
Crystek or Hong Kong X’tal
Crystek or Hong Kong X’tal
Murata
*Crystal frequencies shown are for ÷64 (V
**Wirewound recommended.
= 0V) and ÷32 (V
= V ).
XTALSEL
XTALSEL DD
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MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Typical Application Circuit
V
DD
AV
DD
IF V IS
DD
THEN AV IS
DD
(SEE TABLE)
X1
3.0V TO 3.6V CONNECTED TO V
DD
4.5V TO 5.5V CREATED BY LDO,
AVAILABLE AT AVDD
(PIN 2)
C12
C13
C11
1
2
3
4
28
XTAL1
AVDD
XTAL2
RF INPUT
TO/FROM µP
POWER DOWN
DATA OUT
27
PWRDN
PDOUT
C1
L1
L2
26
25
LNAIN
LNASRC
R2
MAX1473
DATAOUT
C15
5
6
24
23
AGND
V
DD5
R3
LNAOUT
DSP
C14
C3
AV
DD
7
8
9
22
21
20
19
18
17
16
L3
AVDD
DFFB
OPP
DSN
C2
MIXIN1
MIXIN2
AGND
IRSEL
MIXOUT
DGND
C7
10
C4
DFO
IFIN2
C9
11
12
13
14
**
R1
IFIN1
XTALSEL
AGCDIS
15
DVDD
FROM µP
*
Y1
C5
C6
C8
IF FILTER
C10
IN
OUT
GND
COMPONENT VALUES
IN TABLE 2
** SEE MIXER SECTION
* SEE PHASE-LOCKED LOOP SECTION
Chip Information
PROCESS: CMOS
Maxim Integrated
│ 14
www.maximintegrated.com
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Functional Diagram
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ꢖ
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ꢢ
ꢤ
0˚
ꢇꢋ ꢀꢇꢆꢇꢅꢇꢁꢛ
ꢂꢆꢘꢍ
ꢂꢄꢅꢃꢆꢂꢅꢇꢗ
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ꢗꢃꢁꢅꢌꢃꢀ
ꢞ
ꢜ
ꢇ
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ꢀꢁꢂꢇꢁ
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ꢌꢒꢝꢒꢗꢅꢇꢃꢁ
∑
ꢊ
ꢊꢖ
ꢣ
90˚
MAX1473
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ꢘꢚꢌꢎꢁ ꢎꢂꢅꢂꢃꢄꢅ
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Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
28 TSSOP
PACKAGE CODE
U28+1
OUTLINE NO.
21-0066
LAND PATTERN NO.
90-0171
32 Thin QFN-EP
T3255+3
21-0140
90-0001
Maxim Integrated
│ 15
www.maximintegrated.com
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
Added lead-free parts and exposed pad in Ordering Information and Pin Description
tables
4
5/10
1, 8
Updated Absolute Maximum Ratings, AC Electrical Characteristics, Pin Description,
Layout Considerations, Typical Application Circuit, Functional Diagram, and Package
Information; added Voltage Regulator section to the Detailed Description section
2, 3, 4, 8, 9, 12,
13, 14
5
1/11
Updated DC Electrical and AC Electrical Characteristics tables, replaced TOC 4,
updated Tables 1 and 2 and Figure 1; updated Phase-Locked Loop, Data Filter, Data
Slicer, and Layout Considerations sections
6
7
1/12
1/19
3, 5, 6, 10–13
2–5, 8–11, 14
Updated Absolute Maximum Ratings, DC Electrical Characteristics, DC Electrical
Characteristics, Pin Description table, Detailed Description, and Typical Application Circuit
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2019 Maxim Integrated Products, Inc.
│ 16
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