MAX14659ETE+T [MAXIM]
Dual-Channel USB Host Adapter Emulators;型号: | MAX14659ETE+T |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | Dual-Channel USB Host Adapter Emulators |
文件: | 总27页 (文件大小:2438K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MAX14657/MAX14658/
MAX14659
Dual-Channel USB Host Adapter Emulators
General Description
Benefits and Features
●ꢀ IntegratedꢀDualꢀChannels
The MAX14657/MAX14658/MAX14659 are next-genera-
tion dual-channel USB 2.0 host-charger adapter emula-
tors that combine USB Hi-Speed analog switches with a
USB adapter emulator circuit.
•ꢀ More Convenient, High-Current USB Charging
Ports for Users
•ꢀ Simple and Flexible Power-Management Control
•ꢀ Small TQFN Package Minimizes PCB Area
2
The MAX14657 features an I C interface to fully configure
the charging behavior with different address options.
The MAX14658/MAX14659 are controlled by two GPIO
inputs (CB1_/CB0_) and support USB data and automatic
charger mode. In charging downstream port (CDP) mode,
the devices emulate the CDP function while supporting
normal USB traffic. The MAX14657/MAX14658 have a
CEN_ output for an active-high CLS enable input, and
the MAX14659 has a CEN_ output for an active-low CLS
enable input to restart the peripheral connected to the
USB host.
●ꢀ ImprovedꢀChargerꢀInteroperability
•ꢀ USB (CDP) Emulation with Smart CDP and Fool-
Proof CDP
•ꢀ Enhanced Automodes
•ꢀ Foolproof CDP
•ꢀ Meets New USB Battery Charging (BC) Revision
1.2 Specification
•ꢀ Backward Compatible with Previous USB BC
Revisions
•ꢀ Meets China YD/T1591-2009 Charging
Specification
•ꢀ Supports Standby-Mode Charging for USB BC
Revision 1.2 Compatible Devices
The MAX14658/MAX14659 feature 2A high-current
autodetect mode. The MAX14657 can be configured
2
through I C to support various dedicated charger modes
such as Apple 1A/2A forced, or Apple or Samsung 1A/2A
autodetect modes.
●ꢀ ProvideꢀGreaterꢀApplicationꢀFlexibility
2
•ꢀ I C Controls Multiple Modes (MAX14657)
•ꢀ A Slave Address Selection Input Offers Two
Possible Slave Addresses for Each Emulator
(MAX14657)
•ꢀ CB0_ and CB1_ Pins Control Multiple Automatic
and Manual Charger States (MAX14658, MAX14659)
The MAX14657/MAX14658/MAX14659 support CDP and
standard downstream port (SDP) charging while in the
active state (S0), and support the dedicated charging
port (DCP) charging while in the standby state (S3/S4/
S5). All of the devices support low-speed remote wake-up
by monitoring DM_, and also support remote wakeup in
sleep mode (S3).
●ꢀ EnhanceꢀPerformanceꢀwithꢀHighꢀLevelꢀofꢀIntegratedꢀ
Features
•ꢀ Supports Remote Wake-Up
•ꢀ Low-Capacitance USB 2.0 Hi-Speed Switch to
Change Charging Modes
•ꢀ Automatic Current-Limit Switch Control
•ꢀ ±15kV ESD Protection on DP_/DM_
The MAX14657/MAX14658/MAX14659 are available in a
16-pin (3mm x 3mm) TQFN-EP package and are speci-
fied over the -40°C to +85°C extended temperature range.
Applications
●ꢀ Laptop/DesktopꢀComputers
●ꢀ USBꢀHubs
Selector Guide
●ꢀ UniversalꢀChargersꢀIncludingꢀiPod®/iPhone®/iPad®
REMOTE
WAKE-UP IN
AM
PART
NUMBER
I/O
MODE
CEN
POLARITY
iPod®/iPhone®/iPad® are registered trademarks of Apple, Inc
Ordering Information and Typical Operating Circuit appear
at end of data sheet.
Programmable
(CEN default)
MAX14657
I2C
Programmable
For related parts and recommended products to use with this part, refer
to www.maximintegrated.com/MAX14657.related.
MAX14658
MAX14659
GPIO
GPIO
CEN
Yes
Yes
CEN
19-6664; Rev 1; 8/13
MAX14657/MAX14658/
MAX14659
Dual-Channel USB Host Adapter Emulators
Absolute Maximum Ratings
(All voltages referenced to GND.)
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
V
, TDP_, TDM_, DP_, DM_, SDA,
CC
SCL, CB0_, CB1_, CEN_, CEN_, SAS, INT.......-0.3V to +6V
Continuous Current into Any Terminal..............................±30mA
Continuous Power Dissipation (T = +70°C)
A
TQFN (derate 20.8mW/°C above +70°C)...............1666.7mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 1)
Package Thermal Characteristics
TQFN
Junction-to-AmbientꢀThermalꢀResistanceꢀ(θ ) ..........48°C/W
JA
Junction-to-CaseꢀThermalꢀResistanceꢀ(θ )...............10°C/W
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
= 3.0V to 5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +5.0V and T = +25°C.) (Note 2)
CC
A
CC A
PARAMETER
POWER SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CB0_ = high/CB1_ = low
MAX14658 (PM mode)
MAX14659 CB0_ = low/CB1_ = high
(FM mode)
3.0
5.5
MODE_SEL[2:0] = 001 (PM
mode)
MODE_SEL[2:0 ] = 010 (FM
mode)
MAX14657
CB0_ = low/CB1_ = low
V
CC
Supply Voltage
V
V
CC
MAX14658 (AM2 mode)
MAX14659 CB0_ = high/CB1_ = high
(CM mode) (Note 3)
MODE_SEL[2:0] = XXX
except:
4.75
5.25
MODE_SEL[2:0] = 001 (PM
mode)
MAX14657
MODE_SEL[2:0] = 010 (FM
mode) (Note 3)
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MAX14657/MAX14658/
MAX14659
Dual-Channel USB Host Adapter Emulators
Electrical Characteristics (continued)
(V
= 3.0V to 5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +5.0V and T = +25°C.) (Note 2)
CC
A
CC A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CB1_ = CB0_ = low (AM2
mode)
120
MAX14658 CB1_ = CB0_ = high (CM
MAX14659 mode)
150
25
CB1_ = low/CB0_ = high
(PM mode)
V
CC
Supply Current
I
µA
CC
MODE_SEL[2:0] = 000
(AM2 mode)
120
150
25
MODE_SEL[2:0] = 011 (CM
MAX14657
mode)
MODE_SEL[2:0] = 001 (PM
mode)
POR Delay
t
50
ms
POR
ANALOG SWITCHES (DP_, DM_, TDP_, TDM_)
Analog Signal Range
V
, V
(Note 4)
0
V
V
DP DM
CC
TDP_/TDM_ On-Resistance
R
V
= 3V, V = 0V, V , I = 10mA
3.5
0.1
6.5
Ω
ON
CC
CC
IN
CC IN
TDP_/TDM_ On-Resistance
Matching Between Channels
ΔR
V
= 3V, V = 0V, V , I = 10mA
Ω
ON
IN
CC IN
TDP_/TDM_ On-Resistance
Flatness
R
V
V
= 3V, V = 0V, V , I = 10mA
0.1
70
Ω
Ω
FLAT
CC
IN
CC IN
DP_/DM_ Short On-Resistance
R
= 1V, R ꢀ=ꢀ20kΩꢀonꢀDM_
130
SHORT
DP
L
V
V
= 3.6V, V
= V
= 0.3V, 3.3V
= 0.3V, 3.3V;
CC
DP
DM
Off-Leakage Current
I
-1000
-1000
+1000
+1000
nA
nA
COM(OFF)
= V
TDP_
TDM_
On-Leakage Current
I
V
= 3.6V, V
= V = 0.3V, 3.3V
DM_
90
COM(ON)
CC
DP_
DYNAMIC PERFORMANCE
V
or V
= 1.5V, R ꢀ=ꢀ300Ω,ꢀ
L
TDP_
TDM_
Turn-On Time
t
10
10
60
40
µs
µs
ps
ps
ON
C = 35pF, Figure 1
L
V
or V
= 1.5V, R ꢀ=ꢀ300Ω,ꢀ
TDP
TDM L
Turn-Off Time
t
OFF
C = 35pF, Figure 1
L
R = R ꢀ=ꢀ50Ω,ꢀDP_ꢀandꢀDM_ꢀconnectedꢀ
to TDP_ and TDM_, Figure 2
L
S
TDP_/TDM_ Propagation Delay
DP_/DM_ Output Skew
t
, t
PHL PLH
R = R ꢀ=ꢀ50Ω,ꢀDP_ꢀandꢀDM_ꢀconnectedꢀ
L
S
t
SKEW
to TDP_ and TDM_, Figure 2
f = 240MHz, V = 0V, V = 500mV
P-P
DP_/DM On-Capacitance
(Connected to TDP_, TDM_)
C
5
pF
ON
BIAS
IN
Bandwidth
BW
R = R ꢀ=ꢀ50Ω,ꢀFigureꢀ3
1000
-20
MHz
dB
L
S
V
= 0dBm, R = R ꢀ=ꢀ50Ω,ꢀfꢀ=ꢀ250MHz,ꢀ
L S
IN
Off-Isolation
V
ISO
Figure 3
V
= 0dBm, R = R ꢀ=ꢀ50Ω,ꢀfꢀ=ꢀ250MHz,ꢀ
IN
L
S
Crosstalk
V
-25
dB
CT
Figure 3
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MAX14657/MAX14658/
MAX14659
Dual-Channel USB Host Adapter Emulators
Electrical Characteristics (continued)
(V
= 3.0V to 5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +5.0V and T = +25°C.) (Note 2)
CC
A
CC A
PARAMETER
DCP BIAS VOLTAGES AND INTERNAL RESISTORS (Note 3)
DP_/DM_ Short Pulldown
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
R
PD
320
39
500
40
700
41
kΩ
40%V
Bias
V
R
V
R
%V
CC
CC
AP1A(2A)_P(M)
AP1A(2A)_P(M)
AP1A(2A)_M(P)
AP1A(2A)_M(P)
CC
CC
CC
40%V
Impedance
Bias Source
21
52.6
16.24
24
30
53.6
23.2
25
39
54.6
30.16
26
kΩ
53.6%V
53.6%V
Bias
%V
CC
Bias Source
CC
kΩ
Impedance
25%V
25%V
Bias
V
%V
kΩ
CC
SSG_P/M
SSG_P/M
Bias Source
CC
R
5.25
7.5
9.75
Impedance
CDP INTERNAL RESISTORS
DP Pulldown Resistor
DM Pulldown Resistor
R
CDP mode
CDP mode
14.25
14.25
19.53
19.53
24.80
24.80
kΩ
kΩ
DP_CDP
R
DM_CDP
CDP HIGH-SPEED COMPARATORS (Note 3)
Detection Threshold Voltage
CDP LOW-SPEED COMPARATORS (Note 3)
V
100
161
205
mV
TH_CDP
V
V
V
Voltage
Voltage
V
I = 0, 200µA
LOAD
0.5
0.25
0.8
50
0.7
0.4
2.0
150
V
V
DM_SRC
DP_REF
DM_SRC
V
DP_REF
Voltage
V
V
LGC
LGC
I
Current
I
V
= 0.15V, 3.6V
µA
DP_SINK
DP_SINK
DP
CC
LOGIC INPUTS (CB0_, CB1_, SDA, SCL, SAS)
Input Logic High Voltage
Input Logic Low Voltage
Input Leakage Current
V
IH
1.4
-1
V
V
V
0.4
+1
IL
I
V
= 5.5V; V = 0V, V
µA
µs
IN
IN
CC
CB0_/CB1_ Debounce Time
t
250
DEB_CB_
OPEN-DRAIN LOGIC OUTPUTS (SDA, INT, CEN_, CEN_)
INT, SDA, CEN_ Output Low
V
Output asserted, I
= 4mA
0.4
1
V
µA
V
OL
SINK
Voltage
INT, SDA, CEN_ Output
Leakage Current
I
Output not asserted, V
Output asserted, I
= V = 5.5V
OUT
OH
CC
V
0.4
-
CC
CEN_ Output High Voltage
V
I
= 4mA
= 5.5V,
OH
SOURCE
Output not asserted, V
CC
CEN_ Output Leakage Current
1
µA
%
OL
V
= 0V
CEN_
V
BUS
Toggle Time Accuracy
t
±10
VBT
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MAX14657/MAX14658/
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Dual-Channel USB Host Adapter Emulators
Electrical Characteristics (continued)
(V
= 3.0V to 5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +5.0V and T = +25°C.) (Note 2)
CC
A
CC A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I2C TIMING CHARACTERISTICS (SEE FIGURE 4)
I2C Maximum Clock Frequency
f
400
kHz
SCL
ESD PROTECTION
DP_ and DM_ pins
All other pins
±15
±2
ESD Protection
V
ESD
Human Body Model
kV
Note 2: All units are production tested at T = +25°C. Specifications over temperature are guaranteed by design.
A
Note 3: The devices are operational from 3.0V to 5.5V. However, in order for the valid Apple/Samsung resistor-divider networks to
function and to have the required DCP/CDP parameters accuracy, V
must stay within the 4.75V to 5.25V range.
CC
Note 4: Guaranteed by design, not production tested.
Test Circuits/Timing Diagrams
V
CC
V
CC
t < 5ns
t < 5ns
f
r
V
IH
LOGIC
INPUT
MAX14658
MAX14659
50%
V
IL
D_
TD_
V
IN
V
OUT
t
OFF
CB0_
R
L
C
L
V
t
OUT
LOGIC
INPUT
0.9 x V
0.9 x V
0UT
OUT
CB1_
SWITCH
OUTPUT
0V
GND
ON
IN DEPENDS ON SWITCH CONFIGURATION;
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
R
L
t
AND t
DO NOT INCLUDE CEN TOGGLE DELAY.
OFF
ON
V
= V
IN
OUT
R + R
L
ON
Figure 1. Switching Time
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Dual-Channel USB Host Adapter Emulators
Test Circuits/Timing Diagrams (continued)
MAX14658
MAX14659
R
S
S
TDP_
TDM_
DP_
DM_
IN+
IN-
OUT+
OUT-
RISE-TIME PROPAGATION DELAY = t
FALL-TIME PROPAGATION DELAY = t
OR t
OR t
PLHX
PLHY
PHLX
|
PHLY
R
R
L
t
= |t
- t
| OR |t
- t
SK
PLHX PLHY
PHLX PHLY
R
L
CB0_ CB1_
V
CC
t
INFALL
t
INRISE
10%
V+
90%
90%
V
IN+
50%
50%
50%
10%
0V
V+
V
50%
IN-
0V
V+
t
t
OUTRISE
OUTFALL
10%
t
t
PLHX
PHLX
90%
90%
V
OUT+
50%
50%
10%
0V
V+
50%
50%
V
OUT-
0V
t
t
PHLY
PLHY
Figure 2. Propagation Delay and Output Skew
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MAX14657/MAX14658/
MAX14659
Dual-Channel USB Host Adapter Emulators
Test Circuits/Timing Diagrams (continued)
V
V
OUT
IN
OFF-ISOLATION = 20log
CROSSTALK = 20log
V
V
CC
CC
NETWORK
ANALYZER
V
V
OUT
IN
50Ω
50Ω
V
V
0V OR V
IN
CC
CB0_
CB1_
TDP_
DP_
MAX14658
MAX14659
MEAS
REF
OUT
50Ω
50Ω
GND
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN TD_ AND "OFF" D_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
Figure 3. Bandwidth, Off-Isolation, and Crosstalk
START CONDITION
(S)
REPEATED START CONDITION
(Sr)
STOP CONDITION
(P)
t
t
F
R
SDA
SCL
t
BUF
t
t
t
t
SU:STO
HD:STA
HD:DAT
HD:STA
t
t
SU:STA
SU:DAT
START CONDITION
(S)
t
t
t
F
t
LOW
HIGH
R
2
Figure 4. I C Timing Diagram
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Dual-Channel USB Host Adapter Emulators
Typical Operating Characteristics
(V
= +5V, T = +25°C, unless otherwise noted.)
A
CC
DP/DM SHORT ON-RESISTANCE
USB SWITCH ON-RESISTANCE
USB SWITCH ON-RESISTANCE
vs. V
DP
5
5
4
3
2
1
0
160
120
80
40
0
I
= 10mA
DP
T
= +85°C
A
V
= 3.0V
CC
4
3
2
1
0
V
= 3.0V
CC
T
= +25°C
A
T = -40°C
A
V
= 5.5V
CC
V
= 5.5V
CC
V
= 3.3V, I
= 10mA
TD_
I
= 10mA
CC
TD_
0
2
4
6
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
(V)
0
1
2
3
4
5
6
V
(V)
V
V
(V)
DP
TDP/TDM
TDP/TDM
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
TDP/DP LEAKAGE CURRENT
vs. TEMPERATURE
DP/DM SHORT ON-RESISTANCE
100
80
60
40
20
0
120
100
80
60
40
20
0
90
60
30
0
V
= 3.6V, V
= 3.3V
TDP
CC
T
= +85°C
A
T
= +85°C
A
ON-LEAKAGE
T
= -40°C
T
= +25°C
A
A
T
= -40°C
A
T
= +25°C
A
OFF-LEAKAGE
V
= 5.5V, I = 10mA
D_
CM MODE
5.0
CC
0
2
4
6
3.0
3.5
4.0
V
4.5
(V)
5.5
-40
-15
10
35
60
85
V
(V)
TEMPERATURE (°C)
DP/DM
CC
SUPPLY CURRENT
vs. LOGIC LEVEL
LOGIC-INPUT THRESHOLD
vs. SUPPLY VOLTAGE
80
70
60
50
40
30
20
10
0
1.2
0.9
0.6
0.3
0
V
V
= 5.5V
= 0V
CC
CB_ RISING
CB1_
CB_ FALLING
0
0.5
1.0
1.5
2.0 2.5
3.0
3.0
3.5
4.0
4.5
(V)
5.0
5.5
V
LOGIC LEVEL (V)
V
CC
CB0_
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Dual-Channel USB Host Adapter Emulators
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
REMOTE WAKE-UP OPERATION
(FROM PM/CM TO AM2 MODE WITH
AUTODETECTION MODE
(FROM CM TO AM2 MODE)
AUTODETECTION MODE
MOUSE PLUGGED IN)
(MOUSE PLUGGED IN AM2 MODE)
MAX14657 toc09
MAX14657 toc10
MAX14657 toc11
V
V
DP
DP
V
DP
V
DM
V
DM
V
DM
V
BUS
V
V
BUS
BUS
V
SCL
V
SCL
200ms/div
400ms/div
40ms/div
EYE DIAGRAM OF
CALIBRATION TRACES
EYE DIAGRAM
MAX14657 toc12
MAX14657 toc13
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
TIME (x 10^ -9) s
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
TIME (x 10^ -9) s
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Dual-Channel USB Host Adapter Emulators
Pin Configurations
TOP VIEW
12
11
10
9
12
11
10
9
12
11
10
9
CENA 13
DMA 14
8
7
CENB
DMB
DPB
INT
CENA 13
DMA 14
8
7
CENB
DMB
DPB
CENA 13
DMA 14
8
7
CENB
DMB
DPB
MAX14657
MAX14658
MAX14659
6
5
6
5
15
16
6
5
DPA 15
DPA 15
DPA
EP*
EP*
EP*
CB1B
CB1B
16
16
SCL
CB1A
CB1A
+
+
+
1
2
3
4
1
2
3
4
1
2
3
4
TQFN
(3mm x 3mm)
TQFN
(3mm x 3mm)
TQFN
(3mm x 3mm)
*CONNECT EP TO GROUND PLANE.
Pin Descriptions
PIN
NAME
FUNCTION
MAX14657 MAX14658 MAX14659
1
—
1
—
1
SDA I2C Serial Data
CB0A Switch Control Bit. See the switch control input table 1.
—
Power Supply. Connect a 0.1µF capacitor between V
possible to the device.
and GND as close as
CC
2
2
2
V
CC
3
4
3
—
4
3
—
4
GND Ground
SAS I2C Slave Address Selection Input
—
5
CB0B Switch Control Bit. See the switch control input table 1.
—
5
—
5
INT Open-Drain Interrupt Output. INT asserts when interrupt happens.
CB1B Switch Control Bit. See the switch control input table 1.
DPB USB Connector D+ Connection
—
6
6
6
7
7
7
DMB USB Connector D- Connection
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Dual-Channel USB Host Adapter Emulators
Pin Description (continued)
PIN
NAME
FUNCTION
MAX14657 MAX14658 MAX14659
Current-Limit Switch (CLS) Control Output. n-MOSFET open-drain pulldown output
disables the CLS with active-high EN.
8
8
—
8
CENB
Current-Limit Switch (CLS) Control Output. p-MOSFET open-drain pullup output
disables the CLS with active-low EN.
—
—
CENB
9
9
9
TDPB Host USB Transceiver D+ Connection
TDMB Host USB Transceiver D- Connection
TDMA Host USB Transceiver D- Connection
TDPA Host USB Transceiver D+ Connection
10
11
12
10
11
12
10
11
12
Current-Limit Switch (CLS) Control Output. n-MOSFET open-drain pulldown output
disables the CLS with active-high EN.
13
—
13
—
—
CENA
Current-Limit Switch (CLS) Control Output. p-MOSFET open-drain pullup output
disables the CLS with active-low EN.
13
CENA
14
15
16
—
—
14
15
—
16
—
14
15
—
16
—
DMA USB Connector D- Connection
DPA USB Connector D+ Connection
SCL I2C Serial Clock
CB1A Switch Control Bit. See the switch control input table 1.
EP Exposed Pad. Connect EP to the ground plane.
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Dual-Channel USB Host Adapter Emulators
Functional Diagram
V
CC
CDP ENGINE
DEBOUNCE
MAX14657
MAX14658
MAX14659
V
V
V
DP_REF
LGC
DEBOUNCE
DEBOUNCE
LGC
DCP_REF1
R
DP_CDP
I
DP_SINK
DCP_REF2
R
DM_CDP
V
DM_SRC
REF1
DP_
DM_
TDP_
TDM_
500kΩ
DEBOUNCE
DEBOUNCE
DEBOUNCE
DEBOUNCE
DP
DM1
DM2
DM3
POR
REF2
CB0A/
SDA**
REF3
REF4
REF5
CB1A/
SCL**
CONTROL LOGIC
CB0B/
SAS**
CB1B/
INT**
CEN_/
CEN_*
GND
*CEN IS FOR MAX14659 ONLY.
**SDA, SCL, SAS, AND INT ARE FOR MAX14657 ONLY.
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Dual-Channel USB Host Adapter Emulators
Resistor-Dividers
Detailed Description
The internal voltage buffers with series resistors emulate
equivalent resistor-divider networks on the data lines to
provide support for Apple/Samsung devices. The voltage
buffers are disconnected while not in use to minimize the
supply current. The voltage buffers are not connected in
pass-through mode. Table 1 summarizes the equivalent
resistor values connected to DP_/DM_ in different charg-
ing modes.
The MAX14657/MAX14658/MAX14659 adaptor emulator
devices have Hi-Speed USB analog switches that support
USB hosts by identifying the USB port as a charger when
the USB host is in a low-power mode and cannot enu-
merate USB devices. The devices feature low 4pF (typ)
on-capacitanceꢀandꢀlowꢀ3Ωꢀ(typ)ꢀon-resistanceꢀwhenꢀtheꢀ
USB switches are connected. DP_ and DM_ are capable
of handling signals between 0V and 5.5V over the entire
3.0V to 5.5V supply range.
Switch Control
Digital Controls
2
The MAX14657 are controlled by an I C interface, while
the MAX14658/MAX14659 are controlled by the CB0_
Each channel of the MAX14658/MAX14659 features two
digital select inputs, CB0_ and CB1_, for mode selection.
Table 2 shows how the CB1_/CB0_ inputs can be used
to enter Apple 2A auto-detection charger mode (AM2),
pass-through mode (PM), forced charger mode (FM), and
pass-through mode with CDP emulation (CM).
2
and CB1_ logic inputs. The I C interface allows further
customization over which mode the MAX14657 operates
in, and can be used to read back connection information.
Improvements over the MAX14600 USB detector fam-
ily include support for some smart phones that do not
connect after applying 0.6V in charging downstream
port (CDP) mode. The devices also support high-current
charging of Apple devices while in sleep mode.
In CDP emulation mode, the peripheral device with CDP
detection capability draws charging current up to 1.5A
immediately without USB enumeration.
Enhanced Automode
The ICs feature an enhanced automode (AM1, AM2) that
allows full charging for Apple devices, USB-compliant
devices, and Samsung Galaxy tablets.
Table 1. DP_/DM_ Resistor-Dividers
CHARGING MODE
DP_ PULLUP
75kΩ
DP_ PULLDOWN
49.9kΩ
DM_ PULLUP
43.2kΩ
DM_ PULLDOWN
49.9kΩ
AM1
AM2
43.2kΩ
49.9kΩ
75kΩ
49.9kΩ
Table 2. Digital Input State Table for MAX14658/MAX14659
CB1A/B CB0A/B CHARGER/USB MODE
STATUS
2A Autodetection Charger Mode. For Apple, Samsung Galaxy tablets, and
USB-compliant devices. Voltage buffers emulating Apple 2A resistor-dividers
are connected to DP_/DM_.
0
0
CHARGER
AM2
0
1
1
0
USB
PM
FM
USB Pass-Through Mode. DP_/DM_ are connected to TDP_/TDM_.
Forced Dedicated Charger Mode. DP_ and DM_ are shorted.
CHARGER
USB Pass-Through Mode with CDP Emulation. Autoconnects DP_/DM_ to
TDM_/TDM_ depending on CDP detection status.
1
1
USB
CM
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Dual-Channel USB Host Adapter Emulators
2
connected to VBUS in the event the USB host switches
to or from standby mode. CEN_ or CEN_ are pulsed for
1s (typ) on the rising or falling edge of CB0_ or CB1_
(Figure 5 and Figure 6).
I C Controls
The MAX14657 mode is controlled by the MODE_SEL[2:0]
bits. Table 3 shows how these bits control the device. In
addition to being configurable in all modes, the MAX14657
can be configured for the Apple (AP1 and AP2 modes),
Samsung Galaxy (SS mode) devices, and Automodes
(AM1 and AM2).
Pass-Through Mode
When the ICs are configured in pass-through mode (PM),
TDP_/TDM_ are always connected to DP_/DM_ and no
resistor-dividers or power sources are applied to DP_/DM_.
Legacy D+/D- Detect
The devices support charging devices that use a D+/D-
short to indicate it is ready for charging. This is done by
monitoring the voltage at both the DP_ and DM_ terminals
and triggering when they are both higher than their com-
parator thresholds.
Forced Charger Modes
The ICs can be configured in different forced dedicated
charging port (DCP) modes; VBUS is enabled and DP_
and DM_ are shorted (FM mode) or connected to the volt-
age buffers emulating resistor-dividers (all other modes).
Table 4 summarizes the equivalent resistor-divider values
in each forced mode.
Auto Peripheral Reset
The MAX14658/MAX14659 feature an autocurrent limit
switch control output. This feature resets the peripheral
Table 3. Digital Input State Table for MAX14657
MODE_SEL_A/B
CHARGER/USB MODE
STATUS
[2]
[1]
[0]
2A Autodetection Charger Mode. For Apple, Samsung Galaxy tablets, and USB-
compliant devices. Voltage buffers emulating Apple 2A resistor-dividers are
connected to DP_/DM_.
AUTOMODE
CHARGER
0
0
0
AM2
0
0
0
1
1
0
USB
PM
FM
USB Pass-Through Mode. DP_/DM_ are connected to TDP_/TDM_.
Forced Dedicated Charger Mode. DP_ and DM_ are shorted.
FORCED
CHARGER
USB Pass-Through Mode with CDP Emulation. Autoconnects DP_/DM_ to TDP_/
TDM_ depending on CDP detection status.
0
1
1
0
1
0
USB
CM
1A Autodetection Charger Mode. For Apple, Samsung Galaxy tablets, and
USB-compliant devices. Voltage buffers emulating Apple 1A resistor-dividers are
connected to DP_/DM_.
AUTOMODE
CHARGER
AM1
FORCED
CHARGER
Forced 1A Charger Mode for Apple Devices. Voltage buffers emulating Apple 1A
resistor-dividers are connected to DP_/DM_.
1
1
0
1
1
0
AP1
AP2
FORCED
CHARGER
Forced 2A Charger Mode for Apple Devices. Voltage buffers emulating Apple 2A
resistor-dividers are connected to DP_/DM_.
Forced 2A Charger Mode for Samsung Galaxy Tablets. Voltage buffers emulating
Samsung resistor-dividers are connected to DP_/DM_ and DP_ and DM_ are
shorted.
FORCED
CHARGER
1
1
1
SS
Table 4. Forced Charging Modes
CHARGING MODE
DP_ PULLUP
N/A
DP_ PULLDOWN
N/A
DM_ PULLUP
N/A
DM_ PULLDOWN
N/A
FM
SS
30kΩ
10kΩ
30kΩ
10kΩ
AP1
AP2
75kΩ
49.9kΩ
43.2kΩ
75kΩ
49.9kΩ
43.2kΩ
49.9kΩ
49.9kΩ
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MAX14657/MAX14658/
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Dual-Channel USB Host Adapter Emulators
USB
TRANSCEIVER
USB
TRANSCEIVER
V
V
CC
CC
TDM
TDP
TDM
TDP
0.1µF
0.1µF
TDM_ TDP_
TDM_ TDP_
GND
D+
GND
D+
USB
USB
DP_
DM_
DP_
DM_
CONNECTION
CONNECTION
D-
D-
V
BUS
V
BUS
MAX14659
MAX14657
150µF
150µF
V
CC
V
CC
V
BUS
CURRENT-LIMIT
SWITCH
EN
V
CURRENT-LIMIT
SWITCH
EN
BUS
+5V POWER
SUPPLY
+5V POWER
SUPPLY
1kΩ
CEN_
33kΩ
1kΩ
10kΩ
CEN_
PS EN
SAS
INT
SAS
INT
PS EN
SYSTEM CONTROL
CB0_
CB1_
PM/AM
SYSTEM CONTROL
SCL
SDA
SCL
SDA
CM/FM
GND
GND
Figure 6. MAX14657 Peripheral Reset Applications Diagram
Figure 5. MAX14659 Peripheral Reset Applications Diagram
(CEN is CEN for MAX14658)
the voltages on DM_ and DP_ with voltage buffers con-
nected to determine the type of device attached.
Table 5. USB Host Power States
STATE
DESCRIPTION
If a USB-compliant device is connected, DP_ and DM_
are shorted together to commence charging. Once the
charging device is removed, the short between DP_ and
DM_ is disconnected and the voltage buffer is applied. A
pulldown resistor on the shorted DP_/DM_ node ensures
that a disconnect is detected.
S0
System On
Power to the CPU(s) and RAM is maintained;
devices that do not indicate they must remain on
may be powered down.
S1
S2
S3
CPU is Powered Off
Standby (Suspend to Ram): System memory
context is maintained, all other system context is
lost.
USB Pass-Through Mode with CDP Emulation
The ICs feature a pass-through mode with CDP emula-
tion (CM). This is to support the higher charging current
capability during the pass-through mode in normal USB
operation (S0 state). The peripheral device equipped with
CDP detection capability can draw a charging current as
defined in USB battery charger specification 1.2 when the
charging host supports the CDP mode. This is a useful
feature since most host USB transceivers do not have the
CDP function. Table 5 summarizes the USB host power
states.
S4
S5
Hibernate: Platform context is maintained.
Soft-Off
Automatic Detection with Remote Wakeup
Support
The devices feature automatic detection charger mode
(AM1/AM2) for dedicated chargers and USB masters. In
automatic detection charger mode, the device monitors
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Table 6. Register Map/Register Descriptions
REGISTER
DeviceID
Control1
Control2
Control3
Control4
Control5
INT
ADDR
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
TYPE
POR
0x11
0xA7
0x50
0xE9
0x00
0x6B
0x00
0x00
0x00
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
CHIPREV[3:0]
FUO
BIT 0
R
CHIPID[3:0]
R/W
R/W
R/W
R/W
R/W
R
FUO
FUO
FUO
FUO
FUO
FUO
FUO
FUO
FUO
FUO
FUO
FUO
FUO
LOW_PWR
DIS_CDP
CEN_CNT[1:0]
CEN_DEL[2:0]
RFU
MODE_SEL[2:0]
RFU
RFU
RFU
RFU
RFU
FUO
RFU
RWU_DFT
CEN_TOG_STi
RFU
RFU
INT_EN
USB_SW[1:0]
FUO
CEN_POL
USB_XFRi
USB_XFRs
USB_XFRm
RWU_LS
CDP_DEVi
CDP_DEVs
BYPASS_CDPi
BYPASS_CDPs
CDP_CN_TMRi
CDP_CN_TMRs
RFU
RFU
RFU
RWUi
RWUs
RWUm
CEN_TOG_SPi
CEN_TOG_Ss
STATUS
MASK
R
R/W
CDP_DEVm BYPASS_CDPm CDP_CN_TMRm
CEN_TOG_STm CEN_TOG_SPm
FUO = Factory use only. Do not change from POR values.
RFU = Reserved for future use. Do not change from POR values.
Table 7. Device ID Register
ADDRESS:
MODE:
BIT
0x00
Read Only
7
6
5
4
3
2
1
0
NAME
CHIPID[3:0]
CHIPREV[3:0]
0
RESET
CHIPID[3:0]
0
0
0
1
0
0
1
The CHIPID[3:0] bits show information about the version of the MAX14657.
CHIPREV[3:0] The CHIPREV[3:0] bits show information about the revision of the MAX14657 silicon.
Table 8. Control 1 Register
ADDRESS:
MODE:
BIT
0x01
Read/Write
7
FUO
1
6
FUO
0
5
FUO
1
4
FUO
0
3
FUO
0
2
FUO
1
1
0
FUO
1
NAME
FUO
1
RESET
FUO
Factory Use Only. Do not modify from reset values.
Table 9. Control 2 Register
ADDRESS:
MODE:
BIT
0x02
Read/Write
7
6
FUO
1
5
FUO
0
4
3
FUO
0
2
FUO
0
1
DIS_CDP
0
0
FUO
0
NAME
LOW_PWR
0
FUO
RESET
1
Low-Power Mode
LOW_PWR 0 = MAX14657 is in normal operation
1 = MAX14657 is in low-power mode. All circuitry other than the I2C interface is disabled.
Disable CDP Signal
DIS_CDP
0 = CDP signaling enabled
1 = CDP signaling disabled
FUO
Factory Use Only. Do not modify from reset values.
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Table 10. Control 3 Register
ADDRESS:
MODE:
BIT
0x03
Read/Write
7
6
5
4
CEN_DEL[2:0]
0
3
2
1
0
NAME
CEN_CNT[1:0]
MODE_SEL[2:0]
0
RESET
1
1
1
1
0
1
CEN_ State Control. Directly controls the CEN_ output independent of automatic cycling.
00 = CEN_ asserted
CEN_CNT[1:0]
CEN_DEL[2:0]
01 = FUO
10 = CEN_ deasserted (intend to turn on current-limit switch)
11 = CEN_ controlled by CDP/DCP/AM modes
CEN_ Pulse Delay. Controls how long V
000 = 125ms
001 = 250ms
010 = 350ms
011 = 500ms
toggles last outside of AM mode.
BUS
100 = 750ms
101 = 1.0s
110 = 1.5s
111 = 2s
Operating Mode Control.
000 = AM2
001 = PM
010 = FM
MODE_SEL[2:0] 011 = CM
100 = AM1
101 = AP1
110 = AP2
111 = SS
Table 11. Control 4 Register
ADDRESS:
MODE:
BIT
0x04
Read/Write
7
RFU
0
6
RFU
0
5
RFU
0
4
3
RFU
0
2
RFU
0
1
RFU
0
0
NAME
RFU
RFU
0
RESET
0
RFU
Reserved for Future Use
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Table 12. Control 5 Register
ADDRESS:
MODE:
BIT
0x05
Read/Write
7
INT_EN
0
6
5
4
FUO
0
3
CEN_POL
1
2
FUO
0
1
RWU_DFT
1
0
RWU_LS
1
NAME
USB_SW[1:0]
RESET
1
1
Interrupt Enable.
INT_EN
0 = Interrupt disabled
1 = Interrupt enabled
USB DPDT Switch Control. When the USB switch is forced open (00) or closed (01), the state machine and
CEN_ output are disabled.
00 = DP_/DM_ in High-Z
01 = DP_/DM_ connected to TDP_/TDM_
USB_SW[1:0]
10 = DP_/DM_ controlled by CDP/DCP/AM circuitry
11 = DP_/DM_ controlled by CDP/DCP/AM circuitry
FUO
CEN_POL
FUO
Factory Use Only. Do not modify from reset value.
CEN Polarity Select. Controls the polarity of the CEN output.
0 = CEN output is active-low CEN
1 = CEN output is active-high CEN
Factory Use Only. Do not modify from reset value.
Remote Wake-Up Default
0 = Remote wake-up is off
1 = Remote wake-up is on
RWU_DFT
Remote Wake-Up for Low-Speed Only Select
0 = Remote wake-up for both FS/HS and LS USB devices
1 = Remote wake-up for only LS devices
RWU_LS
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Table 13. Interrupt Register
ADDRESS:
MODE:
BIT
0x06
Read Only
7
6
5
4
3
2
1
0
NAME
CDP_DEVi
0
BYPASS_CDPi
0
CDP_CNi RFU USB_XFRi RWUi
CEN_TOG_STi
0
CEN_TOG_SPi
0
RESET
0
0
0
0
CDP Device Detect Status Interrupt. CDP_DEVi is set when a CDP device is detected following the CDP
handshake procedure in CM mode.
0 = No interrupt
CDP_DEVi
1 = Interrupt
Bypass CDP Running Status Interrupt. BYPASS_CDPi is set when the CDP handshake procedure is bypassed.
BYPASS_CDPi 0 = No interrupt
1 = Interrupt
CDP Connect Status Interrupt. CDP_CNi is set whenever a CDP connection check is in progress.
0 = No interrupt
CDP_CNi
1 = Interrupt
RFU
Reserved for Future Use
USB Session Interrupt. USB_XFRi is set when there is USB data detected in CM mode and DP_/DM_ are
connected to TDP/TDM.
0 = No interrupt
1 = Interrupt
USB_XFRi
RWUi
Remote Wake-Up Status Interrupt. RWUi is set whenever a remote wake-up is performed in AM mode.
0 = No interrupt
1 = Interrupt
CEN_ Toggle Start Monitor Interrupt. CEN_TOG_STi is set at the start of a V
toggle, when V
ꢀisꢀfirstꢀ
BUS
BUS
disabled.
0 = No interrupt
1 = Interrupt
CEN_TOG_STi
CEN_ Toggle Stop Monitor Interrupt. CEN_TOG_SPi is set at the end of a V
toggle, when V
is no longer
BUS
BUS
disabled.
0 = No interrupt
1 = Interrupt
CEN_TOG_SPi
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Table 14. Status Register
ADDRESS:
MODE:
BIT
0x07
Read Only
7
6
5
CDP_CNs
0
4
RFU
0
3
2
RWUs
0
1
RFU
0
0
NAME
CDP_DEVs
0
BYPASS_CDPs
0
USB_XFRs
0
CEN_TOGs
0
RESET
CDP Device Detect Status. CDP_DEVs is set when a CDP device is detected following the CDP handshake
procedure in CM mode and cleared when it is disconnected.
0 = CDP device not detected
CDP_DEVs
1 = CDP device detected
Bypass CDP Running Status. BYPASS_CDPs is set when the CDP handshake procedure is bypassed.
BYPASS_CDPs 0 = CDP signaling used
1 = CDP signaling bypassed
CDP Connect Status. CDP_CNs is set while a CDP connection attempt is in progress.
CDP_CNs
0 = No CDP connection check in progress
1 = CDP connection check in progress
RFU
Reserved for Future Use
USB Session Status. USB_XFRs is set while there is USB data detected in CM mode and DP_/DM_ are
connected to TDP/TDM.
0 = No USB session in progress
1 = USB session in progress
USB_XFRs
RWUs
Remote Wake-Up Status. RWUs is set while a remote wake-up is in progress in AM mode.
0 = Not waiting for RWU
1 = Waiting for RWU
CEN_ Toggle Status. CEN_TOGs is cleared at the start of a V
toggle.
toggle and set at the end of the V
BUS
BUS
CEN_TOGs
0 = V
1 = V
toggle in progress
toggle not in progress
BUS
BUS
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Table 15. Mask Register
ADDRESS:
MODE:
BIT
0x08
Read/Write
7
6
5
4
RFU
0
3
2
RWUm
0
1
0
CDP_
DEVm
BYPASS_
CDPm
CEN_TOG_ CEN_TOG_
NAME
CDP_CNm
0
USB_XFRm
0
STm
SPm
RESET
0
0
0
0
CDP Device Detect Status Interrupt Mask. Prevents an interrupt from being generated in CDP_DEVi when
CDP_DEVs is set to 1.
0 = Masked
CDP_DEVm
1 = Not masked
Bypass CDP Running Status Interrupt Mask. Prevents an interrupt from being generated in BYPASS_CDPi
when BYPASS_CDPs is set to 1.
0 = Masked
BYPASS_CDPm
1 = Not masked
CDP Connect Status Interrupt Mask. Prevents an interrupt from being generated in CDP_CNi when CDP_
CNs is set to 1.
0 = Masked
1 = Not masked
CDP_CNm
RFU
Reserved for Future Use
USB Session Interrupt Mask. Prevents an interrupt from being generated in USB_XFRi when USB_XFRs is
set to 1.
0 = Masked
1 = Not masked
USB_XFRm
Remote Wake-Up Status Interrupt Mask. Prevents an interrupt from being generated in RWUi when RWUs is
set to 1.
0 = Masked
1 = Not masked
RWUm
CEN_ Toggle Start Monitor Interrupt Mask. Prevents an interrupt from being generated in CEN_TOG_STi
when CEN_TOG_STs is set to 1.
0 = Masked
1 = Not masked
CEN_TOG_STm
CEN_TOG_SPm
CEN_ Toggle Stop Monitor Interrupt Mask. Prevents an interrupt from being generated in CEN_TOG_SPi
when CEN_TOG_SPs is set to 1.
0 = Masked
1 = Not masked
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Slave Address
Applications Information
2
The MAX14657 is the I C version that has different slave
2
I C Interface
The MAX14657 contain an I C-compatible interface for
addresses for each port (Table 16). Set the Read/Write
bit high to configure the MAX14657 to read mode. Set
the Read/Write bit low to configure the MAX14657 to
write mode. Further, two possible slave addresses can
be configured for each port through the Slave Address
Selection (SAS) input (see Table 16), allowing up to two
MAX14657 devices to share the same interface bus.
The address is the first byte of information sent to the
MAX14657 after the START condition.
2
data communication with a host controller (SCL and
SDA). The interface supports a clock frequency of up to
400kHz. SCL and SDA require pullup resistors that are
connected to a positive supply.
Start, Stop, and Repeated Start Conditions
2
When writing to the MAX14657 using I C, the master
sends a START condition (S) followed by the MAX14657
2
I C address. After the address, the master sends the
Bit Transfer
register address of the register that is to be programmed.
The master then ends communication by issuing a
STOP condition (P) to relinquish control of the bus, or
a Repeated START condition (Sr) to communicate to
One data bit is transferred on the rising edge of each SCL
clock cycle. The data on SDA must remain stable during
the high period of the SCL clock pulse. Changes in SDA
while SCL is high and stable are considered control sig-
nals (see the Start, Stop, and Repeated Start Conditions
section). Both SDA and SCL remain high when the bus is
not active.
2
another I C slave. See Figure 7.
S
Sr
P
SCL
SDA
2
Figure 7. I C START, STOP, and REPEATED START Conditions
2
Table 16. MAX14657 I C Slave Addresses
SAS
Port
A
A6
0
A5
1
A4
0
A3
0
A2
1
A1
0
A0
0
R/W
1/0
1/0
1/0
1/0
READ ADDR
0x49
WRITE ADDR
0x48
GND
B
0
1
0
1
1
0
0
0x59
0x58
A
0
1
0
0
1
0
1
0x4B
0x4A
V
CC
B
0
1
0
1
1
0
1
0x5B
0x5A
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WRITE SINGLE BYTE
S
DEVICE SLAVE ADDRESS - W
A
A
REGISTER ADDRESS
A
8 DATA BITS
P
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 8. Write Byte Sequence
BURST WRITE
S
DEVICE SLAVE ADDRESS - W
A
A
REGISTER ADDRESS
8 DATA BITS - 2
A
A
A
8 DATA BITS - 1
8 DATA BITS - N
P
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 9. Burst Write Sequence
Single Byte Write
Burst Write
In this operation, the master sends an address and two
data bytes to the slave device (Figure 8). The following
procedure describes the single byte write operation:
In this operation, the master sends an address and mul-
tiple data bytes to the slave device (Figure 9). The slave
device automatically increments the register address after
each data byte is sent, unless the register being accessed
is 0x00, in which case the register address remains the
same. The following procedure describes the burst write
operation:
1) The master sends a START condition
2) The master sends the 7-bit slave address plus a write
bit (low)
3) The addressed slave asserts an ACK on the data line
4) The master sends the 8-bit register address
1) The master sends a START condition
2) The master sends the 7-bit slave address plus a write
bit (low)
5) The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
3) The addressed slave asserts an ACK on the data line
4) The master sends the 8-bit register address
6) The master sends 8 data bits
7) The slave asserts an ACK on the data line
8) The master generates a STOP condition
5) The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
6) The master sends 8 data bits
7) The slave asserts an ACK on the data line
8) Repeat 6 and 7 (N-1) times
9) The master generates a STOP condition
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10) The master asserts a NACK on the data line
11) The master generates a STOP condition
Single Byte Read
In this operation, the master sends an address plus two
data bytes and receives one data byte from the slave
device (Figure 10). The following procedure describes the
single byte read operation:
Burst Read
In this operation, the master sends an address plus two
data bytes and receives multiple data bytes from the slave
device (Figure 11). The following procedure describes the
burst byte read operation:
1) The master sends a START condition
2) The master sends the 7-bit slave address plus a write
bit (low)
1) The master sends a START condition
3) The addressed slave asserts an ACK on the data line
4) The master sends the 8-bit register address
2) The master sends the 7-bit slave address plus a write
bit (low)
5) The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
3) The addressed slave asserts an ACK on the data line
4) The master sends the 8-bit register address
6) The master sends a REPEATED START condition
5) The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
7) The master sends the 7-bit slave address plus a read
bit (high)
6) The master sends a REPEATED START condition
8) The addressed slave asserts an ACK on the data line
9) The slave sends 8 data bits
7) The master sends the 7-bit slave address plus a read
bit (high)
READ SINGLE BYTE
S
DEVICE SLAVE ADDRESS - W
A
A
REGISTER ADDRESS
8 DATA BITS
A
Sr
DEVICE SLAVE ADDRESS - R
NA
P
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 10. Read Byte Sequence
BURST READ
S
DEVICE SLAVE ADDRESS - W
A
A
A
REGISTER ADDRESS
8 DATA BITS - 1
A
A
Sr
DEVICE SLAVE ADDRESS - R
8 DATA BITS - 2
8 DATA BITS - 3
A
8 DATA BITS - N
NA
P
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 11. Burst Read Sequence
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8) The slave asserts an ACK on the data line
9) The slave sends 8 data bits
leave SDA high before the rising edge of the ninth clock
pulse and leave it high for the duration of the ninth clock
pulse. Monitoring for NACK bits allows for detection of
unsuccessful data transfers.
10) The master asserts an ACK on the data line
11) Repeat 9 and 10 (N-2) times
High ESD Protection
12) The slave sends the last 8 data bits
13) The master asserts a NACK on the data line
14) The master generates a STOP condition
Electrostatic discharge (ESD) protection structures are
incorporated on all pins to protect against electrostatic
discharges up to ±2kV Human Body Model (HBM)
encountered during handling and assembly. DP_ and
DM_ are further protected against high ESD up to ±15kV
(HBM) without damage. These ESD structures withstand
high ESD both in normal operation and when the device
is powered down. After an ESD event, the IC continues to
function without latchup.
Acknowledge Bits
Data transfers are acknowledged with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the master
and the MAX14657 generate ACK bits. To generate an
ACK, pull SDA low before the rising edge of the ninth
clock pulse and hold it low during the high period of the
ninth clock pulse (see Figure 12). To generate a NACK,
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents test
setup, test methodology, and test results.
S
SCL
SDA
1
2
8
9
Human Body Model
NOT ACKNOWLEDGE
Figure 13 shows the Human Body Model. Figure 14 shows
the current waveform it generates when discharged into a
low impedance. This model consists of a 100pF capacitor
charged to the ESD voltage of interest that is then dis-
chargedꢀintoꢀtheꢀdeviceꢀthroughꢀaꢀ1.5kΩꢀresistor.
ACKNOWLEDGE
Figure 12. Acknowledge
I
(AMPS)
PEAK
R
R
D
1.5kΩ
C
1MΩ
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
100%
90%
r
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
STORAGE
CAPACITOR
S
36.8%
100pF
SOURCE
10%
0
TIME
0
t
RL
t
DL
Figure 13. Human Body ESD Test Model
Figure 14. Human Body Current Waveform
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Dual-Channel USB Host Adapter Emulators
Typical Operating Circuit
CLS
CLS
+5V
+5V
5V
A
EXTERNAL
POWER
SUPPLY
SWITCHING
POWER SUPPLY
B
Li+
BATTERY
+5V
CENA/B
+5V
A
V
BUS
USB A
iPad® OR iPhone®
D-
TDMA
TDPA
DMA
DPA
USB
TRANSCEIVER
D+
GND
MAX14657
PHONE OR MP3
PLAYER
+5V
LAPTOP CHIPSET
B
SAS
V
BUS
D-
TDMB
TDPB
DMB
DPB
USB
TRANSCEIVER
MICRO B
USB A
D+
GND
SCL
SDA
EC
INT
INT
Ordering Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PART
TEMP RANGE
PIN-PACKAGE
16 TQFN-EP*
16 TQFN-EP*
16 TQFN-EP*
MAX14657ETE+T
MAX14658ETE+T
MAX14659ETE+T
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
T = Tape and reel.
16 TQFN
T1633+5
21-0136
90-0032
Chip Information
PROCESS: BiCMOS
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Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
1
4/13
Initial release
—
8/13
Updated Ordering Information
26
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2013 Maxim Integrated Products, Inc.
│ 27
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