MAX1458AAE+T [MAXIM]
Analog Circuit, 1 Func, PDSO16, 5.30 X 0.65 MM, SSOP-16;
| 型号： | MAX1458AAE+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog Circuit, 1 Func, PDSO16, 5.30 X 0.65 MM, SSOP-16 传感器 |
| 文件： | 总20页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1373; Rev 0; 5/98
1 % -Ac c u ra t e , Dig it a lly Trim m e d
S e n s o r S ig n a l Co n d it io n e r
MAX1458
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX1458 highly integrated analog-sensor signal
processor is optimized for piezoresistive sensor calibra-
tion and compensation without any external compo-
nents. It includes a programmable current source for
sensor excitation, a 3-bit programmable-gain amplifier
(PGA), a 128-b it inte rna l EEPROM, a nd four 12-b it
DACs. Achieving a total error factor within 1% of the
sensor’s repeatability errors, the MAX1458 compen-
sates offset, offset temperature coefficient, full-span
output (FSO), FSO temperature coefficient (FSOTC),
and FSO nonlinearity of silicon piezoresistive sensors.
♦ Medium Accuracy (±1%), Single-Chip Sensor
Signal Conditioning
♦ Sensor Errors Trimmed Using Correction
Coefficients Stored in Internal EEPROM—
Eliminates the Need for Laser Trimming and
Potentiometers
♦ Compensates Offset, Offset-TC, FSO, FSOTC,
FSO Linearity
♦ Programmable Current Source (0.1mA to 2.0mA)
for Sensor Excitation
The MAX1458 calibrates and compensates first-order
temperature errors by adjusting the offset and span of
the input signal via digital-to-analog converters (DACs),
thereby eliminating quantization noise. Built-in testabili-
ty features on the MAX1458 result in the integration of
three traditional sensor-manufacturing operations into
one automated process:
♦ Fast Signal-Path Settling Time (<1ms)
♦ Accepts Sensor Outputs from 10mV/V to 40mV/V
♦ Fully Analog Signal Path
• Pretest: Data acquisition of sensor performance
under the control of a host test computer.
Ord e rin g In fo rm a t io n
• Calibration and compensation: Computation and
storage (in an internal EEPROM) of calibration and
c omp e ns a tion c oe ffic ie nts c omp ute d b y the te s t
computer and downloaded to the MAX1458.
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
16 SSOP
MAX1458CAE
MAX1458C/D
MAX1458AAE
0°C to +70°C
Dice*
-40°C to +125°C
16 SSOP
• Final test operation: Verification of transducer cali-
bration and compensation without removal from the
pretest socket.
*Dice are tested at T = +25°C, DC parameters only.
A
Although optimized for use with piezoresistive sensors,
the MAX1458 may also be used with other resistive
sensors (i.e., accelerometers and strain gauges) with
some additional external components.
Functional Diagram appears at end of data sheet.
P in Co n fig u ra t io n
______________________Cu s t o m iza t io n
Maxim can customize the MAX1458 for unique require-
ments. With a dedicated cell library consisting of more
than 90 sensor-specific functional blocks, Maxim can
quickly provide customized MAX1458 solutions. Please
contact Maxim for further information.
TOP VIEW
SCLK
CS
1
2
3
4
5
6
7
8
16 LIMIT
15
V
DD
________________________Ap p lic a t io n s
Piezoresistive Pressure and Acceleration
Transducers and Transmitters
I.C.
14 INP
TEMP
FSOTC
DIO
MAX1458
13 BDRIVE
12 INM
11 I.C.
MAP (Manifold Absolute Pressure) Sensors
Automotive Systems
WE
10 OUT
Hydraulic Systems
V
SS
9 ISRC
Industrial Pressure Sensors
SSOP
________________________________________________________________ Maxim Integrated Products
1
For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V to V ......................................-0.3V to +6V
Operating Temperature Ranges
DD
SS
All Other Pins ...................................(V - 0.3V) to (V + 0.3V)
Short-Circuit Duration, FSOTC, OUT, BDRIVE...........Continuous
MAX1458CAE ......................................................0°C to +70°C
MAX1458AAE .................................................-40°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
SS
DD
Continuous Power Dissipation (T = +70°C)
A
SSOP (derate 8.00mW/°C above +70°C) .....................640mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX1458
ELECTRICAL CHARACTERISTICS
(V = +5V, V = 0, T = +25°C, unless otherwise noted.)
DD
SS
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL CHARACTERISTICS
Supply Voltage
V
4.5
5.0
3
5.5
6
V
DD
Supply Current
I
DD
(Note 1)
mA
ANALOG INPUT (PGA)
Input Impedance
R
1
±0.5
0.01
1
MΩ
IN
Input-Referred Offset Tempco
Amplifier Gain Nonlinearity
Output Step Response
Common-Mode Rejection Ratio
(Notes 2, 3)
µV/°C
%V
DD
63% of final value
ms
CMRR
From V to V
90
dB
SS
DD
Input-Referred Adjustable Offset
Range
At minimum gain (Note 4)
±150
mV
Input-Referred Adjustable FSO
Range
(Note 5)
10 to 40
mV/V
ANALOG OUTPUT (PGA)
Differential Signal-Gain Range
Minimum Differential Signal Gain
Differential Signal-Gain Tempco
Selectable in eight steps
41 to 230
41
V/V
V/V
T
= T
to T
MAX
36
45
A
MIN
±50
ppm/°C
V
= 5.0V, no load
= 4.6V
V
+ 0.15
V
DD
- 0.25
± 0.3
± 0.2
LIMIT
SS
10kΩ load to V
SS
Output Voltage Swing
V
SS
+ 0.25
+ 0.1
V
LIMIT
V
or V
DD
V
LIMIT
No load
V
V
LIMIT
SS
V
V
OUT
= 4.6V,
-0.45
(sink)
0.45
(source)
LIMIT
Output Current Range
Output Noise
mA
= (V + 0.25V) to (V - 0.3V)
LIMIT
SS
DC to 10Hz (gain = 41,
source impedance = 5kΩ)
500
µV
RMS
2
_______________________________________________________________________________________
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MAX1458
ELECTRICAL CHARACTERISTICS (continued)
(V = +5V, V = 0, T = +25°C, unless otherwise noted.)
DD
SS
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CURRENT SOURCE
Bridge Current Range
Bridge Voltage Swing
I
0.1
0.5
2.0
mA
V
BDRIVE
V
V
+ 1.3
V
- 1.3
BDRIVE
SS
DD
Reference Input Voltage Range
(ISRC)
V
ISRC
V
SS
+ 1.3
V
DD
- 1.3
12
V
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution
Bits
Differential Nonlinearity
DNL
∆V
±1.5
2.8
LSB
OUT
Offset DAC Bit Weight
DAC reference = V = 5.0V
mV/bit
mV/bit
mV/bit
mV/bit
DD
∆Code
∆V
OUT
Offset TC DAC Bit Weight
FSO DAC Bit Weight
DAC reference = V
= 2.5V
1.4
1.22
0.6
BDRIVE
∆Code
∆V
ISRC
DAC reference = V = 5.0V
DD
∆Code
∆V
FSOTC
FSO TC DAC Bit Weight
DAC reference = V
= 2.5V
BDRIVE
∆Code
IRO DAC
DAC Resolution
DAC Bit Weight
FSOTC BUFFER
Output Voltage Swing
Current Drive
3
9
Bits
Input referred, V = 5V (Note 6)
DD
mV/bit
No load
V
+ 0.3
V
DD
- 1.3
20
V
SS
V
FSOTC
= 2.5V
-20
µA
INTERNAL RESISTORS
Current-Source Reference
Resistor
R
75
75
kΩ
kΩ
kΩ
ISRC
FSO Trim Resistor
R
FTC
Temperature-Dependent
Resistor
R
Typically 4600ppm/°C tempco
100
TEMP
Note 1: Excludes the sensor or load current.
Note 2: All electronics temperature errors are compensated together with sensor errors.
Note 3: The sensor and the MAX1458 must always be at the same temperature during calibration and use.
Note 4: This is the maximum allowable sensor offset.
Note 5: This is the sensor’s sensitivity normalized to its drive voltage, assuming a desired full-span output of 4V and a bridge
voltage of 2.5V.
Note 6: Bit weight is ratiometric to V
.
DD
_______________________________________________________________________________________
3
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P in De s c rip t io n
PIN
NAME
FUNCTION
Data Clock Input. Used only during programming/testing. Internally pulled to V with a 1MΩ (typical) resis-
tor. Data is clocked in on the rising edge of the clock. The maximum SCLK frequency is 10kHz.
SS
1
SCLK
Chip-Select Input. The MAX1458 is selected when this pin is high. When low, OUT and DIO become high
2
3, 11
4
CS
I.C.
impedance. Internally pulled to V with a 1MΩ (typical) resistor. Leave unconnected for normal operation.
DD
MAX1458
Internally Connected. Leave unconnected.
Temperature Sensor Output. An internal temperature sensor (a 100kΩ, 4600ppm/°C TC resistor) which can
provide a temperature-dependent voltage.
TEMP
Buffered FSOTC DAC Output. An internal 75kΩ resistor (R
Diagram). Optionally, external resistors can be used in place of or in parallel with R
) connects FSOTC to ISRC (see Functional
FTC
5
6
FSOTC
DIO
and R
.
FTC
ISRC
Data Input/Output. Used only during programming/testing. Internally pulled to V with a 1MΩ (typical)
resistor. High impedance when CS is low.
SS
Dual-Function Input Pin. Used to enable EEPROM erase/write operations. Also used to set the DAC refresh-
7
WE
rate mode. Internally pulled to V with a 1MΩ (typical) resistor. Refer to the Chip-Select (CS) and Write-
DD
Enable (WE) section.
8
9
V
Negative Power-Supply Input
SS
Current-Source Reference. An internal 75kΩ resistor (R
Diagram). Optionally, external resistors can be used in place of or in parallel with R
) connects ISRC to V (see Functional
SS
ISRC
ISRC
and R
.
FTC
ISRC
10
12
13
14
15
OUT
INM
PGA Output Voltage
Negative Sensor Input. Input impedance >1MΩ. Rail-to-rail input range.
Sensor Excitation Current Output. This current source drives the bridge.
Positive Sensor Input. Input impedance >1MΩ. Rail-to-rail input range.
BDRIVE
INP
V
DD
Positive Power-Supply Input. Connect a 0.1µF capacitor from V to V
DD SS.
Voltage Limit Input. This pin sets the maximum voltage at OUT. If left unconnected, the output voltage will be
16
LIMIT
limited to 4.6V (V
= 5V). Connect to V
for maximum output swing. The acceptable range is 4.5V ≤
DD
DD
V
LIMIT
≤ V
.
DD
an internal 128-bit EEPROM. This memory contains the
following information as 12-bit-wide words:
_______________De t a ile d De s c rip t io n
The MAX1458 provides an analog amplification path for
the sensor signal. Calibration and temperature com-
pensation are achieved by varying the offset and gain
of a programmable-gain amplifier (PGA) and by varying
the sensor bridge current. The PGA uses a switched-
capacitor CMOS technology, with an input-referred
coarse offset trimming range of approximately ±63mV
(9mV steps). An additional output-referred fine offset
trim is p rovid e d b y the Offs e t DAC (a p p roxima te ly
2.8mV steps). The PGA provides eight gain values from
+41V/V to +230V/V. The bridge current source is pro-
grammable from 0.1mA to 2mA.
•
•
•
•
•
•
Configuration register
Offset calibration coefficient
Offset temperature error compensation coefficient
FSO (full-span output) calibration coefficient
FSO temperature error compensation coefficient
24 user-defined bits for customer programming of
manufacturing data (e.g., serial number and date)
Figure 1 shows a typical pressure-sensor output and
defines the offset, full-scale, and full-span output values
as a function of voltage.
The MAX1458 uses four 12-bit DACs and one 3-bit
DAC, with calibration coefficients stored by the user in
4
_______________________________________________________________________________________
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MAX1458
V
that must be added to the output summing
FS OTC Co m p e n s a t io n
Silicon piezoresistive transducers (PRTs) exhibit a large
positive input resistance tempco (TCR) so that, while
under constant current excitation, the bridge voltage
BDRIVE
junction to correct the error. Use the Offset TC DAC to
adjust the amount of BDRIVE voltage that is added to
the output summing junction (Figure 2).
(V
) increases with temperature. This depen-
BDRIVE
An a lo g S ig n a l P a t h
The fully differential analog signal path consists of four
stages:
dence of V
on the sensor temperature can be
BDRIVE
used to compensate the sensor temperature errors.
PRTs also have a large negative full-span output sensi-
tivity tempco (TCS) so that, with constant voltage exci-
ta tion, full-s p a n outp ut (FSO) will d e c re a s e with
temperature, causing a full-span output temperature
coefficient (FSOTC) error. However, if the bridge volt-
age can be made to increase with temperature at the
same rate that TCS decreases with temperature, the
FSO will remain constant.
•
•
Front-end summing junction for coarse offset correction
3-bit PGA with eight selectable gains ranging from
41 through 230
•
•
Three-input-channel summing junction
Differential to single-ended output buffer (Figure 2)
Coarse Offset Correction
FSOTC c omp e ns a tion is a c c omp lis he d b y re s is tor
The sensor output is first fed into a differential summing
junction (INM (negative input) and INP (positive input))
with a CMRR > 90dB, an input impedance of approxi-
mately 1MΩ, and a common-mode input voltage range
R
and the FSOTC DAC, which modulate the excita-
FTC
tion reference current at ISRC as a function of tempera-
ture (Fig ure 3). FSO DAC s e ts V a nd re ma ins
constant with temperature while the voltage at FSOTC
varies with temperature. FSOTC is the buffered output
of the FSOTC DAC. The re fe re nc e DAC volta g e is
ISRC
from V to V . At this summing junction, a coarse off-
SS
DD
set-correction voltage is added, and the resultant volt-
a g e is fe d into the PGA. The 3-b it (p lus s ig n)
input-referred Offset DAC (IRO DAC) generates the
coarse offset-correction voltage. The DAC voltage ref-
V
, which is temperature dependent. The FSOTC
BDRIVE
DAC alters the tempco of the current source. When the
tempco of the bridge voltage is equal in magnitude and
opposite in polarity to the TCS, the FSOTC errors are
compensated and FSO will be constant with tempera-
ture.
erence is 1.25% of V ; thus, a V
of 5V results in a
DD
DD
front-end offset-correction voltage ranging from -63mV
to +63mV, in 9mV steps (Table 1). To add an offset to
the input signal, set the IRO sign bit high; to subtract an
offset from the input signal, set the IRO sign bit low.
The IRO DAC bits (C2, C1, C0, and IRO sign bit) are
programmed in the configuration register (see Internal
EEPROM section).
OFFS ET TC Co m p e n s a t io n
Compensating offset TC errors involves first measuring
the uncompensated offset TC error, then determining
the percentage of the temperature-dependent voltage
1.25% V
BDRIVE
DD
4.5
SOTC
±
OFFTC
DAC
IRO
DAC
A2 A1 A0
PGA
A = 2.3
LIMIT
FULL-SPAN OUTPUT (FSO)
FULL-SCALE (FS)
INP
OUT
A = 1
Σ
Σ
INM
±
A = 2.3
0.5
V
DD
OFFSET
Offset
DAC
SOFF
P
MIN
P
MAX
PRESSURE
Figure 2. Signal-Path Block Diagram
_______________________________________________________________________________________
Figure 1. Typical Pressure-Sensor Output
5
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Table 1. Input-Referred Offset DAC
Correction Values
Table 2. PGA Gain Settings and IRO DAC
Step Size
OUTPUT-
PGA
OFFSET
CORREC- CORREC-
TION
OFFSET
IRO DAC
PGA
VALUE
REFERRED IRO
DAC STEP SIZE
A2 A1 A0
GAIN
(V/V)
TION AT
V = 5V
DD
(mV)
(V
DD
= 5V) (V)
% of V
(%)
DD
VALUE
SIGN C2 C1 C0
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
41
68
0.369
0.612
0.855
1.098
1.341
1.584
1.827
2.070
+7
+6
+5
+4
+3
+2
+1
+0
-0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
+1.25
+1.08
+0.90
+0.72
+0.54
+0.36
+0.18
0
+63
+54
+45
+36
+27
+18
+9
MAX1458
95
122
149
176
203
230
0
Output Buffer
0
0
OUT can drive 0.1µF of capacitance. If CS is brought
low, OUT becomes high impedance (resulting in typical
output impedance of 1MΩ). The output is current limit-
ed and can be shorted to either V or V indefinitely.
-1
-0.18
-0.36
-0.54
-0.72
-0.90
-1.08
-1.25
-9
-2
-18
-27
-36
-45
-54
-63
-3
DD
SS
-4
The maximum output voltage can be limited using the
LIMIT pin. Output limiting can be performed for sensor
-5
diagnostic purposes. Connect LIMIT to V
to disable
DD
-6
the voltage-limiting feature.
-7
Brid g e Drive
Fine FSO correction is accomplished by varying the
s e ns or e xc ita tion c urre nt with the 12-b it FSO DAC
(Figure 3). Sensor bridge excitation is performed by a
programmable current source capable of delivering up
to 2mA. The reference current at ISRC is established by
Programmable-Gain Amplifier
The programmable-gain amplifier (PGA), which is used
to s e t the c oa rs e FSO, us e s a s witc he d -c a p a c itor
CMOS technology and contains eight selectable gain
levels from 41 to 230, in increments of 27 (Table 2). The
output of the PGA is fed to the output summing junc-
tion. The three PGA gain bits A2, A1, and A0 are stored
in the configuration register.
resistor R
and by the voltage at node ISRC (con-
ISRC
trolled by the FSO DAC). The reference current flowing
through this pin is multiplied by a current mirror (AA
14) and then made available at BDRIVE for sensor exci-
tation. Modulation of this current with respect to tem-
perature can be used to correct FSOTC errors, while
Output Summing Junction
The third stage in the analog signal path consists of a
summing junction for the PGA output, offset correction,
and the offset TC correction. Both the offset and the off-
set TC correction voltages are gained by a factor of 2.3
before being fed into the summing junction, increasing
the offset and offset TC correction range. The offset
sign bit and offset TC sign bit are stored in the configu-
ration register. The offset sign bit determines if the off-
set correction voltage is added to (sign bit is high) or
s ub tra c te d from (s ig n b it is low) the PGA outp ut.
Negative offset TC errors require a logic high for the
offset TC sign bit. Alternately, positive offset TC errors
dictate a logic low for the offset TC sign bit. The output
of the summing junction is fed to the output buffer.
modulation with respect to the output voltage (V
can be used to correct FSO linearity errors.
)
OUT
Dig it a l-t o -An a lo g Co n ve rt e rs
The four 12-bit, sigma-delta DACs typically settle in
less than 100ms. The four DACs have a corresponding
memory register in EEPROM for storage of correction
coefficients.
Use the FSO DAC for fine FSO adjustments. The FSO
DAC takes its reference from V
and controls V
DD
ISRC
which, in conjunction with R
, sets the baseline sen-
ISRC
sor excitation current. The Offset DAC also takes its ref-
erence from V and provides a 1.22mV resolution with
DD
6
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MAX1458
V
DD
V
DD
FSO
DAC
I = I
ISRC
AA ≈ 14I
= I
ISRC BDRIVE
I
BDRIVE
SRC
FSOTC
DAC
FSOTC
R
FTC
R
ISRC
EXTERNAL
SENSOR
Figure 3. Bridge Excitation Circuit
a V
of 5V. The output of the Offset DAC is fed into
DD
Table 3. Configuration Register
the outp ut s umming junc tion whe re it is g a ine d b y
approximately 2.3, which increases the resulting out-
put-referred offset correction resolution to 2.8mV.
EEPROM
DESCRIPTION
ADDRESS (hex)
00h
01h
02h
03h
04h
05h
06h
Offset TC Sign Bit, SOTC
Offset Sign Bit, SOFF
PGA Gain (MSB), A2
PGA Gain, A1
Both the Offset TC and FSOTC DACs take their refer-
ence from BDRIVE, a temperature-dependent voltage. A
nominal V
of 2.5V results in a step size of 0.6mV.
BDRIVE
The Offset TC DAC output is fed into the output sum-
ming junction where it is gained by approximately 2.3,
thereby increasing the Offset TC correction range. The
buffered FSOTC DAC output is available at FSOTC and
PGA Gain (LSB), A0
Reserved “0”
is connected to ISRC via R
to correct FSOTC errors.
FTC
Reserved “0”
In t e rn a l Re s is t o rs
Internal Resistor (R
Selection
and R
)
FTC
ISRC
07h
The MAX1458 contains three internal resistors (R
,
ISRC
R
R
, and R
ISRC
) optimized for common silicon PRTs.
(in conjunction with the FSO DAC) programs the
FTC
TEMP
08h
09h
0Ah
0Bh
Input-Referred Offset (IRO) Sign Bit
Input-Referred Offset (MSB)
Input-Referred Offset
nominal sensor excitation current. R
(in conjunction
FTC
with the FSOTC DAC) compensates the FSOTC errors.
Both R and R have a nominal value of 75kΩ. If
ISRC
FTC
Input-Referred Offset (LSB)
external resistors are used, R
and R
can be dis-
ISRC
FTC
abled by resetting the appropriate bit (address 07h
reset to zero) in the configuration register (Table 3).
In t e rn a l EEP ROM
The MAX1458 has a 128-bit internal EEPROM arranged
as eight 16-bit words. The four uppermost bits for each
register are reserved. The internal EEPROM is used to
store the following (also shown in the memory map in
Table 4):
R
is a hig h-te mp c o re s is tor with a TC of
TEMP
+4600ppm/°C and a nominal resistance of 100kΩ at
+25°C. This resistor can be used with certain sensor
types that require an external temperature sensor.
_______________________________________________________________________________________
7
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Table 4. EEPROM Memory Map
EE Address
Contents
0F
1
0E
0
0D
0
0C
0
0B
0A
1A
2A
3A
09
19
29
39
08
18
28
38
07
17
27
37
06
05
04
14
24
34
03
13
23
33
02
12
22
32
01
11
21
31
00
Configuration
EE Address
Contents
1F
1
1E
0
1D
0
1C
1
1B
16
15
10
MSB
Offset
LSB
MAX1458
EE Address
Contents
2F
1
2E
0
2D
1
2C
0
2B
26
25
20
MSB
Offset TC
LSB
EE Address
Contents
3F
1
3E
0
3D
1
3C
1
3B
36
35
30
MSB
FSO
LSB
EE Address
Contents
4F
1
4E
1
4D
0
4C
0
4B
4A
49
48
47
46
45
44
43
42
41
40
MSB
FSOTC
LSB
5F
0
5E
0
5D
0
5C
0
5B
0
5A
0
59
0
58
0
57
0
56
0
55
54
0
53
0
52
0
51
0
50
0
Reserved*
0
EE Address
Contents
6F
0
6E
0
6D
0
6C
0
6B
7B
6A
7A
69
79
68
78
67
66
65
64
63
73
62
72
61
71
60
70
User defined bits
EE Address
Contents
7F
0
7E
0
7D
0
7C
0
77
76
75
74
User defined bits
= Reserved Bits
Note: The MAX1458 processes the Reserved Bits in the EEPROM. If these bits are not properly programmed, the configuration
and DAC registers will not be updated correctly.
* The contents of the Reserved EE Address 50–5F must all be reset to zero.
•
•
Configuration register (Table 3)
Configuration Register
The configuration register (Table 3) determines the
PGA gain, the polarity of the offset and offset TC coeffi-
cients, and the coarse offset correction (IRO DAC). It
12-bit calibration coefficients for the Offset and FSO
DACs
•
•
12-bit compensation coefficients for the Offset TC
and FSOTC DACs
a ls o e na b le s /d is a b le s inte rna l re s is tors (R
a nd
FTC
R
).
ISRC
Two general-purpose registers available to the user
for storing process information such as serial num-
ber, batch date, and check sums
DAC Registers
The Offset, Offset TC, FSO, and FSOTC registers store
the coefficients used by their respective calibration/
compensation DACs.
Program the EEPROM one bit at a time. The bits have
addresses from 0 to 127 (7F hex).
8
_______________________________________________________________________________________
1 % -Ac c u ra t e , Dig it a lly Trim m e d
S e n s o r S ig n a l Co n d it io n e r
MAX1458
Data Input/Output (DIO)
The DIO line is an input/output pin used to issue com-
ma nd s to the MAX1458 (inp ut mod e ) or re a d the
EEPROM contents (output mode).
De t a ile d De s c rip t io n o f t h e Dig it a l Lin e s
Chip-Select (CS) and Write-Enable (WE)
CS is used to enable OUT, control serial communica-
tion, and force an update of the configuration and DAC
registers.
In inp ut mod e (the d e fa ult mod e ), d a ta on DIO is
latched on each rising edge of SCLK. Therefore, data
on DIO must be stable at the rising edge of SCLK and
should transition on the falling edge of SCLK.
•
A low on CS d is a b le s s e ria l c ommunic a tion a nd
places OUT in a high-impedance state.
•
A transition from low to high on CS forces an update
of the c onfig ura tion a nd DAC re g is te rs from the
EEPROM when the “U” bit is zero.
DIO will switch to output mode after receiving a “READ
EEPROM” c omma nd , a nd will re turn the d a ta b it
addressed by the digital value in the “READ EEPROM”
command. After a low-to-high transition or CS, DIO
returns to input mode and is ready to accept more
commands.
•
•
A transition from high to low on CS terminates pro-
gramming mode.
A logic high on CS enables OUT and serial commu-
nication (see Communication Protocol section).
Co m m u n ic a t io n P ro t o c o l
To initiate communication, the first six bits on DIO after
CS tra ns itions from low to hig h must b e 1010U0
(defined as the INIT SEQUENCE). The MAX1458 will
then begin accepting 16-bit control words (Figure 4).
WE controls the refresh rate for the internal configura-
tion and DAC registers from the EEPROM and enables
the erase/write operations. If communication has been
initiated (see Communication Protocol section), internal
register refresh is disabled.
If the INIT SEQUENCE is not detected, all subsequent
data on DIO is ignored until CS again transitions from
low to high and the correct INIT SEQUENCE is received.
• A low on WE disables the erase/write operations and
also disables register refreshing from the EEPROM.
• A high on WE selects a refresh rate of approximately
400 time s p e r s e c ond a nd e na b le s EEPROM
erase/write operations.
The “U” bit of the INIT SEQUENCE controls the updat-
ing of the DACs and configuration register from the
internal EEPROM. If this bit is low (U = 0), all four inter-
nal DACs and the configuration register will be updated
from the EEPROM on the next rising edge of CS (this is
also the default on power-up). If the “U” bit is high, the
DACs and configuration register will not be updated
from the internal EEPROM; they will retain their current
va lue on a ny s ub s e q ue nt CS ris ing e d g e . The
MAX1458 continues to accept control words until CS is
brought low.
• It is recommended that WE be connected to V
SS
after the MAX1458 EEPROM has been programmed.
SCLK (Serial Clock)
SCLK must be driven externally and is used to input
commands to the MAX1458 and read EEPROM con-
tents. Input data on DIO is latched on the rising edge of
SCLK. Noise on SCLK may disrupt communication. In
nois y e nvironme nts , p la c e a c a p a c itor (0.01µF)
between SCLK and V
.
SS
CS
SCLK
DIO
16 CLK
CYCLES
16 CLK
CYCLES
n x 16 CLK
CYCLES
t
= 200µs
MIN
X
1
0
1
0
U
0
D0 D1 CM3
D0 D1 CM3
BEGIN
PROGRAMMING
SEQUENCE
CONTROL
WORD
CONTROL
WORD
CONTROL
WORDS
Figure 4. Communication Sequence
_______________________________________________________________________________________
9
1 % -Ac c u ra t e , Dig it a lly Trim m e d
S e n s o r S ig n a l Co n d it io n e r
Co n t ro l Wo rd s
After receiving the INIT SEQUENCE on DIO, the MAX1458
begins latching in 16-bit control words, LSB first (Figure 5).
Table 5. MAX1458 Commands
HEX
CODE
FUNCTION
CM3 CM2 CM1 CM0
The first 12 bits (D0–D11) represent the data field. The
last four bits of the control word (the MSBs, CM0–CM3)
are the command field. The MAX1458 supports the
commands listed in Table 5.
ERASE EEPROM
1h
2h
0
0
0
0
0
1
1
0
BEGIN EEPROM WRITE at
Address
READ EEPROM at Address
Maxim Reserved
3h
4h
0
0
0
1
1
0
1
0
ERASE EEPROM Command
When an ERASE EEPROM command is issued, all of
the memory locations in the EEPROM are reset to a
logic “0.” The data field of the 16-bit word is ignored.
MAX1458
END EEPROM WRITE at
Address
5h
8h
0
1
1
0
0
0
1
0
Important: An internal charge pump develops voltages
greater than 20V for EEPROM programming operations.
The EEPROM control logic requires 50ms to erase the
EEPROM. After sending a WRITE or ERASE command,
failure to wait 50ms before issuing another command
may result in data being accidentally written to the
EEPROM. The maximum number of ERASE EEPROM
cycles should not exceed 100.
WRITE Data to
Configuration Register
WRITE Offset DAC
WRITE Offset TC DAC
WRITE FSO DAC
WRITE FSOTC DAC
No Operation
9h
Ah
Bh
Ch
0h
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
BEGIN EEPROM WRITE Command
The BEGIN EEPROM WRITE command stores a logic
high at the memory location specified by the lower
seven bits of the data field (A0–A6). The higher bits of
the data field (A7–A11) are ignored (Figure 6). Note that
to write to the internal EEPROM, WE and CS must be
6h,
7h,
Dh,
Eh,
Fh
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
Load Register
SCLK
DATA
COMMAND
MSB LSB
LSB
MSB
D0 D1 D2
D6 D7 D8
16-BIT CONFIGURATION WORD
DIO
D3 D4 D5
D9 D10 D11 CM0 CM2 CM2 CM3
LSB
MSB LSB
MSB
Figure 5. Control-Word Timing Diagram
CS
WE
16 CLK
CYCLES
16 CLK
CYCLES
n x 16 CLK
CYCLES
t
= 200µs
MIN
SCLK
DIO
X
1
0
1
0
U
0
A0 A1 CM3
A0 A1 CM3
D0 D1 CM3
BEGIN
EEPROM
WRITE
END
EEPROM
WRITE
n
T
WRITE
t
WAIT
INIT SEQUENCE
COMMAND
WORDS
Figure 6. Timing Diagram for WRITE EEPROM Operation
10 ______________________________________________________________________________________
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S e n s o r S ig n a l Co n d it io n e r
MAX1458
high. In addition, the EEPROM should only be written to
at T = +25°C and V = 5V.
8) Wait 1ms.
A
DD
9) Return to Step 5 until all necessary bits have been
set.
Writing to the internal EEPROM is a time-consuming
process and should only be required once. All calibra-
tion/compensation coefficients are determined by writ-
ing directly to the DAC and configuration registers. Use
the following procedure to write these calibration/com-
pensation coefficients to the EEPROM:
10) Read EEPROM to verify that the correct calibra-
tion/compensation coefficients have been stored.
READ EEPROM Command
The READ EEPROM command returns the bit stored at
the memory location addressed by the lower seven bits
of the data field (A0–A6). The higher bits of the data
field (A7–A11) are ignored. Note that after a read com-
mand has been issued, the DIO lines become an out-
put and the state of the addressed EEPROM location
1) Issue an ERASE EEPROM command.
2) Wait 50ms (t
).
WRITE
3) Is s ue on END EEPROM WRITE c omma nd a t
address 00h.
will be available on DIO 200µs (t
) after the falling
READ
4) Wait 1ms (t
).
WAIT
edge of the 16th SCLK cycle (Figure 8). After issuing
the READ EEPROM command, DIO returns to input
mode on the falling edge of CS. Reading the entire
EEPROM requires the READ EEPROM command be
issued 128 times.
5) Is s ue a BEGIN EEPROM WRITE c omma nd
(Figure 7) at the address of the bit to be set.
6) Wait 50ms.
7) Issue an END EEPROM WRITE command (Figure 7)
using the same address as in Step 5.
SCLK
DATA
COMMAND
LSB
MSB LSB
MSB
0
DIO
A0 A1 A2 A3 A4 A5 A6
0
0
0
0
0
0
0
1
16-BIT COMMAND WORD – BEGIN EEPROM WRITE AT ADDRESS COMMAND
LSB
LSB
MSB
SCLK
DATA
COMMAND
MSB LSB
MSB
0
DIO
A0 A1 A2 A3 A4 A5 A6
0
0
0
0
0
1
1
0
16-BIT COMMAND WORD – END EEPROM WRITE AT ADDRESS COMMAND
LSB
MSB
Figure 7. Begin WRITE EEPROM and End WRITE EEPROM Timing Diagrams
CS
t
= 200µs
MIN
16 CLOCK CYCLES
SCLK
DIO
t
READ
X
1
0
1
0
U
0
A0 A1 A2 A3 A4 A5 A6
0
0
0
0
0
1
1
0
0
X
EE DATA
X
READ EEPROM AT ADDRESS COMMAND
DIO IS AN INPUT PIN
INIT SEQUENCE
DIO IS AN
OUTPUT PIN
Figure 8. READ EEPROM Timing Diagram
______________________________________________________________________________________ 11
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S e n s o r S ig n a l Co n d it io n e r
Writing to the Configuration and DAC Registers
Co e ffic ie n t In it ia liza t io n
Select the resistor values and the PGA gain to prevent
overload of the PGA and bridge current source. These
values depend on sensor behavior and require some
sensor characterization data, which may be available
from the sensor manufacturer. If not, the data can be
generated by performing a two-temperature, two-pres-
sure sensor evaluation. The required sensor information
is shown in Table 6 and can be used to obtain the val-
ues for the parameters listed in Table 7.
When writing to the configuration register or directly to
the internal 12-bit DACs, the data field (D0–D11) con-
tains the data to be written to the respective register.
Note that all four DACs and the configuration register
can be updated without toggling the CS line. Every
register write command must be followed by a LOAD
REGISTER command.
MAX1458
__________Ap p lic a t io n s In fo rm a t io n
P o w e r-Up
Table 6. Sensor Information for Typical
PRT
At power up, the following occurs:
1) The DAC and configuration registers are reset to
zero.
SENSOR
DESCRIPTION
TYPICAL
VALUES
PARAMETER
Rb(T)
2) CS transitions from low to high after power-up (an
internal pull-up resistor ensures that this happens if
CS is left unconnected), and the EEPROM contents
are read and processed.
Bridge Impedance
5kΩ at +25°C
Bridge Impedance
Tempco
TCR
2600ppm/°C
1.5mV/V per
PSI at +25°C
3) The DAC and configuration registers are updated
either once or approximately 400 times per second
(as determined by the state of WE).
S(T)
TCS
O(T)
Sensitivity
Sensitivity Tempco
Offset
-2100ppm/°C
4) The MAX1458 begins accepting commands in a ser-
ial format on DIO immediately after receiving the INIT
SEQUENCE.
12mV/V at
+25°C
-1000ppm/°C
of FSO
OTC
S(p)
Offset Tempco
The MAX1458 is shipped with all memory locations in
the inte rna l EEPROM uninitia lize d . The re fore , the
MAX1458 must be programmed for proper operation.
Sensitivity Linearity Error
as % FSO, BSLF
(Best Straight-Line Fit)
0.1% FSO,
BSLF
Co m p e n s a t io n P ro c e d u re
The following compensation procedure was used to
obtain the results shown in Figure 9 and Table 8. It
assumes a pressure transducer with a +5V supply and
an output voltage that is ratiometric to the supply volt-
P
Minimum Input Pressure
Maximum Input Pressure
0 PSI
MIN
P
10 PSI
MAX
Selecting R
ISRC
age. The desired offset voltage (V
and the desired FSO voltage (V
is 4V; thus the full-scale output voltage (V
at P
) is 0.5V,
Whe n us ing a n e xte rna l re s is tor, us e the e q ua tion
OUT
OUT(PMAX)
MIN
- V
OUT
)
below to determine the value of R , and place the
OUT(PMIN)
ISRC
at P
)
resistor between ISRC and V . Since the 12-bit FSO
MAX
SS
will be 4.5V (refer to Figure 1). The procedure requires
a minimum of two test pressures (e.g., zero and full
DAC provides considerable dynamic range, the R
ISRC
value need not be exact. Generally any resistor value
within ±50% of the calculated value is acceptable. If
scale) at two arbitrary test temperatures, T and T .
1
2
Ideally, T and T are the two points where we wish to
both the internal resistors R
and R
are used, set
1
2
ISRC
FTC
perform best linear fit compensation. The following out-
lines a typical compensation procedure:
the IRS bit at EEPROM address bit 7 high. Otherwise,
set IRS low and connect external resistors as shown in
Figure 10.
1) Perform Coefficient Initialization
2) Perform FSO Calibration
R
≈ 14 x Rb(T1)
ISRC
≈ 14 x 5kΩ = 70kΩ
3) Perform FSOTC Compensation
4) Perform Offset TC Compensation
5) Perform Offset Calibration
where Rb(T) is the sensor input impedance at tempera-
ture T1 (+25°C in this example).
12 ______________________________________________________________________________________
1 % -Ac c u ra t e , Dig it a lly Trim m e d
S e n s o r S ig n a l Co n d it io n e r
MAX1458
where S is the sensor sensitivity at T1, V
sensor excitation voltage (initially 2.5V), and ∆P is the
maximum pressure differential.
is the
BDRIVE
Table 7. Compensation Components and
Values
Then calculate the ideal gain using the following formula,
and select the nearest gain setting from Table 2:
PARAMETER
DESCRIPTION
Internal (approximately 75kΩ) or user-
supplied resistor that programs the nomi-
nal sensor excitation current.
R
ISRC
OUTFSO
A
=
=
PGA
SensorFSO
4V
Internal (approximately 75kΩ) or user-
supplied resistor that compensates
FSO TC errors.
= 106V/V
R
FTC
0.0375V
A
Programmable-gain amplifier gain
PGA
where OUTFSO is the desired calibrated transducer
full-span output voltage, and SensorFSO is the sensor
full-span output voltage at T1.
Input-referred offset correction DAC
value
IRO
IRO Sign
IRS
Input-referred offset sign bit
Internal resistor selection bit
Offset correction DAC coefficient
Offset sign bit
In this example, a PGA value of 2 (gain of +95V/V) is
the best selection.
OFF COEF
OFF Sign
Determining Input-Referred OFFSET (IRO)
The input-referred offset register is used to null any
front-end sensor offset errors prior to amplification by
the PGA. This reduces the possibility of saturating the
PGA and maximizes the useful dynamic range of the
PGA (particularly at the higher gain values.)
OFFTC COEF
OFFTC Sign
FSO COEF
FSOTC COEF
Offset TC compensation DAC coefficient
Offset TC sign bit
FSO trim DAC coefficient
FSO TC compensation DAC coefficient
First, calculate the ideal IRO correction voltage using
the following formula, and select the nearest setting
from Table 1:
Selecting R
FTC
Whe n us ing a n e xte rna l re s is tor, us e the e q ua tion
below to determine the value for R , and place the
resistor between ISRC and FSOTC. Since the 12-bit
FSOTC DAC provides considerable dynamic range, the
FTC
IROideal = - O T1 x V
T1
(
)
(
)
[
]
BDRIVE
= - 0.012V/V x 2.5V
(
)
R
value need not be exact. Generally, any resistor
FTC
= - 30mV
value within ±50% of the calculated value is accept-
able.
where IROideal is the exact voltage required to perfect-
ly null the sensor, O(T1) is the sensor offset voltage in
R
x 500ppm/°C
ISRC
V/V at +25°C, and V
(T1) is the nominal sensor
R
BDRIVE
FTC
TCR - | TCS |
70kΩ x 500ppm/°C
excitation voltage at +25°C. In this example, 30mV
must be subtracted from the amplifier front end to null
the sensor perfectly. From Table 1, select an IRO value
of 3 to set the IRO DAC to 27mV, which is nearest the
ideal value. To subtract this value, set the IRO sign bit
to 0. The residual output-referred offset error will be
corrected later with the Offset DAC.
= 70kΩ
2600ppm/ °C - | -2100ppm/ °C |
This approximation works best for bulk, micromachined,
silicon PRTs. Negative values for R indicate uncon-
FTC
ventional sensor behavior that cannot be compensated
by the MAX1458 without additional external circuitry.
Determining OFFTC COEF Initial Value
Generally, OFFTC COEF can initially be set to 0, since
the offset TC error will be compensated in a later step.
Howe ve r, s e ns ors with la rg e offs e t TC e rrors ma y
require an initial coarse offset TC adjustment to prevent
the PGA from saturating during the compensation pro-
cedure as temperature is increased. An initial coarse
offset TC adjustment is required for sensors with an off-
set TC greater than about 10% of the FSO. If an initial
Selecting the PGA Gain Setting
To s e le c t the PGA g a in s e tting , firs t c a lc ula te
SensorFSO, the sensor full-span output voltage at T1:
SensorFSO = S x V
x ∆P
BDRIVE
= 1.5mV/V per PSI x 2.5V x 10 PSI
= 0.0375V
______________________________________________________________________________________ 13
1 % -Ac c u ra t e , Dig it a lly Trim m e d
S e n s o r S ig n a l Co n d it io n e r
coarse offset TC adjustment is required, use the follow-
ing equation:
Th re e -S t e p FS OTC Co m p e n s a t io n
Step 1
Us e the following p roc e d ure to d e te rmine FSOTC
COEF. Four variables, A–D, will be used.
4096 x ∆V
T
( )
OUT
OFFTC COEF =
∆V
T x 2.3
( )
1) Name the existing FSO DAC coefficient “A”.
2) Change FSOTC DAC to 3000.
BDRIVE
4096 x OTC x FSO x ∆T
(
)
3) Ad jus t FSO DAC until V
(T1) is e q ua l to
BDRIVE
TCS x V
x 2.3 x ∆T
BDRIVE
V
(T1).
BIDEAL
MAX1458
4096 x -1000ppm/°C x 4V
(
)
4) Name the existing FSO DAC coefficient “B”.
=
= 1357
-2100ppm/°C x 2.5V x 2.3
5) Readjust the offset voltage (by adjusting the Offset
DAC), if required, to 0.5V.
where OTC is the sensor offset TC error as a ppm/°C of
OUTFSO (Table 6), ∆T is the operating temperature
range in °C, and OFFTC COEF is the numerical decimal
value to be loaded into the DAC. For positive values,
set the OFFTC sign bit high; for negative values, set the
OFFTC sign bit low. If the absolute value of the OFFTC
COEF is larger than 4096, the sensor has a very large
offset TC error, which the MAX1458 is unable to com-
pletely correct.
At this point, it is important that no other changes be
made to the Offset or Offset TC DACs until the Offset
TC Compensation step has been completed.
Step 2
To complete linear FSOTC compensation, take data
measurements at a second temperature, T2 (T2 > T1).
Perform the following steps:
1) Measure the full-span output (measuredV
(T2).
FSO
FS O Ca lib ra t io n
Perform FSO calibration at room temperature with a full-
scale sensor excitation.
2) Calculate V
(T2) using the following equation:
BIDEAL
V
T2 = V
x
(
)
BIDEAL
BDRIVE
1) Set FSOTC COEF to 1000.
desiredV
- measuredV
T2
(
)
FSO
FSO
2) At T1, adjust FSO DAC until V
is about 2.5V.
1 +
BDRIVE
measuredV
T2
(
)
FSO
3) Adjust Offset DAC (and OFFSET sign bit, if needed)
until the T1 offs e t volta g e is 0.5V (s e e OFFSET
Calibration section).
3) Set V
(T2) by adjusting the FSO DAC.
BIDEAL
4) Name the current FSO DAC coefficient “D”.
5) Change FSOTC DAC to 1000.
4) Measure the full-span output (measuredV
).
FSO
5) Calculate the ideal bridge voltage, V
using the following equation:
(T1),
BIDEAL
6) Ad jus t FSO DAC until V
is e q ua l to
BDRIVE
V
(T2).
BIDEAL
V
T1 = V
x
(
)
BIDEAL
BDRIVE
7) Name the FSO DAC coefficient “C”.
desiredV
- measuredV
T1
)
(
FSO
FSO
Step 3
1 +
Insert the data previously obtained from Steps 1 and 2
into the following equation to compute FSOTC COEF:
measuredV
T1
(
)
FSO
Note: If V
voltage swing of (V + 1.3V) to (V
the PGA g a in s e tting . If V
decrease the PGA gain setting by one step and return
to Step 2. If V (T1) is too high, increase the PGA
(T1) is outside the allowable bridge
BIDEAL
1000 B- D + 3000 C - A
(
)
(
)
- 1.3V), readjust
(T1) is too low,
SS
DD
BIDEAL
FSOTC COEF =
B- D + C - A
(
)
(
)
BIDEAL
1) Load this FSOTC COEF value into the FSOTC DAC.
2) Adjust the FSO DAC until V (T2) is equal to
gain setting by one step and return to Step 2.
BDRIVE
6) Set V (T1) by adjusting the FSO DAC.
BIDEAL
V
(T2).
BIDEAL
7) Readjust Offset DAC until the offset voltage is 0.5V
(see OFFSET Calibration section).
This completes both FSO calibration and FSO TC com-
pensation.
14 ______________________________________________________________________________________
1 % -Ac c u ra t e , Dig it a lly Trim m e d
S e n s o r S ig n a l Co n d it io n e r
MAX1458
4) If NewOFFTC COEF is negative, set the SOTC bit
low; otherwise, set it high.
Offs e t TC Co m p e n s a t io n
The offset voltage at T1 was previously set to 0.5V;
therefore, any variation from this voltage at T2 is an
offset TC error. Perform the following steps:
Offset TC Compensation is now complete.
OFFS ET Ca lib ra t io n
At this point the sensor should still be at temperature
T2. The final offset adjustment can be made at T2 or T1
by adjusting the Offset DAC (and optionally the offset
1) Measure the offset voltage at T2.
2) Use the following equation to compute the correc-
tion required:
sign bit, SOFF) until the output (V
) reads 0.5V
OUT(PMIN)
NewOFFTC COEF = CurrentOFFTC COEF +
at zero input pressure. Use the following procedure:
1) Set Offset DAC to zero (Offset COEF = 0).
2) Measure the voltage at OUT.
4096 V
T1 - V
T2
(
(
)
(
)
]
[
OFFSET
OFFSET
2.3 V
T1 - V
T2
)
(
)
]
[
BDRIVE
BDRIVE
3) If V
is greater than the desired offset voltage
OUT
(0.5V in this example), set SOFF low; otherwise set it
high.
Note : Curre ntOFFTC COEF is the c urre nt va lue
stored in the Offset TC DAC. If the Offset TC sign bit
(SOTC) is low, this number is negative.
4) Increase Offset COEF until V
equals the desired
OUT
offset voltage.
3) Load this value into the Offset TC DAC.
Offset calibration is now complete. Table 8 and Figure 9
compare an uncompensated input to a typical compen-
sated transducer output.
Table 8. MAX1458 Calibration and Compensation
Typical Uncompensated Input (Sensor)
Typical Compensated Transducer Output
Offset ..........................................................................±80% FSO
V
OUT
...................................................Ratiometric to V at 5.0V
DD
FSO ..................................................................................15mV/V Offset at +25°C ......................................................0.500V ±5mV
Offset TC ......................................................................-17% FSO FSO at +25°C .........................................................4.000V ±5mV
Offset TC Nonlinearity ..................................................0.7% FSO Offset Accuracy Over Temp. Range ..........±28mV (±0.7% FSO)
FSO TC.........................................................................-35% FSO FSO Accuracy Over Temp. Range .............±20mV (±0.5% FSO)
FSO TC Nonlinearity.....................................................0.5% FSO
Temperature Range ...........................................-40°C to +125°C
COMPENSATION TRANSDUCER ERROR
UNCOMPENSATED SENSOR ERROR
0.8
0.6
0.4
0.2
0
30
20
10
0
FSO
FSO
OFFSET
-0.2
-0.4
-0.6
-0.8
OFFSET
-10
-20
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE °(C)
TEMPERATURE (°C)
Figure 9. Comparison of an Uncalibrated Sensor and a Temperature-Compensated Transducer
______________________________________________________________________________________ 15
1 % -Ac c u ra t e , Dig it a lly Trim m e d
S e n s o r S ig n a l Co n d it io n e r
Ra t io m e t ric Ou t p u t Co n fig u ra t io n
Te s t S ys t e m Co n fig u ra t io n
Ratiometric output configuration provides an output that
is proportional to the power-supply voltage. When used
with ratiometric A/D converters, this output provides
digital pressure values independent of supply voltage.
Mos t a utomotive a nd s ome ind us tria l a p p lic a tions
require ratiometric outputs.
The MAX1458 is designed to support an automated
production pressure-temperature test system with inte-
g ra te d c a lib ra tion a nd te mp e ra ture c omp e ns a tion.
Figure 11 shows the implementation concept for a low-
cost test system capable of testing up to 12 transducer
modules connected in parallel. Three-state outputs on
the MAX1458 allow for parallel connection of transduc-
ers. The test system shown in Figure 11 includes a
dedicated test bus consisting of five wires:
The MAX1458 provides a high-performance ratiometric
output with a minimum number of external components
(Figure 10). These external components include the fol-
lowing:
MAX1458
• Two power-supply lines
•
•
One power-supply bypass capacitor (C1)
• One analog output voltage line from the transducers
to a system digital voltmeter
Two optional resistors, one from FSOTC to ISRC, and
another from ISRC to V , depending on the sensor
• Two serial-interface lines: DIO (input/output) and
SS
type
SCLK (clock)
•
One optional capacitor C2 from BDRIVE to V
For simultaneous testing of more than 12 sensor mod-
ules, use buffers to prevent overloading the data bus. A
digital multiplexer controls the chip-select signal for
each transducer.
SS
+5V
V
DD
C1
0.1µF
BDRIVE
MAX1458
LIMIT
OUT
C2
0.1µF
INP
PGA
Σ
INM
SENSOR
ISRC
V
DD
FSOTC
TEMP
R
FTC
R
ISRC
R
FTC
R
A = 1
ISRC
128-BIT
EEPROM
V
SS
CS
WE
DIGITAL
INTERFACE
SCLK
DIO
TEMP
V
SS
Figure 10. Basic Ratiometric Output Configuration
16 ______________________________________________________________________________________
1 % -Ac c u ra t e , Dig it a lly Trim m e d
S e n s o r S ig n a l Co n d it io n e r
MAX1458
CS[1:N]
DIGITAL
CS1
CS2
CSN
MULTIPLEXER
MODULE 1
MODULE 2
MODULE N
CS
CS
CS
BDRIVE
BDRIVE
INP
BDRIVE
INP
INP
INM
INM
INM
4
4
MAX1458
SCLK
DIO
SCLK
DIO
SCLK
DIO
OUT
OUT
OUT
+5V
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
VOUT
DVM
SCLK
DIO
TEST
OVEN
Figure 11. Automated Test System Concept
3) MAX1458 Communication Software, which enables
programming of the MAX1458 from a computer (IBM
compatible), one module at a time.
MAX1 4 5 8 Eva lu a t io n
____________________________________ De ve lo p m e n t Kit
To expedite the development of MAX1458 based trans-
ducers and test systems, Maxim has produced the
MAX1458 evaluation kit (EV kit). First-time users of the
MAX1458 are strongly encouraged to use this kit. The
MAX1458 EV kit is designed to facilitate manual pro-
gramming of the MAX1458 and includes the following:
4) Interface Adapter and Cable, which allow the con-
nection of the evaluation board to a PC parallel port.
1) Evaluation Board with a silicon pressure sensor.
2) Design/Applications Manual, which describes in
d e ta il the a rc hite c ture a nd func tiona lity of the
MAX1458. This manual was developed for test engi-
neers familiar with data acquisition of sensor data
and provides sensor compensation algorithms and
test procedures.
______________________________________________________________________________________ 17
1 % -Ac c u ra t e , Dig it a lly Trim m e d
S e n s o r S ig n a l Co n d it io n e r
Fu n c t io n a l Dia g ra m
Ch ip In fo rm a t io n
V
DD
TRANSISTOR COUNT: 7772
SUBSTRATE CONNECTED TO V
SS
BDRIVE
MAX1458
LIMIT
OUT
INP
PGA
MAX1458
Σ
INM
ISRC
V
DD
R
FTC
FSOTC
TEMP
R
A = 1
ISRC
128-BIT
EEPROM
V
SS
CS
WE
DIGITAL
INTERFACE
SCLK
DIO
TEMP
V
SS
18 ______________________________________________________________________________________
1 % -Ac c u ra t e , Dig it a lly Trim m e d
S e n s o r S ig n a l Co n d it io n e r
MAX1458
P a c k a g e In fo rm a t io n
______________________________________________________________________________________ 19
1 % -Ac c u ra t e , Dig it a lly Trim m e d
S e n s o r S ig n a l Co n d it io n e r
NOTES
MAX1458
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1998 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX14591EWA+
Interface Circuit, BICMOS, PBGA8, 1.60 X 0.80 MM, 0.40 MM PITCH, ROHS COMPLIANT, WLP-8
MAXIM
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