MAX1394 [MAXIM]
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/2-Channel Single-Ended, 8-Bit, SAR ADCs; 1.5V至3.6V ， 416ksps ，单通道真差分/双通道单端， 8位， SAR型ADC
| 型号： | MAX1394 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/2-Channel Single-Ended, 8-Bit, SAR ADCs |
| 文件： | 总18页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3720; Rev 0; 11/06
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
General Description
Features
The MAX1391/MAX1394 micropower, serial-output,
8-bit, analog-to-digital converters (ADCs) operate with a
single power supply from +1.5V to +3.6V. These ADCs
feature automatic shutdown, fast wake-up, and a high-
speed 3-wire interface. Power consumption is only
ꢀ 416ksps, 8-Bit Successive-Approximation
Register (SAR) ADCs
ꢀ Single True-Differential Analog Input Channel
with Unipolar-/Bipolar-Selected Input (MAX1391)
0.743mW (V
= +1.5V) at the maximum conversion
DD
ꢀ Dual Single-Ended Input Channel with Channel-
rate of 416ksps. AutoShutdown™ between conversions
reduces power consumption at slower throughput rates.
Selected Input (MAX1394)
ꢀ ±±0. ꢀSB Iꢁꢀ, ±±0. ꢀSB Dꢁꢀ, ꢁo Missing Codes
ꢀ ±±0.2 ꢀSB Total Unadꢂusted Error (TUE)
ꢀ 49dB SIꢁAD at 1±±kHz Input Frequency
ꢀ Single-Supply Voltage (+102V to +306V)
ꢀ ±097mW at 416ksps, 108V
The MAX1391/MAX1394 require an external reference
REF
V
that has a wide range from 0.6V to V . The
DD
MAX1391 provides one true-differential analog input
that accepts signals ranging from 0 to V (unipolar
REF
mode) or
vides two single-ended inputs that accept signals rang-
ing from 0 to V . Analog conversion results are
V
/2 (bipolar mode). The MAX1394 pro-
REF
REF
available through a 5MHz 3-wire SPI™-/QSPI™-/
MICROWIRE™-/digital signal processor (DSP)-compati-
ble serial interface. Excellent dynamic performance,
low voltage, low power, ease of use, and small pack-
age sizes make these converters ideal for portable bat-
tery-powered data-acquisition applications, as well as
other applications that demand low-power consumption
and minimal space.
ꢀ ±0.3±mW at 1±±ksps, 108V
ꢀ 301µW at 1ksps, 108V
ꢀ < 1µA Shutdown Current
ꢀ External Reference (±06V to V
)
DD
ꢀ AutoShutdown Between Conversions
ꢀ SPI-/QSPI-/MICROWIRE-/DSP-Compatible,
The MAX1391/MAX1394 are available in a space-sav-
ing (3mm x 3mm), 10-pin TDFN package. The parts
operate over the extended (-40°C to +85°C) and mili-
tary (-55°C to +125°C) temperature ranges.
3- or 4-Wire Serial Interface
ꢀ Small (3mm x 3mm), 1±-Pin TDFꢁ
Applications
Portable Datalogging
Data Acquisition
Typical Operating Circuit and Pin Configurations appear at
end of data sheet.
Medical Instruments
Battery-Powered Instruments
Process Control
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Ordering Information
PART
TEMP RAꢁGE
-40°C to +85°C
-55°C to +125°C
-40°C to +85°C
-55°C to +125°C
PIꢁ-PACKAGE
10 TDFN-EP*
10 TDFN-EP*
10 TDFN-EP*
10 TDFN-EP*
AꢁAꢀOG IꢁPUTS
1-CH DIFF
1-CH DIFF
2-CH S/E
TOP MARK
PKG CODE
T1033-1
T1033-1
T1033-1
T1033-1
MAX1391ETB
MAX1391MTB**
MAX1394ETB
MAX1394MTB**
AOX
—
APA
—
2-CH S/E
*EP = Exposed pad.
**Future product—contact factory for availability.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
ABSOꢀUTE MAXIMUM RATIꢁGS
DD
V
to GND..............................................................-0.3V to +4V
Operating Temperature Ranges
SCLK, CS, OE, CH1/CH2, UNI/BIP,
DOUT to GND.........................................-0.3V to (V
AIN+, AIN-, AIN1, AIN2, REF to GND ........-0.3V to (V
MAX139_E_ _...................................................-40°C to +85°C
MAX139_M_ _................................................-55°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
+ 0.3V)
+ 0.3V)
DD
DD
Maximum Current into Any Pin ......................................... 50mA
Continuous Power Dissipation (T = +70°C)
A
10-Pin TDFN (derate 18.5mW/°C above +70°C) ....1481.5mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
EꢀECTRICAꢀ CHARACTERISTICS
(V
= +1.5V to +3.6V, V
= V , C
= 0.1µF, f
= 5MHz, T = T
to T
, unless otherwise noted. Typical values are at
MAX
DD
REF
DD
REF
SCLK
A
MIN
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOꢀ
COꢁDITIOꢁS
MIꢁ
TYP
MAX
UꢁITS
DC ACCURACY (ꢁote .)
Resolution
8
Bits
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
0.2
0.2
DNL
No missing code overtemperature
Offset nulled
0.15
0.15
0.25
Gain Error
Total Unadjusted Error
TUE
Offset-Error Temperature
Coefficient
25
mLSB/°C
mLSB/°C
LSB
Gain-Error Temperature
Coefficient
0.06
0.05
Channel-to-Channel Offset
Matching
MAX1394 only
MAX1394 only
Channel-to-Channel Gain
Matching
0.05
0.1
LSB
Input Common-Mode Rejection
CMR
V
= 0 to V , MAX1391 only
DD
mV/V
CM
DYꢁAMIC SPECIFICATIOꢁS (ꢁote 3)
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
SINAD
49
49
dB
dB
SNR
THD
Total Harmonic Distortion
Spurious-Free Dynamic Range
-65
-66
dBc
dBc
SFDR
f
f
= 98kHz at -6.5dBFS,
= 102kHz at -6.5dBFS
IN1
IN2
Intermodulation Distortion
IMD
-73
dB
Channel-to-Channel Crosstalk
Full-Power Bandwidth
MAX1394 only
-3dB point
-70
4
dB
MHz
MAX1391
MAX1394
200
150
Full-Linear Bandwidth
SINAD > 48dB
kHz
COꢁVERSIOꢁ RATE
Conversion Time
t
9 clock cycles per conversion
1.8
µs
CONV
.
_______________________________________________________________________________________
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
EꢀECTRICAꢀ CHARACTERISTICS (continued)
(V
= +1.5V to +3.6V, V
= V , C
= 0.1µF, f
= 5MHz, T = T
to T
, unless otherwise noted. Typical values are at
MAX
DD
REF
DD
REF
SCLK
A
MIN
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOꢀ
COꢁDITIOꢁS
MIꢁ
TYP
MAX
UꢁITS
12 clocks per conversion, includes power-
up acquisiton and conversion time
Throughput Rate
416
ksps
Power-Up and Acquisition Time
Aperture Delay
t
Three SCLK cycles
600
ns
ns
ACQ
t
8
AD
Aperture Jitter
t
AJ
30
ps
Serial-Clock Frequency
f
0.1
0
5.0
MHz
CLK
AꢁAꢀOG IꢁPUTS (AIꢁ+, AIꢁ-, AIꢁ1, AIꢁ.)
Unipolar
V
REF
Input Voltage Range
V
V
V
IN
Bipolar, MAX1391 only, (AIN+ - AIN-)
-V
/2
+V
/2
REF
REF
Common-Mode Input Voltage
Range
V
Bipolar, MAX1391 only, [(AIN+) + (AIN-)] / 2
0
V
DD
CM
Channel not selected, or conversion
stopped, or in shutdown mode
Input Leakage Current
1.5
µA
pF
Input Capacitance
16
REFEREꢁCE IꢁPUT (REF)
V
0.05
+
DD
REF Input Voltage Range
V
0.6
V
REF
REF Input Capacitance
REF DC Leakage Current
REF Input Dynamic Current
24
0.025
20
pF
µA
µA
2.5
60
416ksps
DIGITAꢀ IꢁPUTS (SCꢀK, CS, OE, CH1/CH., UꢁI/BIP)
0.3 x
Input-Voltage Low
Input-Voltage High
V
V
V
IL
V
DD
0.7 x
V
IH
V
DD
0.06 x
Input Hysteresis
V
V
DD
Input Leakage Current
Input Capacitance
I
Inputs at GND or V
CS, OE
1
µA
pF
IL
DD
1
C
IN
CH1/CH2, UNI/BIP
12.5
DIGITAꢀ OUTPUT (DOUT)
Output-Voltage Low
0.1 x
V
I
= 2mA
SINK
V
V
OL
V
DD
0.9 x
Output-Voltage High
V
I
I = 2mA
SOURCE
OH
V
DD
Tri-State Leakage Current
Tri-State Output Capacitance
POWER SUPPꢀY
OE = V
OE = V
1
µA
pF
LT
DD
DD
C
10
OUT
Positive Supply Voltage
V
1.5
3.6
V
DD
_______________________________________________________________________________________
3
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
EꢀECTRICAꢀ CHARACTERISTICS (continued)
(V
= +1.5V to +3.6V, V
= V , C
= 0.1µF, f
= 5MHz, T = T
to T
, unless otherwise noted. Typical values are at
MAX
DD
REF
DD
REF
SCLK
A
MIN
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOꢀ
COꢁDITIOꢁS
MIꢁ
TYP
125
150
520
710
5
MAX
150
200
600
800
10
UꢁITS
µA
V
V
V
V
= 1.6V
DD
DD
DD
DD
f
f
= 100ksps
SAMPLE
= 3V
= 1.6V
= 3V
Positive Supply Current (Note 4)
Power-Supply Rejection
I
= 416ksps
DD
SAMPLE
Power-down mode (Note 5)
Power-down mode (Note 6)
0.2
150
2.5
PSR
V
= 1.6V to 3.6V, full-scale input (Note 7)
1000
µV/V
DD
TIMIꢁG CHARACTERISTICS
(V
= +1.5V to +3.6V, V
= V , C
= 0.1µF, f
= 5MHz, T = T
to T
, unless otherwise noted. Typical values are at
MAX
DD
REF
DD
REF
SCLK
A
MIN
T
A
= +25°C.) (Figure 1)
PARAMETER
SYMBOꢀ
COꢁDITIOꢁS
MIꢁ
200
90
90
80
0
TYP
MAX
UꢁITS
ns
SCLK Clock Period
t
10,000
CP
CH
SCLK Pulse-Width High
SCLK Pulse-Width Low
t
ns
t
ns
CL
CS Fall to SCLK Rise Setup
SCLK Rise to CS Fall Ignore
SCLK Fall to DOUT Valid
OE Rise to DOUT Disable
OE Fall to DOUT Enable
t
ns
CSS
CSO
DOV
DOD
t
t
ns
C
= 0 to 30pF
10
80
20
20
ns
LOAD
t
6
9
ns
t
ns
DOE
CSW
OEW
CS Pulse-Width High and Low
OE Pulse-Width High and Low
t
t
80
80
ns
ns
CH1/CH2 Setup Time (to the First
SCLK)
t
MAX1394 only
MAX1394 only
MAX1391 only
MAX1391 only
10
0
ns
ns
ns
ns
CHS
CH1/CH2 Hold Time (to the First
SCLK)
t
CHH
UNI/BIP Setup Time (to the First
SCLK)
t
10
0
UBS
UNI/BIP Hold Time (to the First
SCLK)
t
UBH
ꢁote 1: Devices are production tested at room and +85°C. Specification to -40°C are guaranteed by design.
ꢁote .: V = 1.6V, V
= 1.6V, and V
= 1.6V.
DD
REF
AIN
ꢁote 3: V = 1.6V, V
= 1.6V, V
= 1.6V , f
= 5MHz, f
= 416ksps, and f (sine wave) = 100kHz.
SAMPLE IN
DD
REF
AIN
P-P SCLK
ꢁote 4: All digital inputs swing between V and GND. V
= V , f = 100kHz sine wave, V
= V C = 30pF on DOUT.
DD
REF
DD IN
AIN
REFP-P, LOAD
ꢁote 2: CS = V , OE = UNI/BIP = CH1/CH2 = V
or GND, SCLK is active.
or GND, SCLK is inactive.
DD
DD
DD
ꢁote 6: CS = V , OE = UNI/BIP = CH1/CH2 = V
DD
ꢁote 7: Change in V
at code boundary 254.5.
AIN
4
_______________________________________________________________________________________
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
UNI/BIP OR
CH1/CH2
t
CHS
t
UBS
OE
CS
t
CHH
t
UBH
t
t
OEW
t
t
t
CL
t
CH
CSO
CSS
CSW
SCLK
DOUT
t
t
CP
DOE
t
t
DOD
DOV
HIGH-Z
HIGH-Z
Figure 1. Detailed Serial-Interface Timing Diagram
V
DD
6kΩ
DOUT
DOUT
6kΩ
50pF
GND
50pF
GND
a) HIGH IMPEDANCE TO V , V TO V
,
OH OL
OH
b) HIGH IMPEDANCE TO V , V TO V ,
OL OH OL
AND V TO HIGH IMPEDANCE
OH
AND V TO HIGH IMPEDANCE
OL
Figure 2. Load Circuits for Enable/Disable Times
_______________________________________________________________________________________
2
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
Typical Operating Characteristics
(V
= +1.6V, V
= +1.6V, C
= 0.1µF, C = 30pF, f
= 5MHz. T = +25°C, unless otherwise noted.)
DD
REF
REF
L
SCLK A
INL vs. CODE
INL ERROR vs. REFERENCE VOLTAGE
DNL vs. CODE
0.10
0.08
0.06
0.04
0.02
0
0.10
0.08
0.06
0.04
0.02
0
0.10
0.08
0.06
0.04
0.02
0
V
= 3.6V
DD
V
V
= 1.5V
= 1.5V
DD
REF
MAX INL
-0.02
-0.04
-0.06
-0.08
-0.10
-0.02
-0.04
-0.06
-0.08
-0.10
-0.02
-0.04
-0.06
-0.08
-0.10
MIN INL
1.6
0
32 64 96 128 160 192 224 256
CODE
0.6
1.1
2.1
2.6
3.1
3.6
0
32 64 96 128 160 192 224 256
CODE
REFERENCE VOLTAGE (V)
DNL ERROR vs. REFERENCE VOLTAGE
OFFSET ERROR vs. SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
0.10
0.08
0.06
0.04
0.02
0
400
300
200
100
0
400
300
200
100
0
V
= 3.6V
DD
V
= 1.5V
REF
TEMPERATURE = +25°C
MAX DNL
AIN2
AIN2
-0.02
-0.04
-0.06
-0.08
-0.10
-100
-200
-300
-400
-100
-200
-300
-400
AIN1
AIN1
MIN DNL
V
= 3.6V
DD
0.6
1.1
1.6
2.1
2.6
3.1
3.6
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
SUPPLY VOLTAGE (V)
-55
-25
5
35
65
95
125
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
OFFSET ERROR vs. REFERENCE VOLTAGE
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
400
300
200
100
0
400
300
200
100
0
400
300
200
100
0
V
= 1.5V
V
= 2.6V
DD
REF
TEMPERATURE = +25°C
AIN2
AIN2
-100
-200
-300
-400
-100
-200
-300
-400
-100
-200
-300
-400
AIN1
35
AIN1
V
= 3.6V
3.1
DD
0.6
1.1
1.6
2.1
2.6
3.6
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
SUPPLY VOLTAGE (V)
-55
-25
5
65
95
125
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
Typical Operating Characteristics (continued)
(V
= +1.6V, V
= +1.6V, C
= 0.1µF, C = 30pF, f
= 5MHz. T = +25°C, unless otherwise noted.)
DD
REF
REF
L
SCLK A
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
GAIN ERROR vs. REFERENCE VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
800
700
600
500
400
400
300
200
100
0
600
550
500
450
400
V
SCLK
= 1.5V, C = 33pF
L
V
= 3.6V
REF
DD
f
= 5MHz, f
= 416ksps
SAMPLE
AIN = FULL SCALE, 10kHz SINE WAVE
-100
-200
-300
-400
V
f
= 1.5V, C = 33pF
L
REF
= 5MHz, f
= 416ksps
SCLK
SAMPLE
AIN = FULL SCALE, 10kHz SINE WAVE
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
SUPPLY VOLTAGE (V)
0.6
1.1
1.6
2.1
2.5
3.0
3.5
400
600
-55
-25
5
35
65
95
125
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. CONVERSION RATE
0.5
0.4
0.3
0.2
0.1
0
800
600
400
200
0
2.0
1.6
1.2
0.8
0.4
0
f
A
= 5MHz, f
= FULL SCALE, 100kHz SINE WAVE
= 417ksps
SCLK
IN
SAMPLE
CL = 30pF
V
= V = 3.0V
REF
DD
V
= 3.6V
DD
V
= 1.8V
DD
V
= V = 1.6V
REF
DD
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
VOLTAGE (V)
0
50 100 150 200 250 300 350
(ksps)
-55
-25
5
35
65
95
125
f
TEMPERATURE (°C)
SAMPLE
SAMPLING ERROR
vs. SOURCE IMPEDANCE
SCLK-TO-DOUT TIMING
FFT
100
90
80
70
60
50
40
30
20
10
0
0.3
0.2
0.1
0
0
V
V
f
= 1.6V
= 1.6V
= 417ksps
= 100.4kHz
THD = -79.9dB
SINAD = 49.0dB
SFDR = -71.1dB
DD
REF
S
AIN HIGH-TO-LOW FS TRANSITION
V
= 1.5V
DD
-20
f
IN
-40
-60
-0.1
-0.2
-0.3
V
= 3.6V
DD
AIN HIGH-TO-LOW FS TRANSITION
-80
-100
0
500
1000
1500
2000
2500
0
100
200
300
(pF)
400
500
0
20
40
60
80 100 120 140
SOURCE IMPEDANCE (Ω)
C
FREQUENCY (kHz)
LOAD
_______________________________________________________________________________________
7
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
Pin Description
PIꢁ
ꢁAME
FUꢁCTIOꢁ
MAX1391 MAX1394
Positive Supply Voltage. Connect V to a 1.6V to 3.6V power supply. Bypass V to GND
with a 0.1µF capacitor as close as possible to the device.
DD
DD
1
1
V
DD
2
—
3
—
2
AIN-
AIN2
AIN+
AIN1
GND
Negative Analog Input
Analog Input Channel 2
Positive Analog Input
Analog Input Channel 1
Ground
—
3
—
4
4
External Reference Voltage Input. V
0.1µF capacitor as close as possible to the device.
= 0.6V to (V
+ 0.05V). Bypass REF to GND with a
DD
REF
5
5
—
6
REF
Input-Mode Select. Drive UNI/BIP high to select unipolar input mode. Pull UNI/BIP low to
UNI/BIP select bipolar input mode. In unipolar mode, the output data is in straight binary format. In
bipolar mode, the output data is in two’s complement format.
6
Channel-Select Input. Pull CH1/CH2 low to select channel 1. Drive CH1/CH2 high to select
channel 2.
—
7
CH1/CH2
Active-Low Output Enable. Pull OE low to enable DOUT. Drive OE high to disable DOUT.
Connect to CS to interface with SPI, QSPI, and MICROWIRE devices or set low to interface
7
OE
with DSP devices.
8
9
8
9
CS
Active-Low Chip-Select Input. A falling edge on CS initiates power-up and acquisition.
Serial-Data Output. DOUT changes state on the falling edge of SCLK. DOUT is high
impedance when OE is high.
DOUT
Serial-Clock Input. SCLK drives the conversion process and clocks data out. Acquisition ends
on the 3rd falling edge after the CS falling edge. The LSB is clocked out on the SCLK 11th
falling edge and the device enters AutoShutdown mode (see Figures 8, 9, and 10).
10
10
SCLK
EP
—
—
Exposed Pad. Not internally connected. Connect the exposed pad to GND or leave floating.
V
DD
Detailed Description
The MAX1391/MAX1394 use an input track and hold
(T/H) circuit along with a SAR to convert an analog input
signal to a serial 8-bit digital output data stream. The seri-
al interface provides easy interfacing to microprocessors
and DSPs. Figure 3 shows the simplified functional dia-
gram for the MAX1391 (1 channel, true differential) and
the MAX1394 (2 channels, single ended).
CS
CONTROL
LOGIC AND
TIMING
SCLK
OE
OUTPUT
SHIFT
REGISTER
AIN+ (AIN1)*
AIN- (AIN2)*
INPUT
MUX
AND T/H
8-BIT SAR
ADC
DOUT
True-Differential Analog Input T/H
The equivalent input circuit of Figure 4 shows the
MAX1391/MAX1394 input architecture that is composed
of a T/H, a comparator, and a switched-capacitor DAC.
The T/H enters its tracking mode on the falling edge of
CS (while OE is held low). The positive input capacitor is
connected to AIN+ (MAX1391), or to AIN1 or AIN2
(MAX1394). The negative input capacitor is connected to
AIN- (MAX1391) or GND (MAX1394). The T/H enters its
hold mode on the 3rd falling edge of SCLK and the dif-
REF
UNI/BIP
(CH1/CH2)*
MAX1391
MAX1394
GND
*INDICATES THE MAX1394
Figure 3. Simplified Functional Diagram
8
_______________________________________________________________________________________
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
ference between the sampled positive and negative
input voltages is converted. The time required for the
T/H to acquire an input signal is determined by how
quickly its input capacitance is charged. The required
acquisition time lengthens as the input signal’s source
Analog Input Bandwidth
The ADC’s input-tracking circuitry has a 4MHz full-
power bandwidth, making it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques.
impedance increases. The acquisition time, t
, is the
ACQ
minimum time needed for the signal to be acquired. It is
calculated by the following equation:
Use anti-alias filtering to avoid high-frequency signals
being aliased into the frequency band of interest.
t
≥ 5.6 x (R + R ) x C + t
SOURCE IN IN PU
ACQ
Analog Input Range and Protection
The MAX1391/MAX1394 produce a digital output that
corresponds to the analog input voltage as long as the
analog inputs are within their specified range. When
operating the MAX1391 in unipolar mode (UNI/BIP = 1),
the specified differential analog input range is from 0 to
where
R
is the source impedance of the input signal.
SOURCE
R
= 500Ω, which is the equivalent differential analog
IN
input resistance.
C
= 16pF, which is the equivalent differential analog
IN
V
. When operating in bipolar mode (UNI/BIP = 0),
REF
input capacitance.
the differential analog input range is from -V
/2 to
REF
t
= 400ns.
+V
/2 with a common-mode range of 0 to V . The
PU
REF
DD
MAX1394 has an input range from 0 to V
.
REF
ꢁote: t
is never less than 600ns and any source
ACQ
impedance below 400Ω does not significantly affect the
ADC’s AC performance.
Internal protection diodes confine the analog input volt-
age within the region of the analog power input rails
(V , GND) and allow the analog input voltage to swing
DD
from GND - 0.3V to V
voltages beyond GND - 0.3V and V
+ 0.3V without damage. Input
DD
+ 0.3V forward
DD
bias the internal protection diodes. In this situation, limit
the forward diode current to less than 50mA to avoid
damage to the MAX1391/MAX1394.
REF
GND
Output Data Format
Figures 8, 9, and 10 illustrate the conversion timing for
the MAX1391/MAX1394. Twelve SCLK cycles are
required to read the conversion result and data on
DOUT transitions on the falling edge of SCLK. The con-
version result contains 4 zeros, followed by 8 data bits
with the data in MSB-first format. For the MAX1391, data
is straight binary for unipolar mode and two’s comple-
ment for bipolar mode. For the MAX1394, data is always
straight binary.
DAC
MAX1391
MAX1394
R
SOURCE
AIN2
AIN1 (AIN+)*
CIN+
COMPARATOR
+
ANALOG
SIGNAL
SOURCE
HOLD
-
RIN+
HOLD
CIN-
GND (AIN-)*
RIN-
HOLD
TRACK
V
DD
/2
Transfer Function
Figure 5 shows the unipolar transfer function for the
MAX1391/MAX1394. Figure 6 shows the bipolar trans-
fer function for the MAX1391. Code transitions occur
halfway between successive-integer LSB values.
(*INDICATES THE MAX1391)
Figure 4. Equivalent Input Circuit
_______________________________________________________________________________________
9
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
FULL-SCALE
TRANSITION
FULL-SCALE
TRANSITION
V
REF
2
+FS
=
FS
V
=
REF
7F
7E
FF
FE
FD
ZS = 0
ZS = 0
-FS =
V
256
REF
1 LSB =
-V
REF
2
V
REF
1 LSB =
01
00
FC
FB
256
FF
FE
04
03
81
80
02
01
00
-FS
0
+FS
0
1
2
3
4
FS
-FS + 0.5 LSB
+FS - 1.5 LSB
FS - 1.5 LSB
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
Figure 5. Unipolar Transfer Function
Figure 6. Bipolar Transfer Function
Selecting Unipolar or Bipolar Mode
(MAX1391 Only)
Applications Information
Starting a Conversion
A falling edge on CS initiates the power-up sequence
and begins acquiring the analog input as long as OE is
also asserted low. On the 3rd SCLK falling edge, the
analog input is held for conversion. The most significant
bit (MSB) decision is made and clocked onto DOUT on
the 4th SCLK falling edge. Valid DOUT data is available
to be clocked into the master (microcontroller (µC)) on
the following SCLK rising edge. The rest of the bits are
decided and clocked out to DOUT on each successive
SCLK falling edge. See Figures 8 and 9 for conversion
timing diagrams.
Drive UNI/BIP high to select unipolar mode or pull
UNI/BIP low to select bipolar mode. UNI/BIP can be
connected to V
for logic-high, to GND for logic-low,
DD
or actively driven. UNI/BIP needs to be stable for t
UBS
prior to the first rising edge of SCLK after the CS falling
edge (see Figure 1) for a valid conversion result when
being actively driven.
Selecting Analog Input AIN1 or AIN2
(MAX1394 Only)
Pull CH1/CH2 low to select AIN1 or drive CH1/CH2
high to select AIN2 for conversion. CH1/CH2 can be
connected to V
for logic-high, to GND for logic-low,
DD
Once a conversion has been initiated, CS can go high at
any time. Further falling edges of CS do not reinitiate an
acquisition cycle until the current conversion completes.
Once a conversion completes, the first falling edge of CS
begins another acquisition/conversion cycle.
or actively driven. CH1/CH2 needs to be stable for t
CHS
prior to the first rising edge of SCLK after the CS falling
edge (see Figure 1) for a valid conversion result when
being actively driven.
1± ______________________________________________________________________________________
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
0.1µF capacitor to GND for best performance (see the
AutoShutdown Mode
The ADC automatically powers down on the SCLK
falling edge that clocks out the LSB. This is the falling
edge after the 11th SCLK. DOUT goes low when the
LSB has been clocked into the master (µC) on the 16th
rising SCLK edge.
Typical Operating Circuit).
Serial Interface
The MAX1391/MAX1394 serial interface is fully compati-
ble with SPI, QSPI, and MICROWIRE (see Figure 7). If a
serial interface is available, set the µC’s serial interface
in master mode so the µC generates the serial clock.
Choose a clock frequency between 100kHz and 5MHz.
CS and OE can be connected together and driven
simultaneously. OE can also be connected to GND if the
DOUT bus is not shared and driven independently.
Alternatively, drive OE high to force the MAX1391/
MAX1394 into power-down. Whenever OE goes high,
the ADC powers down and disables DOUT regardless
of CS, SCLK, or the state of the ADC. DOUT enters a
high-impedance state after t
.
DOD
External Reference
SPI and MICROWIRE
When using SPI or MICROWIRE, make the µC the bus
master and set CPOL = 0 and CPHA = 0 or CPOL = 1
and CPHA = 1. (These are the bits in the SPI or
MICROWIRE control register.) Two consecutive 1-byte
reads are required to get the entire 8-bit result from the
ADC. The MAX1391/MAX1394 shut down after clocking
out the LSB. DOUT then becomes high impedance.
DOUT transitions on SCLK’s falling edge and is
clocked into the µC on the SCLK’s rising edge. See
Figure 7 for connections and Figures 8 and 9 for timing
diagrams. The conversion result contains 4 zeros, fol-
lowed by the 8 data bits with the data in MSB-first for-
mat. When using CPOL = 0 and CPHA = 0 or CPOL = 1
and CPHA = 1, the MSB of the data is clocked into the
µC on the SCLK’s fifth rising edge. To be compatible
with SPI and MICROWIRE, connect CS and OE togeth-
er and drive simultaneously.
The MAX1391/MAX1394 use an external reference
between 0.6V and (V
+ 50mV). Bypass REF with a
DD
I/O
OE
CS
SCK
SCLK
MAX1391
MAX1394
MISO
I/O
DOUT
UNI/BIP
(CH1/CH2)*
a) SPI
CS
OE
CS
SCK
SCLK
MAX1391
MAX1394
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 8 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1391/MAX1394 require a minimum of 12
clock cycles from the µC to clock out the 8 bits of data.
See Figure 7 for connections and Figures 8 and 9 for
timing diagrams. The conversion result contains 4
zeros, followed by the 8 data bits with the data in MSB-
first format. The MAX1391/MAX1394 shut down after
clocking out the LSB. DOUT then becomes high imped-
ance. When using CPOL = 0 and CPHA = 0 or CPOL =
1 and CPHA = 1, the MSB of the data is clocked into
the µC on the SCLK’s fifth rising edge. To be compati-
ble with QSPI, connect CS and OE together and drive
simultaneously.
MISO
I/O
DOUT
UNI/BIP
(CH1/CH2)*
b) QSPI
I/O
SK
OE
CS
SCLK
MAX1391
MAX1394
SI
DOUT
I/O
UNI/BIP
(CH1/CH2)*
DSP Interface
Figure 10 shows the timing for DSP operation. Figure
11 shows the connections between the MAX1391/
MAX1394 and several common DSPs.
c) MICROWIRE
*INDICATES THE MAX1394
Figure 7. Common Serial-Interface Connections to the
MAX1391/MAX1394
______________________________________________________________________________________ 11
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
SAMPLING INSTANT
POWER-UP
HOLD AND CONVERT
(t
ADC
STATE
POWER-
DOWN
POWER-DOWN
AND ACQUIRE
(t
)
CONV
)
ACQ
UNI (AIN2)*
UNI/BIP
(CH1/CH2)*
BIPOLAR (AIN1)*
CS = OE
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
HIGH-Z
HIGH-Z
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
*INDICATES THE MAX1394
Figure 8. Serial-Interface Timing for SPI/QSPI (CPOL = CPHA = 1) and MICROWIRE (G6 = 0, G5 = 1)
SAMPLING INSTANT
POWER-UP
ADC
STATE
POWER-
DOWN
HOLD AND CONVERT
(t
POWER-DOWN
AND ACQUIRE
(t
)
CONV
)
ACQ
UNI (AIN2)*
UNI/BIP
(CH1/CH2)*
BIPOLAR (AIN1)*
CS = OE
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
HIGH-Z
HIGH-Z
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
*INDICATES THE MAX1394
Figure 9. Serial-Interface Timing for SPI/QSPI (CPOL = CPHA = 0) and MICROWIRE (G6 = 0, G5 = 0)
1. ______________________________________________________________________________________
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
SAMPLING INSTANT
POWER-UP
HOLD AND CONVERT
POWER-
DOWN
POWER-
DOWN
ADC
AND ACQUIRE
(t
(t
)
CONV
STATE
)
ACQ
OE
UNI/BIP
(CH1/CH2)*
BIPOLAR (AIN1)*
UNI (AIN2)*
CS
FS
16
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
SCLK
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
*INDICATES THE MAX1394
Figure 10. DSP Serial-Timing Diagram
As shown in Figure 11, drive the MAX1391/MAX1394
chip-select input (CS) with the DSP’s frame-sync signal.
OE may be connected to GND or driven independently.
For continuous conversion operation, keep OE low and
make the CS falling edge coincident with the 16th
falling edge of the SCLK.
Figure 13 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at the MAX1391/MAX1394s’ GND
pin or use the ground plane.
High-frequency noise in the power supply (V
)
DD
to GND
degrades the ADC’s performance. Bypass V
DD
with a 0.1µF capacitor as close to the device as possi-
ble. Minimize capacitor lead lengths for best supply
noise rejection. To reduce the effects of supply noise, a
10Ω resistor can be connected as a lowpass filter to
attenuate supply noise.
Unregulated Two-Cell or Single Lithium
LiMnO Cell Operation
2
Low operating voltage (1.5V to 3.6V) and ultra-low-power
consumption make the MAX1391/MAX1394 ideal for low
cost, unregulated, battery-powered applications without
the need for a DC-DC converter. Power the MAX1391/
MAX1394 directly from two alkaline/NiMH/NiCd cells in
series or a single lithium coin cell as shown in the Typical
Operating Circuit.
Exposed Pad
The MAX1391/MAX1394 TDFN package has an
exposed pad on the bottom of the package. This pad is
not internally connected. Connect the exposed pad to
the GND pin on the MAX1391/MAX1394 or leave float-
ing for proper electrical performance.
Fresh alkaline cells have a voltage of approximately
1.5V per cell (3V with 2 cells in series) and approach
end of life at 0.8V (1.6V with 2 cells in series). A typical
2 x AA alkaline discharge curve is shown in Figure 12a.
A typical CR2032 lithium (LiMnO ) coin cell discharge
2
curve is shown in Figure 12b.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. For the MAX1391/
MAX1394, this straight line is between the end points of
the transfer function once offset and gain errors have
been nullified. INL deviations are measured at every
step and the worst-case deviation is reported in the
Electrical Characteristics section.
Layout, Grounding, and Bypassing
For best performance, use PCBs. Board layout must
ensure that digital and analog signal lines are separat-
ed from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
______________________________________________________________________________________ 13
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
3.0
I/O
FSX
FSR
CLKX
CLKR
DR
OE
CS
2.8
2.6
2.4
2.2
2.0
1.8
1.6
MAX1391
MAX1394
SCLK
DOUT
I/O
UNI/BIP
(CH1/CH2)*
a) TMS320C541 CONNECTION DIAGRAM
T = +25°C
A
I/O
TFS
OE
CS
0
100 200 300 400 500 600 700
DAYS
RFS
MAX1391
MAX1394
SCLK
SCLK
DOUT
Figure 12a. Typical 2 x AA Discharge Curve at 100ksps
DR
I/O
UNI/BIP
(CH1/CH2)*
3.0
2.8
2.6
2.4
2.2
2.0
1.8
b) ADSP218x CONNECTION DIAGRAM
I/O
SC2
SLK
SDR
I/O
OE
CS
MAX1391
MAX1394
SCLK
DOUT
UNI/BIP
(CH1/CH2)*
T = +25°C
A
1.6
c) DSP563xx CONNECTION DIAGRAM
0
10
20
30
40
50
*INDICATES THE MAX1394 ONLY
DAYS
Figure 11. Common DSP Connections to the MAX1391/MAX1394
Figure 12b. Typical CR2032 Discharge Curve at 100ksps
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. A DNL error specification less
than 1 LSB guarantees no missing codes and a
monotonic transfer function. For the MAX1391/
MAX1394, DNL deviations are measured at every step
and the worst-case deviation is reported in the
Electrical Characteristics section.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise plus the RMS distortion. RMS
noise includes all spectral components to the Nyquist
frequency excluding the fundamental, the first five har-
monics (HD2–HD6), and the DC offset. RMS distortion
includes the first five harmonics (HD2–HD6).
SIGNAL
2
RMS
SINAD = 20 × log
2
NOISE
+ DISTORTION
RMS
RMS
14 ______________________________________________________________________________________
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
where V is the fundamental amplitude, and V through
1
2
V
are the amplitudes of the 2nd- through 6th-order
harmonics.
6
POWER SUPPLY
Spurious-Free Dynamic Range (SFDR)
V
DD
V
DD
GND
SFDR is a dynamic figure of merit that indicates the
lowest usable input signal amplitude. SFDR is the ratio
of the RMS amplitude of the fundamental (maximum
signal component) to the RMS value of the next-largest
spurious component, excluding DC offset. SFDR is
specified in decibels relative to the carrier (dBc).
STAR
GROUND
POINT
10Ω
(OPTIONAL)
Intermodulation Distortion (IMD)
IMD is the ratio of the RMS sum of the intermodulation
products to the RMS sum of the two fundamental input
tones. This is expressed as:
V
DD
GND
DV
DGND
DD
DIGITAL
CIRCUITRY
DATA
MAX1391/MAX1394
2
2
2
2
V
+ V
+.....+ V
+ V
IMN
IM1
IM2
IM3
IMD = 20 × log
2
2
V
+ V
2
1
Figure 13. Power-Supply Grounding Connections
The fundamental input tone amplitudes (V and V ) are
1 2
at -6.5dBFS. 14 intermodulation products (V _) are
IM
used in the MAX1391/MAX1394 IMD calculation. The
intermodulation products are the amplitudes of the out-
Signal-to-Noise Ratio (SNR)
SNR is a dynamic figure of merit that indicates the con-
verter’s noise performance. For a waveform perfectly
reconstructed from digital samples, the theoretical
maximum SNR is the ratio of the full-scale analog input
(RMS value) to the RMS quantization error (residual
error). The ideal, theoretical minimum analog-to-digital
noise is caused by quantization error only and results
directly from the ADC’s resolution (N bits):
put spectrum at the following frequencies, where f
IN1
and f
are the fundamental input tone frequencies:
IN2
• 2nd-order intermodulation products:
+ f , f - f
f
IN1
IN2 IN2 IN1
• 3rd-order intermodulation products:
2 x f - f , 2 x f - f , 2 x f + f , 2 x f
+ f
+ f
IN1 IN2
IN2 IN1
IN1
IN2
IN2
IN2
IN1
• 4th-order intermodulation products:
3 x f - f , 3 x f - f , 3 x f + f , 3 x f
SNR
= 6.02 x N + 1.76
dB dB
dB[max]
IN1 IN2
IN2 IN1
IN1
IN2
IN1
In reality, there are other noise sources such as thermal
noise, reference noise, and clock jitter that also
degrade SNR. SNR is computed by taking the ratio of
the RMS signal to the RMS noise. RMS noise includes
all spectral components to the Nyquist frequency
excluding the fundamental, the first five harmonics, and
the DC offset.
• 5th-order intermodulation products:
3 x f
3 x f
- 2 x f , 3 x f
- 2 x f , 3 x f
+ 2 x f
,
IN1
IN2
IN2
IN2
IN1
IN1
IN2
+ 2 x f
IN1
Channel-to-Channel Crosstalk
Channel-to-channel crosstalk indicates how well each
analog input is isolated from the others. The channel-to-
channel crosstalk for the MAX1394 is measured by
applying DC to channel 2 while a sine wave is applied
to channel 1. An FFT is taken for channels 1 and 2, and
the difference (in dB) is reported as the channel-to-
channel crosstalk.
Total Harmonic Distortion (THD)
THD is a dynamic figure of merit that indicates how much
harmonic distortion the converter adds to the signal.
THD is the ratio of the RMS sum of the first five harmon-
ics of the fundamental signal to the fundamental itself.
This is expressed as:
Aperture Delay
The MAX1391/MAX1394 sample data on the falling
edge of its third SCLK cycle (Figure 14). In actuality,
there is a small delay between the falling edge of the
sampling clock and the actual sampling instant.
2
2
2
2
2
V
+ V
+ V
+ V
+ V
6
2
3
4
5
THD = 20 × log
V
1
Aperture delay (t ) is the time defined between the
AD
______________________________________________________________________________________ 12
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
falling edge of the sampling clock and the instant when
an actual sample is taken.
Aperture Jitter
THIRD FALLING EDGE
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the aperture delay (Figure 14).
SCLK
DC Power-Supply Rejection Ratio (PSRR)
DC PSRR is defined as the change in the positive full-
scale transfer function point caused by a full range vari-
t
AD
ANALOG
INPUT
ation in the analog power-supply voltage (V ).
DD
t
AJ
SAMPLED
DATA
Chip Information
TRANSISTOR COUNT: 9106
PROCESS: BiCMOS
T/H
(INTERNAL
SIGNAL)
TRACK
HOLD
Figure 14. T/H Aperture Timing
Typical Operating Circuit
0.1µF
2 x AA CELLS
REF
V
DD
REF
INPUT
OE
CS
CPU
VOLTAGE
0.1µF
MAX1391
MAX1394
SS
+
-
AIN+ (AIN1)*
SCL
SCLK
DOUT
INPUT
VOLTAGE
AIN- (AIN2)*
GND
MISO
UNI/BIP
(CH1/CH2)*
*INDICATES THE MAX1394
16 ______________________________________________________________________________________
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
Pin Configurations
TOP VIEW
TOP VIEW
9
8
7
9
8
7
10
6
10
6
MAX1391
MAX1394
1
3
4
5
1
2
3
5
2
4
3mm x 3mm TDFꢁ
3mm x 3mm TDFꢁ
______________________________________________________________________________________ 17
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www0maxim-ic0com/packages.)
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
1
H
21-0137
2
PACKAGE VARIATIONS
COMMON DIMENSIONS
MIN. MAX.
SYMBOL
PKG. CODE
T633-1
N
6
D2
1.50–0.10 2.30–0.10 0.95 BSC
1.50–0.10 2.30–0.10
E2
e
JEDEC SPEC
MO229 / WEEA
MO229 / WEEA
MO229 / WEEC
MO229 / WEEC
MO229 / WEEC
b
[(N/2)-1] x e
1.90 REF
1.90 REF
1.95 REF
1.95 REF
1.95 REF
2.00 REF
2.00 REF
2.40 REF
2.40 REF
0.40–0.05
0.40–0.05
0.30–0.05
0.30–0.05
0.30–0.05
A
0.70
2.90
2.90
0.00
0.20
0.80
3.10
3.10
0.05
0.40
T633-2
6
D
E
0.95 BSC
T833-1
8
1.50–0.10 2.30–0.10 0.65 BSC
1.50–0.10 2.30–0.10 0.65 BSC
1.50–0.10 2.30–0.10 0.65 BSC
T833-2
8
A1
L
T833-3
8
T1033-1
T1033-2
T1433-1
T1433-2
10
10
14
14
1.50–0.10 2.30–0.10 0.50 BSC MO229 / WEED-3 0.25–0.05
k
0.25 MIN.
0.20 REF.
1.50–0.10 2.30–0.10
0.25–0.05
0.20–0.05
0.20–0.05
A2
0.50 BSC MO229 / WEED-3
1.70–0.10 2.30–0.10 0.40 BSC
1.70–0.10 2.30–0.10 0.40 BSC
- - - -
- - - -
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
2
-DRAWING NOT TO SCALE-
H
21-0137
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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