MAX1392MUB_技术文档

19-3709; Rev 0; 5/05

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

General Description

Features

The MAX1392/MAX1395 micropower, serial-output,

10-bit, analog-to-digital converters (ADCs) operate with

a single power supply from +1.5V to +3.6V. These

ADCs feature automatic shutdown, fast wake-up, and a

high-speed 3-wire interface. Power consumption is only

♦ 357ksps 10-Bit Successive-Approximation

Register (SAR) ADCs

♦ Single True-Differential Analog Input Channel

with Unipolar-/Bipolar-Selected Input (MAX1392)

0.740mW (V

= +1.5V) at the maximum conversion

DD

♦ Dual Single-Ended Input Channel with Channel-

rate of 357ksps. AutoShutdown™ between conversions

reduces power consumption at slower throughput rates.

Selected Input (MAX1395)

♦

0ꢀ5 ꢁSB IꢂꢁL 0ꢀ5 ꢁSB DꢂꢁL ꢂo Missing Codes

1 ꢁSB Total Unadꢃusted Error

The MAX1392/MAX1395 require an external reference

REF

V

that has a wide range from 0.6V to V . The

DD

MAX1392 provides one true-differential analog input

that accepts signals ranging from 0 to V (unipolar

♦ 61dB SIꢂAD at 85kHz Input Frequency

♦ Single Supply Voltage (+1ꢀ5V to +3ꢀ6V)

♦ 0ꢀ945mW at 350kspsL 1ꢀ8V

♦ 0ꢀ27mW at 100kspsL 1ꢀ8V

REF

mode) or

vides two single-ended inputs that accept signals rang-

ing from 0 to V . Analog conversion results are

V

/2 (bipolar mode). The MAX1395 pro-

REF

available through a 5MHz, 3-wire SPI™-/QSPI™-

/MICROWIRE™-/digital signal processor (DSP)-compat-

ible serial interface. Excellent dynamic performance,

low voltage, low power, ease of use, and small pack-

age sizes make these converters ideal for portable bat-

tery-powered data-acquisition applications, and for

other applications that demand low power consumption

and minimal space.

♦ 3ꢀ1µW at 1kspsL 1ꢀ8V

♦ <1µA Shutdown Current

♦ External Reference (0ꢀ6V to V

)

DD

♦ AutoShutdown Between Conversions

♦ SPI-/QSPI-/MICROWIRE-/DSP-CompatibleL

The MAX1392/MAX1395 are available in a space-sav-

ing (3mm x 3mm) 10-pin TDFN package or 10-pin

µMAX^®package. The parts operate over the extended

(-40°C to +85°C) and military (-55°C to +125°C) tem-

perature ranges.

3- or 4-Wire Serial Interface

♦ Small (3mm x 3mm)L 10-Pin TDFꢂ or µMAX

(3mm x 5mm) Package

Applications

Typical Operating Circuit and Pin Configurations appear at

end of data sheet.

Portable Datalogging

Data Acquisition

AutoShutdown is a trademark of Maxim Integrated Products, Inc.

SPI/QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

µMAX is a registered trademark of Maxim Integrated Products, Inc.

Medical Instruments

Battery-Powered Instruments

Process Control

Ordering Information

PART

TEMP RAꢂGE

-40°C to +85°C

-55°C to +125°C

-40°C to +85°C

-55°C to +125°C

PIꢂ-PACKAGE

10 TDFN-EP*

10 µMAX

AꢂAꢁOG IꢂPUTS

1-CH DIFF

2-CH S/E

TOP MARK

MAX1392ETB**

MAX1392EUB**

MAX1392MTB**

MAX1392MUB**

MAX1395ETB

AOY

—

10 TDFN-EP*

10 µMAX

—

10 TDFN-EP*

10 µMAX

APB

—

MAX1395EUB**

MAX1395MTB**

MAX1395MUB**

*EP = Exposed pad.

2-CH S/E

10 TDFN-EP*

10 µMAX

2-CH S/E

—

2-CH S/E

—

**Future product—contact factory for availability.

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

ABSOꢁUTE MAXIMUM RATIꢂGS

DD

V

to GND..............................................................-0.3V to +4V

Operating Temperature Ranges

SCLK, CS, OE, CH1/CH2, UNI/BIP,

DOUT to GND.........................................-0.3V to (V

AIN+, AIN-, AIN1, AIN2, REF to GND ........-0.3V to (V

MAX139_E_ _...................................................-40°C to +85°C

MAX139_M_ _................................................-55°C to +125°C

Junction Temperature......................................................+150°C

Storage Temperature Range.............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

+ 0.3V)

DD

Maximum Current into Any Pin ......................................... 50mA

Continuous Power Dissipation (T = +70°C)

A

10-Pin TDFN (derate 18.5mW/°C above +70°C) ....1481.5mW

10-Pin µMAX (derate 5.6mW/°C above +70°C)........444.4mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

EꢁECTRICAꢁ CHARACTERISTICS

(V

= +1.5V to +3.6V, V

= V , C

= 0.1µF, f

= 5MHz, T = T

to T

, unless otherwise noted. Typical values are at

MAX

DD

REF

DD

REF

SCLK

A

MIN

T

A

= +25°C.)

PARAMETER

SYMBOꢁ

COꢂDITIOꢂS

MIꢂ

TYP

MAX

UꢂITS

DC ACCURACY (ꢂote 1)

Resolution

10

Bits

LSB

Integral Nonlinearity

Differential Nonlinearity

Offset Error

INL

0.5

1

DNL

No missing code overtemperature

Offset nulled

0.25

Gain Error

Total Unadjusted Error

TUE

Offset-Error Temperature

Coefficient

0.001

0.00025

0.1

LSB/°C

LSB

Gain-Error Temperature

Coefficient

Channel-to-Channel Offset

Matching

MAX1395 only

Channel-to-Channel Gain

Matching

0.1

LSB

Input Common-Mode Rejection

CMR

V

= 0 to V , MAX1392 only

mV/V

CM

DD

DYꢂAMIC SPECIFICATIOꢂS (Note 2)

Signal-to-Noise Plus Distortion

Signal-to-Noise Ratio

SINAD

SNR

V

= V

= 1.6 to 3.6V

61

dB

REF

DD

Total Harmonic Distortion

THD

-83

-84

-73

-74

dBc

Spurious-Free Dynamic Range

SFDR

f

= 83kHz at -6.5dBFS,

= 87kHz at -6.5dBFS

IN1

IN2

Intermodulation Distortion

IMD

-75

dB

Channel-to-Channel Crosstalk

Full-Power Bandwidth

MAX1395 only

-3dB point

-70

4

dB

MHz

MAX1392

MAX1395

200

150

Full-Linear Bandwidth

SINAD > 59dB

kHz

2

_______________________________________________________________________________________

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

EꢁECTRICAꢁ CHARACTERISTICS (continued)

(V

= +1.5V to +3.6V, V

= V , C

= 0.1µF, f

= 5MHz, T = T

to T

, unless otherwise noted. Typical values are at

MAX

DD

REF

DD

REF

SCLK

A

MIN

T

A

= +25°C.)

PARAMETER

SYMBOꢁ

COꢂDITIOꢂS

MIꢂ

TYP

MAX

UꢂITS

COꢂVERSIOꢂ RATE

Conversion Time

t

11 clock cycles

2.2

µs

CONV

14 clocks per conversion; includes power-

up, acquisition, and conversion time

Throughput Rate

357

ksps

Power-Up and Acquisition Time

Aperture Delay

t

Three SCLK cycles

600

ns

ACQ

t

8

AD

Aperture Jitter

t

30

ps

AJ

Serial Clock Frequency

f

0.1

0

5.0

MHz

CLK

AꢂAꢁOG IꢂPUTS (AIꢂ+L AIꢂ-L AIꢂ1L AIꢂ2)

Unipolar

V

REF

Input Voltage Range

V

IN

Bipolar, MAX1392 only (AIN+ - AIN-)

-V

/2

+V

/2

REF

Common-Mode Input Voltage

Range

V

Bipolar, MAX1392 only [(AIN+) + (AIN-)] / 2

0

V

CM

DD

1

Channel not selected, or conversion

stopped, or in shutdown mode

Input Leakage Current

µA

pF

Input Capacitance

16

REFEREꢂCE IꢂPUT (REF)

V

0.05

+

DD

REF Input Voltage Range

V

0.6

V

REF

REF Input Capacitance

REF DC Leakage Current

REF Input Dynamic Current

24

0.025

20

pF

µA

2.5

60

357ksps

DIGITAꢁ IꢂPUTS (SCꢁKL CSL OEL CH1/CH2L UꢂI/BIP)

0.3 x

Input-Voltage Low

Input-Voltage High

V

IL

V

DD

0.7 x

V

IH

V

DD

0.06 x

Input Hysteresis

V

DD

Input Leakage Current

Input Capacitance

I

Inputs at GND or V

CS, OE

1

µA

pF

IL

DD

1

C

IN

CH1/CH2, UNI/BIP

12.5

DIGITAꢁ OUTPUT (DOUT)

Output-Voltage Low

0.1 x

V

I

= 2mA

SINK

V

OL

V

DD

0.9 x

Output-Voltage High

V

= 2mA

SOURCE

OH

V

DD

_______________________________________________________________________________________

3

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

EꢁECTRICAꢁ CHARACTERISTICS (continued)

(V

= +1.5V to +3.6V, V

= V , C

= 0.1µF, f

= 5MHz, T = T

to T

, unless otherwise noted. Typical values are at

MAX

DD

REF

DD

REF

SCLK

A

MIN

T

A

= +25°C.)

PARAMETER

SYMBOꢁ

COꢂDITIOꢂS

MIꢂ

TYP

MAX

UꢂITS

µA

Tri-State Leakage Current

Tri-State Output Capacitance

POWER SUPPꢁY

I

OE = V

1

LT

DD

C

OE = V

10

pF

OUT

DD

Positive Supply Voltage

V

1.5

3.6

140

225

600

800

10

V

DD

V

= 1.6V

150

200

520

710

5

DD

f

= 100ksps

SAMPLE

= 3V

= 1.6V

= 3V

Positive Supply Current (Note 3)

I

µA

= 357ksps

Power-down mode (Note 4)

Power-down mode (Note 5)

0.2

2.5

Power-Supply Rejection

(Note 6)

PSR

V

= 1.5V to 3.6V, full-scale input

150

1000

µV/V

DD

TIMIꢂG CHARACTERISTICS

(V

= +1.5V to +3.6V, V

= V , C

= 0.1µF, f

= 5MHz, T = T

to T

, unless otherwise noted. Typical values are at

MAX

DD

REF

DD

REF

SCLK

A

MIN

T

A

= +25°C.) (Figure 1)

PARAMETER

SYMBOꢁ

COꢂDITIOꢂS

MIꢂ

200

90

80

0

TYP

MAX

UꢂITS

ns

SCLK Clock Period

t

10000

CP

CH

SCLK Pulse-Width High

SCLK Pulse-Width Low

CS Fall to SCLK Rise Setup

SCLK Rise to CS Fall Ignore

SCLK Fall to DOUT Valid

OE Rise to DOUT Disable

OE Fall to DOUT Enable

CS Pulse-Width High or Low

OE Pulse-Width High or Low

t

ns

t

ns

CL

t

ns

CSS

t

ns

CSO

DOV

DOD

C

= 0 to 30pF

10

80

20

ns

LOAD

t

6

9

ns

t

ns

DOE

CSW

OEW

t

80

10

0

ns

CH1/CH2 Setup Time (to the First SCLK)

CH1/CH2 Hold Time (to the First SCLK)

UNI/BIP Setup Time (to the First SCLK)

UNI/BIP Hold Time (to the First SCLK)

t

MAX1395 only

MAX1392 only

ns

CHS

t

ns

CHH

t

10

0

ns

UBS

t

ns

UBH

ꢂote 1: V = 1.5V, V

= 1.5V, and V

= 1.5V.

P-P SCLK

DD

REF

AIN

ꢂote 2: V = 1.5V, V

= 1.5V, V

= 1.5V , f

= 5MHz, f

= 357ksps, and f (sine-wave) = 85kHz.

SAMPLE IN

DD

AIN

ꢂote 3: All digital inputs swing between V and GND. V

= V , f = 85kHz sine-wave, V

= V

C

= 30pF on DOUT.

DD

REF

DD IN

AIN

REFP-P, LOAD

ꢂote 4: CS = V , OE = UNI/BIP = CH1/CH2 = V

or GND, SCLK is active.

or GND, SCLK is inactive.

DD

ꢂote 5: CS = V , OE = UNI/BIP = CH1/CH2 = V

DD

ꢂote 6: Change in V

at code boundary 1022.5.

AIN

4

_______________________________________________________________________________________

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

UNI/BIP OR

CH1/CH2

t

CHS

t

UBS

OE

CS

t

CHH

t

UBH

t

OEW

t

CL

t

CH

CSO

CSS

CSW

SCLK

DOUT

t

CP

DOE

t

DOD

DOV

HIGH-Z

Figure 1. Detailed Serial-Interface Timing Diagram

V

DD

10mA

DOUT

10mA

50pF

GND

50pF

GND

b) HIGH IMPEDANCE TO V , V TO V ,

OL

a) HIGH IMPEDANCE TO V , V TO V

AND V TO HIGH IMPEDANCE

,

OH OL

OH

OL OH

OH

AND V TO HIGH IMPEDANCE

OL

Figure 2. Load Circuits for Enable/Disable Times

_______________________________________________________________________________________

5

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

Typical Operating Characteristics

(V

DD

= +1.5V, V

= +1.5V, C

= 0.1µF, C = 30pF, f

= 5MHz. T = +25°C, unless otherwise noted.)

A

REF

L

SCLK

INL vs. CODE

INL ERROR vs. REFERENCE VOLTAGE

DNL vs. CODE

1.0

0.8

1.0

0.8

V

DD

= 3.6V

0.8

0.6

0.4

MAX INL

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

MIN INL

0

128 256 384 512 640 768 896 1024

CODE

0.6

1.1

1.6

2.1

2.6

3.1

3.6

0

128 256 384 512 640 768 896 1024

CODE

REFERENCE VOLTAGE (V)

DNL ERROR vs. REFERENCE VOLTAGE

OFFSET ERROR vs. SUPPLY VOLTAGE

OFFSET ERROR vs. TEMPERATURE

1.0

0.8

400

300

200

100

0

400

300

200

100

0

V

= 3.6V

V

= 1.5V

V

DD

= 3.6V

DD

REF

TEMPERATURE = +25°C

0.6

AIN2

0.4

MAX DNL

MIN DNL

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

AIN1

-100

-200

-300

-400

-100

-200

-300

-400

AIN1

0.6

1.1

1.6

2.1

2.6

3.1

3.6

1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6

SUPPLY VOLTAGE (V)

-55

-25

5

35

65

95

125

REFERENCE VOLTAGE (V)

TEMPERATURE (°C)

OFFSET ERROR

vs. REFERENCE VOLTAGE

GAIN ERROR vs. SUPPLY VOLTAGE

GAIN ERROR vs. TEMPERATURE

400

300

200

100

0

400

300

200

100

0

400

300

200

100

0

V

= 1.5V

REF

V

= 3.6V

V

DD

= 3.6V

DD

TEMPERATURE = +25°C

AIN2

-100

-200

-300

-400

-100

-200

-300

-400

-100

-200

-300

-400

AIN1

1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6

SUPPLY VOLTAGE (V)

0.6

1.1

1.6

2.1

2.6

3.1

3.6

-55

-25

5

35

65

95

125

REFERENCE VOLTAGE (V)

TEMPERATURE (°C)

6

_______________________________________________________________________________________

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

Typical Operating Characteristics (continued)

(V

DD

= +1.5V, V

= +1.5V, C

= 0.1µF, C = 30pF, f

= 5MHz. T = +25°C, unless otherwise noted.)

SCLK A

REF

L

GAIN ERROR

vs. REFERENCE VOLTAGE

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

SUPPLY CURRENT vs. TEMPERATURE

400

300

200

100

0

600

550

500

450

400

800

700

600

500

V

= 3.6V

V

REF

= 1.5V, C = 33pF

L

DD

f

= 5MHz, f

= 357ksps

SCLK

SAMPLE

AIN = FULL SCALE, 10kHz SINE WAVE

-100

-200

-300

-400

V

f

= 1.5V, C = 33pF

L

REF

= 5MHz, f

= 357ksps

SCLK

SAMPLE

AIN = FULL SCALE, 10kHz SINE WAVE

400

3.6

0.6

1.1

1.6

2.1

2.6

3.1

-55

-25

5

35

65

95

125

1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6

SUPPLY VOLTAGE (V)

REFERENCE VOLTAGE (V)

TEMPERATURE (°C)

SUPPLY CURRENT

vs. CONVERSION RATE

SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE

SHUTDOWN CURRENT

vs. SUPPLY VOLTAGE

800

600

400

200

0

2.0

0.5

0.4

0.3

0.2

0.1

0

f

= 5MHz, f

= 357ksps

SCLK

SAMPLE

AIN = FULL SCALE, 85kHz SINE WAVE

C = 30pF

L

1.6

1.2

0.8

0.4

0

V

DD

= V = 3.0V

REF

V

DD

= 1.8V

V

DD

= 3.6V

V

DD

= V = 1.6V

REF

0

50 100 150 200 250 300 350

(ksps)

-55

-25

5

35

65

95

125

1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6

SUPPLY VOLTAGE (V)

f

TEMPERATURE (°C)

SAMPLE

SAMPLING ERROR

vs. SOURCE IMPEDANCE

SCLK-TO-DOUT TIMING

FFT

100

90

80

70

60

50

40

30

20

10

0

-20

1.0

0.8

V

= 1.6V

= 357ksps

= 85kHz

DD

REF

AIN HIGH-TO-LOW FS TRANSITION

f

S

IN

V

DD

= 1.5V

0.6

0.4

THD = -82.7dB

SINAD = 61.3dB

SFDR = -83.8dB

-40

0.2

V

= 3.6V

DD

-60

0

-0.2

-0.4

-0.6

-0.8

-1.0

-80

AIN LOW-TO-HIGH FS TRANSITION

-100

-120

0

100

200

300

(pF)

400

500

600

0

20 40 60 80 100 120 140 160 180

FREQUENCY (kHz)

0

500

1000

1500

2000

2500

C

SOURCE IMPEDENCE (Ω)

LOAD

_______________________________________________________________________________________

7

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

Pin Description

PIꢂ

ꢂAME

FUꢂCTIOꢂ

MAX1392 MAX1395

Positive Supply Voltage. Connect V to a 1.5V to 3.6V power supply. Bypass V to GND

with a 0.1µF capacitor as close to the device as possible.

DD

1

V

DD

2

—

3

—

2

AIN-

AIN2

AIN+

AIN1

GND

Negative Analog Input

Analog Input Channel 2

Positive Analog Input

Analog Input Channel 1

Ground

—

3

—

4

External Reference Voltage Input. V

0.1µF capacitor as close to the device as possible.

= 0.6V to (V

+ 0.05V). Bypass REF to GND with a

DD

REF

5

—

6

REF

Input-Mode Select. Drive UNI/BIP high to select unipolar input mode. Pull UNI/BIP low to

UNI/BIP select bipolar input mode. In unipolar mode, the output data is in straight binary format. In

6

bipolar mode, the output data is in two’s-complement format.

Channel-Select Input. Pull CH1/CH2 low to select channel 1. Drive CH1/CH2 high to select

channel 2.

—

7

CH1/CH2

Active-Low Output Enable. Pull OE low to enable DOUT. Drive OE high to disable DOUT.

Connect to CS to interface with SPI, QSPI, and MICROWIRE devices or set low to interface

7

OE

with DSP devices.

8

9

8

9

CS

Active-Low Chip-Select Input. A falling edge on CS initiates power-up and acquisition.

Serial-Data Output. DOUT changes state on the falling edge of SCLK. DOUT is high

impedance when OE is high.

DOUT

Serial-Clock Input. SCLK drives the conversion process and clocks data out. Acquisition ends

on the 3rd falling edge after the CS falling edge. The LSB is clocked out on the SCLK 13th

falling edge and the device enters AutoShutdown mode (see Figures 8, 9, and 10).

10

—

10

—

SCLK

EP

Exposed Pad. Not internally connected. Connect the exposed pad to GND or leave floating.

V

DD

Detailed Description

The MAX1392/MAX1395 use an input track and hold

(T/H) circuit along with a SAR to convert an analog input

signal to a serial 10-bit digital output data stream. The

serial interface provides easy interfacing to microproces-

sors and DSPs. Figure 3 shows the simplified functional

diagram for the MAX1392 (1 channel, true differential)

and the MAX1395 (2 channels, single ended).

CS

CONTROL

LOGIC AND

TIMING

SCLK

OE

OUTPUT

SHIFT

REGISTER

AIN+ (AIN1)*

AIN- (AIN2)*

INPUT

MUX

AND T/H

10-BIT SAR

ADC

DOUT

True-Differential Analog Input T/H

The equivalent input circuit of Figure 4 shows the

MAX1392/MAX1395 input architecture, which is com-

posed of a T/H, a comparator, and a switched-capacitor

DAC. The T/H enters its tracking mode on the falling

edge of CS (while OE is held low). The positive input

capacitor is connected to AIN+ (MAX1392), or to AIN1 or

AIN2 (MAX1395). The negative input capacitor is con-

nected to AIN- (MAX1392) or GND (MAX1395). The T/H

enters its hold mode on the 3rd falling edge of SCLK

REF

UNI/BIP

(CH1/CH2)*

MAX1392

MAX1395

GND

*INDICATES THE MAX1395

Figure 3. Simplified Functional Diagram

8

_______________________________________________________________________________________

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

and the difference between the sampled positive and

negative input voltages is converted. The time required

for the T/H to acquire an input signal is determined by

how quickly its input capacitance is charged. The

required acquisition time lengthens as the input signal’s

source impedance increases. The acquisition time,

Analog Input Bandwidth

The ADC’s input-tracking circuitry has a 4MHz full-

power bandwidth, making it possible to digitize high-

speed transient events and measure periodic signals

with bandwidths exceeding the ADC’s sampling rate by

using undersampling techniques.

t

, is the minimum time needed for the signal to be

ACQ

Use anti-alias filtering to avoid high-frequency signals

being aliased into the frequency band of interest.

acquired. It is calculated by the following equation:

t

≥ 7.4 x (R + R ) x C + t

ACQ

SOURCE

IN

PU

Analog Input Range and Protection

The MAX1392/MAX1395 produce a digital output that

corresponds to the analog input voltage as long as the

analog inputs are within their specified range. When

operating the MAX1392 in unipolar mode (UNI/BIP = 1),

the specified differential analog input range is from 0 to

where:

R

is the source impedance of the input signal.

SOURCE

R

= 500Ω, which is the equivalent differential analog

IN

input resistance.

C

= 16pF, which is the equivalent differential analog

IN

V

. When operating in bipolar mode (UNI/BIP = 0),

REF

input capacitance.

the differential analog input range is from -V

/2 to

REF

t

= 400ns.

+V

/2 with a common mode range of 0 to V . The

PU

REF

DD

MAX1395 has an input range from 0 to V

.

REF

ꢂote: t

is never less than 600ns and any source

ACQ

impedance below 400Ω does not significantly affect the

Internal protection diodes confine the analog input volt-

age within the region of the analog power input rails

ADC’s AC performance.

(V , GND) and allow the analog input voltage to swing

DD

from GND - 0.3V to V

voltages beyond GND - 0.3V and V

+ 0.3V without damage. Input

DD

+ 0.3V forward

DD

bias the internal protection diodes. In this situation, limit

the forward diode current to less than 50mA to avoid

damage to the MAX1392/MAX1395.

REF

GND

Output Data Format

Figures 8, 9, and 10 illustrate the conversion timing for

the MAX1392/MAX1395. Fourteen SCLK cycles are

required to read the conversion result and data on

DOUT transitions on the falling edge of SCLK. The con-

version result contains 4 zeros, followed by 10 data bits

with the data in MSB-first format. For the MAX1392, data

is straight binary for unipolar mode and two’s comple-

ment for bipolar mode. For the MAX1395, data is always

straight binary.

DAC

MAX1392

R

SOURCE

MAX1395

AIN2

AIN1 (AIN+)*

CIN+

COMPARATOR

+

ANALOG

SIGNAL

SOURCE

HOLD

-

RIN+

HOLD

CIN-

GND- (AIN-)*

RIN-

HOLD

TRACK

V

DD

/2

Transfer Function

Figure 5 shows the unipolar transfer function for the

MAX1392/MAX1395. Figure 6 shows the bipolar trans-

fer function for the MAX1392. Code transitions occur

halfway between successive-integer LSB values.

*INDICATES THE MAX1392

Figure 4. Equivalent Input Circuit

_______________________________________________________________________________________

9

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

FULL-SCALE

TRANSITION

FULL-SCALE

TRANSITION

V

REF

2

FS

V

+FS

=

REF

3FF

3FE

3FD

1FF

1FE

ZS = 0

-FS =

V

1024

REF

1 LSB =

-V

REF

2

V

1024

REF

1 LSB =

3FC

3FB

001

000

3FF

3FE

004

003

002

001

000

201

200

-FS

0

+FS

0

1

2

3

4

FS

FS - 1.5 LSB

-FS + 0.5 LSB

+FS - 1.5 LSB

INPUT VOLTAGE (LSB)

Figure 5. Unipolar Transfer Function

Figure 6. Bipolar Transfer Function

Selecting Unipolar or Bipolar Mode

(MAX1392 Only)

Applications Information

Starting a Conversion

A falling edge on CS initiates the power-up sequence

and begins acquiring the analog input as long as OE is

also asserted low. On the 3rd SCLK falling edge, the

analog input is held for conversion. The most significant

bit (MSB) decision is made and clocked onto DOUT on

the 4th SCLK falling edge. Valid DOUT data is available

to be clocked into the master (microcontroller (µC)) on

the following SCLK rising edge. The rest of the bits are

decided and clocked out to DOUT on each successive

SCLK falling edge. See Figures 8 and 9 for conversion

timing diagrams.

Drive UNI/BIP high to select unipolar mode or pull

UNI/BIP low to select bipolar mode. UNI/BIP can be

connected to V

for logic high, to GND for logic low,

DD

or actively driven. UNI/BIP needs to be stable for t

UBS

prior to the first rising edge of SCLK after the CS falling

edge (see Figure 1) for a valid conversion result when

being actively driven.

Selecting Analog Input AIN1 or AIN2

(MAX1395 Only)

Pull CH1/CH2 low to select AIN1 or drive CH1/CH2

high to select AIN2 for conversion. CH1/CH2 can be

connected to V

for logic high, to GND for logic low,

DD

Once a conversion has been initiated, CS can go high at

any time. Further falling edges of CS do not reinitiate an

acquisition cycle until the current conversion completes.

Once a conversion completes, the first falling edge of CS

begins another acquisition/conversion cycle.

or actively driven. CH1/CH2 needs to be stable for t

CHS

prior to the first rising edge of SCLK after the CS falling

edge (see Figure 1) for a valid conversion result when

being actively driven.

10 ______________________________________________________________________________________

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

0.1µF capacitor to GND for best performance (see the

AutoShutdown Mode

The ADC automatically powers down on the SCLK

falling edge that clocks out the LSB. This is the falling

edge after the 13th SCLK. DOUT goes low when the

LSB has been clocked into the master (µC) on the 16th

rising SCLK edge.

Typical Operating Circuit).

Serial Interface

The MAX1392/MAX1395 serial interface is fully compati-

ble with SPI, QSPI, and MICROWIRE (see Figure 7). If a

serial interface is available, set the µC’s serial interface

in master mode so the µC generates the serial clock.

Choose a clock frequency between 100kHz and 5MHz.

CS and OE can be connected together and driven

simultaneously. OE can also be connected to GND if the

DOUT bus is not shared and driven independently.

Alternatively, drive OE high to force the MAX1392/

MAX1395 into power-down. Whenever OE goes high,

the ADC powers down and disables DOUT regardless

of CS, SCLK, or the state of the ADC. DOUT enters a

high-impedance state after t

.

DOD

External Reference

SPI and MICROWIRE

When using SPI or MICROWIRE, make the µC the bus

master and set CPOL = 0 and CPHA = 0 or CPOL = 1

and CPHA = 1. (These are the bits in the SPI or

MICROWIRE control register.) Two consecutive 1-byte

reads are required to get the entire 10-bit result from

the ADC. The MAX1392/MAX1395 shut down after

clocking the LSB and DOUT becomes high impedance.

DOUT transitions on SCLK’s falling edge and is

clocked into the µC on the SCLK’s rising edge. See

Figure 7 for connections and Figures 8 and 9 for timing

diagrams. The conversion result contains 4 zeros, fol-

lowed by the 10 data bits with the data in MSB-first for-

mat. When using CPOL = 0 and CPHA = 0 or CPOL = 1

and CPHA = 1, the MSB of the data is clocked into the

µC on the SCLK’s fifth rising edge. To be compatible

with SPI and MICROWIRE, connect CS and OE togeth-

er and drive simultaneously.

The MAX1392/MAX1395 use an external reference

between 0.6V and (V

+ 50mV). Bypass REF with a

DD

I/O

OE

CS

SCK

SCLK

MAX1392

MAX1395

MISO

I/O

DOUT

UNI/BIP

(CH1/CH2)*

a) SPI

CS

OE

CS

SCK

SCLK

MAX1392

QSPI

Unlike SPI, which requires two 1-byte reads to acquire

the 10 bits of data from the ADC, QSPI allows the mini-

mum number of clock cycles necessary to clock in the

data. The MAX1392/MAX1395 require a minimum of 14

clock cycles from the µC to clock out the 10 bits of

data. See Figure 7 for connections and Figures 8 and 9

for timing diagrams. The conversion result contains 4

zeros, followed by the 10 data bits with the data in

MSB-first format. The MAX1392/MAX1395 shut down

after clocking out the LSB. DOUT then becomes high

impedance. When using CPOL = 0 and CPHA = 0 or

CPOL = 1 and CPHA = 1, the MSB of the data is

clocked into the µC on the SCLK’s fifth rising edge. To

be compatible with QSPI, connect CS and OE together

and drive simultaneously.

MAX1395

MISO

I/O

DOUT

UNI/BIP

(CH1/CH2)*

b) QSPI

I/O

SK

OE

CS

SCLK

MAX1392

MAX1395

SI

DOUT

I/O

UNI/BIP

(CH1/CH2)*

DSP Interface

Figure 10 shows the timing for DSP operation. Figure 11

shows the connections between the MAX1392/

MAX1395 and several common DSPs.

c) MICROWIRE

*INDICATES THE MAX1395

Figure 7. Common Serial-Interface Connections to the

MAX1392/MAX1395

______________________________________________________________________________________ 11

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

SAMPLING INSTANT

POWER-UP

AND ACQUIRE

HOLD

AND CONVERT

ADC

STATE

POWER-

DOWN

POWER-DOWN

(t

)

(t

)

ACQ

CONV

UNI (AIN2)*

UNI/BIP

(CH1/CH2)*

BIPOLAR (AIN1)*

CS = OE

SCLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1

HIGH-Z

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DOUT

*INDICATES THE MAX1395

Figure 8. Serial-Interface Timing for SPI/QSPI (CPOL = CPHA = 1) and MICROWIRE (G6 = 0, G5 = 1)

SAMPLING INSTANT

POWER-UP

AND ACQUIRE

HOLD

AND CONVERT

ADC

STATE

POWER-

DOWN

POWER-DOWN

(t

)

(t

)

ACQ

CONV

UNI (AIN2)*

UNI/BIP

(CH1/CH2)*

BIPOLAR (AIN1)*

CS = OE

SCLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1

HIGH-Z

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DOUT

*INDICATES THE MAX1395

Figure 9. Serial-Interface Timing for SPI/QSPI (CPOL = CPHA = 0) and MICROWIRE (G6 = 0, G5 = 0)

12 ______________________________________________________________________________________

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

SAMPLING INSTANT

POWER-UP

AND ACQUIRE

HOLD

AND CONVERT

POWER-

DOWN

POWER-

DOWN

ADC

STATE

(t

)

(t

)

ACQ

CONV

OE

UNI/BIP

(CH1/CH2)*

BIPOLAR (AIN1)*

UNI (AIN2)*

CS

SCLK

DOUT

FS

16

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

1

2

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

*INDICATES THE MAX1395

Figure 10. DSP Serial-Timing Diagram

As shown in Figure 11, drive the MAX1392/MAX1395

chip-select input (CS) with the DSP’s frame-sync signal.

OE may be connected to GND or driven independently.

For continuous conversion operation, keep OE low and

make the CS falling edge coincident with the 14th

falling edge of the SCLK. Fourteen-bit data transfers

can also be performed with compatible DSPs.

Figure 13 shows the recommended system ground

connections. Establish a single-point analog ground

(star ground point) at the MAX1392/MAX1395s’ GND

pin or use the ground plane.

High-frequency noise in the power supply (V

)

DD

to GND

degrades the ADC’s performance. Bypass V

DD

with a 0.1µF capacitor as close to the device as possi-

ble. Minimize capacitor lead lengths for best supply

noise rejection. To reduce the effects of supply noise, a

10Ω resistor can be connected as a lowpass filter to

attenuate supply noise.

Unregulated Two-Cell or Single Lithium

LiMnO Cell Operation

2

Low operating voltage (1.5V to 3.6V) and ultra-low-power

consumption make the MAX1392/MAX1395 ideal for low

cost, unregulated, battery-powered applications without

the need for a DC-DC converter. Power the MAX1392/

MAX1395 directly from two alkaline/NiMH/NiCd cells in

series or a single lithium coin cell as shown in the Typical

Operating Circuit.

Exposed Pad

The MAX1392/MAX1395 TDFN package has an

exposed pad on the bottom of the package. This pad is

not internally connected. Connect the exposed pad to

the GND pin on the MAX1392/MAX1395 or leave float-

ing for proper electrical performance.

Fresh alkaline cells have a voltage of approximately

1.5V per cell (3V with 2 cells in series) and approach

end of life at 0.8V (1.6V with 2 cells in series). A typical

2xAA alkaline discharge curve is shown in Figure 12a.

A typical CR2032 lithium (LiMnO ) coin cell discharge

2

curve is shown in Figure 12b.

Definitions

Integral Nonlinearity (INL)

INL is the deviation of the values on an actual transfer

function from a straight line. For the MAX1392/

MAX1395, this straight line is between the end points of

the transfer function once offset and gain errors have

been nullified. INL deviations are measured at every

step and the worst-case deviation is reported in the

Electrical Characteristics section.

Layout, Grounding, and Bypassing

For best performance, use PC boards. Board layout

must ensure that digital and analog signal lines are

separated from each other. Do not run analog and digi-

tal (especially clock) lines parallel to one another, or

digital lines underneath the ADC package.

______________________________________________________________________________________ 13

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

I/O

FSX

FSR

CLKX

CLKR

DR

OE

CS

MAX1392

MAX1395

SCLK

DOUT

I/O

UNI/BIP

(CH1/CH2)*

a) TMS320C541 CONNECTION DIAGRAM

T = +25°C

A

I/O

TFS

OE

CS

0

100 200 300 400 500 600 700

DAYS

RFS

MAX1392

MAX1395

SCLK

DOUT

Figure 12a. Typical 2xAA Discharge Curve at 100ksps

DR

I/O

UNI/BIP

(CH1/CH2)*

3.0

2.8

2.6

2.4

2.2

2.0

1.8

b) ADSP218x CONNECTION DIAGRAM

I/O

SC2

SLK

SDR

I/O

OE

CS

MAX1392

MAX1395

SCLK

DOUT

UNI/BIP

(CH1/CH2)*

T = +25°C

A

1.6

c) DSP563xx CONNECTION DIAGRAM

0

10

20

30

40

50

*INDICATES THE MAX1395

DAYS

Figure 11. Common DSP Connections to the MAX1392/MAX1395

Figure 12b. Typical CR2032 Discharge Curve at 100ksps

Differential Nonlinearity (DNL)

DNL is the difference between an actual step width and

the ideal value of 1 LSB. A DNL error specification of

less than 1 LSB guarantees no missing codes and a

monotonic transfer function. For the MAX1392/

MAX1395, DNL deviations are measured at every step

and the worst-case deviation is reported in the

Electrical Characteristics section.

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS sig-

nal to the RMS noise plus the RMS distortion. RMS

noise includes all spectral components to the Nyquist

frequency excluding the fundamental, the first five har-

monics (HD2–HD5), and the DC offset. RMS distortion

includes the first five harmonics (HD2–HD5).









SIGNAL

2

RMS

SINAD = 20 × log













2

NOISE

+ DISTORTION

RMS

14 ______________________________________________________________________________________

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

where V is the fundamental amplitude, and V through

1

2

V

are the amplitudes of the 2nd- through 6th-order

harmonics.

6

POWER SUPPLY

Spurious-Free Dynamic Range (SFDR)

V

DD

V

DD

GND

SFDR is a dynamic figure of merit that indicates the

lowest usable input signal amplitude. SFDR is the ratio

of the RMS amplitude of the fundamental (maximum

signal component) to the RMS value of the next-largest

spurious component, excluding DC offset. SFDR is

specified in decibels relative to the carrier (dBc).

STAR

GROUND

POINT

10Ω

(OPTIONAL)

Intermodulation Distortion (IMD)

IMD is the ratio of the RMS sum of the intermodulation

products to the RMS sum of the two fundamental input

tones. This is expressed as:

V

DD

GND

DV

DGND

DD

DIGITAL

CIRCUITRY

DATA

MAX1392/MAX1395













2

V

+ V

+.....+ V

+ V

IMN

IM1

IM2

IM3

IMD = 20 × log

2

V

+ V

2

1

Figure 13. Power-Supply Grounding Connections

The fundamental input tone amplitudes (V and V ) are

1 2

at -6.5dBFS. Fourteen intermodulation products (V _)

IM

are used in the MAX1392/MAX1395 IMD calculation.

The intermodulation products are the amplitudes of the

Signal-to-Noise Ratio (SNR)

SNR is a dynamic figure of merit that indicates the con-

verter’s noise performance. For a waveform perfectly

reconstructed from digital samples, the theoretical

maximum SNR is the ratio of the full-scale analog input

(RMS value) to the RMS quantization error (residual

error). The ideal, theoretical minimum analog-to-digital

noise is caused by quantization error only and results

directly from the ADC’s resolution (N bits):

output spectrum at the following frequencies, where f

IN1

and f

are the fundamental input tone frequencies:

IN2

• 2nd-order intermodulation products:

+ f , f - f

f

IN1

IN2 IN2 IN1

• 3rd-order intermodulation products:

2 x f - f , 2 x f - f , 2 x f + f , 2 x f

+ f

IN1 IN2

IN2 IN1

IN1

IN2

IN1

• 4th-order intermodulation products:

3 x f - f , 3 x f - f , 3 x f + f , 3 x f

SNR

= 6.02 x N + 1.76

dB dB

dB[max]

IN1 IN2

IN2 IN1

IN1

IN2

IN1

In reality, there are other noise sources such as thermal

noise, reference noise, and clock jitter that also

degrade SNR. SNR is computed by taking the ratio of

the RMS signal to the RMS noise. RMS noise includes

all spectral components to the Nyquist frequency

excluding the fundamental, the first five harmonics, and

the DC offset.

• 5th-order intermodulation products:

3 x f - 2 x f , 3 x f - 2 x f , 3 x f + 2 x

IN1

, 3 x f

IN2

+ 2 x f

IN2

IN1

f

IN2

IN2 IN1

Channel-to-Channel Crosstalk

Channel-to-channel crosstalk indicates how well each

analog input is isolated from the others. The channel-to-

channel crosstalk for the MAX1395 is measured by

applying DC to channel 2 while an AC sine wave is

applied to channel 1. An FFT is taken for channel 1 and

channel 2 and the difference (in dB) is reported as the

channel-to-channel crosstalk.

Total Harmonic Distortion (THD)

THD is a dynamic figure of merit that indicates how much

harmonic distortion the converter adds to the signal.

THD is the ratio of the RMS sum of the first five harmon-

ics of the fundamental signal to the fundamental itself.

This is expressed as:





2



V

+ V

6



2

3

4

5

THD = 20 × log





V









1

______________________________________________________________________________________ 15

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

Aperture Delay

The MAX1392/MAX1395 sample data on the falling

edge of its third SCLK cycle (Figure 14). In actuality,

there is a small delay between the falling edge of the

THIRD FALLING EDGE

sampling clock and the actual sampling instant.

Aperture delay (t ) is the time defined between the

AD

SCLK

falling edge of the sampling clock and the instant when

an actual sample is taken.

t

AD

ANALOG

INPUT

Aperture Jitter

Aperture jitter (t ) is the sample-to-sample variation in

AJ

t

AJ

the aperture delay (Figure 14).

SAMPLED

DATA

DC Power-Supply Rejection Ratio (PSRR)

DC PSRR is defined as the change in the positive full-

scale transfer function point caused by a full range vari-

T/H

(INTERNAL

SIGNAL)

TRACK

HOLD

ation in the analog power-supply voltage (V ).

DD

Figure 14. T/H Aperture Timing

Chip Information

TRANSISTOR COUNT: 9106

Typical Operating Circuit

PROCESS: BiCMOS

0.1µF

2 x AA CELLS

REF

INPUT

V

DD

REF

OE

CS

CPU

VOLTAGE

0.1µF

MAX1392

MAX1395

SS

+

-

AIN+ (AIN1)*

SCL

SCLK

DOUT

INPUT

VOLTAGE

AIN- (AIN2)*

GND

MISO

UNI/BIP

(CH1/CH2)*

*INDICATES THE MAX1395 ONLY

16 ______________________________________________________________________________________

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

Pin Configurations

TOP VIEW

9

8

7

10

6

V

1

2

3

4

5

10 SCLK

DD

AIN-

AIN+

GND

REF

9

8

7

6

DOUT

CS

MAX1392

OE

UNI/BIP

1

3

4

5

2

µMAX

3mm x 3mm TDFꢂ

TOP VIEW

9

8

7

10

6

V

1

2

3

4

5

10 SCLK

DD

AIN2

AIN1

GND

REF

9

8

7

6

DOUT

CS

MAX1395

OE

CH1/CH2

1

3

4

5

2

µMAX

3mm x 3mm TDFꢂ

______________________________________________________________________________________ 17

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to wwwꢀmaxim-icꢀcom/packages.)

D2

D

A2

PIN 1 ID

N

0.35x0.35

b

[(N/2)-1] x e

REF.

PIN 1

INDEX

AREA

E

E2

DETAIL A

e

A1

k

C

L

A

L

e

PACKAGE OUTLINE, 6,8,10 & 14L,

TDFN, EXPOSED PAD, 3x3x0.80 mm

1

-DRAWING NOT TO SCALE-

21-0137

G

2

COMMON DIMENSIONS

SYMBOL

MIN.

0.70

2.90

0.00

0.20

MAX.

0.80

3.10

0.05

0.40

A

D

E

A1

L

k

0.25 MIN.

0.20 REF.

A2

PACKAGE VARIATIONS

DOWNBONDS

ALLOWED

PKG. CODE

T633-1

N

6

D2

E2

e

JEDEC SPEC

b

[(N/2)-1] x e

1.90 REF

1.95 REF

2.00 REF

2.40 REF

1.50 0.10 2.30 0.10 0.95 BSC

1.50 0.10 2.30 0.10 0.65 BSC

MO229 / WEEA

MO229 / WEEC

0.40 0.05

0.30 0.05

NO

T633-2

6

T833-1

8

NO

T833-2

8

NO

T833-3

8

YES

NO

T1033-1

T1433-1

T1433-2

10

14

1.50 0.10 2.30 0.10 0.50 BSC MO229 / WEED-3 0.25 0.05

1.70 0.10 2.30 0.10 0.40 BSC

- - - -

0.20 0.05

YES

NO

PACKAGE OUTLINE, 6,8,10 & 14L,

TDFN, EXPOSED PAD, 3x3x0.80 mm

2

-DRAWING NOT TO SCALE-

21-0137

G

2

18 ______________________________________________________________________________________

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to wwwꢀmaxim-icꢀcom/packages.)

e

4X S

10

INCHES

DIM MIN

MAX

MILLIMETERS

MIN

-

MAX

1.10

0.15

0.95

3.05

3.00

3.05

3.00

5.05

0.70

A

-

0.043

0.006

0.037

0.120

0.118

0.120

0.118

0.199

A1

A2

D1

D2

E1

E2

H

0.002

0.030

0.116

0.114

0.116

0.114

0.187

0.05

0.75

2.95

2.89

2.95

2.89

4.75

0.40

H

Ø0.50 0.1

0.6 0.1

L

0.0157 0.0275

0.037 REF

L1

b

0.940 REF

0.007

0.0106

0.177

0.090

0.270

1

e

0.0197 BSC

0.500 BSC

0.6 0.1

c

0.0035 0.0078

0.0196 REF

0.200

BOTTOM VIEW

0.498 REF

S

TOP VIEW

α

0°

6°

0°

6°

D2

E2

GAGE PLANE

A2

c

A

E1

b

L

α

A1

D1

L1

FRONT VIEW

SIDE VIEW

PROPRIETARY INFORMATION

TITLE:

PACKAGE OUTLINE, 10L uMAX/uSOP

APPROVAL

DOCUMENT CONTROL NO.

REV.

1

21-0061

I

1

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19

Printed USA

is a registered trademark of Maxim Integrated Products, Inc.


型号：	MAX1392MUB
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs 1.5V至3.6V ， 357ksps ，单通道真差分/双通道单端， 10位， SAR型ADC
文件：	总19页 (文件大小：875K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX1392MUB [MAXIM]

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