MAX1366 [MAXIM]
Microcontroller-Interface, 4.5-/3.5-Digit Panel Meters with 4â20mA Output;
| 型号： | MAX1366 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Microcontroller-Interface, 4.5-/3.5-Digit Panel Meters with 4â20mA Output 微控制器 |
| 文件： | 总36页 (文件大小：937K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3977; Rev 0; 1/06
Microcontroller-Interface,
4.5-/3.5-Digit Panel Meters with 4–20mA Output
General Description
Features
The MAX1366/MAX1368 low-power, 4.5- and 3.5-digit,
panel meters feature an integrated sigma-delta analog-
to-digital converter (ADC), LED display drivers, voltage
digital-to-analog converter (DAC), and a 4–20mA (or 0
to 16mA) current driver.
♦ Microcontroller (µC)-Interface, Digital Panel Meter
20-Bit Sigma-Delta ADC
4.5-Digit Resolution (±±1,111 Count, MAꢀ±ꢁ33)
ꢁ.5-Digit Resolution (±±111 Count, MAꢀ±ꢁ36)
No Integrating/Autozeroing Capacitors
±00MΩ Input Impedance
The MAX1366/MAX1368’s analog input voltage range is
programmable to either 2ꢀ or 200mꢀ. The MAX1368
drives a 3.5-digit ( 1999 count) display and the
MAX1366 drives a 4.5-digit ( 19,999 count) display.
The ADC output directly drives the LED display as well
as the voltage DAC, which, in turn, drives the 4–20mA
(or 0 to 16mA) current-loop output.
±200mꢂ or ±2.000ꢂ Input Range
♦ LED Display
Common-Cathode 7-Segment LED Driver
Programmable LED Current (0 to 20mA)
2.5Hz Update Rate
In normal operation, the 0 to 16mA/4–20mA current-
loop output follows the 2ꢀ or 200mꢀ analog input to
drive remote panel-meter displays, data loggers, and
other industrial controllers. For added flexibility, the
MAX1366/MAX1368 allow direct access to the ADC
result, DAC output, and the ꢀ/I converter input.
♦ Output DAC and Current Driver
±±5-Bit DAC ꢃith ±4-Bit Linear ꢂ/I Converter
Selectable 0 to ±3mA or 4–20mA Current Output
Unipolar/Bipolar Modes
±50µA ꢄero Scale, ±40ppmꢅS/ꢆC (typ)
±0.5ꢇ ꢈain Error, ±25ppmꢅS/ꢆC (typ)
Separate 7ꢂ to ꢁ0ꢂ Supply for Current-Loop
Output
The sigma-delta ADC does not require external preci-
sion integrating capacitors, autozero capacitors, crystal
oscillators, charge pumps, or other circuitry commonly
required in dual-slope ADC panel-meter circuits. On-
chip analog input and reference buffers allow direct
interface with high-impedance signal sources. Excellent
common-mode rejection and digital filtering provides
greater than 100dB rejection of simultaneous 50Hz and
60Hz line noise. Other features include data hold and
peak detection and overrange/underrange detection.
♦ 2.7ꢂ to 5.25ꢂ ADC/DAC Supply
♦ 4.75ꢂ to 5.25ꢂ ꢂ/I Converter Supply
♦ Internal 2.046ꢂ Reference or External Reference
♦ SPI™-/QSPI™-/MICROWIRE™-Compatible Serial
The MAX1366/MAX1368 require a 2.7ꢀ to 5.25ꢀ supply,
a 4.75ꢀ to 5.25ꢀ ꢀ/I supply, and a 7ꢀ to 30ꢀ loop sup-
ply. They are available in a space-saving (7mm x
7mm), 48-pin TQFP package and operate over the
extended (-40°C to +85°C) temperature range.
Interface
♦ 46-Pin, 7mm x 7mm TQꢅP Package
Ordering Information
Applications
Industrial Process Control
Automated Test Equipment
Data-Acquisition Systems
Digital Panel Meters
PART
TEMP RANꢈE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAꢈE
48 TQFP
MAꢀ±ꢁ33ECM
MAꢀ±ꢁ36ECM
48 TQFP
Digital ꢀoltmeters
Selector Guide
Digital Multimeters
RESOLUTION
PART
PACKAꢈE CODE
(DIꢈITS)
Pin Configuration appears at end of data sheet.
MAX1366ECM
MAX1368ECM
C48-6
C48-6
4.5
3.5
Typical Operating Circuits appear at end of data sheet.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
±
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
ABSOLUTE MAꢀIMUM RATINꢈS
(With reference to GND, unless otherwise specified.)
SEG_ to LEDG.........................................-0.3ꢀ to (ꢀ
DIG_ to LEDG..........................................-0.3ꢀ to (ꢀ
+ 0.3ꢀ)
+ 0.3ꢀ)
LEDꢀ
LEDꢀ
Aꢀ , Dꢀ
-0.3ꢀ to +6.0ꢀ
DD
DD ....................................................................
AIN+, AIN-, REF+, REF-.........................ꢀ
REG_FORCE, CMP, DAC_ꢀDD, DACꢀOUT,
CONꢀ_IN, 4-20OUT.............................-0.3ꢀ to (Aꢀ
EN_BPM, EN_I, REFSELE, DACDATA_SEL,
CLK, EOC, CS_DAC, SCLK, DIN
DOUT.....................................................-0.3ꢀ to (Dꢀ
NEGꢀ .......................................................-2.6ꢀ to (Aꢀ
LED_EN....................................................-0.3ꢀ to (Dꢀ
SET...........................................................-0.3ꢀ to (Aꢀ
to (Aꢀ
+ 0.3ꢀ)
+ 0.3ꢀ)
LOWBATT ................................................-0.3ꢀ to (Aꢀ + 0.3ꢀ)
NEGꢀ
DD
DD
REF_DAC .................................................-0.3ꢀ to (Aꢀ
+ 0.3ꢀ)
DD
DACꢀOUT................................................-0.3ꢀ to (Aꢀ + 0.3ꢀ)
DD
DD
DIG_ Sink Current .............................................................300mA
DIG_ Source Current...........................................................50mA
SEG_ Sink Current ..............................................................50mA
SEG_ Source Current..........................................................50mA
Maximum Current Input into Any Other Pin ........................50mA
+ 0.3ꢀ)
+ 0.3ꢀ)
+ 0.3ꢀ)
+ 0.3ꢀ)
DD
DD
DD
DD
Continuous Power Dissipation (T = +70°C)
A
REG_AMP, REG_ꢀDD ...........................................-0.3ꢀ to +6.0ꢀ
LEDG.....................................................................-0.3ꢀ to +0.3ꢀ
GND_DAC .............................................................-0.3ꢀ to +0.3ꢀ
GND_ꢀ/I.................................................................-0.3ꢀ to +0.3ꢀ
48-Pin TQFP (derate 22.7mW/°C above +70°C).....1818.2mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Aꢀ
= Dꢀ
= DAC_ꢀDD = +2.7ꢀ to +5.25ꢀ, GND = 0, LEDG = 0, ꢀ
= +2.7ꢀ to +5.25ꢀ, ꢀ
- ꢀ
= 2.048ꢀ (external
REF-
DD
DD
LEDꢀ
REF+
reference), ꢀ
noted. All specifications are at T = T
= 7ꢀ, ꢀ
= +5.0ꢀ, C
= 0.1µF, REF- = GND, C
. Typical values are at T = +25°C, unless otherwise noted.)
= 0.1µF. Internal clock mode, unless otherwise
EXT
REG_AMP
REF+
NEGꢀ
to T
A
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAꢀ
UNITS
ADC ACCURACY
MAX1366
-19,999
-1999
+19,999
+1999
Noise-Free Resolution
Integral Nonlinearity (Note 1)
Range-Change Ratio
Counts
Counts
MAX1368
2.000ꢀ range
200mꢀ range
1
1
INL
(ꢀ
AIN+
(ꢀ
AIN+
- ꢀ
- ꢀ
= 0.100ꢀ) on 200mꢀ range;
= 0.100ꢀ) on 2.0ꢀ range
AIN-
AIN-
10:1
Ratio
Rollover Error
ꢀ
- ꢀ
= full scale
= 0 (Note 2)
= 0 (Note 4)
1
Counts
AIN+
AIN-
Output Noise
10
µꢀ
P-P
Offset Error (Zero Input Reading)
Gain Error
ꢀ
- ꢀ
-0
+0
Counts
%FSR
AIN+
AIN-
(Note 3)
- ꢀ
-0.5
+0.5
Offset Drift (Zero Reading Drift)
Gain Drift
ꢀ
0.1
1
µꢀ/°C
AIN+
AIN-
ppm/°C
INPUT CONꢂERSION RATE
External Clock Frequency
External Clock Duty Cycle
4.9152
MHz
%
40
60
Internal clock
External clock, f
5
5
Update Rate
Hz
= 4.9152MHz
CLK
ANALOꢈ INPUTS (AIN+, AIN-) (bypass to ꢈND ꢃith 0.±µꢅ or greater capacitors)
RANGE bit = 0
AIN Input ꢀoltage Range (Note 5)
-2.0
-0.2
+2.0
+0.2
ꢀ
RANGE bit = 1
2
_______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
ELECTRICAL CHARACTERISTICS (continued)
(Aꢀ
= Dꢀ
= DAC_ꢀDD = +2.7ꢀ to +5.25ꢀ, GND = 0, LEDG = 0, ꢀ
= +2.7ꢀ to +5.25ꢀ, ꢀ
- ꢀ
= 2.048ꢀ (external
REF-
DD
DD
LEDꢀ
REF+
reference), ꢀ
noted. All specifications are at T = T
= 7ꢀ, ꢀ
= +5.0ꢀ, C
= 0.1µF, REF- = GND, C
. Typical values are at T = +25°C, unless otherwise noted.)
= 0.1µF. Internal clock mode, unless otherwise
EXT
REG_AMP
REF+
NEGꢀ
to T
A
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAꢀ
UNITS
AIN Absolute Input ꢀoltage
Range to GND
-2.2
+2.2
ꢀ
Internal clock mode,
50Hz and 60Hz 2%
100
100
150
Normal-Mode 50Hz and 60Hz
Rejection (Simultaneously)
dB
dB
External clock mode,
50Hz and 60Hz 2%, f
= 4.9152MHz
CLK
Common-Mode 50Hz and 60Hz
Rejection (Simultaneously)
For 50Hz and 60Hz 2%, R
10kΩ
<
SOURCE
CMR
CMR
Common-Mode Rejection
Input Leakage Current
Input Capacitance
At DC
100
10
dB
nA
pF
nA
10
Average Dynamic Input Current
(Note 6)
-20
+20
LOW-BATTERY ꢂOLTAꢈE MONITOR (LOWBATT)
LOWBATT Trip Threshold
2.048
10
ꢀ
LOWBATT Leakage Current
pA
mꢀ
Hysteresis
20
INTERNAL REꢅERENCE (REꢅ- = ꢈND, INTREꢅ = Dꢂ
)
DD
REF Input ꢀoltage
ꢀ
Aꢀ
= 5ꢀ
DD
2.007
2.048
1
2.089
ꢀ
REF
REF Output Short-Circuit Current
mA
REF Output Temperature
Coefficient
TC
40
ppm/°C
ꢀREF
Load Regulation
Line Regulation
I
= 0 to 300µA, I
= 0 to 30µA
6
µꢀ/µA
µꢀ/ꢀ
SOURCE
SINK
50
0.1Hz to 10Hz
10Hz to 10kHz
25
Noise ꢀoltage
µꢀ
P-P
400
EꢀTERNAL REꢅERENCE (INTREꢅ BIT = 0)
REF Input ꢀoltage
Differential, (ꢀ
- ꢀ
)
2.048
ꢀ
REF+
REF-
Absolute REF+, REF- Input
ꢀoltage to GND (ꢀ
must be
-2.2
+2.2
ꢀ
REF+
)
greater than ꢀ
REF-
Internal clock mode,
50Hz and 60Hz 2%
100
120
150
Normal-Mode 50Hz and 60Hz
Rejection (Simultaneously)
dB
dB
External clock mode,
50Hz and 60Hz 2%, f
= 4.9152MHz
CLK
Common-Mode 50Hz and 60Hz
Rejection (Simultaneously)
For 50Hz and 60Hz 2%, R
10kΩ
<
SOURCE
CMR
CMR
Common-Mode Rejection
Input Leakage Current
At DC
100
10
dB
nA
_______________________________________________________________________________________
ꢁ
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
ELECTRICAL CHARACTERISTICS (continued)
(Aꢀ
= Dꢀ
= DAC_ꢀDD = +2.7ꢀ to +5.25ꢀ, GND = 0, LEDG = 0, ꢀ
= +2.7ꢀ to +5.25ꢀ, ꢀ
- ꢀ
= 2.048ꢀ (external
REF-
DD
DD
LEDꢀ
REF+
reference), ꢀ
noted. All specifications are at T = T
= 7ꢀ, ꢀ
= +5.0ꢀ, C
= 0.1µF, REF- = GND, C
. Typical values are at T = +25°C, unless otherwise noted.)
= 0.1µF. Internal clock mode, unless otherwise
EXT
REG_AMP
REF+
NEGꢀ
to T
A
MIN
MAX A
PARAMETER
Input Capacitance
SYMBOL
CONDITIONS
MIN
-20
TYP
MAꢀ
+20
UNITS
pF
10
Average Dynamic Input Current
CHARꢈE PUMP
(Note 6)
nA
Output ꢀoltage
NEGꢀ
C
= 0.1µF to GND
-2.60
-10
-2.42
-2.30
ꢀ
NEGꢀ
DIꢈITAL INPUTS (SCLK, DIN, CS, CLK)
Input Current
I
IN
ꢀ
= 0 or Dꢀ
+10
µA
ꢀ
IN
DD
0.3 x
Input Low ꢀoltage
ꢀ
INL
Dꢀ
DD
0.7 x
Input High ꢀoltage
ꢀ
ꢀ
INH
Dꢀ
DD
Input Hysteresis
ꢀ
Dꢀ = 3ꢀ
200
mꢀ
HYS
DD
DIꢈITAL OUTPUTS (DOUT, EOC)
Output Low ꢀoltage
ꢀ
I
I
= 1mA
0.4
ꢀ
ꢀ
OL
SINK
0.8 x
Output High ꢀoltage
ꢀ
= 200µA
SOURCE
OH
D
ꢀDD
Tri-State Leakage Current
I
-10
+10
µA
pF
L
Tri-State Output Capacitance
ADC POWER SUPPLY (Note ±0)
C
15
OUT
Aꢀ
Dꢀ
ꢀoltage
ꢀoltage
Aꢀ
Dꢀ
2.70
2.70
5.25
5.25
ꢀ
DD
DD
DD
ꢀ
DD
Power-Supply Rejection Aꢀ
Power-Supply Rejection Dꢀ
PSR
PSR
(Note 7)
(Note 7)
80
dB
dB
DD
A
D
100
DD
640
305
320
180
20
Aꢀ Current (Notes 8, 9)
I
µA
DD
AꢀDD
Standby mode
Dꢀ
Dꢀ
= +5.25ꢀ
= +3.3ꢀ
DD
DD
Dꢀ Current (Notes 8, 9)
DD
I
µA
DꢀDD
Standby mode
DAC POWER SUPPLY
DAC Supply ꢀoltage
DAC Supply Current
ꢀ
2.70
4.75
5.25
0.21
ꢀ
DAC_ꢀDD
0.10
mA
LINEAR REꢈULATOR AND ꢂ/I CONꢂERTER POWER REQUIREMENTS
REG_AMP Supply ꢀoltage
REG_AMP Supply Current
REG_ꢀDD ꢀoltage
ꢀ
5.25
0.30
ꢀ
mA
ꢀ
REG_AMP
0.19
5.20
ꢀ
REG_ꢀDD
4
_______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
ELECTRICAL CHARACTERISTICS (continued)
(Aꢀ
= Dꢀ
= DAC_ꢀDD = +2.7ꢀ to +5.25ꢀ, GND = 0, LEDG = 0, ꢀ
= +2.7ꢀ to +5.25ꢀ, ꢀ
- ꢀ
= 2.048ꢀ (external
REF-
DD
DD
LEDꢀ
REF+
reference), ꢀ
noted. All specifications are at T = T
= 7ꢀ, ꢀ
= +5.0ꢀ, C
= 0.1µF, REF- = GND, C
. Typical values are at T = +25°C, unless otherwise noted.)
= 0.1µF. Internal clock mode, unless otherwise
EXT
REG_AMP
REF+
NEGꢀ
to T
A
MIN
MAX A
PARAMETER
REG_ꢀDD Supply Current
LED DRIꢂERS (Table 7)
LED Supply ꢀoltage
SYMBOL
CONDITIONS
MIN
TYP
MAꢀ
UNITS
Includes 20mA programmed current
25.2
27.4
mA
ꢀ
2.70
5.25
10
ꢀ
LEDꢀ
LED Shutdown Supply Current
I
µA
SHDN
Seven segments and decimal point on,
LED Supply Current
Display Scan Rate
I
176
180
mA
Hz
LEDꢀ
R
= 25kΩ
SET
MAX1366
MAX1368
512
640
f
OSC
Segment Current Slew Rate
DIG_ ꢀoltage Low
I
/∆t
25
mA/µs
ꢀ
SEG
ꢀ
I
= 176mA
DIG_
0.178
0.300
10
DIG
Segment-Drive Source-Current
Matching
∆I
3
%
SEG
SEG
Segment-Drive Source Current
LED Drivers Bias Current
Interdigit Blanking Time
4-20OUT OUTPUT ACCURACY
Zero-Scale Error
I
ꢀ
- ꢀ
= 0.6ꢀ, R = 25kΩ
SET
15.0
21.5
120
4
25.5
mA
µA
µs
LEDꢀ
SEG
From Aꢀ
DD
4mA or 0mA, at +25°C
4mA or 0mA, at +25°C
10
40
0.2
25
2
50
0.5
4
µA
ppmFS/°C
%FS
Zero-Scale Error Tempco
Gain Error
Gain-Error Tempco
ppmFS/°C
µA
Span Linearity
Power-Supply Rejection
Signal Path Noise
PSR
ꢀ
= 7ꢀ to 36ꢀ
4
µA/ꢀ
EXT
10pF to AGND on 4-20OUT
Limited to 12.5 x ꢀ / 1.28kΩ
2.0
20
µA
RMS
4–20mA Current Limit
mA
REF
TIMINꢈ CHARACTERISTICS (Notes ±±, ±2, ꢅigure 6)
SCLK Operating Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
DIN-to-SCLK Setup
f
Dꢀ = 2.7ꢀ
0
100
100
50
0
4.2
MHz
ns
SCLK
DD
t
CH
t
ns
CL
DS
DH
t
ns
DIN-to-SCLK Hold
t
ns
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Fall to DOUT ꢀalid
t
50
0
ns
CSS
CSH
t
ns
t
C
= 50pF, Figures 11, 12
LOAD
120
ns
DO
_______________________________________________________________________________________
5
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
ELECTRICAL CHARACTERISTICS (continued)
(Aꢀ
= Dꢀ
= DAC_ꢀDD = +2.7ꢀ to +5.25ꢀ, GND = 0, LEDG = 0, ꢀ
= +2.7ꢀ to +5.25ꢀ, ꢀ
- ꢀ
= 2.048ꢀ (external
REF-
DD
DD
LEDꢀ
REF+
reference), ꢀ
noted. All specifications are at T = T
= 7ꢀ, ꢀ
= +5.0ꢀ, C
= 0.1µF, REF- = GND, C
. Typical values are at T = +25°C, unless otherwise noted.)
= 0.1µF. Internal clock mode, unless otherwise
EXT
REG_AMP
REF+
NEGꢀ
to T
A
MIN
MAX A
PARAMETER
CS Rise to DOUT Disable
CS Fall to DOUT Enable
SYMBOL
CONDITIONS
= 50pF, Figures 11, 12
= 50pF, Figures 11, 12
MIN
TYP
MAꢀ
120
UNITS
ns
t
C
C
TR
Dꢀ
LOAD
LOAD
t
120
ns
Note ±: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error
and offset error.
Note 2: Offset calibrated. See OFFSET_CAL1 AND OFFSET_CAL2 in the On-Chips Registers section.
Note ꢁ: Offset nulled.
Note 4: Offset-drift error is eliminated by recalibration at the new temperature.
Note 5: The input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pair.
Note 3:
ꢀ
or ꢀ
= -2.2ꢀ to +2.2ꢀ. ꢀ
or ꢀ
= -2.2ꢀ to +2.2ꢀ. All input structures are identical. Production tested on
AIN+
AIN-
REF+
REF-
AIN+ and REF+ only. ꢀ
must always be greater than ꢀ
.
REF-
REF+
Note 7: Measured at DC by changing the power-supply voltage from 2.7ꢀ to 5.25ꢀ and measuring the effect on the conversion
error with external reference. PSRR at 50Hz and 60Hz exceeds 120dB with filter notches at 50Hz and 60Hz (Figure 1).
Note 6: CLK and SCLK are disabled.
Note 1: LED drivers are disabled.
Note ±0: Power-supply currents are measured with all digital inputs at either GND or Dꢀ and with the device in internal clock mode.
DD
Note ±±: All input signals are specified with t
= t = 5ns (10% to 90% of Dꢀ ) and are timed from a voltage level of 50% of
FALL DD
RISE
Dꢀ , unless otherwise noted.
DD
Note ±2: See the serial-interface timing diagrams (Figures 7–11).
Typical Operating Characteristics
(A
ꢀDD
= D
= +5ꢀ, ꢀ
= +5.0ꢀ, GND = 0, LEDG = 0, ꢀ
= +2.7ꢀ to +5.25ꢀ, ꢀ
- ꢀ
= 2.048ꢀ (external reference),
ꢀDD
DAC_ꢀDD
LEDꢀ
REF+
REF-
ꢀ
EXT
= 7ꢀ, C
= 0.1µF, REF- = GND, C = 0.1µF, RANGE bit = 1, internal clock mode. T = +25°C, unless otherwise noted.)
REF+
NEGꢀ A
MAX1366
OFFSET ERROR vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
1000
0.19
0.14
700
600
500
400
300
200
100
0
900
800
700
600
500
400
300
200
100
0
0.09
AV
DD
AV
DD
0.04
DV
DD
-0.01
-0.06
-0.11
-0.16
DV
DD
DAC_VDD
35
DAC_VDD
4.2
2.7
3.2
3.7
4.7
5.2
-40
-15
10
60
85
2.75
3.25
3.75
4.25
4.75
5.25
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
3
_______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
Typical Operating Characteristics
(A
ꢀDD
= D
= +5ꢀ, ꢀ
= +5.0ꢀ, GND = 0, LEDG = 0, ꢀ
= +2.7ꢀ to +5.25ꢀ, ꢀ
- ꢀ
= 2.048ꢀ (external reference),
ꢀDD
DAC_ꢀDD
LEDꢀ
REF+
REF-
ꢀ
EXT
= 7ꢀ, C
= 0.1µF, REF- = GND, C = 0.1µF, RANGE bit = 1, internal clock mode. T = +25°C, unless otherwise noted.)
REF+
NEGꢀ A
MAX1366
MAX1366
GAIN ERROR vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1366
OFFSET ERROR vs. TEMPERATURE
0.6
0
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
-0.08
-0.09
-0.10
0.08
0.06
0.04
0.02
0
0.5
0.4
0.3
0.2
0.1
0
-0.02
-0.04
-0.06
-0.08
-0.1
-0.2
-0.10
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
2.75
3.25
3.75
4.25
4.75
5.25
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
MAX1366
MAX1366
NOISE DISTRIBUTION
( 200mV INPUT RANGE) INL vs. OUTPUT CODE
( 2V INPUT RANGE) INL vs. OUTPUT CODE
25
20
15
10
5
1.0
1.0
0.5
0
0.5
0
-0.5
-1.0
-0.5
-1.0
0
-0.2-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
NOISE (LSB)
-20,000
-10,000
0
10,000
20,000
-20,000
-10,000
0
10,000
20,000
OUTPUT CODE
OUTPUT CODE
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
DATA OUTPUT RATE
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.050
2.049
2.048
2.047
2.046
2.045
2.044
5.10
2.054
2.053
2.052
5.08
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
2.051
2.050
2.049
2.048
2.047
2.046
2.045
2.044
2.75
3.25
3.75
4.25
4.75
5.25
-40
-15
10
35
60
85
0
10
20
30
40
50
60
70
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
Typical Operating Characteristics
(A
ꢀDD
= D
= +5ꢀ, ꢀ
= +5.0ꢀ, GND = 0, LEDG = 0, ꢀ
= +2.7ꢀ to +5.25ꢀ, ꢀ
- ꢀ
= 2.048ꢀ (external reference),
ꢀDD
DAC_ꢀDD
LEDꢀ
REF+
REF-
ꢀ
EXT
= 7ꢀ, C
= 0.1µF, REF- = GND, C = 0.1µF, RANGE bit = 1, internal clock mode. T = +25°C, unless otherwise noted.)
REF+
NEGꢀ A
DATA OUTPUT RATE
vs. SUPPLY VOLTAGE
OFFSET ERROR
vs. COMMON-MODE VOLTAGE
V
STARTUP SCOPE SHOT
NEG
5.020
0.20
0.15
0.10
0.05
0
5.015
V
DD
5.010
5.005
5.000
4.995
4.990
4.985
2V/div
1V/div
V
NEG
-0.05
-0.10
-0.15
-0.20
4.980
2.70
3.21
3.72
4.23
4.74
5.25
-2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0
20ms/div
SUPPLY VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
DAC ZERO-CODE OFFSET ERROR
vs. TEMPERATURE
CHARGE-PUMP OUTPUT VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
SEGMENT CURRENT
vs. SUPPLY VOLTAGE
30
25
20
15
10
5
-2.40
-2.42
-2.44
-2.46
-2.48
-2.50
0.4
R
ISET
= 25kΩ
0.3
0.2
0.1
0
-0.1
-0.2
0
-40
-15
10
35
60
85
2.70
3.21
3.72
4.23
4.74
5.25
2.75
3.25
3.75
4.25
4.75
5.25
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
6
_______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
Typical Operating Characteristics (continued)
(A
ꢀDD
= D
= +5ꢀ, ꢀ
= +5.0ꢀ, GND = 0, LEDG = 0, ꢀ
= +2.7ꢀ to +5.25ꢀ, ꢀ
- ꢀ
= 2.048ꢀ (external reference),
ꢀDD
DAC_ꢀDD
LEDꢀ
REF+
REF-
ꢀ
EXT
= 7ꢀ, C
= 0.1µF, REF- = GND, C
= 0.1µF, RANGE bit = 1, internal clock mode. T = +25°C, unless otherwise noted.)
REF+
NEGꢀ
A
DAC GAIN ERROR
vs. TEMPERATURE
4-20OUT ZERO-SCALE ERROR
STEP RESPONSE
vs. TEMPERATURE
MAX1366/68 toc20
0
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
50
40
EXTERNAL REFERENCE = 2.048V
500mV/div
10mA/div
CONV_IN
= 1V
30
20
10
0
4-20OUT
= 21.7mA
-10
-20
-30
-40
-50
-40
-15
10
35
60
85
-40 -20
0
20
40
60
80
100µs/div
TEMPERATURE (°C)
TEMPERATURE (°C)
4-20OUT vs. DAC CODE
(4-20OUT SPAN LINEARITY)
4-20OUT GAIN ERROR
vs. TEMPERATURE
POWER-SUPPLY REJECTION
vs. CURRENT OUTPUT (4-20OUT)
2.5
2.0
1.5
1.0
0.5
0
50
40
150
100
50
EXTERNAL REFERENCE = 2.048V
30
4–20mA MODE
20
10
0
0
OFFSET ENABLED
(EN_I = HIGH)
0 TO 16mA MODE
-10
-20
-30
-40
-50
-50
-100
-150
-0.5
-20,000
-10,000
0
10,000
20,000
-40 -20
0
20
40
60
80
4
6
8
10 12 14 16 18 20
DAC CODE (COUNTS)
TEMPERATURE (°C)
4-20OUT OUTPUT CURRENT (mA)
_______________________________________________________________________________________
1
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
Pin Description
PIN
NAME
ꢅUNCTION
Positive Analog Input. Positive side of fully differential analog input. Bypass AIN+ to GND with a
0.1µF or greater capacitor.
1
AIN+
Negative Analog Input. Negative side of fully differential analog input. Bypass AIN- to GND with a
0.1µF or greater capacitor.
2
3
4
AIN-
GND
Ground. Connect to star ground.
Analog Positive Supply ꢀoltage. Connect Aꢀ
to GND with a 0.1µF capacitor.
to a +2.7ꢀ to +5.25ꢀ power supply. Bypass Aꢀ
DD
DD
Aꢀ
Dꢀ
DD
Digital Positive Supply ꢀoltage. Connect Dꢀ to a +2.7ꢀ to +5.25ꢀ power supply. Bypass Dꢀ
DD
DD
5
6
DD
to GND with a 0.1µF capacitor.
Segment Current Set. Connect to ground through a resistor to set the segment current. See Table
7 for segment-current selection.
SET
7
REG_ꢀDD
REG_FORCE
REG_AMP
CMP
ꢀ/I Converter Regulated Supply Output. REG_ ꢀDD is typically 2.5ꢀ.
REG_ꢀDD Control. Drives the gate of external depletion mode FET.
Regulator/Reference Buffer Supply. Connect to a 4.75ꢀ to 5.25ꢀ power supply.
Regulator Compensation Node. Connect a 0.1µF capacitor from CMP to REG_FORCE.
DAC Analog Supply. Connect DAC_ꢀDD to a +2.7ꢀ to +5.25ꢀ power supply.
DAC ꢀoltage Output. DAC output impedance is typically 6.2kΩ.
ꢀ/I Converter Input
8
9
10
11
12
13
14
15
16
DAC_ꢀDD
DACꢀOUT
CONꢀ_IN
4–20OUT
GND_DAC
GND_ꢀ/I
4–20mA (0 to 16mA) Current-Loop Output. Referenced to GND.
DAC Analog Ground. Connect to star ground.
ꢀ/I Converter Analog Ground. Connect to star ground.
ꢀ-to-I Converter/DAC Reference Input. Connect a voltage source for external reference operation
or leave floating for internal reference. Bypass REF_DAC with a 0.1µF capacitor to GND for either
internal or external reference operation.
17
REF_DAC
18
19
EN_BPM
EN_I
Active-High ꢀ/I-Converter Bipolar-Mode Enable. Set high for bipolar mode. Set low for unipolar mode.
Active-High ꢀ/I-Converter 4mA Offset Enable. Set low for 0 to 16mA output. Set high for 4–20mA
DAC External Reference Selection. Set low for internal reference. Set high for external reference.
Leave REF_DAC unconnected when REFSELE is low.
20
REFSELE
DAC Data-Source Select. Set high to select DAC register. Set low to have the DAC follow the ADC
output.
21
22
DACDATA_SEL
CS_DAC
DAC SPI Chip Select. See Table 8.
External Clock Input. When the EXTCLK register bit is set to one, CLK is the master clock input for
the modulator, filter, and DAC. When the EXTCLK register bit is reset to zero, the internal clock is
used. The default power-on state is EXTCLK = 0 (internal clock mode). Connect CLK to GND or
23
24
CLK
Dꢀ
when using internal clock.
DD
Active-Low End-of-Conversion Logic Output. A logic-low at EOC indicates that a new ADC result is
available in the ADC result register.
EOC
±0 ______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
Pin Description (continued)
PIN
NAME
ꢅUNCTION
Serial Clock Input. Apply an external clock to SCLK to facilitate communication through the serial
bus. SCLK may idle high or low.
25
SCLK
Serial Data Output. DOUT presents serial data in response to register queries. Data shifts out on
the falling edge of SCLK. DOUT goes high impedance when CS is high.
26
27
DOUT
DIN
Serial Data Input. Data present at DIN is shifted into the internal registers in response to a rising
edge at SCLK when CS is low.
28
29
30
31
32
33
34
35
36
CS
Active-Low Chip-Select Input. Forcing CS low activates the serial interface. (See Table 8.)
LEDG
DIG0
DIG1
DIG2
DIG3
DIG4
SEGA
SEGB
LED Segment-Drivers Ground
Digit 0 Driver Out (Connected to GLED for the MAX1368)
Digit 1 Driver Out
Digit 2 Driver Out
Digit 3 Driver Out
Digit 4 Driver Out
Segment A Driver
Segment B Driver
LED-Display Segment-Driver Supply. Connect to a +2.7ꢀ to +5.25ꢀ supply. Bypass with a 0.1µF
capacitor to LEDG.
37
LEDꢀ
38
39
40
41
42
43
SEGC
SEGD
SEGE
SEGF
Segment C Driver
Segment D Driver
Segment E Driver
Segment F Driver
SEGG
SEGDP
Segment G Driver
Segment Decimal-Point Driver
Active-High LED Enable. The MAX1366/MAX1368 display driver turns off when LED_EN is low.
The MAX1366/MAX1368 LED-display driver turns on when LED_EN is high.
44
45
46
LED_EN
NEGꢀ
-2.5ꢀ Charge-Pump ꢀoltage Output. Connect a 0.1µF capacitor to GND.
Low-Battery-ꢀoltage Monitor. When the LOWBATT input voltage is lower than 2.048ꢀ, the
LOWBATT bit in the status register is set to one.
LOWBATT
Negative Reference ꢀoltage Input. For internal reference operation, connect REF- to GND. For
external reference operation, bypass REF- to GND with a 0.1µF capacitor and
47
48
REF-
set ꢀ
from -2.2ꢀ to +2.2ꢀ (ꢀ
> ꢀ
).
REF-
REF-
REF+
Positive Reference ꢀoltage Input. For internal reference operation, connect a 4.7µF capacitor from
REF+ to GND. For external reference operation, bypass REF+ to GND with a 0.1µF capacitor and
REF+
set ꢀ
from -2.2ꢀ to +2.2ꢀ, provided that ꢀ
> ꢀ
.
REF-
REF+
REF+
______________________________________________________________________________________ ±±
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
Functional Diagram
AV
DV
CLK SCLK DIN DOUT CS CS_DAC
EOC DACDATA_SEL SET
LEDV
DD
DD
SERIAL I/O AND CONTROL
+2.5V
SEGA
AIN+
AIN-
SEGG
LED
DRIVER
ADC
DIG0(1)
DIG4(4)
DISPLAY REGISTER
ADC REGISTER
DAC REGISTER
INPUT
BUFFER
LED_EN
LEDG
DAC_VDD
DACVOUT
CONV_IN
REF+
REF-
CS_DAC DIN SCLK
CURRENT
SUMMER
AND
OUTPUT
DAC
V/I
CONVERTER
-2.5V
4-20OUT
2.048V
BANDGAP
REFERENCE
AMPLIFIER
DAC REF
BUFFER
EN_I
OFFSET
GENERATOR
CHARGE
PUMP
NEGV
-2.5V
EN_BPM
5V REGULATOR
MAX1366
(MAX1368)
GND
REFSELE REF_DAC REG_AMP CMP REG_FORCE REG_VDD
Detailed Description
For added flexibility, the MAX1366/MAX1368 allow
direct access to the ADC register, LED display register,
and DAC output register using the SPI interface.
The MAX1366/MAX1368 low-power, highly integrated
ADCs with LED drivers convert a 2ꢀ differential input
voltage (one count is equal to 100µꢀ for the MAX1366
and 1mꢀ for the MAX1368) with a sigma-delta ADC and
output the result to an LED display. An additional
200mꢀ input range (one count is equal to 10µꢀ for the
MAX1366 and 100µꢀ for the MAX1368) is available to
measure small signals with finer resolution.
The MAX1366/MAX1368 include a 2.048ꢀ reference,
internal charge pump, and a high-accuracy on-chip
oscillator. The devices feature on-chip buffers for the dif-
ferential input signal and external-reference inputs,
allowing direct interface with high-impedance signal
sources. In addition, they use continuous internal offset
calibration and offer > 100dB of 50Hz and 60Hz line-
noise rejection. Other features include data hold and
peak detection and overrange/underrange detection.
In addition to displaying the results on an LED display,
these devices feature a DAC and ꢀ-to-I converter for
4–20mA (or 0 to 16mA) current output that proportional-
ly follows the ADC input. The MAX1366/MAX1368 use
an external depletion-mode nMOS transistor to regulate
7ꢀ to 30ꢀ for the ꢀ/I converter. Use the 4–20mA (or 0 to
16mA) output to drive a remote display, data logger,
PLC input, or other 4–20mA devices in a current loop.
Analog Input Protection
The MAX1366/MAX1368 provide internal protection
diodes that limit the analog input range on AIN+, AIN-,
REF+, and REF- from NEGꢀ to (Aꢀ
+ 0.3ꢀ). If the
DD
analog input exceeds this range, limit the input current
to 10mA.
The MAX1366/MAX1368 interface with a µC using an
SPI-/QSPI-/MICROWIRE-compatible serial interface.
±2 ______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
Internal Analog Input/Reference Buffers
0
The MAX1366/MAX1368 analog input/reference buffers
allow the use of high-impedance signal sources. The
-40
input buffers’ common-mode input range allows the ana-
log inputs and the reference to range from -2.2ꢀ to +2.2ꢀ.
-80
Modulator
The MAX1366/MAX1368 perform analog-to-digital con-
versions using a single-bit, 3rd-order, sigma-delta mod-
-120
ulator. The sigma-delta modulator converts the input
signal into a digital pulse train whose average duty
-160
cycle represents the digitized signal information. The
modulator quantizes the input signal at a much higher
-200
sample rate than the bandwidth of the input. The
0
10
20
30
40
50
60
MAX1366/MAX1368 modulator provides 3rd-order fre-
quency shaping of the quantization noise resulting from
the single-bit quantizer. The modulator is fully differen-
tial for maximum signal-to-noise ratio and minimum sus-
ceptibility to power-supply noise. A single-bit data
stream is then presented to the digital filter to remove
the frequency-shaped quantization noise.
FREQUENCY (Hz)
4
Figure 1. Frequency Response of the SINC Filter (Notch at 60Hz)
ratio (OSR) for the MAX1368 is 128 and the OSR for the
MAX1366 is 1024. The output data rate for the digital fil-
ter corresponds to the positioning of the first notch of
the filter’s frequency response. The notches of the
SINC4 filter are repeated at multiples of the first notch
frequency. The SINC4 filter provides an attenuation of
better than 100dB at these notches. For example, 50Hz
is equal to 10 times the first notch frequency and 60Hz
is equal to 12 times the first notch frequency. For large
step changes at the input, allow a settling time of
800ms before valid data is read.
Digital Filtering
The MAX1366/MAX1368 contain an on-chip digital low-
pass filter that processes the data stream from the
modulator using a SINC4 response:
4
sin(x)
x
The SINC4 filter has a settling time of four output data
periods (4 x 200ms). The MAX1366/MAX1368 have
25% overrange capability built into the modulator and
Clock Modes
Configure the MAX1366/MAX1368 to use either the
internal oscillator or an externally applied clock to drive
the modulator, filter, and DAC. Set the EXTCLK bit in
the control register to zero to put the device in internal
clock mode. Set the EXTCLK bit to one to put the
device in external clock mode. When using the internal
digital filter. The digital filter is optimized for the f
CLK
equal to 4.9152MHz. The frequency response of the
SINC4 filter is calculated as follows:
4
−N
−1
1(1− Z
)
H(z)=
H(f)=
oscillator, connect CLK to GND or Dꢀ . The
DD
N
(1−Z
)
MAX1366/MAX1368 operate with a 4.9152MHz clock to
achieve maximum rejection of 50Hz/60Hz common-
mode, power-supply, and normal-mode noise.
4
f
sin Nπ
f
1
N
m
Internal Clock Mode
The MAX1366/MAX1368 contain an internal oscillator.
The power-up condition for the MAX1366/MAX1368 is
internal clock operation with the EXTCLK bit in the con-
trol register equal to zero. Using the internal oscillator
saves board space by removing the need for an exter-
nal clock source.
πf
sin
f
m
where N is the oversampling ratio, and f = N x output
m
data rate = 5Hz.
Filter Characteristics
Figure 1 shows the filter frequency response. The
SINC4 characteristic -3dB cutoff frequency is 0.228
times the first notch frequency (5Hz). The oversampling
External-Clock Mode
For external clock operation, set the EXTCLK bit in the
control register to one and drive CLK with a 4.9152MHz
______________________________________________________________________________________ ±ꢁ
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
Table ±. LED Priority Table
A
A
A
A
A
DISPLAY ꢂALUES
ꢅORM
SEꢈ_SEL SPI/ADC HOLD PEAK
F
E
F
F
E
F
E
B
B
B
B
B
G
G
G
G
F
C
C
C
C
C
D
E
DP
LED segment
registers
DP
DP
DP
DP
1
0
X
1
X
X
X
X
D
D
D
D
G
DIGIT 4
DIGIT 3
DIGIT 2
DIGIT 1
DIGIT 0
LED display register
(user written)
0
0
0
0
1
0
0
X
1
0
LED display register
Peak register
Figure 2. Segment Connection for the MAX1366 (4.5 Digits)
0
0
ADC result register
A
A
A
A
X = Don’t care.
F
E
F
F
E
B
B
B
B
G
G
G
F
C
C
C
C
Figure 4 shows a typical common-cathode configura-
tion for two digits. In common-cathode configuration,
the cathodes of all LEDs in a digit are connected
together. Each segment driver of the MAX1366/
MAX1368 connects to its corresponding LED’s anodes.
For example, segment driver SEGA connects to all LED
segments designated as A. Similar configurations are
used for other segment drivers.
D
E
DP
DP
DP
DP
D
D
D
G
DIGIT 4
DIGIT 3
DIGIT 2
DIGIT 1
Figure 3. Segment Connection for the MAX1368 (3.5 Digits)
clock source for best 50Hz/60Hz rejection perfor-
mance. Other external clock frequencies allow for cus-
tom conversion rates. A 2.4576MHz clock signal
reduces the conversion rate and the LED update rate
by a factor of two while keeping good 50Hz/60Hz noise
rejection. The MAX1366/MAX1368 operate with an
external clock source of up to 5.05MHz.
The MAX1366/MAX1368 use a multiplexing scheme to
drive one digit at a time. The scan rate is fast enough to
make the digits appear to be lit. Figure 5 shows the
data-timing diagram for the MAX1366/MAX1368 where
t is the display scan period (typically around 1/512Hz
or 1.9531ms). t
time each digit is on and is calculated as follows:
in Figure 5 denotes the amount of
ON
Charge Pump
The MAX1366/MAX1368 contain an internal charge pump
to provide the negative supply voltage for the internal
analog input/reference buffers. The bipolar input range of
the analog input/reference buffers allows this device to
accept negative inputs with high source impedances.
Connect a 0.1µF capacitor from NEGꢀ to GND.
t
5
1.95312ms
5
t
=
=
= 390.60µs
ON
Decimal-Point Control
The MAX1366/MAX1368 allow for full decimal-point
control and feature leading-zero suppression.
LED Driver (Table 1)
The MAX1366 has a 4.5-digit common-cathode display
driver, and the MAX1368 has a 3.5-digit common-cath-
ode display driver.
Use the DPON, DPSET1, and DPSET2 bits in the con-
trol register to set the value of the decimal point (Tables
2 and 3). The MAX1366/MAX1368 overrange and
underrange display is shown in Table 4.
Figures 2 and 3 show the connection schemes for a
standard seven-segment LED display. The LED update
rate is 2.5Hz.
Current Output
The MAX1366/MAX1368 feature a 4–20mA (0 to 16mA)
current output for driving remote panel meters, data log-
gers, and process controllers in industrial applications.
The DAC output is proportional to the input of the ADC
and LED display. In the simplest configuration, connect
DAC_ꢀOUT directly to CONꢀ_IN to have the current out-
put (4–20mA or 0 to 16mA) follow the analog inputs.
The MAX1366/MAX1368 automatically display the results
of the ADC, if desired. The MAX1366/MAX1368 also
allow independent control of the LED driver through the
serial interface, allowing for data processing of the ADC
result before showing the result on the LED. Additionally,
each LED segment can be individually controlled (see
the LED Segment-Display Register sections).
±4 ______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
SEGDP
SEGG
SEGF
SEGE
SEGD
SEGC
SEGB
SEGA
A
B
C
D
E
F
G
DP
A
B
C
D
E
F
G
DP
DIGIT 1
A
DIGIT 2
A
F
E
F
B
B
G
G
C
C
E
DP
DP
D
D
Figure 4. 2-Digit Common-Cathode Configuration
t
ON
DIGIT 4 (MSD)
INTERDIGIT
BLANKING TIME
DIGIT 2
DIGIT 1
DIGIT 0 (LSD)
t
DATA
4
MSD
3
2
1
0
LSD
4
3
2
1
0
4
Figure 5. LED Voltage Waveform
Table ꢁ. Decimal-Point Control Table—
MAꢀ±ꢁ36
Table 2. Decimal-Point Control Table—
MAꢀ±ꢁ33
DISPLAY ꢄERO INPUT
DISPLAY
OUTPUT
ꢄERO INPUT
READINꢈ
DPON
DPSET± DPSET2
DPON DPSET± DPSET2
OUTPUT
READINꢈ
1
1
1
1
0
0
1
1
0
1
0
1
1888
188.8
18.88
1.888
0.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
18888
18888
18888
18888
1888.8
188.88
18.888
1.8888
0
0
0.0
0.00
0.000
0
0
0.0
0.00
0.000
0.0000
______________________________________________________________________________________ ±5
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
CS OR CS_DAC
t
t
CSH
CSS
t
CSH
t
CH
SCLK
t
DS
t
DH
DIN
t
t
t
TR
DV
DO
DOUT
Figure 6. ADC and DAC Timing Diagram
CS
SCLK
1
0
RS4 RS3 RS2 RS1 RS0
CONTROL BYTE
x
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
DIN
DOUT
Figure 7. Serial-Interface, 16-Bit, Write Timing Diagram
Custom signal conditioning can be inserted between
DAC_ꢀOUT and CONꢀ_IN, or CONꢀ_IN can be driven
independently by a voltage source if desired. See
Figures 20–23 for the transfer functions of the DAC and
ꢀ/I converter.
Table 4. LED During Overrange and
Underrange Conditions
CONDITION
Overrange
MAꢀ±ꢁ36
1---
MAꢀ±ꢁ33
1----
Note: The MAX1366/MAX1368 expect a 6kΩ (typ)
source impedance from the voltage source driving
CONꢀ_IN.
Underrange
-1---
-1----
Current Offset
Set EN_I high for a current span of 4–20mA. Set EN_I
low for a current span of 0 to 16mA. See Table 5 for
current output.
Bipolar Mode
Set EN_BPM high to engage bipolar operation. In bipo-
lar mode, the current output at 4-20OUT (4–20mA or 0
to 16mA) maps the analog input voltage ( 2ꢀ or
200mꢀ). In bipolar mode, a 0ꢀ analog input maps to
midscale (12mA). See Table 5 for current output. Also
see Figures 21 and 22.
Unipolar Mode
Set EN_BPM low to engage unipolar operation. In unipo-
lar mode, the current output at 4-20OUT (4–20mA or 0 to
16mA) maps the analog input voltage (0 to 2ꢀ or 0 to
200mꢀ). Negative voltages at the analog input result in a
4mA or 0mA output, depending on the EN_I setting. See
Table 5 for current output. See Figures 21 and 22.
±3 ______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
CS
CS_DAC
SCLK
1
0
RS4 RS3 RS2 RS1 RS0
CONTROL BYTE
X
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
DIN
DOUT
Figure 8. Serial-Interface, 8-Bit, Write Timing Diagram
CS
CS_DAC
SCLK
1
1
RS4 RS3 RS2 RS1 RS0
CONTROL BYTE
X
DIN
DATA BYTE
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
Figure 9. Serial-Interface, 16-Bit, Read Timing Diagram
Table 5. Current-Output Table
CURRENT OUTPUT (mA)
ANALOꢈ INPUT
UNIPOLAR MODE
(EN_I = LOW)
UNIPOLAR MODE
(EN_I = HIꢈH)
BIPOLAR MODE
(EN_I = LOW)
BIPOLAR MODE
(EN_I = HIꢈH)
Negative Full Scale
0ꢀ
0
0
4
4
0
8
4
12
20
Positive Full Scale
16
20
16
______________________________________________________________________________________ ±7
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
CS
CS_DAC
SCLK
1
1
RS4 RS3 RS2 RS1 RS0
CONTROL BYTE
X
DIN
DATA BYTE
D7 D6 D5 D4 D3 D2 D1 D0
DOUT
Figure 10. Serial-Interface, 8-Bit, Read Timing Diagram
CS
CS_DAC
SCLK
D14
D9
D8
D5 D4 D3
D1 D0
D15
D13 D12 D11 D10
D7 D6
D2
DIN
DATA BYTE
Figure 11. DAC Serial Interface
DV
DD
DV
DD
6kΩ
6kΩ
DOUT
DOUT
DOUT
DOUT
C
50pF
C
50pF
LOAD
LOAD
6kΩ
C
LOAD
50pF
C
50pF
LOAD
6kΩ
GND
GND
GND
GND
A) V TO HIGH IMPEDANCE
B) HIGH IMPEDANCE TO
AND V TO V
B) HIGH IMPEDANCE TO
AND V TO V
B) V TO HIGH IMPEDANCE
OH
OL
V
OH
V
OL
OL
OH
OH
OL
Figure 12. Load Circuits for Disable Time
Figure 13. Load Circuits for Enable Time
±6 ______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
ANALOG SUPPLY
FERRITE
BEAD
10µF
0.1µF
10µF
0.1µF
AV
DD
DV
DD
REF+
0.1µF
0.1µF
R
REF
MAX1366
MAX1368
REF-
4–20mA/0 TO 16mA
CURRENT-LOOP
OUTPUT
ACTIVE
GAUGE
4-20OUT
R
R
AIN+
AIN-
SCLK
DIN
DOUT
CS
0.1µF
DUMMY
GAUGE
0.1µF
EOC
GND
Figure 14. Strain-Gauge Application with the MAX1366/MAX1368
TEMP
SENSOR
THERMOCOUPLE
JUNCTION
MAX1366
MAX1368
AIN+
AIN-
SPI
µC
0.1µF
+5V
NEGV
+2.048V
REF+
REF-
MAX6062
4–20mA/0 TO 16mA
CURRENT-LOOP OUTPUT
4-20OUT
GND
0.47µF
Figure 15. Thermocouple Application with the MAX1366/MAX1368
______________________________________________________________________________________ ±1
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
ADC
RESULT
ADC
RESULT
LED
LED
1 - - - -
19,999
> 4E1Fh
4E1Fh
1 - - -
1999
> 7CFh
7CFh
2
1
0002h
2
1
002h
0001h
0000h
001h
000h
0
0
- 0 FFFFh
- 0
- 1
- 2
FFFh
FFEh
FFDh
- 1
- 2
FFFEh
FFFDh
B1E0h
-19,999
830h
-1999
< B1E0h
- 1 - - - -
- 1 - - - < 830h
-100µV 0 +100µV
+100µV
0
-100µV
-2V
+2V
-200mV
+200mV
ANALOG INPUT VOLTAGE
ANALOG INPUT VOLTAGE
Figure 18. MAX1368 Transfer Function— 200mV Range
Figure 16. MAX1366 Transfer Function— 2V Range
LED
ADC
RESULT
ADC
RESULT
LED
1 - - - -
19,999
> 4E1Fh
4E1Fh
1 - - -
1999
> 7CFh
7CFh
2
1
0002h
002h
2
1
0001h
0000h
001h
000h
0
0
- 0 FFFFh
FFFh
FFEh
- 0
- 1
- 1
- 2
FFFEh
FFFDh
- 2 FFDh
B1E0h
-19,999
830h
-1999
< B1E0h
- 1 - - - -
< 830h
- 1 - - -
-10µV 0 +10µV
-1mV 0
+1mV
-200mV
+200mV
-2V
+2V
ANALOG INPUT VOLTAGE
ANALOG INPUT VOLTAGE
Figure 17. MAX1366 Transfer Function— 200mV Range
Figure 19. MAX1368 Transfer Function— 2V Range
The FET breakdown and saturation voltages determine
the usable range of loop voltages (ꢀ ). The external
5.2V Linear Regulator with Compensation
The MAX1366/MAX1368 feature a 5.2ꢀ linear regulator.
The 5.2ꢀ regulator consists of an op amp and connec-
tions to an external depletion-mode FET. The 5.2ꢀ reg-
ulator regulates the loop voltage that powers the
voltage-to-current converter and the rest of the trans-
mitter circuitry. The regulator output voltage is available
at REG_ꢀDD and is given by the equation:
EXT
FET parameters such as ꢀ
(off), I
, and transcon-
GS
DSS
ductance must be chosen so that the op amp output on
the REG_FORCE pin can control the FET operating
point while swinging in the range from ꢀREG_AMP to
REG_ꢀDD. See the Selecting Depletion Mode FET
section in the Applications Information section.
Connect a 0.1µF capacitor between CMP and
REG_FORCE to ensure stable operation of the regulator.
ꢀ
= 2.54 x ꢀ
REF+
REG_ꢀDD
20 ______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
UNIPOLAR:
BIPLOLAR:
UNIPOLAR:
BIPLOLAR:
CURRENT
OFFSET
DISABLED
(EN_I = 0)
1.25
16
8
0
0
- FS
+ FS
0
- FS
FS = FULL SCALE
0
+ FS
ADC OUTPUT CODE
ADC OUTPUT CODE
FS = FULL SCALE
Figure 22. Output Current (4-20OUT) vs. ADC Output Code
(Current Offset Disabled)
Figure 20. DAC Output Voltage vs. ADC Output Code
UNIPOLAR:
BIPLOLAR:
OFFSET ENABLED:
OFFSET DISABLED:
CURRENT
OFFSET
ENABLED
(EN_I = 1)
20
12
20
16
4
0
4
0
- FS
+ FS
0
1. 25
V/I CONVERTER INPUT ( V )
0
ADC OUTPUT CODE
FS = FULL SCALE
Figure 21. Output Current (4-20OUT) vs. ADC Output Code
(Current Offset Enabled)
Figure 23. 4-20OUT Output Current vs. V/I Converter Input
Voltage
Leading-Zero Suppression
The MAX1366/MAX1368 include a leading-zero sup-
pression circuitry to turn off unnecessary zeros. For
example, when DPSET1 and DPSET2 = [0,0], 0.0 is dis-
played instead of 000.0 (MAX1366). This feature saves
a substantial amount of power by not lighting unneces-
sary LEDs.
Interdigit Blanking
The MAX1366/MAX1368 also include interdigit-blanking
circuitry. Without this feature, it is possible to see a faint
digit next to a digit that is completely on. The
interdigit-blanking circuitry prevents ghosting over into
the next digit for a short period of time. The typical
interdigit blanking time is 4µs.
______________________________________________________________________________________ 2±
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
registers are accessed next, and whether a read or
Applications Information
write operation takes place. Transitions on the serial
Power-On Reset
At power-on, the serial interface, logic, LED drivers,
digital filter, modulator, and DAC circuits reset. The
registers return to their default values.
clock after the command byte transfer, cause a write or
read from the device until the correct number of bits
have been transferred (8 or 16). Once this has
occurred, the MAX1366/MAX1368 wait for the next
command byte. CS must not go high between data
transfers. If CS is toggled before the end of a write or
read operation, the device mode may be unknown.
Clock in 32 zeros to clear the device state and reset the
interface so it is ready to receive a new command byte.
Serial Interface
The SPI/QSPI/MICROWIRE serial interface consists of a
chip select (CS), a serial clock (SCLK), a data in (DIN),
a data out (DOUT), DAC chip select (CS_DAC), and an
EOC output. CS and CS_DAC enable access to regis-
ters in the MAX1366/MAX1368. CS allows a read and
write to all registers of the MAX1366/MAX1368 exclud-
ing the DAC register and CS_DAC enables a write to
the DAC register (see Table 8). EOC provides an end-
To write to the DAC register, pull CS_DAC low and
clock in 16 data bits. Data bits are clocked in MSB first
(see the DAC Operation section).
On-Chip Registers (Excluding
DAC Register)
of-conversion signal with a period of 200ms (f
=
CLK
4.9152MHz). The MAX1366/MAX1368 update the ADC
register when EOC goes high. Data is valid in the ADC
register when EOC returns low. The serial interface pro-
vides access to 13 on-chip registers, allowing control to
all the power modes and functional blocks. Table 6 lists
the address and read/write accessibility of all the regis-
ters excluding the DAC register.
The MAX1366/MAX1368 contain 12 on-chip registers.
These registers configure the various functions of the
device and allow independent reading of the ADC
results and writing to the LED display. Table 6 lists the
address and size of each register. The first of these
registers is the status register. The 8-bit status register
contains the status flags for the ADC. The second reg-
ister is the 16-bit control register. This register sets the
LED display controls, range modes, power-down
modes, offset calibration, and the reset register func-
tion (CLR). The third register is the 16-bit overrange
register, which sets the overrange limit of the analog
input. The fourth register is the 16-bit underrange regis-
ter, which sets the underrange limit of the analog input.
Registers 5 through 7 contain the display data for the
individual segments of the LED. The eighth register
contains the custom offset value. The ninth register
contains the 16 MSBs of the ADC conversion result.
The 10th register contains the LED data. The 11th reg-
ister contains the peak analog input value. The last reg-
ister contains the lower 4 LSBs of the 20-bit ADC
conversion result.
A logic-high on CS and CS_DAC tri-states DOUT and
causes the MAX1366/MAX1368 to ignore any signals
on SCLK and DIN. To clock data in or out of the internal
shift register, drive CS or CS_DAC low. SCLK synchro-
nizes the data transfer. The rising edge of SCLK clocks
DIN into the shift register, and the falling edge of SCLK
clocks DOUT out of the shift register. DIN and DOUT
are transferred MSB first (data is left justified). Figures
6–10 show the detailed serial-interface timing diagrams
for the 8- and 16-bit read/write operations.
All communication with the MAX1366/MAX1368, with
exception of the DAC register, begins with a command
byte on DIN, where the first logic one on DIN is recog-
nized as the START bit (MSB) for the command byte.
The following seven clock cycles load the command
into a shift register. These 7 bits specify which of the
22 ______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
Table 3. Register-Address Table
REꢈISTER
ADDRESS RS[4:0]
00000
NAME
WIDTH
8
ACCESS
Read only
R/W
1
2
Status register
Control register
00001
16
16
16
16
16
8
3
00010
Overrange register
R/W
4
00011
Underrange register
R/W
5
00100
LED segment-display register 1
LED segment-display register 2
LED segment-display register 3
ADC custom offset register
ADC result register (16 MSBs)
LED data register
R/W
6
00101
R/W
7
00110
R/W
8
00111
16
16
16
16
8
R/W
9
01000
R/W
10
11
12
—
01001
R/W
01010
Peak register
R/W
10100
ADC result register 2 (4 LSBs)
Reserved
R/W
All other addresses
—
—
Table 7. Segment-Current Selection
Table 1. ꢅET Characteristics
R
(kΩ)
I
(mA)
ꢅET TYPE
n-CHANNEL DEPLETION MODE
30mA
(ꢀ * - REG_ꢀDD) min
ISET
SEꢈ
25
20
I
DS
50
100
10
5
Bꢀ
DS
EXT
ꢀ
REG_ꢀDD max
30mA x (ꢀ - REG_ꢀDD) min
PINCHOFF
500
1
Power dissipation
*V is the 7V to 30V loop voltage.
EXT
> 2500
LED driver disabled
EXT
Table 6. CS and CS_DAC Table
DESCRIPTION
CS
CS_DAC
Reserved.
0
0
Read or write to on-chip registers
excluding the DAC register.
0
1
1
1
0
1
Write to the DAC register only.
DOUT is high impedance. DIN and
SCLK are ignored.
______________________________________________________________________________________ 2ꢁ
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
Control and Status Registers
Command Byte (Write Only)
MSB
Bit 7
LSB
Bit 0
X
Bit 6
Bit 5
RS4
Bit 4
RS3
Bit 3
RS2
Bit 2
RS1
Bit 1
RS0
START(1)
R/W
START: Start bit. The first 1 clocked into the MAX1366/
MAX1368 is the first bit of the command byte.
only. Write commands to a read-only register are
ignored.
(R/W): Read/Write. Set this bit to 1 to read from the
specified register. Set this bit to zero to write to the
selected register. Note that certain registers are read
(RS4–RS0): Register address bits. RS4 to RS0 specify
which register is accessed.
ꢀ: Don’t care.
Status Register (Read Only)
MSB
LSB
SIGN
OꢀER
UNDER
LOW_BATT
DRDY
0
0
0
Default values: 00h
This register contains the status of the conversion
results.
value in the underrange register). Clears by reading the
status register, unless the condition remains true.
SIꢈN: Latched negative-polarity indicator. Latches high
when the result is negative. Clears by reading the sta-
tus register, unless the condition remains true.
LOW_BATT: Low-battery bit. Latches high if the volt-
age at the LOWBATT is lower than 2.048ꢀ (typ). Clears
by reading the status register, unless the condition
remains true.
OꢂER: Overrange bit. Latches high if an overrange
condition occurs (the ADC result is larger than the
value in the overrange register). Clears by reading the
status register, unless the condition remains true.
DRDY: Data-ready bit. Latches high to indicate a com-
pleted conversion result with valid data. Read the ADC
result register to clear this bit.
UNDER: Underrange bit. Latches high if an underrange
condition occurs (the ADC result is less than the
Control Register (Read/Write)
MSB
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
PD_ANA
LSB
SPI/ADC
EXTCLK
INTREF
DPON
DPSET2
DPSET1
PD_DIG
Bit 7
Bit 6
Bit 5
Bit 4
CLR
Bit 3
Bit 2
Bit 1
Bit 0
OFFSET_
CAL2
HOLD
PEAK
RANGE
SEG_SEL
OFFSET_CAL1
ENABLE
Default values: 0000h
This register is the primary control register for the
MAX1366/MAX1368. It is a 16-bit read/write register. It
is used to indicate the desired clock and reference
source. It sets the LED display controls, range modes,
power-down modes, offset calibration, and the reset
register function (CLR).
ENABLE: (Default = 1.) LED driver enable bit. When set
to 1, the MAX1366/MAX1368 enables the LED display
drivers. A 0 in this location disables the LED dis-
play drivers.
OꢅꢅSET_CAL2: (Default = 0.) Enhanced offset-calibra-
tion start bit (RANGE = 1). To achieve the lowest possi-
ble offset in the 200mꢀ input range, perform an
enhanced offset calibration by setting this bit to 1. The
calibration takes about nine cycles (1800ms). After the
calibration completes, set this bit to zero to resume
ADC conversions.
24 ______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
PD_DIꢈ: (Default = 0.) Power-down digital select bit.
When set to 1, the digital circuits (digital filter and LED
drivers) go into power-down mode. This also resets the
values of the internal SRAM in the digital filter to zeros.
When set to zero, the device returns to full power-up
mode. When powering down PD_DIG, power down the
LED segment drivers by clearing the ENABLE bit to zero.
OꢅꢅSET_CAL±: (Default = 0.) Automatic offset-calibra-
tion enable bit. When set to 1, the MAX1366/
MAX1368 disable automatic offset calibration. When
this bit is set to zero, automatic offset calibration is
enabled.
SEꢈ_SEL: (Default = 0.) SEG_SEL segment selection
bit. When set to 1, the LED segment drivers use the
LED segment registers to display individual segments
that can form letters or numbers or other information on
the display. The LED data register is not displayed.
Send the data first to the LED segment-display regis-
ters and then set this bit high.
DPSET[2:±]: (Default = 00.) Decimal-point selection
bits (Table 2 and 3).
DPON: (Default = 0.) Decimal-point enable bit (Tables
2 and 3).
INTREꢅ: (Default = 0.) Reference select bit. For internal
reference operation, set INTREF to 1. For external refer-
ence operation, set INTREF to zero.
CLR: (Default = 0.) Clear all registers bit. When set to
1, all registers reset to their power-on reset states after
CS makes a low-to-high transition.
EꢀTCLK: (Default = 0.) External clock select bit. The
EXTCLK bit controls selection of the internal clock or an
external clock source. A 1 in this location selects the
signal at the CLK input as the clock source. A zero in
this location selects and powers up the internal clock
oscillator.
RANꢈE: (Default = 0.) Input range select bit. When set
to zero, the input voltage range is 2ꢀ. When set to 1,
the input voltage range is 200mꢀ.
PEAK: (Default = 0.) Peak bit. When set to 1 (and the
HOLD bit is set to zero), the LED shows the result
stored in the peak register (see Table 6).
SPI/ADC: (Default = 0.) Display select bit. The SPI/ADC
bit controls selection of the data fed into LED data reg-
ister. A 1 in this location selects SPI/QSPI/MICROWIRE
data (user writes this data to the LED data register). A
zero in this location selects the ADC result register
data, unless hold or peak functions are active (Table 1).
HOLD: (Default = 0.) Hold bit. When set to 1, the LED
register does not update from the ADC conversion
results and holds the last result on the LED. The
MAX1366/MAX1368 continue to perform conversions
during HOLD (Table 1).
Note: When changing any one of the following control
bits: OFFSET_CAL1, RANGE, PD_ANA, PD_DIG,
INTREF, and EXTCLK, wait 800ms before reading the
ADC results.
PD_ANA: (Default = 0.) Power-down analog select bit.
When set to 1, the analog circuits (analog modulator
and ADC input buffers) go into the power-down mode.
When set to zero, the device is in full power-up mode.
Overrange Register (Read/Write)
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default values:
7CF0h (for 3.5-digit, +1999)
4E1Fh (for 4.5-digit, +19,999)
dashes for the MAX1366 or a 1 followed by three dash-
es for the MAX1368 (Table 4).
The data is represented in two’s-complement format.
The overrange register is a 16-bit read/write register (D15
is the MSB). When the conversion result exceeds the
value in the overrange register, the OꢀER bit in the status
register latches to 1. The LED shows a 1 followed by four
______________________________________________________________________________________ 25
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
Underrange Register (Read/Write)
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default values:
8300h (for 3.5-digit, -2000)
B1E0h (for 4.5-digit, -20,000)
The underrange data register is 16-bit read/write regis-
ter (D15 is the MSB). When the conversion result falls
below the value in the underrange register, the UNDR
bit in the status register sets to 1. The LED shows a -1
followed by four dashes for the MAX1366 or a -1 fol-
lowed by three dashes for the MAX1368 (Table 4).
The data is represented in two’s-complement format.
Default values: 0000h
LED Segment-Display Register 1 (Read/Write)
MSB
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
X
Bit 8
B0
A1
G1
D1
F1
E1
DP2
LSB
Bit 0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
C0
A0
G0
D0
F0
E0
DP1
LED segment-display register 1 is a 16-bit read/write
register. When the LED bit (in the control register) is set
to 1, the MAX1366/MAX1368 provide direct access to
individual LED segments. The bits in the LED segment-
display register determine if a segment is on or off.
Write a zero to turn on a segment and a 1 to turn off a
segment.
C0: Segment C driver bit of digit 0. The default value
turns on the LED segment.
B0: Segment B driver bit of digit 0. The default value
turns on the LED segment.
ꢀ: Don’t care.
DP2: Segment DP driver bit of digit 2. The default value
turns on the LED segment.
DP±: Segment DP driver bit of digit 1. The default value
turns on the LED segment.
E±: Segment E driver bit of digit 1. The default value
turns on the LED segment.
E0: Segment E driver bit of digit 0. The default value
turns on the LED segment.
ꢅ±: Segment F driver bit of digit 1. The default value
turns on the LED segment.
ꢅ0: Segment F driver bit of digit 0. The default value
turns on the LED segment.
D±: Segment D driver bit of digit 1. The default value
turns on the LED segment.
D0: Segment D driver bit of digit 0. The default value
turns on the LED segment.
ꢈ±: Segment G driver bit of digit 1. The default value
turns on the LED segment.
ꢈ0: Segment G driver bit of digit 0. The default value
turns on the LED segment.
A±: Segment A driver bit of digit 1. The default value
turns on the LED segment.
A0: Segment A driver bit of digit 0. The default value
turns on the LED segment.
23 ______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
LED Segment-Display Register 2 (Read/Write)
MSB
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
G2
F3
E3
DP4
MINUS
B2
C2
A2
LSB
Bit 0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
X
Bit 2
Bit 1
D2
F2
E2
DP3
B1
C1
Default values: 0000h
LED segment-display register 2 is a 16-bit read/write
register. When the SEG_SEL bit (in the control register)
is set to 1, the MAX1366/MAX1368 provide direct
access to individual LED segments. The bits in the LED
segment-display register determine if a segment is on
or off. Write a zero to turn on a segment and a 1 to turn
off a segment.
ꢅ2: Segment F driver bit of digit 2. The default value
turns on the LED segment.
D2: Segment D driver bit of digit 2. The default value
turns on the LED segment.
ꢈ2: Segment G driver bit of digit 2. The default value
turns on the LED segment.
A2: Segment A driver bit of digit 2. The default value
turns on the LED segment.
C±: Segment C driver bit of digit 1. The default value
turns on the LED segment.
C2: Segment C driver bit of digit 2. The default value
turns on the LED segment.
B±: Segment B driver bit of digit 1. The default value
turns on the LED segment.
B2: Segment B driver bit of digit 2. The default value
MINUS: Segment minus driver bit. The default value
turns on the LED minus segment. Setting this bit to 1
enables the plus sign on the LED display.
turns on the LED segment.
DP4: Segment DP driver bit of digit 4. The default value
turns on the LED segment (MAX1366 only).
DPꢁ: Segment DP driver bit of digit 3. The default value
turns on the LED segment.
Eꢁ: Segment E driver bit of digit 3. The default value
turns on the LED segment (MAX1366 only).
E2: Segment E driver bit of digit 2. The default value
turns on the LED segment.
ꢅꢁ: Segment F driver bit of digit 3. The default value
turns on the LED segment (MAX1366 only).
LED Segment-Display Register 3 (Read/Write)
MSB
LSB
X
X
BC_
B3
C3
A3
G3
D3
Default values: 00h
LED segment-display register 3 is an 8-bit read/write
register. When the SEG_SEL bit (in the control register)
is set to 1, the MAX1366/MAX1368 provide direct
access to individual LED segments. The bits in the LED
segment-display register determine if a segment is on
or off. Write a zero to turn on a segment and a 1 to turn
off a segment.
Aꢁ: Segment A driver bit of digit 3. The default value
turns on the LED segment (MAX1366 only).
Cꢁ: Segment C driver bit of digit 3. The default value
turns on the LED segment (MAX1366 only).
Bꢁ: Segment B driver bit of digit 3. The default value
turns on the LED segment (MAX1366 only).
BC_: Segment B and C driver bit of digit 3 (3.5 digits)
or digit 4 (4.5 digits). The default value turns on the LED
segment.
Dꢁ: Segment D driver bit of digit 3. The default value
turns on the LED segment (MAX1366 only).
ꢈꢁ: Segment G driver bit of digit 3. The default value
turns on the LED segment (MAX1366 only).
ꢀ: Don’t care.
______________________________________________________________________________________ 27
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
ADC Custom Offset-Calibration Register 3 (Read/Write)
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default values: 0000h
In addition to automatic offset calibration, the
MAX1366/MAX1368 offer a user-defined custom offset
16-bit read/write register. The final result of the ADC
conversion is the input after autocalibration minus
the value in the custom offset. The custom offset value
is stored in this register. D15 is the MSB. The data is
represented in two’s-complement format.
ADC Result Register 1 (Read Only)
LSB
(MAꢀ±ꢁ36)
LSB
(MAꢀ±ꢁ33)
MSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default values: 0000h
ADC result register 1 is a 16-bit read-only register. This
register stores the 16 MSBs of the ADC result. The data
is represented in two’s-complement format.
For the MAX1366, the data is 16-bit and D15 is the
MSB. For the MAX1368, the data is 12-bit, D15 is the
MSB, and D4 is the LSB.
ADC Result Register 2 (Read Only)
MSB
LSB
D3
D2
D1
D0
0
0
0
0
Default values: 00h
ADC result register 2 is an 8-bit read-only register. This
register stores the 4 LSBs of the ADC result.
Use this result with the result in ADC result register 1 to
form a 20-bit two’s-complement conversion result.
LED Data Register (Read/Write)
LSB
(MAꢀ±ꢁ36)
LSB
(MAꢀ±ꢁ33)
MSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default values: 0000h
The LED data register is a 16-bit read/write register.
This register updates from ADC result register 1 or from
the serial interface by selecting the SPI/ADC bit in the
control register. The data is represented in two’s-com-
plement format.
For the MAX1366, the data is 16-bit and D15 is the
MSB. For the MAX1368, the data is 12-bit, D15 is the
MSB, and D4 is the LSB, followed by 4 trailing sub-bits.
26 ______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
LED Data Register (Read/Write)
LSB
(MAꢀ±ꢁ36)
LSB
(MAꢀ±ꢁ33)
MSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default values: B1E0h
The peak data register is a 16-bit read-only register.
Set the PEAK bit to 1 to enable the PEAK function. This
register stores the peak value of the ADC conversion
result. First, the current ADC result is saved to the
PEAK register, then the new ADC conversion result is
compared to this value. If the new value is larger than
the value in the peak register, the MAX1366/MAX1368
save the new value to the peak register. If the new
value is less than the value in the peak register, the
value in the peak register remains unchanged. Set the
PEAK bit to zero to clear the value in the PEAK register.
The data is represented in two’s-complement format.
For the MAX1366, the data is 16-bit and D15 is the
MSB. For the MAX1368, the data is 12-bit, D15 is the
MSB, and D4 is the LSB followed by 4 trailing sub-bits.
Register (Read/Write) section). The default power-on
state sets the MAX1366/MAX1368 to use the external
reference with the INTREF bit cleared to zero.
DAC Operation
For the MAX1366/MAX1368, a voltage proportional to
the ADC input is available at DACꢀOUT. Connect
DACꢀOUT to CONꢀ_IN for normal operation. (See
Figure 20 for DAC transfer function).
For internal-reference operation, set the INTREF bit to
one connect REF- to GND, and bypass REF+ to GND
,
with a 4.7µF capacitor. The internal reference provides
a nominal 2.048ꢀ source between REF+ and GND. The
internal-reference temperature coefficient is typically
40ppm/°C.
In normal operation, pull DACDATA_SEL low to use the
ADC output as the DAC input. Pull DACDATA_SEL high
to allow data to be written to the DAC register using the
SPI/QSPI/MICROWIRE interface. Once DACDATA_SEL
is pulled high, the three digital inputs (CS_DAC, DIN,
and SCLK) load the digital input data serially into the
DAC. (See Figure 11.)
For external-reference operation, set INTREF to GND.
REF+ and REF- are fully differential. For a valid external-
reference input, ꢀ
must be greater than ꢀ
.
REF-
REF+
Bypass REF+ and REF- with a 0.1µF or greater capaci-
tor to GND in external-reference mode.
To clock data into the DAC shift register, drive CS_DAC
low. SCLK synchronizes the data transfer. Immediately,
following CS_DAC high-to-low transition, the data shifts
synchronously into the serial shift register on the rising
edge of the serial clock input (SCLK). After 16 data bits
have been loaded into the serial input register, the data
latches to the DAC register on the rising edge of
CS_DAC. The DAC output updates on the next conver-
sion clock (2.5Hz). DIN is transferred MSB first.
Figure 14 shows the MAX1366/MAX1368 operating
with an external single-ended differential reference. In
this figure, REF- is connected to the top of the strain
gauge and REF+ is connected to the midpoint of the
resistor-divider of the supply.
Figure 15 shows the MAX1366/MAX1368 operating with
an external single-ended reference. In this figure, REF-
is connected to GND and REF+ is driven with an exter-
nal 2.048ꢀ reference. Bypass REF+ to GND with a
0.1µF capacitor.
Reference
ADC Reference
The MAX1366/MAX1368 reference sets the full-scale
range of the ADC transfer function. With a nominal
2.048ꢀ reference, the ADC full-scale range is 2ꢀ with
DAC Reference
The DAC of the MAX1366/MAX1368 accepts either an
external reference or an internal reference. For external-
reference operation, disable the DAC reference buffer by
RANGE = GND. With RANGE = Dꢀ
the full-scale
DD,
range is 200mꢀ. A decreased reference voltage
decreases full-scale range (see the Transfer Functions
section).
setting REFSELE to Dꢀ
to REF_DAC.
and connect a voltage source
DD
The MAX1366/MAX1368 accept either an external ref-
erence or an internal reference (INTREF). The INTREF
logic selects the reference mode (see the Control
For internal-reference operation, enable the DAC refer-
ence buffer by setting REFSELE to GND. In this mode,
leave REFDAC floating.
______________________________________________________________________________________ 21
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
In either internal or external reference operation,
bypass REF_DAC with a 0.1µF capacitor to GND.
Choose a reference with output impedance (load regu-
lation equivalent) of 100mΩ or less, such as the
MAX6126. For best performance, use an external
source from the ADC and DAC.
the analog input range to have an absolute value of
anywhere between -2.2ꢀ and +2.2ꢀ.
Thermocouple Measurement
Figure 15 shows a connection from a thermocouple to
the MAX1366/MAX1368. In this application, the
MAX1366/MAX1368 take advantage of the on-chip input
buffers that allow large source impedances on the front
end. The decoupling capacitors reduce noise pickup
from the thermocouple leads. To place the differential
voltage from the thermocouple at a suitable common-
mode voltage, the AIN- input of the MAX1366/MAX1368
is biased to GND. Use an external temperature sensor,
such as the DS75, and a microcontroller to perform cold-
junction temperature compensation.
Offset Calibration
The MAX1366/MAX1368 offer on-chip offset calibration.
The device offset calibrates during every conversion
when the OFFSET_CAL1 bit is zero in the control regis-
ter. Enhanced offset calibration is only needed in the
MAX1366 when the RANGE bit = 1. It is performed on
demand by setting the OFFSET_CAL2 bit to 1.
Enhanced Offset Calibration
Enhanced offset calibration is a more accurate calibra-
tion method that is needed in the case of the 200mꢀ
range and 4.5-digit resolution. The MAX1366 performs
enhanced calibration on demand by setting the
OFFSET_CAL2 bit to 1.
Transfer Functions
ADC Transfer Functions
Figures 16–19 show the transfer functions of the
MAX1366/MAX1368. The output data is stored in the
ADC data register in two’s complement.
The transfer function for the MAX1366 with AIN+ - AIN-
Power-Down Modes
The MAX1366/MAX1368 feature independent power-down
control of the analog and digital LED driver’s circuitry.
≥ 0 and RANGE = GND is:
ꢀ
− ꢀ
AIN−
AIN+
(1) COUNT = 1.024
x 20,000
Writing a 1 to the PD_DIG and PD_ANA bits in the con-
trol word, powers down the analog and digital circuitry,
reducing the supply current to 268µA (typ). PD_DIG
powers down the digital filter, while PD_ANA powers
down the analog modulator and ADC input buffers.
Writing a zero to the ENABLE bit in the control word
powers down the LED drivers.
ꢀ
− ꢀ
REF+
REF−
The transfer function for the MAX1366 with AIN+ - AIN-
< 0 and RANGE = GND is:
ꢀ
− ꢀ
AIN−
AIN+
(2) COUNT = 1.024
x 20,000 +1
ꢀ
− ꢀ
REF+
REF−
Peak
The MAX1366/MAX1368 feature peak-detection circuitry.
When activated (PEAK bit = 1), the devices display
only the highest voltage measured to the LED.
The transfer function for the MAX1368 with AIN+ - AIN-
≥ 0 and RANGE = GND is:
ꢀ
− ꢀ
AIN−
− ꢀ
AIN+
(3) COUNT = 1.024
x 2000
ꢀ
Hold
The MAX1366/MAX1368 feature data-hold circuitry.
When activated (HOLD bit = 1), the device holds the
current reading on the LED.
REF+ REF−
The transfer function for the MAX1368 with AIN+ - AIN-
< 0 and RANGE = GND is:
ꢀ
− ꢀ
AIN−
AIN+
Low Battery
The MAX1366/MAX1368 feature a low-battery detection
input. When the voltage at LOWBATT drops below
2.048ꢀ (typ), LOWBATT in the status register goes high.
(4) COUNT = 1.024
x 2000 +1
ꢀ
− ꢀ
REF+
REF−
The transfer function for the MAX1366 with AIN+ - AIN-
≥ 0 and RANGE = Dꢀ
is:
DD
Strain-Gauge Measurement
Connect the differential inputs of the MAX1366/
MAX1368 to the bridge network of the strain gauge. In
Figure 14, the analog supply voltage powers the bridge
network and the MAX1366/MAX1368, along with the
reference voltage. The MAX1366/MAX1368 handle an
analog input voltage range of 200mꢀ and 2ꢀ full
scale. The analog/reference inputs of the parts allow
ꢀ
− ꢀ
AIN−
AIN+
(5) COUNT = 1.024
x 20,000 x10
ꢀ
− ꢀ
REF+
REF−
ꢁ0 ______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
The transfer function for the MAX1366 with AIN+ - AIN-
Figure 23 shows the MAX1366/MAX1368 transfer func-
tion of the output current (4-20OUT) versus the input
voltage of the ꢀ/I converter.
< 0 and RANGE = Dꢀ
is:
DD
ꢀ
− ꢀ
AIN−
AIN+
(6) COUNT = 1.024
x 20,000 x 10+1
The transfer function for the MAX1366/MAX1368 with
the current offset enabled (EN_I is high) is:
ꢀ
− ꢀ
REF+
REF−
The transfer function for the MAX1368 with AIN+ - AIN-
16mA
1.25
IOUT ≅
x ꢀ
+4mA
CONꢀ_IN
≥ 0 and RANGE = Dꢀ
is:
DD
ꢀ
− ꢀ
AIN−
AIN+
(7) COUNT = 1.024
x 2000 x 10
The transfer function for the MAX1366/MAX1368 with
the current offset disabled (EN_I is low) is:
ꢀ
− ꢀ
REF+
REF−
The transfer function for the MAX1368 with AIN+ - AIN-
16mA
1.25
IOUT ≅
x ꢀ
CONꢀ_IN
< 0 and RANGE = Dꢀ
is:
DD
ꢀ
− ꢀ
AIN−
AIN+
(8) COUNT = 1.024
x 2000 x 10+1
Supplies, Layout, and Bypassing
ꢀ
− ꢀ
REF+
REF−
Power up Aꢀ
and Dꢀ before applying an analog
DD
DD
input and external-reference voltage to the device. If
this is not possible, limit the current into these inputs to
50mA. When the analog and digital supplies come from
the same source, isolate the digital supply from the
analog supply with a low-value resistor (10Ω) or ferrite
bead. For best performance, ground the MAX1366/
MAX1368 to the analog ground plane of the circuit
board. Avoid running digital lines under the device as
this can couple noise onto the IC. Run the analog
ground plane under the MAX1366/MAX1368 to mini-
mize coupling of digital noise. Make the power-supply
lines to the MAX1366/MAX1368 as wide as possible to
provide low-impedance paths and reduce the effects of
glitches on the power-supply line. Shield fast-switching
signals, such as clocks, with digital ground to avoid
radiating noise to other sections of the board. Avoid
running clock signals near the analog inputs. Avoid
crossover of digital and analog signals. Running traces
that are on opposite sides of the board at right angles to
each other reduces feedthrough effects. A microstrip
technique is best, but is not always possible with dou-
ble-sided boards. With this technique, the component
side of the board is dedicated to ground planes while
signals are placed on the solder side. Good decoupling
is important when using high-resolution ADCs.
Decouple the supplies with 0.1µF ceramic capacitors to
GND. Place these components as close to the device
as possible to achieve the best decoupling.
DAC Transfer Functions
Figure 20 shows the DAC transfer function for the
MAX1366/MAX1368 in unipolar and bipolar modes.
The transfer function for the DAC in the MAX1366/
MAX1368 unipolar mode is:
Note: The input at ꢀ
expects a source impe-
CONꢀ_IN
dence of typically 6kΩ when driving ꢀ
externally.
CONꢀ_IN
N
ꢀ
=
x ꢀ
REF
DACꢀOUT
32,768−1
where N = two’s complement ADC output code.
In unipolar mode, ꢀ
is equal to 0ꢀ for all two’s
DACꢀOUT
complement ADC codes less than zero (see Figure 21).
The transfer function for the DAC in the MAX1366/
MAX1368 in bipolar mode is:
N+19,999
ꢀ
=
x ꢀ
REF
DACꢀOUT
6536
where N = two’s complement ADC output.
Writing into the DAC Independently
A user can independently write to the DAC but cannot
input codes greater than +19,999 or less than -19,999.
In bipolar mode, a -19,999 DAC code provides 4mA
(0mA) output current and a +19,999 DAC code pro-
vides a 20mA (16mA) output current.
Selecting Segment Current
A resistor from ISET to ground sets the current for each
LED segment. See Table 7 for more detail. Use the fol-
lowing formula to set the segment current:
1.20ꢀ
Voltage-to-Current Transfer Function
Figures 20 and 21 show the MAX1366/MAX1368 trans-
fer function of the output current (4-20OUT) versus the
ADC output code.
I
=
x 400
SEG
R
ISET
______________________________________________________________________________________ ꢁ±
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
R
values below 25kΩ increase the I
. However,
Table 9 provides the FET characteristics for selecting
an external DMOS transistor. The DN25D FET transistor
from Supertex meets all the requirements of Table 7.
Other suitable transistors include ND2020L and
ND2410L from Siliconix.
ISET
SEG
the internal current-limit circuit limits the I
to less than
SEG
30mA. At higher I
device is not guaranteed. In addition, the power dissipat-
ed may exceed the package power-dissipation limit.
values, proper operation of the
SEG
Connect a 0.1µF capacitor between CMP and
REG_FORCE to ensure stable regulator compensation.
Choosing Supply Voltage to Minimize
Power Dissipation
The MAX1366/MAX1368 drive a peak current of 25.5mA
into LEDs with a 2.2ꢀ forward-voltage drop when operat-
ed from a supply voltage of at least 3.0ꢀ. Therefore, the
minimum voltage drop across the internal LED drivers is
0.8ꢀ (3.0ꢀ - 2.2ꢀ = 0.8ꢀ). The MAX1366/MAX1368 sink
when the outputs are operating and the LED segment
drivers are at full current (8 x 25.5mA = 204mA). For a
3.3ꢀ supply, the MAX1366/MAX1368 dissipate 224.4mW
((3.3ꢀ - 2.2ꢀ) x 204 = 224.4mW). If a higher supply volt-
age is used, the driver absorbs a higher voltage, and the
driver’s power dissipation increases accordingly.
However, if the LEDs used have a higher forward-voltage
drop than 2.2ꢀ, the supply voltage must be raised
accordingly to ensure that the driver always has at least
0.8ꢀ headroom. For an LEDꢀ supply voltage of 2.7ꢀ, the
maximum LED forward voltage is 1.9ꢀ to ensure 0.8ꢀ dri-
ver headroom. The voltage drop across the drivers with
a nominal +5ꢀ supply (5.0ꢀ - 2.2ꢀ = 2.8ꢀ) is almost
three times the drop across the drivers with a nominal
3.3ꢀ supply (3.3ꢀ - 2.2ꢀ = 1.1ꢀ). Therefore, the driver’s
power dissipation increases three times. The power dis-
sipation in the part causes the junction temperature to
rise accordingly. In the high ambient temperature case,
the total junction temperature may be very high (>
+125°C). At higher junction temperatures, the ADC per-
formance degrades. To ensure the dissipation limit for
the MAX1366/MAX1368 is not exceeded and the ADC
performance is not degraded; a diode can be inserted
between the power supply and LEDꢀ.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. This straight line is either a
best-straight-line fit or a line drawn between the end
points of the transfer function, once offset and gain
errors have been nullified. INL for the MAX1366/
MAX1368 is measured using the end-point method.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. A DNL error specification of
less than 1 LSB guarantees no missing codes and a
monotonic transfer function.
Rollover Error
Rollover error is defined as the absolute-value differ-
ence between a near positive full-scale reading and
near negative full-scale reading. Rollover error is tested
by applying a full-scale positive voltage, swapping
AIN+ and AIN-, and adding the results.
Zero-Input Reading
Ideally, with AIN+ connected to AIN-, the MAX1366/
MAX1368 LED displays zero. Zero-input reading is the
measured deviation from the ideal zero and the actual
measured point.
Gain Error
Gain error is the amount of deviation between the mea-
sured full-scale transition point and the ideal full-scale
transition point.
Selecting Depletion-Mode FET
An external depletion-mode FET (DMOS) works in con-
junction with the regulator circuit to supply the ꢀ/I con-
verter with loop power. REG_FORCE regulates the gate
of the DMOS so that the drain voltage is 5.2ꢀ (typ) and
allows the 4–20mA (0 to 16mA) loop to be directly pow-
ered from a 7ꢀ to 30ꢀ supply. DMOS I consists of the
DS
current output at 4-20OUT, a 4mA offset current, and
1mA (typ) consumed by the ꢀ/I converter.
Common-Mode Rejection (CMR)
CMR is the ability of a device to reject a signal that is
common to both input terminals. The common-mode
signal can be either an AC or a DC signal or a combi-
nation of the two. CMR is often expressed in decibels.
Normal-Mode 50Hz and 60Hz Rejection
(Simultaneously)
For offset-enabled mode (EN_I = 1):
Normal-mode rejection is a measure of how much output
changes when 50Hz and 60Hz signals are injected into
only one of the differential inputs. The MAX1366/
MAX1368 sigma-delta converter uses its internal digital
filter to provide normal-mode rejection to both 50Hz and
60Hz power-line frequencies simultaneously.
I
= I
+ 4mA + 1mA
4-20OUT
DS
For offset-disabled mode (EN_I = 0):
= I + 1mA
I
DS
4-20OUT
where I is the current in the DMOS.
DS
ꢁ2 ______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
Power-Supply Rejection (PSR)—ADC
PSR is a measure of the data converter’s level of immu-
nity to power-supply fluctuations. PSR assumes that the
converter’s linearity is unaffected by changes in the
power-supply voltage. Power-supply rejection ratio
(PSRR) is the ratio of the input signal change to the
change in the converter output. PSRR is typically mea-
sured in dB.
Power-Supply Rejection—V/I Converter
PSR is a measure of the data converter’s level of immu-
nity to power-supply fluctuations. PSR assumes that the
converter’s linearity is unaffected by changes in the
power-supply voltage. Note that the ꢀ/I converter cur-
rent output (4–20mA) power-supply rejection is with
respect to the 7ꢀ to 30ꢀ loop supply.
MAX1366 Typical Operating Circuit
DAC_VDD
SUPPLY VOLTAGE
IN
MAX6126
OUTF
0.1µF
OUTS
GNDS
GND
0.1µF
SEGA–SEGDP
SEGMENT
CONNECTIONS
DIG0–DIG4
DIGIT
CONNECTIONS
GND_DAC
REF_DAC
DACVOUT
AIN+
AIN-
V
EXT
7V TO 30V
V
IN
0.1µF
CONV_IN
EN_BPM
CMP
DEPLETION-
MODE
FET
REG_FORCE
EN_I
REG_VDD
REG_AMP
4.75V TO
5.25V
DACDATA_SEL
REFSELE
4-20OUT
DV
DD
4–20mA/0 TO 16mA
CURRENT-LOOP OUTPUT
MAX1366
4–20mA
PLC INPUT
CLK
R
L
ADC
SCLK
CS
DIN
LOWBATT
µC
LEDV
LED_EN
0.1µF
DOUT
EOC
DV
DD
10µF
0.1µF
DAC_VDD
AV
CS_DAC
DD
L
ISO
0.1µF
SET
NEGV
GND REF- REF+
LEDG GND_V/I
2.7V TO
5.25V
10µF
0.1µF
10µF
25kΩ
______________________________________________________________________________________ ꢁꢁ
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
MAX1368 Typical Operating Circuit
DAC_VDD
SUPPLY VOLTAGE
IN
MAX6126
OUTF
0.1µF
OUTS
GND
GNDS
0.1µF
SEGA–SEGDP
SEGMENT
CONNECTIONS
DIGO
DIG1–DIG4
DIGIT
CONNECTIONS
GND_DAC
REF_DAC
DACVOUT
AIN+
AIN-
V
EXT
V
IN
7V TO 30V
0.1µF
CONV_IN
EN_BPM
CMP
DEPLETION-
MODE
FET
REG_FORCE
EN_I
REG_VDD
REG_AMP
4.75V TO
5.25V
DACDATA_SEL
DV
DD
REFSELE
CLK
4-20OUT
4–20mA/0 TO 16mA
CURRENT-LOOP OUTPUT
MAX1368
4–20mA
PLC INPUT
SCLK
CS
R
ADC
L
µC
DIN
DOUT
EOC
LOWBATT
LEDV
LED_EN
0.1µF
CS_DAC
DV
DD
10µF
0.1µF
DAC_VDD
AV
DD
L
ISO
SET
NEGV
GND REF- REF+
LEDG GND_V/I
0.1µF
2.7V TO
5.25V
10µF
0.1µF
10µF
25kΩ
ꢁ4 ______________________________________________________________________________________
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
Pin Configuration
TOP VIEW
AIN+
AIN-
GND
1
2
36 SEGB
35 SEGA
34 DIG4
33 DIG3
32 DIG2
31 DIG1
30 DIG0
29 LEDG
3
AV
DD
DV
DD
4
5
SET
REG_VDD
REG_FORCE
REG_AMP
CMP
6
MAX1366
MAX1368
7
8
CS
9
28
27
26
25
DIN
10
11
12
DAC_VDD
DACVOUT
DOUT
SCLK
TQꢅP
Chip Information
TRANSISTOR COUNT: 83,463
PROCESS: CMOS
______________________________________________________________________________________ ꢁ5
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to ꢃꢃꢃ.maxim-ic.com/packages.)
PACKAGE OUTLINE, 32/48L LQFP, 7x7x1.4mm
1
21-0054
F
2
PACKAGE OUTLINE, 32/48L LQFP, 7x7x1.4mm
2
21-0054
F
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ ꢁ3
© 2006 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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