MAX1361_V01 [MAXIM]
4-Channel, 10-Bit, System Monitors with Programmable Trip Window and SMBus Alert Response;
| 型号： | MAX1361_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 4-Channel, 10-Bit, System Monitors with Programmable Trip Window and SMBus Alert Response |
| 文件： | 总24页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3268; Rev 5; 9/10
4-Channel, 10-Bit, System Monitors with Programmable
Trip Window and SMBus Alert Response
/MAX1362
General Description
Features
The MAX1361/MAX1362 low-power, 10-bit, 4-channel,
analog-to-digital converters (ADCs) feature a digitally
programmable window comparator with an interrupt out-
put for automatic system-monitoring applications. Once
configured, monitor mode automatically asserts an inter-
rupt when any analog input exceeds the programmed
upper or lower thresholds, without interaction to the
host. The MAX1361/MAX1362 respond to the SMBus™
alert, allowing quick identification of the alarming device
on a shared interrupt. A programmable delay between
monitoring intervals lowers power consumption at
reduced monitoring rates.
♦ Monitor Mode
Programmable Lower/Upper Trip Threshold
Alarm-Status Register Records Fault Events
SMBus Alert Response
Programmable Sampling Intervals
♦ 10-Bit I2C-Compatible ADC
1 LSB IꢀLꢁ 1 LSB DꢀL
♦ 4-Channel Single-Ended or 2-Channel Fully
Differential Inputs
♦ Software Programmable Bipolar/Unipolar
Conversions
In addition, the MAX1361/MAX1362 integrate an internal
voltage reference, a clock, and a 1.7MHz, high-speed,
I2C-compatible, 2-wire, serial interface. The optimized
interface allows a maximum conversion rate of 94.4ksps
in normal mode while reading back the conversion
results. Each of the four analog inputs is configurable for
single-ended or fully differential operation and unipolar
or bipolar operation. Two scan modes utilize on-chip
random access memory (RAM) to allow eight conver-
sions of a selected channel or scanning of a group of
channels to reduce interface overhead.
These devices operate from a single 2.7V to 3.6V
(MAX1361) or 4.5V to 5.5V (MAX1362) supply and
require only 436µA at the maximum sampling rate of
150ksps in monitor mode and 670µA at the maximum
sampling rate of 94.4ksps. AutoShutdown™ powers
down the devices between conversions, reducing sup-
ply current to less than 0.5µA when idle.
♦ Fast Sampling Rate
94.4ksps While Continuously Reading
Conversions
150ksps in Monitor Mode
♦ High-Speed I2C-Compatible Serial Interface
100kHz/400kHz Standard/Fast Mode
Up to 1.7MHz High-Speed Mode
4 Available I2C Slave Addresses
♦ Single Supply
2.7V to 3.6V (MAX1361)
4.5V to 5.5V (MAX1362)
♦ Internal Reference
2.048V (MAX1361)
4.096V (MAX1362)
♦ External Reference: 1V to V
♦ Low Power
DD
The full-scale analog-input range is determined by the
internal reference or by an externally applied reference
436µA in Monitor Mode (150ksps)
670µA at 94.4ksps
voltage ranging from 1V to V . The MAX1361 features
DD
6µA at 1ksps
a 2.048V internal reference, and the MAX1362 features
a 4.096V internal reference.
0.5µA in Power-Down Mode
♦ Small Package
The MAX1361/MAX1362 are available in a 10-pin
®
10-Pin µMAX
µMAX package and are specified over the extended
-40°C to +85°C temperature range. For 12-bit applica-
tions, refer to the pin-compatible MAX1363/MAX1364
data sheet.
SMBus is a trademark of Intel Corporation.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
Applications
System Monitoring/Supervision
Servers/Workstations
High Reliability Power Supplies
Medical Instrumentation
Typical Operating Circuit and Pin Configuration appear at
end of data sheet.
Ordering Information/Selector Guide
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
10 μMAX
I2C SLAVE ADDRESS
0110100/0110101
0110110/0110111
SUPPLY VOLTAGE (V)
2.7 to 3.6
MAX1361EUB+
MAX1361MEUB+
10 μMAX
2.7 to 3.6
+Denotes a lead(Pb)-free/RoHS-compliant package.
Ordering Information/Selector Guide continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricingꢁ deliveryꢁ and ordering informationꢁ please contact Maxim Direct at 1-888-629-4642ꢁ
or visit Maxim’s website at www.maxim-ic.com.
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
ABSOLUTE MAXIMUM RATIꢀGS
DD
AIN0–AIN3, A0, REF to GND......................-0.3V to (V
SDA, SCL, INT to GND.............................................-0.3V to +6V
V
to GND..............................................................-0.3V to +6V
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
+ 0.3V)
DD
Maximum Current Into Any Pin......................................... 50mA
Continuous Power Dissipation (T = +70°C)
A
10-Pin µMAX (derate 8.6mW/°C above +70°C)........689.7mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 2.7V to 3.6V (MAX1361), V
= 4.5V to 5.5V (MAX1362), V
= 2.048V (MAX1361), V
= 4.096V (MAX1362), C
=
DD
DD
REF
REF
REF
0.1µF, f
= 1.7MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
SCL
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (f
= 94.4ksps) (Note 1)
SAMPLE
/MAX1362
Resolution
10
Bits
LSB
LSB
LSB
Relative Accuracy
Differential Nonlinearity
Offset Error
INL
(Note 2)
1
1
1
DNL
No missing codes
Offset-Error Temperature
Coefficient
Relative to FSR
0.3
ppm/°C
Gain Error
(Note 3)
1
LSB
Gain Temperature Coefficient
Relative to FSR
0.3
0.1
ppm/°C
Channel-to-Channel Offset
Matching
LSB
LSB
Channel-to-Channel Gain
Matching
0.1
DYNAMIC PERFORMANCE (f
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Full-Power Bandwidth
= 10kHz, V
= V
, f = 94.4ksps)
REF SAMPLE
IN(SINE-WAVE)
IN(P-P)
SINAD
60
-70
70
dB
dB
THD
Up to the 5th harmonic
SFDR
dB
SINAD > 57dB
-3dB point
3.0
5.0
MHz
MHz
Full-Linear Bandwidth
CONVERSION RATE
Internal clock
6.8
Conversion Time (Note 4)
Throughput Rate (Note 5)
t
μs
CONV
External clock
10.6
Internal clock, SCAN[1:0] = 01
External clock
53
f
ksps
94.4
150
SAMPLE
Monitor mode, SCAN[1:0] = 10
2
_______________________________________________________________________________________
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
/MAX1362
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.7V to 3.6V (MAX1361), V
= 4.5V to 5.5V (MAX1362), V
= 2.048V (MAX1361), V
= 4.096V (MAX1362), C
=
DD
DD
REF
REF
REF
0.1µF, f
= 1.7MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
SCL
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ns
Track/Hold Acquisition Time
Internal Clock Frequency
800
2.8
60
30
MHz
External clock, fast mode
Aperture Delay (Note 6)
t
ns
AD
External clock, high-speed mode
ANALOG INPUT (AIN0–AIN3)
Unipolar
Bipolar
0
V
REF
Input Voltage Range, Single-
Ended and Differential (Note 7)
V
-V
/2
+V
/2
REF
REF
1
Input Multiplexer Leakage
Current
ON/OFF leakage current, V
= 0V or V
0.01
22
μA
pF
AIN_
DD
Input Capacitance
C
IN
INTERNAL REFERENCE (Note 8)
MAX1361
MAX1362
2.027
4.055
2.048
4.096
2.068
4.137
Reference Voltage
V
REF
T
A
= +25°C
V
Reference-Voltage Temperature
Coefficient
TCV
25
ppm/°C
REF
REF Short-Circuit Current
REF Source Impedance
EXTERNAL REFERENCE
REF Input Voltage Range
REF Input Current
2
mA
1.5
kꢀ
V
(Note 9)
1
V
V
REF
DD
I
f
= 94.4ksps
SAMPLE
40
μA
REF
DIGITAL INPUTS/OUTPUTS (SCL, SDA, A )
0
x
x
Input High Voltage
Input Low Voltage
V
0.7
0.1
V
V
V
V
IH
DD
x
V
DD
V
0.3
IL
SCL, SDA
Ao
DD
Input Hysteresis
V
V
HYST
x
0.1
V
DD
Input Current
I
±10
μA
pF
V
IN
Input Capacitance
Output Low Voltage
INT OUTPUT
C
15
IN
V
I
I
= 3mA
= 3mA
0.4
OL
SINK
SINK
Output Low Voltage
INT Leakage Current
Output Capacitance
POWER REQUIREMENTS
0.4
V
No faults detected
10
μA
pF
15
MAX1361
MAX1362
2.7
4.5
3.6
5.5
Supply Voltage
V
DD
V
_______________________________________________________________________________________
3
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.7V to 3.6V (MAX1361), V
= 4.5V to 5.5V (MAX1362), V
= 2.048V (MAX1361), V
= 4.096V (MAX1362), C
=
DD
DD
REF
REF
REF
0.1µF, f
= 1.7MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
SCL
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Internal
reference
f
=
SAMPLE
660
1600
150ksps,
monitor mode
(Note 10)
External
reference
436
900
670
530
230
380
60
1350
1150
900
Internal
reference
f
=
SAMPLE
94.4ksps, external
clock
External
reference
Internal
reference
f
=
SAMPLE
MAX1361 40ksps, internal
clock
External
reference
/MAX1362
Internal
reference
f
=
SAMPLE
10ksps,
internal clock
External
reference
Internal
reference
330
6
f
= 1ksps,
SAMPLE
internal clock
External
reference
Supply Current
I
μA
DD
Internal
reference
f
=
SAMPLE
666
436
900
670
530
230
380
60
1600
1350
1150
900
150ksps,
monitor mode
(Note10)
External
reference
Internal
reference
f
=
SAMPLE
94.4ksps, external
clock
External
reference
Internal
reference
f
=
SAMPLE
MAX1362 40ksps,
internal clock
External
reference
Internal
reference
f
=
SAMPLE
10ksps, internal
clock
External
reference
Internal
reference
330
6
f
= 1ksps,
SAMPLE
internal clock
External
reference
Internal reference on
330
0.5
Shutdown Current
μA
Internal reference off
10
Power-Supply Rejection Ratio
PSRR
Full-scale input (Note 11)
±0.01
±0.5
LSB/V
4
_______________________________________________________________________________________
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
/MAX1362
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.7V to 3.6V (MAX1361), V
= 4.5V to 5.5V (MAX1362), V
= 2.048V (MAX1361), V
= 4.096V (MAX1362), C
=
DD
DD
REF
REF
REF
0.1µF, f
= 1.7MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
SCL
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS FOR FAST MODE (Figures 1a, 2)
Serial Clock Frequency
f
400
kHz
μs
SCL
Bus Free Time Between a
STOP (P) and a
START (S) Condition
t
1.3
0.6
BUF
Hold Time for START (S)
Condition
t
t
μs
HD, STA
Low Period of the SCL Clock
High Period of the SCL Clock
t
1.3
0.6
μs
μs
LOW
t
HIGH
Setup Time for a Repeated
START Condition (Sr)
0.6
μs
SU, STA
Data Hold Time
Data Setup Time
t
t
0
900
ns
ns
HD, DAT
SU, DAT
100
Rise Time of Both SDA and SCL
Signals, Receiving
t
Measured from 0.3V to 0.7V
0
300
300
ns
ns
μs
R
DD
DD
DD
Fall Time of SDA Transmitting
t
Measured from 0.3V to 0.7V
DD
F
0
Setup Time for STOP (P)
Condition
t
0.6
SU, STO
Capacitive Load for Each Bus
Line
C
400
50
pF
ns
B
Pulse Width of Spike Suppressed
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C = 400pF, Figures 1a, 2) (Note 12)
B
Serial-Clock Frequency
f
(Note 13)
1.7
MHz
ns
SCLH
Hold Time, Repeated START
Condition (Sr)
t
160
HD, STA
Low Period of the SCL Clock
High Period of the SCL Clock
t
(Note 13)
320
120
ns
ns
LOW
t
HIGH
Setup Time for a Repeated
START Condition (Sr)
t
160
ns
SU, STA
Data Hold Time
t
t
(Note 14)
0
150
ns
ns
ns
HD, DAT
SU, DAT
Data Setup Time
10
20
Rise Time of SCL Signal
t
Measured from 0.3V to 0.7V
80
RCL
DD
DD
DD
Rise Time of SCL Signal After
Acknowledge Bit
t
Measured from 0.3V to 0.7V
20
160
ns
RCL1
DD
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
t
Measured from 0.3V to 0.7V
20
20
20
80
ns
ns
ns
FCL
DD
DD
DD
DD
t
Measured from 0.3V to 0.7V
160
160
RDA
DD
t
Measured from 0.3V to 0.7V
DD
FDA
Setup Time for STOP (P)
Condition
t
160
ns
SU, STO
Capacitive Load for Each Bus
C
400
10
pF
ns
B
Pulse Width of Spike Suppressed
0
_______________________________________________________________________________________
5
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.7V to 3.6V (MAX1361), V
= 4.5V to 5.5V (MAX1362), V
= 2.048V (MAX1361), V
= 4.096V (MAX1362), C
=
DD
DD
REF
REF
REF
0.1µF, f
= 1.7MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
SCL
A
MIN
ꢀote 1: Devices configured for unipolar single-ended inputs.
ꢀote 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain and offset have
been calibrated.
ꢀote 3: Offset nulled.
ꢀote 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period.
Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode.
ꢀote 5: The throughput rate of the I2C bus is limited to 94.4ksps. The MAX1361/MAX1362 can perform conversions up to 150ksps
in monitor mode when not reading back results on the I2C bus.
ꢀote 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
ꢀote 7: The absolute input voltage range for the analog inputs (AIN0–AIN3) is from GND to V
.
DD
ꢀote 8: When the internal reference is configured to be available at AIN3/REF (SEL[2:1] = 11), decouple AIN3/REF to GND with a
0.01µF capacitor.
ꢀote 9: ADC performance is limited by the converter’s noise floor, typically 300µV
.
P-P
ꢀote 10: Maximum conversion throughput in internal clock mode when the data is not clocked out.
ꢀote 11: For the MAX1361, PSRR is measured as
/MAX1362
N
⎡
⎤
⎥
2
−1
⎢ V (3.6V) − V (2.7V) ×
⎡
⎤
FS
FS
⎣
⎦
V
REF
⎢
⎥
⎦
⎣
(3.6V − 2.7V)
and for the MAX1362, PSRR is measured as
N
⎡
⎤
⎥
2
V
−1
REF
⎢ V (5.5V) − V (4.5V) ×
⎡
⎤
FS
FS
⎣
⎦
⎢
⎥
⎦
⎣
(5.5V − 4.5V)
ꢀote 12: C = total capacitance of one bus line in pF.
B
ꢀote 13: f
must meet the minimum clock low time plus the rise/fall times.
SCLH
ꢀote 14: A master device must provide a data hold time for SDA (referred to V of SCL) to bridge the undefined region of SCL’s
IL
falling edge.
Typical Operating Characteristics
(V
= 3.3V (MAX1361), V
= 5V (MAX1362), f
= 1.7MHz, external clock, f = 94.4ksps, single-ended, unipolar,
SAMPLE
DD
DD
SCL
T
A
= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
DIFFERENTIAL NONLINEARITY
FFT PLOT
vs. DIGITAL CODE
0.5
0.4
0
0.3
f
f
= 94.4ksps
SAMPLE
= 10kHz
-20
IN
0.2
0.1
0
0.3
-40
-60
0.2
0.1
0
-80
-0.1
-0.2
-0.3
-0.4
-0.5
-100
-120
-140
-160
-0.1
-0.2
-0.3
0
10
20
30
40
50
0
200
400
600
800
1000
0
200
400
600
800
1000
FREQUENCY (kHz)
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
6
_______________________________________________________________________________________
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
/MAX1362
Typical Operating Characteristics (continued)
(V
= 3.3V (MAX1361), V
= 5V (MAX1362), f
= 1.7MHz, external clock, f = 94.4ksps, single-ended, unipolar,
SAMPLE
DD
DD
SCL
T
A
= +25°C, unless otherwise noted.)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
SUPPLY CURRENT vs. TEMPERATURE
vs. TEMPERATURE
800
0.50
0.6
0.5
0.4
0.3
0.2
0.1
0
SDA = SCL = V
DD
750
0.45
MAX1362
SETUP BYTE
EXT REF: 10111010
INT REF: 11011010
INTERNAL REFERENCE
MAX1362
0.40
700
650
600
550
500
450
400
350
300
0.35
0.30
0.25
MAX1361
INTERNAL REFERENCE
EXTERNAL REFERENCE
0.20
MAX1362
MAX1361
0.15
0.10
0.05
0
EXTERNAL REFERENCE
MAX1361
2.7
3.2
3.7
4.2
4.7
5.2
-40 -25 -10
5
20 35 50 65 80
-40 -25 -10
5
20 35 50 65 80
INPUT VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
NORMALIZED REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE (EXTERNAL CLOCK)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
1.0010
1.0008
1.0006
1.0004
1.0002
1.0000
0.9998
0.9996
0.9994
0.9992
0.9990
1.00010
800
750
700
650
600
550
500
450
400
350
300
250
200
NORMALIZED TO REFERENCE VALUE
AT +25°C
A) INTERNAL REFERENCE ALWAYS ON
B) EXTERNAL REFERENCE
MAX1362
NORMALIZED TO
REFERENCE VALUE AT
1.00008
1.00006
1.00004
1.00002
1.00000
0.99998
0.99996
0.99994
0.99992
0.99990
A
MAX1362
V
DD
= 5V
B
MAX1361
NORMALIZED TO
REFERENCE VALUE AT
= 3.3V
MAX1361
V
DD
0
10 20 30 40 50 60 70 80 90 100
CONVERSION RATE (ksps)
-40 -25 -10
5
20 35 50 65 80
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
(V)
TEMPERATURE (°C)
V
DD
OFFSET ERROR vs. TEMPERATURE
OFFSET ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-40 -25 -10
5
20 35 50 65 80
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
-40 -25 -10
5
20 35 50 65 80
TEMPERATURE (°C)
V
(V)
TEMPERATURE (°C)
DD
_______________________________________________________________________________________
7
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
Typical Operating Characteristics (continued)
(V
= 3.3V (MAX1361), V
= 5V (MAX1362), f
= 1.7MHz, external clock, f
= 94.4ksps, single-ended, unipolar,
SAMPLE
DD
DD
SCL
T
A
= +25°C, unless otherwise noted.)
MONITOR-MODE SUPPLY CURRENT
vs. SPEED
GAIN ERROR vs. SUPPLY VOLTAGE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
700
600
500
400
300
200
100
0
INTERNAL REF
EXTERNAL REF
2.7
3.2
3.7
4.2
(V)
4.7
5.2
0
25
50
75
100
125
150
V
SPEED (ksps)
DD
/MAX1362
Pin Description
PIꢀ
1
ꢀAME
AIN0
AIN1
AIN2
FUꢀCTIOꢀ
Analog Input
Analog Input
Analog Input
2
3
4
AIN3/V
A0
Analog Input or Reference Input or Output. See Table 3.
REF
5
I2C Address Select Input. Connect to V or GND. See Table 1.
DD
6
INT
Active-Low, Open-Drain Interrupt Output
I2C Clock Input
I2C Data Input/Output
7
SCL
SDA
GND
8
9
Ground
10
V
Positive Supply Voltage. Bypass V to GND with a 0.1µF capacitor.
DD
DD
Functional Diagram
V
DD
SDA
SCL
A0
I2C
INTERFACE
CLK
AIN0
AIN1
10-BIT
ADC
4:1
MUX
CONTROL
INT
AIN2
TRIP
THRESHOLDS
INT
REF
AIN3/
REF
MAX1361/MAX1362
GND
8
_______________________________________________________________________________________
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
/MAX1362
t
R
t
F
SDA
t
t
HD.DAT
SU.DAT
t
t
BUF
HD.STA
t
LOW
t
t
SU.STO
SU.STA
9
SCL
t
SU.STA
t
HIGH
t
R
t
F
S
Sr
ACK
P
S
Figure 1a. F/S-Mode 2-Wire Serial-Interface Timing
t
t
RDA
FDA
SDA
t
t
HD.DAT
SU.DAT
t
HD.STA
t
LOW
t
SU.STO
t
SU.STA
1
9
SCL
t
t
HD.STA
HIGH
t
t
FCL
t
RCL1
RCL
ACK
Sr
Sr
S
P
HS-MODE
F/S-MODE
Figure 1b. HS-Mode 2-Wire Serial-Interface Timing
Detailed Description
V
DD
The MAX1361/MAX1362 4-channel ADCs use succes-
sive-approximation conversion techniques and fully dif-
ferential input track/hold (T/H) circuitry to capture and
convert analog signals to a serial 10-bit digital output.
The MAX1361/MAX1362 feature a monitor mode with
programmable trip thresholds and window comparator.
The monitor function asserts an interrupt when any
channel violates the programmed upper or lower
thresholds. SMBus alert response allows the host
microcontroller (µC) to quickly identify which device
caused the interrupt. A programmable delay between
monitoring intervals lowers power consumption at lower
monitor rates.
I
OL
V
SDA
OUT
400pF
I
OH
Figure 2. Load Circuits
The MAX1361/MAX1362 integrate an internal voltage
reference and clock. The software configures the ana-
log inputs for unipolar/bipolar and single-ended/fully
differential operation. Integrated first-in/first-out (FIFO)
allows conversion of all channels, or eight conversions
on a selected channel to reduce interface overhead. An
I2C-compatible serial interface complies with standard,
fast, and high-speed (1.7MHz) modes.
_______________________________________________________________________________________
9
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
10 conversion clock cycles and is equivalent to trans-
ferring a charge of 11pF x (V + - V -) from C to the
binary-weighted capacitive DAC, forming a digital rep-
resentation of the analog-input signal.
Power Supply
The MAX1361 (2.7V to 3.6V) and MAX1362 (4.5V to
5.5V) operate from a single supply and consume 670µA
(typ) at sampling rates up to 94.4ksps and 436µA in
monitor mode at 150ksps. The MAX1361 features a
2.048V internal reference and the MAX1362 features a
4.096V internal reference. All devices can be config-
IN
IN
T/H
Use a low source impedance to ensure an accurate
sample. A source impedance of up to 1.5kΩ does not
significantly degrade sampling accuracy. For larger
source impedances, connect a 100pF capacitor from
the analog input to GND or buffer the input.
ured for use with an external reference from 1V to V
.
DD
Bypass V
to GND using a 0.1µF or greater ceramic
DD
capacitor for best performance.
In internal clock mode, the T/H circuitry enters track
mode on the eighth rising clock edge of the address
byte (see the Slave Address section). The T/H circuitry
enters hold mode on the falling clock edge of the
acknowledge bit of the address byte (the ninth clock
pulse). The conversions are then internally clocked, dur-
ing which time the MAX1361/MAX1362 hold SCL low.
Analog Input and Track/Hold
The MAX1361/MAX1362 analog-input architecture con-
tains an analog-input multiplexer (MUX), fully differential
T/H, comparator, and a fully differential switched
capacitive digital-to-analog converter (DAC). Figure 3
shows the equivalent input circuit for the MAX1361/
MAX1362.
In external clock mode, the T/H circuitry enters track
mode after a valid address on the rising edge of the
clock during the read bit (R/W = 1, bit 8). Hold mode is
entered on the rising edge of the second clock pulse
during the shifting out of the 1st byte of the result. The
next 10 clock cycles perform the conversions (see
Figure 13).
In single-ended mode, the analog-input MUX connects
/MAX1362
C
between the analog input selected by CS[3:0] and
T/H
GND (see the Configuration/Setup Bytes (Write Cycle)
section). In differential mode, the analog-input MUX
connects C
selected by CS[3:0].
to the plus and minus analog inputs
T/H
The time required for the T/H circuitry to acquire an
input signal is a function of the input sample capaci-
tance. If the analog-input source impedance is high,
the acquisition-time constant lengthens and more time
must be allowed between conversions. The acquisition
During the acquisition interval, the T/H switches are in
the track position, and C
charges to the analog-input
T/H
signal. At the end of the acquisition interval, the T/H
switches move to the hold position, retaining the charge
on C
as a stable sample of the input signal.
T/H
time (t
) is the minimum time needed for the signal
ACQ
During the conversion, a switched capacitive DAC
adjusts to restore the comparator input voltage to 0V
within the limits of 10-bit resolution. This action requires
to be acquired. It is calculated by:
t
≥ 7 x (R + R ) x C
SOURCE IN IN
ACQ
HOLD
ANALOG INPUT MUX
REF
C
T/H
AIN0
TRACK
CAPACITIVE
DAC
AIN1
AIN2
V
/2
DD
AIN3/REF
CAPACITIVE
DAC
TRACK
C
T/H
MAX1361
MAX1362
REF
HOLD
Figure 3. Equivalent Input Circuit
10 ______________________________________________________________________________________
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
/MAX1362
where R
is the analog-input source impedance,
Internal Reference
The internal reference is 2.048V for the MAX1361 and
4.096V for the MAX1362. SEL0 of the setup byte con-
trols whether AIN3/REF is used for an analog input or a
reference (SEL0 = 0 selects AIN3/REF as AIN3, and
SEL0 = 1 selects AIN3/REF as REF). Decouple
AIN3/REF to GND with a 0.1µF capacitor and a 2kΩ
resistor in series when AIN3/REF is configured as an
internal reference output (SEL[1:0] = 11). See the
Typical Operating Circuit. Once powered up, the refer-
ence remains on until reconfigured. Do not use the ref-
erence to supply current for external circuitry.
SOURCE
R
= 2.5kΩ, and C = 22pF. For internal clock mode,
IN
ACQ
IN
t
= 1.5/f
.
, and for external clock mode t
=
ACQ
SCL
2/f
SCL
Analog-Input Bandwidth
The MAX1361/MAX1362 feature input-tracking circuitry
with a 5MHz small-signal bandwidth. The 5MHz input
bandwidth makes it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals from aliasing into the frequency band of
interest, use anti-aliasing filtering.
External Reference
The external reference ranges from 1V to V . For max-
DD
imum conversion accuracy, the reference must deliver
40µA and have an impedance of 500Ω or less. For
noisy or high-output-impedance references, insert a
0.1µF bypass capacitor to GND as close to AIN3/REF
as possible.
Analog-Input Range and Protection
Internal protection diodes clamp the analog inputs to V
DD
and GND. These diodes allow the analog inputs to swing
from (V - 0.3V) to (V + 0.3V) without causing dam-
GND
DD
age to the device. For accurate conversions the inputs
must remain within 50mV below GND or above V
.
DD
Clock Modes
The clock mode determines the conversion clock and
the data acquisition and conversion time. The clock
mode also affects the scan mode. The state of the
setup byte’s INT/EXT clock bit determines the clock
mode. At power-up, the MAX1361/MAX1362 default to
internal clock mode (INT/EXT clock = 0).
Single-Ended/Differential Input
The SE/DIF of the configuration byte configures the
MAX1361/MAX1362 analog-input circuitry for single-
ended or differential input. In single-ended mode (SE/DIF
= 1), the digital conversion results are the difference
between the analog input selected by CS[3:0] and GND.
In differential mode (SE/DIF = 0), the digital conversion
results are the difference between the plus and the minus
analog inputs selected by CS[3:0] (see Tables 5 and 6).
Internal Clock
See the Configuration/Setup Bytes (Write Cycle) section.
In internal clock mode (INT/EXT clock = 0), the MAX1361/
MAX1362 use an internal oscillator for the conversion
clock. The MAX1361/MAX1362 begin tracking the analog
input after a valid address on the eighth rising edge of the
clock. On the falling edge of the ninth clock, the analog
signal is acquired and the conversion begins. While con-
verting, the MAX1361/MAX1362 hold SCL low (clock
stretching). After completing the conversion, the results
are stored in internal memory. For scan-mode configura-
tions with multiple conversions (see the Scan Modes sec-
tion), all conversions happen in succession with each
additional result stored in memory. Once all conversions
are complete, the MAX1361/MAX1362 release SCL,
allowing it to go high. The master can now clock the
results out in the same order as the scan conversion.
Unipolar/Bipolar
Unipolar mode sets the differential input range from 0 to
V
. A negative differential analog input in unipolar
REF
mode causes the digital output code to be zero.
Selecting bipolar mode sets the differential input range
to
V
/2. The digital output code is binary in unipolar
REF
mode and two’s complement in bipolar mode. (See the
Transfer Functions section.)
In single-ended mode the MAX1361/MAX1362 always
operate in unipolar mode. The analog inputs are inter-
nally referenced to GND with a full-scale input range
from 0 to V
(Table 7).
REF
Reference
SEL[1:0] of the setup byte controls the reference and
the AIN3/REF configuration. When AIN3/REF is config-
ured as a reference input or reference output (SEL0 =
1), differential conversions on AIN3/REF appear as if
AIN3/REF is connected to GND. A single-ended conver-
sion in scan mode on AIN3/REF is ignored by an internal
limiter that sets the highest available channel at AIN2
(Table 2).
The converted results are read back in a FIFO
sequence. If AIN3/REF is configured as a reference
input or output, AIN3/REF is excluded from multichan-
nel scan. If reading continues past the final result
stored in memory, the pointer wraps around and points
to the first result. Only the current conversion results
are read from memory. The MAX1361/MAX1362 must
______________________________________________________________________________________ 11
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
be addressed with a read command to obtain new con-
version results.
high voltage spikes on the bus lines and minimize
crosstalk and undershoot of the bus signals.
One bit transfers during each SCL clock cycle. A mini-
mum of nine clock cycles is required to transfer a byte
in or out of the MAX1361/MAX1362 (8 bits and an
ACK/NACK). The data on SDA must remain stable dur-
ing the high period of the SCL clock pulse. Changes in
SDA while SCL is high and stable are considered con-
trol signals (see the START and STOP Conditions sec-
tion). Both SDA and SCL remain high when the bus is
not busy.
External Clock
See the Configuration/Setup Bytes (Write Cycle) section.
When configured for external clock mode (INT/EXT = 1),
the MAX1361/MAX1362 use SCL as the conversion clock.
In external clock mode, the MAX1361/MAX1362 begin
tracking the analog input on the eighth rising clock edge
of a valid slave address byte. Two SCL clock cycles later,
the analog signal is acquired and the conversion begins.
Unlike internal clock mode, converted data is clocked out
immediately in the format described in the Reading a
Conversion (Read Cycle) section.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high (Figure 4). A repeated START
condition (Sr) can be used in place of a STOP condition
to leave the bus active and the mode unchanged (see
the HS I2C Mode section).
The device continuously converts input channels dictat-
ed by the scan mode until given a not acknowledge
(NACK). There is no need to readdress the device with
a read command to obtain new conversion results.
/MAX1362
The conversion must complete in 1ms or droop on the
T/H capacitor degrades conversion results. Use internal
clock mode if the SCL clock period exceeds 60µs.
Use external clock mode for conversion rates from
40ksps to 94.4ksps. Use internal clock mode for con-
versions under 40ksps. Internal clock mode consumes
less power. Monitor mode always uses internal clock
mode regardless of conversion rate.
Acknowledge and ꢀot-Acknowledge Conditions
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the mas-
ter and the MAX1361/MAX1362 (slave) generate
acknowledge bits. To generate an acknowledge, the
receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the
clock pulse (Figure 5).
Applications Section
Power-On Reset
The configuration and setup registers default to a sin-
gle-ended, unipolar, single-channel conversion on AIN0
using the internal clock with V
as the reference and
DD
AIN3/REF configured as an analog input. The memory
contents are unknown at power-up (see the Software
Description section).
S
Sr
P
SDA
SCL
2
I C-Compatible 2-Wire Serial Interface
The MAX1361/MAX1362 use an I2C-compatible 2-wire
interface consisting of a serial-data line (SDA) and seri-
al-clock line (SCL). SDA and SCL facilitate bidirectional
communication between the MAX1361/MAX1362 and
the master at rates up to 1.7MHz. The master (typically
a microcontroller) initiates data transfer on the bus and
generates the SCL signal to permit data transfer. The
MAX1361/MAX1362 behave as I2C slave devices that
transfer and receive data.
Figure 4. START and STOP Conditions
S
NOT ACKNOWLEDGE
SDA
SDA and SCL must be pulled high for proper I2C opera-
tion. This is typically done with pullup resistors (750Ω or
greater). Series resistors (R ) are optional (see the
S
ACKNOWLEDGE
8 9
1
2
SCL
Typical Operating Circuit section). The resistors protect
the input architecture of the MAX1361/MAX1362 from
Figure 5. Acknowledge Bits
12 ______________________________________________________________________________________
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
/MAX1362
SLAVE ADDRESS
S
0
1
1
0
1
0
0
R/W
ACK
SDA
SCL
1
2
3
4
5
6
7
8
9
Figure 6. MAX1361/MAX1362 Slave Address Byte
2
The MAX1361/MAX1362 continuously wait for a START
condition followed by its slave address. When the device
recognizes its slave address, it is ready to accept or
send data depending on the R/W bit (Figure 6).
Table 1. I C Slave Selection Table
A0 STATE
Low
SUFFIX
EUB
ADDRESS
0110100
0110101
0110110
0110111
High
EUB
HS I2C Mode
At power-up, the MAX1361/MAX1362 bus timing is set
for fast mode (F/S mode, up to 400kHz I2C clock), which
limits the conversion rate to approximately 22ksps.
Switch to high-speed mode (HS mode, up to 1.7MHz
I2C clock) to achieve conversion rates up to 94.4ksps.
The MAX1361/MAX1362 convert up to 150ksps in moni-
tor mode, regardless of I2C mode. If conversion results
are unread, I2C bandwidth limitations do not apply in
monitor mode.
Low
MEUB
MEUB
High
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master reattempts com-
munication at a later time.
Select HS mode by addressing all devices on the bus
with the HS-mode master code 0000 1XXX (X = don’t
care). After successfully receiving the HS-mode master
code, the MAX1361/MAX1362 issue a NACK, allowing
SDA to be pulled high for one clock cycle (Figure 7).
Slave Address
The MAX1361/MAX1362 have a 7-bit I2C slave
address. The slave address is selected using A0. The
MAX1361/MAX1362 (EUB and MEUB) have 2 base
address options, allowing up to 4 devices concurrently
per I2C bus (see Table 1).
After the NACK, the MAX1361/MAX1362 operate in HS
mode. Send a repeated START (Sr) followed by a slave
address to initiate HS-mode communication. If the mas-
ter generates a STOP condition the MAX1361/MAX1362
return to F/S mode. Use a repeated START condition
(Sr) in place of a STOP condition to leave the bus active
and the mode unchanged.
HS-MODE MASTER CODE
S
0
0
0
0
1
X
X
X
NACK
Sr
SDA
SCL
F/S MODE
HS MODE
Figure 7. F/S-Mode to HS-Mode Transfer
______________________________________________________________________________________ 13
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
START
CONDITION
R/W BIT FROM
THE MASTER
ADDRESS
FROM THE MASTER
CONFIGURATION
BYTE FROM THE MASTER
SETUP
BYTE FROM THE MASTER
START
0
A
A
A
STOP
Figure 8. Example of Writing Setup and Control Bytes
START
CONDITION
R/W BIT FROM
THE MASTER
MONITOR
SETUP BIT
ADDRESS
FROM THE MASTER
SETUP BYTE
1
ALARM RESET, SCAN
SPEED, INT_EN
START
0
A
A
A
A
FROM THE MASTER
CH 0 LT [11:4]
A
CH 0 LT [3:0]; UT [11:8]
A
CH 0 UT [7:0]
A
CH 1 LT [11:4]
STOP
Figure 9. Example of Extended Setup-Byte Writing
/MAX1362
Table 2. Configuration Byte Format*
BIT
ꢀAME
DESCRIPTIOꢀ
7(MSB) CONFIG The configuration byte always starts with 0.
SCAN1, SCAN0 = [0,0], scans from channel 0 to the upper channel chosen by CS1, CS0.
SCAN1, SCAN0 = [0,1], converts a single channel chosen by CS1, CS0 eight times.
SCAN1, SCAN0 = [1,0] monitor mode monitors from channel 0 to the upper channel chosen by CS1, CS0.
SCAN1, SCAN0 = [1,1], single channel conversion for the channel is chosen by CS0, CS1.
6
5
SCAN1
SCAN0
4
3
2
CS3
CS2
CS1
CS3, CS2 = [1,1] enables readback of monitor-mode setup data.
Selects the upper limit of the channel range used for the conversion sequence in scan modes SCAN = [0,0]
and monitor modes SCAN = [1,0].
Selects the conversion channel when SCAN = [0,1] or when SCAN = [1,1].
(Tables 5 and 6)
1
CS0
1 = single-ended inputs.
0 = differential inputs.
AIN0 and AIN1 form the first differential pair and AIN2 and AIN3 form the second differential pair. (See Tables
4 and 5.)
0
SE/DIF
Selects single-ended or differential conversions. In single-ended mode, input signal voltages are referenced
to GND. In differential mode, the voltage difference between two channels is measured.
When single-ended mode is used, the MAX1361/MAX1362 perform unipolar conversions regardless of the
UNI/BIP bit in the setup byte.
(Table 7)
*Power-on defaults: 0x01
14 ______________________________________________________________________________________
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
/MAX1362
When idle, the MAX1361/MAX1362 continuously wait
for a START condition followed by their slave address.
Software Description
Configuration/Setup Bytes (Write Cycle)
A write cycle begins with the bus master issuing a
START condition followed by 7 address bits and a write
bit (R/W = 0). If the address byte is successfully
received, the MAX1361/MAX1362 (slave) issue an ACK.
The master then writes to the slave. If the most signifi-
cant bit (MSB) is 1, the slave recognizes the received
byte as the setup byte (Table 4). If the MSB is 0, the
slave recognizes that byte as the configuration byte
(Table 2). Write to the configuration byte before writing
to the setup byte (Figure 8). If enabling RESET in the
setup byte, rewrite the configuration byte after writing
the setup byte, since RESET clears the contents of the
configuration byte back to the power-up state.
Upon reading a valid address byte, the MAX1361/
MAX1362 power up. The internal reference requires
10ms to wake up. Therefore, power up the internal ref-
erence 10ms prior to conversion or leave the reference
continuously powered. Wake-up is transparent when
using an external reference or V
as the reference.
DD
Automatic shutdown results in dramatic power savings,
particularly at slow conversion rates with internal clock.
For example, using an external reference at a conver-
sion rate of 10ksps, the average supply current for the
MAX1361 is 60µA (typ) and drops to 6µA (typ) at
1ksps. At 0.1ksps, the average supply current is just
1µA. Table 3 shows AIN3/REF configuration and refer-
ence power-down state.
When the monitor-setup bit of the setup byte is set to 1,
writing extends up to 13 bytes to clock in monitor-setup
data. Terminate writing monitor-setup data at any time
by issuing a STOP or repeated START condition. If the
slave receives a byte successfully, it issues an ACK
(Figure 9).
ꢀote: When operating in HS mode, a STOP condition
returns the bus into F/S mode (see the HS I2C Mode
section).
Scan Modes
SCAN1 and SCAN0 of the configuration byte set the
scan-mode configuration. When configuring AIN3/REF
for reference input or output (SEL0 = 1), AIN3/REF is
excluded from a multichannel scan. The scanned
results write to memory in the same order as the con-
version. Start a conversion sequence by initiating a
read with the desired scan mode. Read the results from
memory in the order they were converted (see the
Reading a Conversion (Read Cycle) section).
Automatic Shutdown
AutoShutdown occurs between conversions when the
MAX1361/MAX1362 are idle. When operating in exter-
nal clock mode, issue a STOP, NACK, or repeated
START condition to place the devices in idle mode and
benefit from automatic shutdown. A STOP condition is
not necessary in internal clock mode for automatic
shutdown because power-down occurs once all con-
versions are complete. Shutdown reduces supply cur-
rent to less than 0.5µA (external reference mode, typ)
and 300µA (internal reference mode, typ).
Selecting channel scan mode [0,0] starts converting
from channel 0 up to the channel chosen by CS1, CS0.
Selecting channel scan mode [0,1] converts the chan-
nel selected by CS1, CS0 eight times and returns eight
consecutive results.
Selecting monitor mode [1,0] initiates a continuous con-
version scan sequence from channel 0 to the channel
selected by CS1, CS0. See the Monitor Mode section
for more details.
Selecting channel scan mode [1,1] performs a single
conversion on the channel selected by CS1, CS0 and
returns the result.
Table 3. Reference Voltage and AIꢀ3/REF Format
IꢀT REF
POWERDOWꢀ
IꢀTERꢀAL
REFEREꢀCE STATE
SEL1
SEL0
REFEREꢀCE VOLTAGE
AIꢀ3/REF
0
0
1
1
1
1
0
1
0
0
1
1
X
X
0
1
0
1
V
Analog input
Reference input
Analog input
Always off
Always off
Always off
Always on
Always off
Always on
DD
External reference
Internal reference
Internal reference
Internal reference
Internal reference
Analog input
Reference output
Reference output
______________________________________________________________________________________ 15
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
Table 4. Setup-Byte Format*
BIT
NAME
DESCRIPTION
7 (MSB)
Setup
Setup byte always starts with 1.
When [0,0], REF/AIN3 = AIN3, REF = V
DD.
6
5
REF/AIN SEL1
REF/AIN SEL0
When [0,1], REF/AIN3 = REF, REF = external reference.
When [1,0], REF/AIN3 = AIN3, REF = internal reference.
When [1,1], REF/AIN3 = REF, REF = internal reference.
(Table 3)
1 = internal reference always powered up.
0 = internal reference always powered down.
(Table 3)
INT REF Power
Down
4
3
0 = internal clock.
INT/EXT Clock
1 = external clock (MAX1361/MAX1362 use the SCL clock for conversions).
0 = unipolar.
1 = bipolar.
Selects unipolar or bipolar conversion mode. In unipolar mode, analog signal in 0 to V
range
/2.
REF
REF
2
UNI/BIP
can be converted. In differential bipolar mode, input signal can range from -V
/2 to +V
REF
/MAX1362
When single-ended mode is chosen, the SE/DIF bit of configuration byte overrides UNI/BIP, and
conversions are performed in unipolar mode.
1 = no action.
1
0
Reset
0 = resets INT and configuration register. Setup register and channel trip thresholds are unaffected.
0 = no action.
1 = extends writing up to 13 bytes (104 bits) of alarm reset mask. Scans speed selection and
alarm thresholds. See the Configuring Monitor Mode section.
Monitor Setup
*Power-on defaults: 0x82
Table 5. Channel Selection in Single-
Ended Mode (SE/DIF = 1)
Table 7. SE/DIF and UNI/BIP Table
SE/DIF
UNI/BIP
MODE
CS1
CS0
CH0
CH1
CH2
CH3
0
0
1
1
0
1
0
1
Differential inputs, unipolar
Differential inputs, bipolar
Single-ended inputs, unipolar
Single-ended inputs, unipolar
0
0
1
1
0
1
0
1
+
+
+
+
Reading a Conversion (Read Cycle)
Initiate a read cycle to start a conversion sequence and
to obtain conversion results. See the Scan Modes
section for details on the channel-scan sequence. Read
cycles begin with the bus master issuing a START
condition followed by 7 address bits and a read bit
(R/W = 1). After successfully receiving the address byte,
the MAX1361/MAX1362 (slave) issue an ACK. The master
then reads from the slave. (See Figures 10–13.)
Table 6. Channel Selection in Differential
Mode (SE/DIF = 0)
CS1
CS0
CH0
CH1
CH2
CH3
0
0
1
1
0
1
0
1
+
-
-
+
+
-
-
The result is transmitted in 2 bytes. The 1st byte con-
sists of a leading 1 followed by a 2-bit binary channel
address tag, a 12/10 bit flag (0 for the MAX1361/
MAX1362), 2 bits of 1s, the first 2 bits of the data result,
and the expected ACK from the master. The 2nd byte
+
16 ______________________________________________________________________________________
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
/MAX1362
Table 8. Data Format
DATA
(MSB)
10
12/
HIGH CH1 CH0
HIGH HIGH
D8
D7
D6
D5
D4
D3
D2
D1
D0
0 = 10b
1 = 12b
ACK/
NACK
1
0/1
0/1
1
1
0/1
0/1
ACK 0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
START
CONDITION
R/W
ADDRESS
FROM THE MASTER
1, CH ADD, 10b/12b FLAG,
1,1 RESULT (2 MSBs)
START
1
ACK
ACK
ACK STOP
RESULT (8 LSBs)
t
t
CONV
ACQ
Figure 10. Example of Reading the Conversion Result—External Clock Mode
R/W
ADDRESS
FROM THE MASTER
MAX1361/MAX1362 1, CH ADD, 10b/12b, 1,1
START
1
ACK
ACK STOP
ACK
RESULT (8 LSBs)
KEEPS SCL LOW
RESULT (2 MSBs)
6.8μs MAX
t
t
CONV
ACQ
Figure 11. Example of a Single Conversion Using the Internal Clock, SCAN = 1,1
R/W
ADDRESS
FROM THE MASTER
MAX1361/MAX1362
KEEPS SCL LOW
START
1
ACK
CONVERSION 1
CONVERSION 2
t
t
t
t
CONV
ACQ
CONV
ACQ
6.8μs MAX
MAX1361/MAX1362
KEEPS SCL LOW
1, CH ADD, 10b/12b, 1,1
RESULT (2 MSBs)
RESULT 1
(8 LSBs)
ACK
ACK
CONVERSION N
t
t
CONV
ACQ
1, CH ADD, 10b/12b, 1,1
RESULT (2 MSBs)
RESULT N
(8 LSBs)
ACK
ACK STOP
Figure 12. Example of Scan-Mode Conversions Using the Internal Clock, SCAN = 0,0 and 0,1
______________________________________________________________________________________ 17
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
R/W
ADDRESS
FROM THE MASTER
1, CH ADD, 10b/12b
1,1 RESULT (2 MSBs)
START
1
ACK
ACK
ACK
ACQ
RESULT (8 LSBs)
t
t
CONVERSION 1
ACQ
1, CH ADD, 10b/12b, 1,1
RESULT (2 MSBs)
ACK
ACK
RESULT N (8 LSBs)
t
ACQ
t
CONVERSION N
ACQ
Figure 13. Example of Scan-Mode Conversions Using the External Clock, SCAN = 0,0 and 0,1
contains D7–D0. To read the next conversion result,
issue an ACK. To stop reading, issue a NACK.
6) Clears the alarm register. See the Configuring
Monitor Mode section.
/MAX1362
When the MAX1361/MAX1362 receive a NACK, they
release SDA allowing the master to generate a STOP or
a repeated START condition.
7) Monitor mode resumes.
8) If there is still an active fault, the device asserts INT
again. See step 1.
Writing SCAN1 and SCAN0 bits = [1,0] in the configura-
tion byte activates monitor mode. The MAX1361/
MAX1362 scan from channels 0 up to the channel
selected by [CS1:CS0] at a rate determined by the
scan delay bits. The MAX1361/MAX1362 compare the
conversion results with the lower and upper thresholds
for each channel. When any conversion exceeds the
threshold, the MAX1361/MAX1362 assert an interrupt
by pulling INT low (if enabled). The MAX1361/
MAX1362 set the corresponding flag bit in the alarm-
status register and write conversion results to the
latched-fault register to record the event causing the
alarm condition.
Monitor Mode
Monitor-Mode Overview
The MAX1361/MAX1362 automatically monitor up to four
input channels. For systems with limited I2C bandwidth,
monitor mode allows the µC to set a window by
programming lower and upper thresholds during initial-
ization, and only intervening if the MAX1361/MAX1362
detect an alarm condition. This allows an interrupt-driven
approach as an alternative to continuously polling the
ADC with the µC. Monitor mode reduces processor over-
head and conserves I2C bandwidth.
The following shows an example of events in monitor
mode:
INT active state is randomly delayed with respect to the
conversion. Depending on the number of channels
scanned and the position in the channel scan
sequence, the maximum possible delay for asserting
INT is five conversion periods (34µs typ, delay = 0,0,0).
1) Fault condition(s) detected, INT asserted.
2) Host µC services interrupt and send SMBus alert to
identify the alarming device. The MAX1361/
MAX1362 respond with the I2C slave address,
pending arbitration rules. (See the SMBus Alert sec-
tion.)
Configuring Monitor Mode
To write monitoring setup data, set the monitor-setup bit
(bit 0 in setup byte) to 1 to extend writing up to 104 bits
(13 bytes) of monitoring setup data. The number of bits
written to the MAX1361/MAX1362 depends on whether
the part is in single-ended or differential mode and
whether the upper channel limit is set by [CS1:CS0]
(Table 9).
3) The MAX1361/MAX1362 release the INT.
4) Host-µC reads the alarm-status register, latched-
fault register, and current-conversion results to
determine the alarming channel(s) and course of
action.
5) Host µC services alarm(s); adjusts system parame-
ters as needed and/or adjust lower and upper
thresholds.
Terminate writing at any time by using a STOP or
repeated START condition. Previous monitoring setup
data not overwritten remains valid.
18 ______________________________________________________________________________________
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
/MAX1362
Table 9. Monitor-Mode Setup Data Format
Alarm reset, scan
speed, INT_EN ,
(8 bits)
AIN1 thresholds
(skip if differential mode, or
CS1, CS0 < 1) (24 bits)
AIN2 thresholds (skip if AIN3 thresholds (skip if differential
AIN0 thresholds
(24 bits)
CS1, CS0 < 2)
(24 bits)
mode, or CS1, CS0 < 3)
(24 bits)
Table 10. Alarm Resetꢁ Scan Speed Registerꢁ and IꢀT_Eꢀ Data Format
RESET
RESET
RESET
RESET
DELAY 2
DELAY 1
DELAY 0
IꢀT_Eꢀ
ALARM CH 0 ALARM CH 1 ALARM CH 2 ALARM CH 3
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
A 1 written to the reset alarm CH_ clears the alarm, oth-
erwise no action occurs (Table 10). Deassert INT by
clearing all alarms or by initiating an SMBus alert during
an alarm condition (see the SMBus Alert section)
Table 11. Delay Settings
MOꢀITOR-MODE
COꢀVERSIOꢀ RATE
(ksps)
DELAY 2 DELAY 1 DELAY 0
The Delay 2, Delay 1, and Delay 0 bits set the speed of
monitoring by changing the delay between conver-
sions. Delay 2, 1, and 0 = 000 sets the maximum possi-
ble speed; 001 divides the maximum speed by
approximately 2. Increasing delay values further
divides the previous speed by two (Table 11).
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
150.0*
75.0
37.5
18.8
9.4
INT_EN controls the open-drain INT output. Set INT_EN
to 1 to enable the hardware interrupt. Set INT_EN to 0
to disable the hardware interrupt output. The INT output
is high impedance when disabled or when there are no
alarms. The master can also poll the alarm status regis-
ter at any time to check the alarm status.
4.7
2.3
1.2
*When using delay = [0,0,0] in internal reference mode and
AIN3/REF configured as a REF output, the MAX1361/MAX1362
may exhibit a code-dependant gain error due to insufficient
internal reference drive. Gain error caused by this phenomenon
is typically less than 1%FSR (0.1µF C
resistor) and increases with a larger C
Repeat clocking channel threshold data up to the chan-
nel programmed by CS1 and CS0 (Table 12). For differ-
ential input mode, omit odd channels; the lower and
upper threshold data applies to channel pairs. There is
no need to clock in dummy data for odd (or even)
channels (Table 6).
in series with a 2kΩ
REF
. Avoid this gain error
REF
by using an external reference, V , as a reference or use an
DD
internal reference with AIN3/REF as an analog input (see Table
4). Alternatively, choose delay bits other than [0,0,0] to lower the
conversion rate.
Table 12. Lower and Upper Threshold Data Format
BYTE
B7
B6
B5
B4
B3
B2
B1
B0
ACKꢀOWLEDGE
LT9
(MSB)
1
X
X
LT8
LT7
LT6
LT5
LT4
ACK
UT9
(MSB)
2
LT3
UT7
LT2
UT6
LT1
UT5
LT0 (LSB)
UT4
X
X
UT8
ACK
ACK
3
UT3
UT2
UT1
UT0 (LSB)
X = Don’t care.
ACK = Acknowledge.
______________________________________________________________________________________ 19
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
Table 13. Readback-Mode Format
AIꢀ1 THRESHOLDS
(SKIP IF DIFFEREꢀTIAL
MODE OR CS1ꢁ CS0 < 1)
AIꢀ3 THRESHOLDS
(SKIP IF DIFFEREꢀTIAL
MODE OR CS1ꢁ CS0 < 3)
AIꢀ0
THRESHOLDS
AIꢀ2 THRESHOLDS
(SKIP IF CS1ꢁ CS0 < 2)
SCAꢀ SPEED AꢀD IꢀT_Eꢀ
1 D2 D1 D0 INT_EN
1
1
1
24 bits
24 bits
24 bits
24 bits
Table 14. Reading in Monitor-Mode Data Format
ALARM-STATUS REGISTER
LATCHED-FAULT REGISTER
CURREꢀT-COꢀVERSIOꢀ RESULTS
16, 32, 48, or 64 bits (depends on CSO, CS1,
16, 32, 48, or 64 bits (depends on CSO, CS1,
8 bits
and SE/DIF)
and SE/DIF)
Table 15. Alarm-Status Register
CH0 UP
CH0 LOW
CH1 UP
CH1 LOW
CH2 UP
CH2 LOW
CH3 UP
CH3 LOW
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
/MAX1362
0 = Not-alarm condition.
1 = Alarm condition.
Alarm-Status Register
Table 16. Latched-Fault and Current-
Conversion Register
The latched-fault register records a snapshot of the
alarming channel at the instance that a fault condition is
asserted. An alarm-status bit of 1 (Table 15) indicates a
fault, and the data in the latched-fault register of the
corresponding channel contains the conversion result
that caused the alarm to trip. Resetting alarms does not
clear the latched-fault register, thus the latched-fault
register contains valid data only if an alarm status bit is
high for the given channel.
AIꢀ0
AIꢀ1
AIꢀ2
AIꢀ3
16-bit read
16-bit read
16-bit read
16-bit read
To disable alarming on a specific channel, set the lower
threshold to 0x800 and the upper threshold to 0x7FF for
bipolar mode, or set the lower threshold to 0x000 and
the upper threshold to 0xFFF for unipolar mode.
The current-conversion register contains the most
recent conversion results. If the user attempts to read
past the last result of the current-conversion register,
the MAX1361/MAX1362 wraps back to the beginning of
the current-conversion result.
Readback Mode
Select readback mode by setting CS3, CS2 to [1,1] in
the configuration byte. Begin a read operation to start
reading back monitor-setup data. Clock out delay bit
settings, INT_EN bit, and the lower and upper thresh-
olds programmed for each channel. Readback mode
follows exactly the same format as writing to the moni-
tor-setup data, with the exception of the first 4 alarm-
reset bits, which are always 1 (Table 13).
The latched-fault register and current-conversion regis-
ter follow the data format detailed in Tables 8 and 16.
Register length depends on the number of conversions
in one monitoring sequence. For example, when chan-
nel pairs 0/1 and channels 2/3 are monitored differential-
ly, there are only two conversion results to report. The
latched-fault register is 2 x 16 bits long, after which two
current-conversion results follow. Likewise, if CS0 and
CS1 limit the upper bound of the channel scan range
from CH0 to CH2 in single-ended mode, the latched-
fault register clocks out 3 x 16 bits of data followed by
the current-conversion results, also 3 x 16 bits.
Reading in Monitor Mode
Reading in monitor mode reads back the alarm-status
register, latched-fault register, and current-conversion
results as shown in Table 14.
The MAX1361/MAX1362 register pointer loops back to
the beginning of the current-conversion result after
reading the last conversion result. Stop reading at any
time by asserting a STOP condition or NACK.
ꢀote: The MAX1361/MAX1362 do not update the current-
conversion results register while reading in monitor mode.
Monitor mode resumes after a STOP condition or NACK.
20 ______________________________________________________________________________________
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
/MAX1362
sive-integer LSB values. Figures 14 and 15 show the
transfer functions for unipolar and bipolar operations,
respectively.
Resetting Alarm
Reset alarms by writing to monitor-setup data. See the
Configuring Monitor Mode section and Table 10.
Layout, Grounding, and Bypassing
Only use PC boards. Wire-wrap configurations are not
recommended since the layout should ensure proper
separation of analog and digital traces. Do not run ana-
log and digital lines parallel to each other, and do not
layout digital signal paths underneath the ADC pack-
age. Use separate analog and digital PC board ground
sections with only one star point (Figure 16).
SMBus Alert
The SMBus-alert feature provides a quick method to
identify alarming devices on a shared interrupt. Upon
receiving an interrupt signal, the host µC can broadcast
a receive byte request to the alert-response slave
address (0001100). Any slave device that generated an
interrupt attempts to identify itself by putting its own
address on the bus. The alert response can activate
several different slave devices simultaneously. If more
than one slave attempts to respond, bus arbitration
rules apply, and the device with the lower address wins
as a consequence of the open-collector bus. The losing
device does not generate an acknowledgement and
continues to hold the alert line low until serviced.
Successful reading of the alert response address de-
asserts INT.
High-frequency noise in the power supply (V ) could
DD
influence the proper operation of the ADC’s fast com-
parator. Bypass V
to the star ground with a network of
DD
two parallel capacitors, 0.1µF and 4.7µF, located as
close as possible to the MAX1361/MAX1362 power sup-
ply. Minimize capacitor lead length for best supply noise
rejection. For extremely noisy supplies, add an attenua-
tion resistor (5Ω) in series with the power supply.
The MAX1361/MAX1362 resume monitoring after clean-
ing an alarm-status register. INT may immediately re-
assert if a fault is still present, or if the alarm register
has not been thoroughly cleared.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
Transfer Functions
Output data coding for the MAX1361/MAX1362 is bina-
ry in unipolar mode and two’s complement in bipolar
mode with 1 LSB = V
/2N, where N is the number of
REF
bits. Code transitions occur halfway between succes-
OUTPUT CODE
OUTPUT CODE
FULL-SCALE
TRANSITION
V
REF
2
FS =
+ AIN-
011...111
011...110
111...111
111...110
FS = REF + GND
ZS = GND
ZS = AIN-
-V
REF
2
V
1024
-FS =
+ AIN-
000...010
000...001
000...000
100...010
100...001
100...000
REF
1 LSB =
V
1024
REF
1 LSB =
111...111
111...110
111...101
011...111
011...110
011...101
100...001
100...000
000...001
000...000
AIN-
-FS + 0.5 LSB
512
INPUT VOLTAGE (LSB)
0
1
+FS - 1 LSB
INPUT VOLTAGE (LSB)
V
FS - 0.5 LSB
REF
(GND)
AIN- ≥
2
Figure 14. Unipolar Transfer Function
Figure 15. Bipolar Transfer Function
______________________________________________________________________________________ 21
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
SUPPLIES
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
GND
3V OR 5V
V
= 3V/5V
LOGIC
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
4.7μF
0.1μF
R* = 5Ω
SINAD(dB) = 20 x log (SignalRMS/NoiseRMS)
V
DD
GND
3V/5V DGND
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
DIGITAL
CIRCUITRY
MAX1361
MAX1362
/MAX1362
*OPTIONAL
ENOB = (SINAD - 1.76)/6.02
Figure 16. Power-Supply Grounding Connection
⎡
⎢
⎣
⎤
⎥
⎦
Signal
RMS
SINAD(dB) = 20 × log
Noise
+ THD
RMS
RMS
MAX1361/MAX1362’s INL is measured using the end-
point method.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fun-
damental itself. This is expressed as:
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
⎛
⎜
⎞
⎟
2
2
2
2
V
+ V + V + V
3 4 5
2
THD = 20 × log
Aperture Jitter
V
⎜
⎝
⎟
⎠
1
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
where V is the fundamental amplitude, and V through
5
harmonics.
1
2
Aperture Delay
V
are the amplitudes of the 2nd- through 5th-order
Aperture delay (t ) is the time between the falling
AD
edge of the sampling clock and the instant when an
actual sample is taken.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest distortion
component.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
SNR (MAX)[dB] = 6.02dB x N + 1.76dB
22 ______________________________________________________________________________________
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
/MAX1362
Ordering Information/Selector Guide (continued)
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
I2C SLAVE ADDRESS
0110100/0110101
0110110/0110111
SUPPLY VOLTAGE (V)
MAX1362EUB+
MAX1362MEUB+
10 μMAX
4.5 to 5.5
10 μMAX
4.5 to 5.5
+Denotes a lead(Pb)-free/RoHS-compliant package.
Typical Operating Circuit
Pin Configuration
3V/5V
TOP VIEW
0.1μF
4.7μF
+
AIN0
AIN1
AIN2
1
2
3
4
5
10
9
V
DD
V
DD
GND
SDA
SCL
INT
INT
AIN0
AIN1
MAX1361
MAX1362
*R
*R
S
8
MAX1361
MAX1362
SDA
SCL
ANALOG
INPUTS
AIN3/V
7
REF
A0
6
S
2kΩ
AIN3/REF
GND
μMAX
C
REF
0.1μF
R
P
3V/5V
R
P
3V/5V
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
R
P
SDA
μC
SCL
INT
PACKAGE
TYPE
PACKAGE
CODE
OUTLIꢀE
ꢀO.
LAꢀD
PATTERꢀ ꢀO.
*OPTIONAL
10 µMAX
U10CN+1
21-0061
90-0330
______________________________________________________________________________________ 23
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
4
3/08
Removed L grade from data sheet
1, 13, 23
2
Changed the number of possible I C addresses to 4 (instead of 6) in the Features and
Slave Address section
5
9/10
1, 13
/MAX1362
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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