MAX13108EETL-T [MAXIM]
Telephone Relay Driver, BICMOS, 5 X 5 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, MO-220, TQFN-40;
| 型号： | MAX13108EETL-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Telephone Relay Driver, BICMOS, 5 X 5 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, MO-220, TQFN-40 转换器 电平转换器 |
| 文件： | 总18页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3802; Rev 3; 6/08
16-Channel Buffered CMOS
Logic-Level Translators
2/MAX3108E
General Description
Features
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-bit bidirectional CMOS logic-level translators pro-
vide the level shifting necessary to allow data transfer in
multivoltage systems. These devices are inherently
bidirectional due to their design and do not require the
use of a direction input. Externally applied voltages,
♦ Wide Supply Voltage Range
Range of 1.65V to 5.5V
V
CC
V Range of 1.2V to V
L
CC
♦ ESD Protection on I/O V
Lines
CC
15ꢀV ꢁuꢂan ꢃody ꢄodel
♦ Up to 20ꢄbps Throughput
V
and V , set the logic levels on either side of the
L
CC
devices. Logic signals present on the V side of the
L
♦ Low 0.03µA Typical Quiescent Current
♦ WLP and TQFN Pacꢀages
device appear as a higher voltage logic signal on the
V
CC
side of the device, and vice-versa.
Pin Configurations
The MAX13101E/MAX13102E/MAX13103E feature an
enable input (EN) that, when low, reduces the V
and
CC
TOP VIEW OF BOTTOM LEADS
V supply currents to less than 2µA. The MAX13108E
L
features a multiplexing input (MULT) that selects one
byte between the two, thus allowing multiplexing of the
signals. The MAX13101E/MAX13102E/MAX13103E/
30 29 28 27 26 25 24 23 22 21
MAX13108E have 1ꢀ5V ESꢁ protection on the ꢂ/O V
CC
I/O V 13
CC
I/O V
I/O V
I/O V
I/O V
4
3
2
1
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
CC
CC
CC
CC
side for greater protection in applications that route sig-
nals externally. Three different output configurations are
I/O V 14
CC
I/O V 15
CC
available during shutdown, allowing the ꢂ/O on the V
CC
side or the V side to be put in a high-impedance state
L
I/O V 16
CC
or pulled to ground through an internal 65Ω resistor.
MAX13101E
MAX13102E
MAX13103E
V
V
CC
CC
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
V
L
V
L
accept V
voltages from +1.6ꢀV to +ꢀ.ꢀV and V
L
CC
I/O V 1
L
I/O V 16
L
voltages from +1.2V to V , ma5ing them ideal for data
CC
I/O V 2
L
I/O V 15
L
*EP
transfer between low-voltage ASꢂCs/PLꢁs and higher
voltage systems. The MAX13101E/MAX13102E/
MAX13103E/MAX13108E are available in 36-bump
WLP and 40-pin TQFN pac5ages, and operate over the
extended -40°C to +8ꢀ°C temperature range.
I/O V 3
L
I/O V 14
L
+
I/O V 4
L
I/O V 13
L
11
1
2
3
4
5
6
7
8
9
10
Applications
*EXPOSED PAD CONNECTED TO GROUND
TQFN
CMOS Logic-Level
Translation
PꢁAs
Pin Configurations continued at end of data sheet.
ꢁigital Still Cameras
Smart Phones
Portable Equipment
Cell Phones
Typical Operating Circuit appears at end of data sheet.
Ordering Information/Selector Guide
DATA
I/O V STATE
I/O V
STATE
ꢄULTIPLEXER
FEATURE
L
CC
PART
PIN-PACKAGE
RATE (ꢄbps) DURING SꢁUTDOWN DURING SꢁUTDOWN
36 WLP**
3.06mm x 3.06mm
ꢄAX13101EEWX+*
MAX13101EETL+
20
High impedance
65Ω to GNꢁ
65Ω to GNꢁ
No
No
40 TQFN-EP***
ꢀmm x ꢀmm x 0.8mm
20
High impedance
Note: All devices are specified over the -40°C to +8ꢀ°C operating temperature range.
+ꢁenotes a lead-free/RoHS-compliant pac5age.
*Future product—contact factory for availability.
**WLP bumps are in a 6 x 6 array.
***EP = Exposed pad.
Ordering Inforꢂation/Selector Guide continued at end of data sheet.
________________________________________________________________ ꢄaxiꢂ Integrated Products
1
For pricing, delivery, and ordering inforꢂation, please contact ꢄaxiꢂ Direct at 1-888-629-4642,
or visit ꢄaxiꢂ’s website at www.ꢂaxiꢂ-ic.coꢂ.
16-Channel Buffered CMOS
Logic-Level Translators
AꢃSOLUTE ꢄAXIꢄUꢄ RATINGS
(All voltages referenced to GNꢁ.)
Operating Temperature Range ...........................-40°C to +8ꢀ°C
V
V
ꢂ/O V
...........................................................................-0.3V to +6V
Maximum Junction Temperature .....................................+1ꢀ0°C
Storage Temperature Range ............................-6ꢀ°C to +1ꢀ0°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
-0.3V to +6V
L...........................................................................................
......................................................-0.3V to (V
+ 0.3V)
CC_
CC
ꢂ/O V
-0.3V to (V + 0.3V)
L_.....................................................................
L
EN, MULT .................................................................-0.3V to +6V
Short-Circuit ꢁuration ꢂ/O V , ꢂ/O V to GNꢁ .......Continuous
L_
CC_
Continuous Power ꢁissipation (T = +70°C)
A
36-Bump WLP (derate 17.0mW/°C above +70°C).....1361mW
40-Pin TQFN (derate 3ꢀ.7mW/°C above +70°C) .......28ꢀ7mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CꢁARACTERISTICS
(V
= +1.6ꢀV to +ꢀ.ꢀV, V = +1.2V to V , EN = V (MAX13101E/MAX13102E/MAX13103E), MULT = V or GNꢁ (MAX13108E),
CC
L CC L L
T
A
= T
to T
, unless otherwise noted. Typical values are at V
= +1.6ꢀV, V = +1.2V, T = +2ꢀ°C.) (Notes 1, 2)
CC L A
MꢂN
MAX
PARAꢄETER
POWER SUPPLIES
V Supply Range
SYꢄꢃOL
CONDITIONS
ꢄIN
TYP
ꢄAX
UNITS
V
1.2
V
CC
V
V
L
L
V
Supply Range
V
1.6ꢀ
ꢀ.ꢀ0
CC
CC
ꢂ/O V _ = GNꢁ, ꢂ/O V _ = GNꢁ
CC
L
or ꢂ/O V _ = V , ꢂ/O V _ = V ,
Supply Current from V
ꢂ
0.03
0.03
0.03
10
µA
µA
µA
µA
CC
CC
L
L
CC
L
QVCC
EN = V , MULT = GNꢁ or V
L
L
ꢂ/O V _ = GNꢁ, ꢂ/O V _ = GNꢁ
CC
L
Supply Current from V
ꢂ
or ꢂ/O V _ = V , ꢂ/O V _ = V ,
20
1
QVL
CC
CC
L
L
EN = V , MULT = GNꢁ or V
L
L
T
A
= +2ꢀ°C, EN = GNꢁ, ꢂ/O V _ = GNꢁ,
CC
ꢂ/O V _ = GNꢁ,
L
MAX13101E/MAX13102E/MAX13103E
V
Shutdown Supply Current
ꢂ
ꢂ
CC
SHꢁN-VCC
SHꢁN-VL
T
A
= +2ꢀ°C, EN = GNꢁ, ꢂ/O V _ = GNꢁ,
CC
ꢂ/O V _ = GNꢁ,
L
MAX13101E/MAX13102E/MAX13103E
V Shutdown Supply Current
L
0.03
0.02
0.02
0.02
0.02
2
1
T
A
= +2ꢀ°C, EN = GNꢁ,
MAX13102E/MAX13103E
ꢂ/O V _ Tri-State Output
CC
Lea5age Current
µA
T = +2ꢀ°C, MULT = GNꢁ (ꢂ/O V 1 - ꢂ/O V 8)
A
CC
CC
or MULT = V (ꢂ/O V 9 - ꢂ/O V 16)
1
L
CC
CC
MAX13108E
T
A
= +2ꢀ°C, EN = GNꢁ, MAX13101E/
1
MAX13103E
ꢂ/O V _ Tri-State Output Lea5age
L
Current
µA
T
A
= +2ꢀ°C, MULT = GNꢁ (ꢂ/O V 1 - ꢂ/O
L
2/MAX3108E
V 8) or MULT = V (ꢂ/OV 9 - ꢂ/O V 16)
1
L
L
L
L
MAX13108E
ꢂ/O V _ Pulldown Resistance
L
ꢁuring Shutdown
EN = GNꢁ, MAX13102E
4
10
5Ω
2
_______________________________________________________________________________________
16-Channel Buffered CMOS
Logic-Level Translators
2/MAX3108E
ELECTRICAL CꢁARACTERISTICS (continued)
(V
= +1.6ꢀV to +ꢀ.ꢀV, V = +1.2V to V , EN = V (MAX13101E/MAX13102E/MAX13103E), MULT = V or GNꢁ (MAX13108E),
CC
L CC L L
T
A
= T
to T
, unless otherwise noted. Typical values are at V
= +1.6ꢀV, V = +1.2V, T = +2ꢀ°C.) (Notes 1, 2)
CC L A
MꢂN
MAX
PARAꢄETER
SYꢄꢃOL
CONDITIONS
ꢄIN
TYP
ꢄAX
UNITS
ꢂ/O V _ Pulldown Resistance
CC
ꢁuring Shutdown
EN = GNꢁ, MAX13101E
4
10
5Ω
EN or MULT ꢂnput Lea5age
Current
T
A
= +2ꢀ°C
1
µA
LOGIC-LEVEL TꢁRESꢁOLDS
ꢂ/O V _ ꢂnput-Voltage High
L
Threshold
2/3 x
V
L
V
V
V
V
V
V
V
ꢂHL
ꢂ/O V _ ꢂnput-Voltage Low
L
Threshold
1/3 x
V
L
V
ꢂLL
ꢂ/O V _ ꢂnput-Voltage High
CC
Threshold
2/3 x
V
CC
V
ꢂHC
ꢂ/O V _ ꢂnput-Voltage Low
CC
Threshold
1/3 x
V
CC
V
ꢂLC
EN, MULT ꢂnput-Voltage High
Threshold
V
V - 0.4
L
ꢂH-SHꢁN
EN, MULT ꢂnput-Voltage Low
Threshold
V
0.4
V - 0.4
ꢂL-SHꢁN
ꢂ/O V _ Output-Voltage High
V
ꢂ/O V _ source current = 20µA, ꢂ/O V _ ≥ V
V
V
V
V
L
OHL
L
CC
ꢂHC
L
ꢂ/O V _ Output-Voltage Low
V
ꢂ/O V _ sin5 current = 20µA, ꢂ/O V _ ≤ V
ꢂLC
0.4
0.4
L
OLL
L
CC
ꢂ/O V _ Output-Voltage High
V
ꢂ/O V _ source current = 20µA, ꢂ/O V _ ≥ V
V
- 0.4
CC
OHC
CC
L
ꢂHL CC
ꢂ/O V _ Output-Voltage Low
V
ꢂ/O V _ sin5 current = 20µA, ꢂ/O V _ ≤ V
CC
OLC
CC
L
ꢂLL
RISE/FALL-TIꢄE ACCELERATOR STAGE
ꢂ/O V
side
V
/ 2
CC
CC
Transition-ꢁetect Threshold
V
ns
Ω
ꢂ/O V side
V / 2
L
L
Accelerator Pulse ꢁuration
V = 1.2V, V
L
= 1.6ꢀV
= 1.6ꢀV
20
60
ꢀ
CC
CC
V = 1.2V, V
L
ꢂ/O V _ Output-Accelerator Sin5
L
ꢂmpedance
V = ꢀV, V
L
= ꢀV
CC
V = 1.2V, V
= 1.6ꢀV
1ꢀ
ꢀ
L
CC
CC
CC
ꢂ/O V _ Output-Accelerator Sin5
CC
ꢂmpedance
Ω
Ω
Ω
V = ꢀV, V
L
= ꢀV
CC
V = 1.2V, V
L
= 1.6ꢀV
30
ꢀ
ꢂ/O V _ Output-Accelerator
L
Source ꢂmpedance
V = ꢀV, V
L
= ꢀV
CC
V = 1.2V, V
L
= 1.6ꢀV
20
7
ꢂ/O V _ Output-Accelerator
CC
Source ꢂmpedance
V = ꢀV, V
L
= ꢀV
CC
ESD PROTECTION
ꢂ/O V _
CC
Human Body Model
1ꢀ
5V
_______________________________________________________________________________________
3
16-Channel Buffered CMOS
Logic-Level Translators
TIꢄING CꢁARACTERISTICS
(V
= +1.6ꢀV to +ꢀ.ꢀV, V = +1.2V to V , EN = V (MAX13101E/MAX13102E/MAX13103E), MULT = V or GNꢁ (MAX13108E),
CC
L CC L L
T
A
= T
to T
, unless otherwise noted. Typical values are at V
= +1.6ꢀV, V = +1.2V, T = +2ꢀ°C.) (Notes 1, 2)
CC L A
MꢂN
MAX
PARAꢄETER
ꢂ/O V _ Rise Time
SYꢄꢃOL
CONDITIONS
ꢄIN
TYP
ꢄAX
UNITS
R = ꢀ0Ω, C
= 1ꢀpF, t
≤ 3ns,
S
ꢂ/OVL_
RꢂSE
t
1ꢀ
ns
L
RVL
(Figures 2a, 2b)
R = ꢀ0Ω, C
(Figures 2a, 2b)
= 1ꢀpF, t
≤ 3ns,
S
ꢂ/OVL_
FALL
ꢂ/O V _ Fall Time
t
1ꢀ
1ꢀ
1ꢀ
20
20
ꢀ
ns
ns
L
FVL
R = ꢀ0Ω, C
= ꢀ0pF, t
= ꢀ0pF, t
= ꢀ0pF, t
≤ 3ns,
≤ 3ns,
≤ 3ns,
S
ꢂ/OVCC_
RꢂSE
FALL
RꢂSE
ꢂ/O V _ Rise Time
t
RVCC
CC
(Figures 1a, 1b)
R = ꢀ0Ω, C
S
ꢂ/OVCC_
ꢂ/O V _ Fall Time
CC
t
ns
FVCC
(Figures 1a, 1b)
Propagation ꢁelay
(ꢁriving ꢂ/O V _)
L
R = ꢀ0Ω, C
S
ꢂ/OVCC_
t
t
ns
PVL-VCC
(Figures 1a, 1b)
Propagation ꢁelay
(ꢁriving ꢂ/O V _)
CC
R = ꢀ0Ω, C
= 1ꢀpF, t
≤ 3ns,
S
ꢂ/OVL_
RꢂSE
ns
PVCC-VL
(Figures 2a, 2b)
R = ꢀ0Ω, C
= ꢀ0pF, C
= ꢀ0pF, C
ꢂ/OVCC_
=
=
S
ꢂ/OVCC_
ꢂ/OVL_
Channel-to-Channel S5ew
t
ns
SKEW
1ꢀpF, t
≤ 3ns
RꢂSE
R = ꢀ0Ω, C
S
ꢂ/OVL_
Part-to-Part S5ew
t
10
1
ns
PPSKEW
1ꢀpF, t
≤ 3ns, ΔT = +20°C (Notes 3, 4)
RꢂSE
A
Propagation ꢁelay from
t
C
C
= ꢀ0pF (Figure 3)
ꢂ/OVCC_
µs
EN-VCC
ꢂ/O V _ to ꢂ/O V _ After EN
L
CC
Propagation ꢁelay from
ꢂ/O V _ to ꢂ/O V _ After EN
t
= 1ꢀpF (Figure 4)
1
µs
EN-VL
ꢂ/OVL_
CC
L
R
C
= ꢀ0Ω, C
= ꢀ0pF,
≤ 3ns
SOURCE
ꢂ/OVCC_
Maximum ꢁata Rate
20
Mbps
= 1ꢀpF, t
ꢂ/OVL_
RꢂSE
Note 1: All units are 100% production tested at T = +2ꢀ°C. Limits over the operating temperature range are guaranteed by design
A
and not production tested.
Note 2: For normal operation, ensure that V < (V
+ 0.3V). ꢁuring power-up, V > (V
+ 0.3V) does not damage the device.
CC
L
CC
L
Note 3: V
from device 1 must equal V
of device 2. V from device 1 must equal V of device 2.
CC L L
CC
Note 4: Guaranteed by design, not production tested.
2/MAX3108E
4
_______________________________________________________________________________________
16-Channel Buffered CMOS
Logic-Level Translators
2/MAX3108E
Test Circuits/Timing Diagrams
t
≤ 3ns
RISE/FALL
MAX13101E
MAX13102E
MAX13103E
MAX13108E
I/O V
L_
90%
50%
V
CC
50%
V
L
10%
EN/(MULT)
t
PLH
6kΩ
t
PHL
I/O V
L_
I/O V
CC_
I/O V
CC_
6kΩ
90%
10%
90%
50%
R
S
C
SOURCE
I/OVCC_
10%
ALL UNUSED I/O V
AND I/O V CONNECTED TO GND
L_
CC_
t
t
RVCC
FVCC
( ) ARE FOR THE MAX13108E
t
= t or t
PVL-VCC PHL PLH
Figure 1a. ꢁriving ꢂ/O V
Figure 1b. Timing for ꢁriving ꢂ/O V
L_
L_
t
≤ 3ns
RISE/FALL
MAX13101E
I/O V
90%
50%
CC_
MAX13102E
MAX13103E
MAX13108E
V
CC
V
L
50%
10%
EN/(MULT)
t
6kΩ
PLH
t
PHL
R
S
I/O V
L_
6kΩ
I/O V
90%
SOURCE
C
I/OVL_
L_
I/O V
CC_
90%
50%
10%
10%
ALL UNUSED I/O V
AND I/O V CONNECTED TO GND
L_
CC_
( ) ARE FOR THE MAX13108E
t
t
RVL
FVL
t = t or t
PVCC-VL PHL PLH
Figure 2a. ꢁriving ꢂ/O V
Figure 2b. Timing for ꢁriving ꢂ/O V
CC_
CC_
_______________________________________________________________________________________
5
16-Channel Buffered CMOS
Logic-Level Translators
Test Circuits/Timing Diagrams (continued)
MAX13101E
MAX13102E
MAX13103E
MAX13108E
V
0
V
L
EN/(MULT)
t
EN/(MULT)
EN-VCC
SOURCE
I/O V
6kΩ
L
I/O V
CC_
I/O V
L_
L_
0
6kΩ
V
L
V
CC
V
CC
2
100kΩ
C
I/OVCC
I/O V
CC_
( ) ARE FOR THE MAX13108E
Figure 3. Propagation ꢁelay from ꢂ/O V to ꢂ/O V
After EN
L_
CC_
MAX13101E
MAX13102E
MAX13103E
MAX13108E
V
0
V
L
EN/(MULT)
t
EN-VL
EN/(MULT)
SOURCE
CC
6kΩ
I/O V
CC_
I/O V
CC_
0
I/O V
L_
V
L
6kΩ
V
2
L
V
CC
I/O V
L_
100kΩ
C
I/OVL
0
( ) ARE FOR THE MAX13108E
Figure 4. Propagation ꢁelay from ꢂ/O V
to ꢂ/O V After EN
L_
CC_
2/MAX3108E
6
_______________________________________________________________________________________
16-Channel Buffered CMOS
Logic-Level Translators
2/MAX3108E
Typical Operating Characteristics
(V
= 3.3V, V = 1.8V, data rate = 20Mbps, T = +2ꢀ°C, unless otherwise noted.)
CC
L
A
V SUPPLY CURRENT vs. V SUPPLY VOLTAGE
V SUPPLY CURRENT vs. V SUPPLY VOLTAGE
L
CC
L
L
(DRIVING I/0 V , V = 1.8V)
(DRIVING I/0 V , V = 5.5V)
L_
L
CC_ CC
2500
2000
1500
1000
500
120
DRIVING ONE I/O V
CC
DRIVING ONE I/O VL
FIGURE 1a
FIGURE 2a
100
80
60
40
20
0
C
= 15pF
I/OVCC_
C
= 15pF
I/OVL_
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
V SUPPLY VOLTAGE (V)
L
V
CC
V
SUPPLY CURRENT vs. V SUPPLY VOLTAGE
V
SUPPLY CURRENT vs. V SUPPLY VOLTAGE
CC
CC
L
CC
(DRIVING I/0 V , V = 5.5V)
(DRIVING I/0 V , V = 1.8V)
CC_ CC
L_
L
8000
7000
6000
5000
4000
3000
2000
1000
0
8000
7000
6000
5000
4000
3000
2000
1000
0
DRIVING ONE I/O V
CC
DRIVING ONE I/O V
FIGURE 1a
L
FIGURE 2a
C
I/OVL_
= 15pF
C
= 15pF
I/OVCC_
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
V SUPPLY VOLTAGE (V)
L
V
CC
V SUPPLY CURRENT vs. TEMPERATURE
L
V
SUPPLY CURRENT vs. TEMPERATURE
CC
(DRIVING I/O V
)
(DRIVING I/O V
)
CC_
CC_
800
700
600
500
400
300
200
100
0
3000
2500
2000
1500
1000
500
DRIVING ONE I/O V
CC
DRIVING ONE I/O V
CC
FIGURE 2a
= 15pF
FIGURE 2a
= 15pF
C
I/OVL_
C
I/OVL_
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
16-Channel Buffered CMOS
Logic-Level Translators
Typical Operating Characteristics (continued)
(V
= 3.3V, V = 1.8V, data rate = 20Mbps, T = +2ꢀ°C, unless otherwise noted.)
L A
CC
V SUPPLY CURRENT vs. CAPACITIVE LOAD
V
SUPPLY CURRENT vs. CAPACITIVE LOAD
RISE/FALL TIME vs. CAPACITIVE LOAD ON
I/O V _ (DRIVING I/O V
L
CC
ON I/O V (DRIVING I/O V
)
ON I/O V
(DRIVING I/O V
)
L_
)
L_
L_
CC_
CC_
CC
1200
1000
800
600
400
200
0
5000
4
3
2
1
0
DRIVING ONE I/O V
CC
DRIVING ONE I/O V
FIGURE 1a
L
FIGURES 1a, 1b
FIGURE 2a
4000
3000
2000
1000
0
t
RVCC
t
FVCC
10
20
30
40
50
10
20
30
40
50
10
20
30
40
50
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
RISE/FALL TIME vs. CAPACITIVE LOAD
ON I/O V (DRIVING I/O V
PROPAGATION DELAY vs. CAPACITIVE LOAD
ON I/O V (DRIVING I/O V
)
CC_
)
L_
L_
CC_
7
6
5
4
3
2
1
0
10
FIGURES 2a, 2b
FIGURES 1a, 1b
8
t
PLH
6
t
t
RVL
FVL
4
t
PHL
2
0
10
20
30
40
50
10
20
30
40
50
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
2/MAX3108E
8
_______________________________________________________________________________________
16-Channel Buffered CMOS
Logic-Level Translators
2/MAX3108E
Typical Operating Characteristics (continued)
(V
= 3.3V, V = 1.8V, data rate = 20Mbps, T = +2ꢀ°C, unless otherwise noted.)
L A
CC
PROPAGATION DELAY vs. CAPACITIVE LOAD
ON I/O V (DRIVING I/O V
)
RAIL-TO-RAIL DRIVING (DRIVING I/O V )
L
MAX13101E-3/8E toc13
L_
CC_
5
4
3
2
1
0
FIGURES 2a, 2b
t
C
= 50pF
PHL
I/OVCC_
I/0 V
1V/div
L_
t
PLH
GND
I/0 V
CC_
2V/div
GND
10ns/div
10
20
30
40
50
CAPACITIVE LOAD (pF)
Pin Description—MAX13101E/MAX13102E/MAX13103E
PIN
NAꢄE
FUNCTION
TQFN
WLP
ꢁ6
C2
A3
B3
C3
A4
B4
C4
Aꢀ
C6
Bꢀ
Cꢀ
A6
B6
A1
1, 21, 30
GNꢁ
ꢂ/O V ꢀ
Ground
ꢂnput/Output ꢀ. Referenced to V .
2
3
L
L
ꢂ/O V 6
ꢂnput/Output 6. Referenced to V .
L
L
4
ꢂ/O V 7
ꢂnput/Output 7. Referenced to V .
L
L
ꢀ
ꢂ/O V 8
ꢂnput/Output 8. Referenced to V .
L
L
6
ꢂ/O V 9
ꢂnput/Output 9. Referenced to V .
L
L
7
ꢂ/O V 10 ꢂnput/Output 10. Referenced to V .
L L
8
ꢂ/O V 11 ꢂnput/Output 11. Referenced to V .
L L
9
ꢂ/O V 12 ꢂnput/Output 12. Referenced to V .
L L
10
11
12
13
14
1ꢀ, 36
EN
Global Enable ꢂnput. Pull EN low for shutdown. ꢁrive EN to V or V for normal operation.
CC L
ꢂ/O V 13 ꢂnput/Output 13. Referenced to V .
L
L
ꢂ/O V 14 ꢂnput/Output 14. Referenced to V .
L
L
ꢂ/O V 1ꢀ ꢂnput/Output 1ꢀ. Referenced to V .
L
L
ꢂ/O V 16 ꢂnput/Output 16. Referenced to V .
L
L
V
Logic Supply Voltage, +1.2V ≤ V ≤ V . Bypass V to GNꢁ with a 0.1µF capacitor.
L CC L
L
V
Supply Voltage, +1.6ꢀV ≤ V ≤ +ꢀ.ꢀV. Bypass V to GNꢁ with a 0.1µF capacitor.
CC
CC
CC
For full ESꢁ protection, connect a 1.0µF capacitor from V
to GNꢁ, located as close to the
16, 3ꢀ
F1
V
CC
CC
V
input as possible.
CC
17
18
E6
F6
ꢂ/O V 16 ꢂnput/Output 16. Referenced to V
.
.
CC
CC
ꢂ/O V 1ꢀ ꢂnput/Output 1ꢀ. Referenced to V
CC
CC
_______________________________________________________________________________________
9
16-Channel Buffered CMOS
Logic-Level Translators
Pin Description—MAX13101E/MAX13102E/MAX13103E (continued)
PIN
NAꢄE
ꢂ/O V 14 ꢂnput/Output 14. Referenced to V
FUNCTION
TQFN
19
20
22
23
24
2ꢀ
26
27
28
29
31
32
33
34
37
38
39
40
—
WLP
ꢁꢀ
Eꢀ
Fꢀ
.
.
.
.
.
CC
CC
CC
CC
CC
CC
ꢂ/O V 13 ꢂnput/Output 13. Referenced to V
CC
ꢂ/O V 12 ꢂnput/Output 12. Referenced to V
CC
ꢁ4
E4
F4
ꢂ/O V 11 ꢂnput/Output 11. Referenced to V
CC
ꢂ/O V 10 ꢂnput/Output 10. Referenced to V
CC
ꢂ/O V
ꢂ/O V
ꢂ/O V
ꢂ/O V
ꢂ/O V
ꢂ/O V
ꢂ/O V
ꢂ/O V
ꢂ/O V
9
8
7
6
ꢀ
4
3
2
1
ꢂnput/Output 9. Referenced to V
ꢂnput/Output 8. Referenced to V
ꢂnput/Output 7. Referenced to V
ꢂnput/Output 6. Referenced to V
ꢂnput/Output ꢀ. Referenced to V
ꢂnput/Output 4. Referenced to V
ꢂnput/Output 3. Referenced to V
ꢂnput/Output 2. Referenced to V
ꢂnput/Output 1. Referenced to V
.
.
.
.
.
.
.
.
.
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
ꢁ3
E3
F3
ꢁ2
E2
F2
ꢁ1
E1
B1
C1
A2
B2
—
ꢂ/O V 1
ꢂnput/Output 1. Referenced to V .
L
L
ꢂ/O V 2
ꢂnput/Output 2. Referenced to V .
L
L
ꢂ/O V 3
ꢂnput/Output 3. Referenced to V .
L
L
ꢂ/O V 4
L
ꢂnput/Output 4. Referenced to V .
L
EP
Exposed Pad. Connect EP to GNꢁ.
Pin Description—MAX13108E
PIN
NAꢄE
FUNCTION
TQFN
WLP
ꢁ6
C2
A3
B3
C3
A4
B4
C4
Aꢀ
1, 21, 30
GNꢁ
Ground
ꢂnput/Output ꢀ. Referenced to V .
2
3
4
ꢀ
6
7
8
9
ꢂ/O V ꢀ
L
L
ꢂ/O V 6
ꢂnput/Output 6. Referenced to V .
L
L
ꢂ/O V 7
ꢂnput/Output 7. Referenced to V .
L
L
ꢂ/O V 8
ꢂnput/Output 8. Referenced to V .
L
L
ꢂ/O V 9
ꢂnput/Output 9. Referenced to V .
L
L
ꢂ/O V 10 ꢂnput/Output 10. Referenced to V .
L
L
ꢂ/O V 11 ꢂnput/Output 11. Referenced to V .
L
L
ꢂ/O V 12 ꢂnput/Output 12. Referenced to V .
2/MAX3108E
L
L
10 ______________________________________________________________________________________
16-Channel Buffered CMOS
Logic-Level Translators
2/MAX3108E
Pin Description—MAX13108E (continued)
PIN
NAꢄE
FUNCTION
TQFN
WLP
Multiplexing ꢂnput. ꢁrive MULT low to enable channels 9 to 16. ꢁriving MULT low puts
10
C6
MULT
channels 1 to 8 into tri-state. ꢁrive MULT to V or V to enable channels 1 to 8. ꢁriving
CC L
MULT to V
or V puts channels 9 to 16 into tri-state.
L
CC
11
12
Bꢀ
Cꢀ
A6
B6
A1
ꢂ/O V 13 ꢂnput/Output 13. Referenced to V .
L L
ꢂ/O V 14 ꢂnput/Output 14. Referenced to V .
L
L
13
ꢂ/O V 1ꢀ ꢂnput/Output 1ꢀ. Referenced to V .
L L
14
ꢂ/O V 16 ꢂnput/Output 16. Referenced to V .
L L
1ꢀ, 36
V
Logic Supply Voltage, +1.2V ≤ V ≤ V . Bypass V to GNꢁ with a 0.1µF capacitor.
L CC L
L
V
Supply Voltage, +1.6ꢀV ≤ V ≤ +ꢀ.ꢀV. Bypass V
to GNꢁ with a 0.1µF capacitor.
CC
CC
CC
16, 3ꢀ
F1
V
For full ESꢁ protection, connect a 1.0µF capacitor from V
to GNꢁ, located as close to the
CC
CC
V
input as possible.
CC
17
18
19
20
22
23
24
2ꢀ
26
27
28
29
31
32
33
34
37
38
39
40
—
E6
F6
ꢁꢀ
Eꢀ
Fꢀ
ꢁ4
E4
F4
ꢁ3
E3
F3
ꢁ2
E2
F2
ꢁ1
E1
B1
C1
A2
B2
—
ꢂ/O V 16 ꢂnput/Output 16. Referenced to V
.
.
.
.
.
.
.
CC
CC
CC
CC
CC
CC
CC
CC
ꢂ/O V 1ꢀ ꢂnput/Output 1ꢀ. Referenced to V
CC
ꢂ/O V 14 ꢂnput/Output 14. Referenced to V
CC
ꢂ/O V 13 ꢂnput/Output 13. Referenced to V
CC
ꢂ/O V 12 ꢂnput/Output 12. Referenced to V
CC
ꢂ/O V 11 ꢂnput/Output 11. Referenced to V
CC
ꢂ/O V 10 ꢂnput/Output 10. Referenced to V
CC
ꢂ/O V
ꢂ/O V
ꢂ/O V
ꢂ/O V
ꢂ/O V
ꢂ/O V
ꢂ/O V
ꢂ/O V
ꢂ/O V
9
8
7
6
ꢀ
4
3
2
1
ꢂnput/Output 9. Referenced to V
ꢂnput/Output 8. Referenced to V
ꢂnput/Output 7. Referenced to V
ꢂnput/Output 6. Referenced to V
ꢂnput/Output ꢀ. Referenced to V
ꢂnput/Output 4. Referenced to V
ꢂnput/Output 3. Referenced to V
ꢂnput/Output 2. Referenced to V
ꢂnput/Output 1. Referenced to V
.
.
.
.
.
.
.
.
.
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
ꢂ/O V 1
ꢂnput/Output 1. Referenced to V .
L
L
ꢂ/O V 2
ꢂnput/Output 2. Referenced to V .
L
L
ꢂ/O V 3
ꢂnput/Output 3. Referenced to V .
L
L
ꢂ/O V 4
L
ꢂnput/Output 4. Referenced to V .
L
EP
Exposed Pad. Connect EP to GNꢁ.
______________________________________________________________________________________ 11
16-Channel Buffered CMOS
Logic-Level Translators
Functional Diagrams
V
CC
V
L
V
CC
V
L
MULT
EN
MAX13101E
MAX13102E
MAX13103E
MAX13108E
I/O V 1
L
I/O V
I/O V
I/O V
I/O V
I/O V
1
2
3
4
5
CC
CC
CC
CC
CC
I/O V 1
L
I/O V
I/O V
I/O V
I/O V
I/O V
1
CC
2
CC
3
CC
4
CC
5
CC
I/O V 2
L
I/O V 2
L
I/O V 3
L
I/O V 3
L
I/O V 4
L
I/O V 4
L
I/O V 5
L
I/O V 5
L
I/O V 6
L
I/O V
I/O V
I/O V
6
7
8
CC
CC
CC
I/O V 6
L
I/O V
I/O V
I/O V
I/O V
6
CC
7
CC
8
CC
9
CC
I/O V 7
L
I/O V 7
L
I/O V 8
L
I/O V 8
L
I/O V 9
L
I/O V 9
L
I/O V
9
CC
I/O V 10
L
I/O V 10
CC
I/O V 10
L
I/O V 10
CC
I/O V 11
L
I/O V 11
CC
I/O V 11
L
I/O V 11
CC
I/O V 12
L
I/O V 12
CC
I/O V 12
L
I/O V 12
CC
I/O V 13
L
I/O V 13
CC
I/O V 13
L
I/O V 13
CC
I/O V 14
L
I/O V 14
CC
I/O V 14
L
I/O V 14
CC
I/O V 15
L
I/O V 15
CC
I/O V 15
L
I/O V 15
CC
2/MAX3108E
I/O V 16
CC
I/O V 16
L
I/O V 16
CC
I/O V 16
L
GND
GND
12 ______________________________________________________________________________________
16-Channel Buffered CMOS
Logic-Level Translators
2/MAX3108E
Detailed Description
V
BATT
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
logic-level translators provide the level shifting neces-
sary to allow data transfer in a multivoltage system.
V
CC
SUPPLY
DISABLE
+1.2V TO +5.5V
Externally applied voltages, V
and V , set the logic
L
CC
V
CC
V
L
levels on either side of the device. Logic signals pre-
sent on the V side of the device appear as a higher
L
voltage logic signal on the V
side of the device, and
MAX13101E
CC
MAX13102E
MAX13103E
MAX13108E
vice-versa. The MAX13101E/MAX13102E/MAX13103E/
MAX13108E are bidirectional level translators allowing
R
DSON
< 50Ω
data translation in either direction (V ↔V ) on
L
CC
I/O V
1
I/O V 1
CC
L
any single data line. The MAX13101E/MAX13102E/
MAX13103E/MAX13108E accept V from +1.2V to V
.
CC
L
All devices have a V
range from +1.6ꢀV to +ꢀ.ꢀV,
CC
I/O V 16
I/O V 16
L
CC
ma5ing them ideal for data transfer between low-volt-
age ASꢂCs/PLꢁs and higher voltage systems.
GND
The MAX13101E/MAX13102E/MAX13103E feature an
output enable mode that reduces V
supply current to
CC
Figure ꢀ. Recommended Circuit for Powering ꢁown V
CC
less than 1µA, and V supply current to less than 2µA
L
when in shutdown. The MAX13108E features a multi-
plexing input that selects one byte between the two,
thus allowing multiplexing of the signals. The
MAX13101E/MAX13102E/MAX13103E/MAX13108E
the bidirectional nature, both input stages become
active during the one-shot pulse. This can lead to some
current feeding into the external source that is driving
the translator. However, this behavior helps to speed
up the transition on the driven side.
have 1ꢀ5V ESꢁ protection on the ꢂ/O V
side for
CC
greater protection in applications that route signals
externally. The MAX13101E/MAX13102E/MAX13103E/
MAX13108E operate at a guaranteed data rate of
20Mbps. The maximum data rate depends heavily
on the load capacitance (see the Typical Operating
Characteristics) and the output impedance of the
external driver.
For proper full-speed operation, the output current of a
device that drives the inputs of the MAX13101E/
MAX13102E/MAX13103E/MAX13108E should meet the
following requirement:
i > 108 x V x (C + 10pF)
where, i is the driver output current, V is the logic-supply
Power-Supply Sequencing
voltage (i.e., V or V ) and C is the parasitic capaci-
L
CC
tance of the signal line.
For proper operation, ensure that +1.6ꢀV ≤ V
≤ +ꢀ.ꢀV,
CC
+1.2V ≤ V ≤ +ꢀ.ꢀV, and V ≤ V . ꢁuring power-up
L
L
CC
Enable Output Mode (EN)
sequencing, V ≥ V
does not damage the device.
L
CC
The MAX13101E/MAX13102E/MAX13103E feature an
enable input (EN) that, when driven low, places the
device into shutdown mode. ꢁuring shutdown, the
When V
is disconnected and V is powering up, up to
CC
L
10mA of current can be sourced to each load on the V
L
side, yet the device does not latch up. To guarantee that
no excess lea5age current flows and that the device
MAX13101E ꢂ/O V _ ports are pulled down to ground
CC
with internal 65Ω resistors and the ꢂ/O V _ ports enter
L
does not interfere with the ꢂ/O on the V side, V
should
L
CC
tri-state. MAX13102E ꢂ/O V _ lines enter tri-state and
CC
be connected to GNꢁ with a max ꢀ0Ω resistor when the
supply is not present (Figure ꢀ).
the ꢂ/OV _ lines are pulled down to ground with internal
L
V
CC
65Ω resistors. All ꢂ/O V _ and ꢂ/O V _ lines on the
CC
L
MAX13103E enter tri-state while the device is in shut-
Input Driver Requirements
down mode. ꢁuring shutdown, the V
supply current
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
architecture is based on a one-shot accelerator output
stage (Figure 6). Accelerator output stages are always
in tri-state except when there is a transition on any of
CC
reduces to less than 1µA, and the V supply current
L
reduces to less than 2µA. To guarantee minimum shut-
down supply current, all ꢂ/O V _ need to be driven to
L
GNꢁ or V , or pulled to GNꢁ or V through 1005Ω
the translators on the input side, either ꢂ/O V _ or
L
ꢂ/O V _. Then a short pulse is generated, during
CC
which the accelerator output stages become active and
charge/discharge the capacitances at the ꢂ/Os. ꢁue to
L
L
resistors. All ꢂ/O V _ need to be driven to GNꢁ or
CC
V
CC,
or pulled to GNꢁ or V
ꢁrive EN to logic-high (V or V ) for normal operation.
through 1005Ω resistors.
CC
CC
L
______________________________________________________________________________________ 13
16-Channel Buffered CMOS
Logic-Level Translators
Multiplexing Input (MULT)
The MAX13108E features a multiplexing input (MULT)
that enables 8 of the 16 channels and places the
remaining 8 into tri-state. Figure 7 depicts a typical mul-
tiplexing configuration using the MAX13108E. ꢁrive
V
V
CC
L
RISE-TIME
ACCELERATOR
MULT high to enable ꢂ/O V 1 through ꢂ/O V 8 and
CC
CC
ꢂ/O V 1 through ꢂ/O V 8. ꢁriving MULT high sets
L
CC
L
I/O V
I/O V
L_
CC_
ꢂ/O V 9 through ꢂ/O V 16 and ꢂ/O V 9 through ꢂ/O
CC
L
V 16 into tri-state. ꢁrive MULT low to enable ꢂ/O V
9
L
CC
L
through ꢂ/O V 16 and ꢂ/O V 9 through ꢂ/O V 16.
CC
L
ꢁriving MULT low sets ꢂ/O V 1 through ꢂ/O V 8 and
CC
CC
FALL-TIME
ACCELERATOR
ꢂ/O V 1 through ꢂ/O V 8 into tri-state.
L
L
1ꢀ5k ESD Protection
As with all Maxim devices, ESꢁ-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
RISE-TIME
ACCELERATOR
The ꢂ/O V _ lines have extra protection against static
CC
discharge. Maxim’s engineers have developed state-of-
the-art structures to protect these pins against ESꢁ of
1ꢀ5V without damage. The ESꢁ structures withstand
high ESꢁ in all states: normal operation, tri-state output
mode, and powered down. After an ESꢁ event, Maxim’s
E versions 5eep wor5ing without latchup, whereas com-
peting products can latch and must be powered down
to remove the latchup condition.
FALL-TIME
ACCELERATOR
MAX13101E
MAX13102E
MAX13103E
MAX13108E
ESꢁ protection can be tested in various ways. The
ꢂ/O V _ lines of the MAX13101E/ MAX13102E/
CC
MAX13103E/MAX13108E are characterized for protec-
tion to 1ꢀ5V using the Human Body Model.
Figure 6. Simplified ꢁiagram (1 ꢂ/O Line)
MULT
I/O V 1
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
1
2
3
4
5
6
7
8
L
CC
CC
CC
CC
CC
CC
CC
CC
I/O V 2
L
I/O V 3
L
I/O V 4
L
PORT A
I/O V 5
L
I/O V 6
L
I/O V 7
L
I/O V 8
L
MAX13108E
I/O V 9
I/O V
9
L
CC
I/O V 10
I/O V 10
CC
L
I/O V 11
I/O V 11
CC
L
I/O V 12
I/O V 12
CC
L
PORT B
I/O V 13
I/O V 13
CC
L
2/MAX3108E
I/O V 14
I/O V 14
CC
L
I/O V 15
I/O V 15
CC
L
I/O V 16
I/O V 16
CC
L
Figure 7. MAX13108E Multiplexing Configuration
14 ______________________________________________________________________________________
16-Channel Buffered CMOS
Logic-Level Translators
2/MAX3108E
R 1MΩ
C
R 1500Ω
D
I
100%
90%
P
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR
RESISTANCE
AMPERES
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
36.8%
C
100pF
STORAGE
CAPACITOR
S
10%
0
SOURCE
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 8a. Human Body ESꢁ Test Model
Figure 8b. Human Body Model Current Waveform
ESD Test Conditions
ESꢁ performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
Applications Information
Power-Supply Decoupling
To reduce ripple and the chance of transmitting incor-
rect data, bypass V and V
to ground with 0.1µF
CC
L
Human Body Model
Figure 8a shows the Human Body Model and Figure 8b
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESꢁ voltage of inter-
est, which is then discharged into the test device
through a 1.ꢀ5Ω resistor.
capacitors. To ensure full 1ꢀ5V ESꢁ protection,
bypass V to ground with a 1µF ceramic capacitor.
Place all capacitors as close to the power-supply inputs
as possible.
CC
Capacitive Loading
Capacitive loading on the ꢂ/O lines impacts the rise time
(and fall time) of the MAX13101E/MAX13102E/
MAX13103E/MAX13108E when driving the signal lines.
The actual rise time is a function of the parasitic capaci-
tance, the supply voltage, and the drive impedance of
the MAX13101E/MAX13102E/MAX13103E/MAX13108E.
Machine Model
The Machine Model for ESꢁ tests all pins using a
200pF storage capacitor and zero discharge resis-
tance. ꢂts objective is to emulate the stress caused by
contact that occurs with handling and assembly during
manufacturing. All pins require this protection during
manufacturing, not just inputs and outputs. Therefore,
after PC board assembly, the Machine Model is less
relevant to ꢂ/O ports.
For proper operation, the signal must reach the V
required before the rise-time accelerators turn off.
as
OH
______________________________________________________________________________________ 15
16-Channel Buffered CMOS
Logic-Level Translators
Ordering Information/Selector Guide (continued)
DATA
I/O V STATE
I/O V
STATE
ꢄULTIPLEXER
FEATURE
L
CC
PART
PIN-PACKAGE
RATE (ꢄbps) DURING SꢁUTDOWN DURING SꢁUTDOWN
36 WLP**
3.06mm x 3.06mm
ꢄAX13102EEWX+
MAX13102EETL+
ꢄAX13103EEWX+
MAX13103EETL+
ꢄAX13108EEWX+
MAX13108EETL+
20
20
20
20
20
20
65Ω to GNꢁ
65Ω to GNꢁ
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
No
No
40 TQFN-EP***
ꢀmm x ꢀmm x 0.8mm
36 WLP**
3.06mm x 3.06mm
High impedance
High impedance
High impedance
High impedance
No
40 TQFN-EP***
ꢀmm x ꢀmm x 0.8mm
No
36 WLP**
3.06mm x 3.06mm
Yes
Yes
40 TQFN-EP***
ꢀmm x ꢀmm x 0.8mm
Note: All devices are specified over the -40°C to +8ꢀ°C operating temperature range.
+ꢁenotes a lead-free/RoHS-compliant pac5age.
**WLP bumps are in a 6 x 6 array.
***EP = Exposed pad.
Pin Configurations (continued)
TOP VIEW OF BOTTOM LEADS
30 29 28 27 26 25 24 23 22 21
I/O V 13
CC
I/O V
I/O V
I/O V
I/O V
4
3
2
1
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
CC
CC
CC
CC
I/O V 14
CC
I/O V 15
CC
I/O V 16
CC
V
V
CC
CC
MA131018E
V
L
V
L
I/O V 1
L
I/O V 16
L
I/O V 2
L
I/O V 15
L
*EP
I/O V 3
L
I/O V 14
L
+
I/O V 4
L
I/O V 13
L
11
1
2
3
4
5
6
7
8
9
10
2/MAX3108E
* EXPOSED PAD CONNECTED TO GROUND
TQFN
16 ______________________________________________________________________________________
16-Channel Buffered CMOS
Logic-Level Translators
2/MAX3108E
Pin Configurations (continued)
MAX13108E
MAX13101E/MAX13102E/MAX13103E
1
2
3
4
5
6
1
2
3
4
5
6
F
E
F
E
V
I/O V
I/O V
I/O V
3
4
5
I/O V
6
7
8
I/O V
9
I/O V 12 I/O V 15
V
I/O V
I/O V
I/O V
3
4
5
I/O V
6
7
8
I/O V
9
I/O V 12 I/O V 15
CC CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
I/O V
I/O V
1
2
I/O V
I/O V
I/O V 10 I/O V 13 I/O V 16
I/O V
I/O V
1
2
I/O V
I/O V
I/O V 10 I/O V 13 I/O V 16
CC CC CC
CC
CC
CC
CC
CC
CC
D
C
B
D
C
B
I/O V 11 I/O V 14
GND
I/O V 11 I/O V 14
GND
CC
CC
CC
CC
CC
I/O V 2
I/O V 5
I/O V 8
I/O V 11
I/O V 14
EN
I/O V 2
I/O V 5
I/O V 8
I/O V 11
I/O V 14
MULT
L
L
L
L
L
L
L
L
L
L
I/O V 1
L
I/O V 4
L
I/O V 7
L
I/O V 10
L
I/O V 13
L
I/O V 16
L
I/O V 1
L
I/O V 4
L
I/O V 7
L
I/O V 10
L
I/O V 13
L
I/O V 16
L
A
A
V
I/O V 3
L
I/O V 6
L
I/O V 9
L
I/O V 12
L
I/O V 15
L
V
I/O V 3
L
I/O V 6
L
I/O V 9
L
I/O V 12
L
I/O V 15
L
+
L
+
L
WLP
(BOTTOM VIEW)
WLP
(BOTTOM VIEW)
Typical Operating Circuit
Chip Information
PROCESS: BiCMOS
+1.8V
+3.3V
Pac5age Information
For the latest pac5age outline information and land patterns, go
to www.ꢂaxiꢂ-ic.coꢂ/pacꢀages.
V
L
V
CC
PACKAGE TYPE PACKAGE CODE DOCUꢄENT NO.
36 WLP
W363A3-1
T40ꢀꢀ-1
21-0024
21-0140
EN/(MULT)
40 TQFN-EP
MAX13101E
MAX13102E
MAX13103E
MAX13108E
+1.8V
SYSTEM
CONTROLLER
+3.3V
SYSTEM
DATA
I/O V
I/O V
DATA
L_
CC_
GND
( ) ARE FOR MAX13108E
______________________________________________________________________________________ 17
16-Channel Buffered CMOS
Logic-Level Translators
Revision History
REVISION
NUꢄꢃER
REVISION
DATE
PAGES
CꢁANGED
DESCRIPTION
Release of the MAX13101EETL+
Changed UCSP to WLP pac5aging
2
8/06
—
1, 2, 9, 10, 11, 16,
17, 18, 19
3
6/08
2/MAX3108E
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim ꢂntegrated Products
is a registered trademar5 of Maxim ꢂntegrated Products, ꢂnc.
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