MAX1305ECM+ [MAXIM]
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges; 8 /4 / 2通道， 12位，同时采样ADC ，提供± 10V ， ± 5V ， 0〜 + 5V模拟输入范围
| 型号： | MAX1305ECM+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges |
| 文件： | 总37页 (文件大小：374K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3052; Rev 4; 8/09
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
General Description
Features
o Up to Eight Channels of Simultaneous Sampling
The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–
MAX1314 12-bit, analog-to-digital converters (ADCs) offer
eight, four, or two independent input channels.
Independent track-and-hold (T/H) circuitry provides simul-
taneous sampling for each channel. The MAX1304/
MAX1305/MAX1306 provide a 0 to +5V input range with
6V fault-tolerant inputs. The MAX1308/MAX1309/
MAX1310 provide a 5V input range with 16.5V fault-tol-
erant inputs. The MAX1312/MAX1313/MAX1314 have a
10V input range with 16.5V fault-tolerant inputs. These
ADCs convert two channels in 0.9µs, and up to eight
channels in 1.98µs, with an 8-channel throughput of
456ksps per channel. Other features include a 20MHz T/H
input bandwidth, internal clock, internal (+2.5V) or external
(+2.0V to +3.0V) reference, and power-saving modes.
8ns Aperture Delay
100ps Channel-to-Channel T/H Match
o Extended Input Ranges
0 to +5V (MAX1304/MAX1305/MAX1306)
-5V to +5V (MAX1308/MAX1309/MAX1310)
-10V to +10V (MAX1312/MAX1313/MAX1314)
o Fast Conversion Time
One Channel in 0.72µs
Two Channels in 0.9µs
Four Channels in 1.26µs
Eight Channels in 1.98µs
o High Throughput
1075ksps/Channel for One Channel
901ksps/Channel for Two Channels
680ksps/Channel for Four Channels
456ksps/Channel for Eight Channels
A 20MHz, 12-bit, bidirectional parallel data bus pro-
vides the conversion results and accepts digital inputs
that activate each channel individually.
o
1 LSB INL, 0.9 LSB DNL (max)
o 84dBc SFDR, -86dBc THD, 71dB SINAD,
All devices operate from a +4.75V to +5.25V analog supply
and a +2.7V to +5.25V digital supply and consume 57mA
total supply current when fully operational.
f
IN
= 500kHz at 0.4dBFS
o 12-Bit, 20MHz, Parallel Interface
o Internal or External Clock
Each device is available in a 48-pin 7mm x 7mm TQFP
package and operates over the extended -40°C to
+85°C temperature range.
o +2.5V Internal Reference or +2.0V to +3.0V
External Reference
o +5V Analog Supply, +3V to +5V Digital Supply
Applications
55mA Analog Supply Current
1.3mA Digital Supply Current
SIN/COS Position Encoder
Multiphase Motor Control
Shutdown and Power-Saving Modes
o 48-Pin TQFP Package (7mm x 7mm Footprint)
Multiphase Power Monitoring
Power-Grid Synchronization
Power-Factor Monitoring
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
48 TQFP
48 TQFP
48 TQFP
48 TQFP
48 TQFP
48 TQFP
48 TQFP
48 TQFP
48 TQFP
48 TQFP
48 TQFP
48 TQFP
Vibration and Waveform Analysis
MAX1304ECM+
MAX1304ECM/V+
MAX1305ECM+
MAX1306ECM+
MAX1308ECM+
MAX1308ECM/V+
MAX1309ECM+
MAX1309ECM/V+
MAX1310ECM+
MAX1312ECM+
MAX1313ECM+
MAX1314ECM+
Selector Guide
PART
INPUT RANGE (V) CHANNEL COUNT
MAX1304ECM
MAX1305ECM
MAX1306ECM
MAX1308ECM
MAX1309ECM
MAX1310ECM
MAX1312ECM
MAX1313ECM
MAX1314ECM
0 to +5
8
4
2
8
4
2
8
4
2
0 to +5
0 to +5
5
5
5
10
10
10
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
ABSOLUTE MAXIMUM RATINGS
AV to AGND .........................................................-0.3V to +6V
REF , REF, MSV to AGND.....................-0.3V to (AV + 0.3V)
MS DD
DD
DV
to DGND.........................................................-0.3V to +6V
REF+, COM, REF- to AGND.....................-0.3V to (AV + 0.3V)
Maximum Current into Any Pin Except AV , DV , AGND,
DD DD
DGND ........................................................................... 50mA
DD
DD
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7, I.C. to AGND (MAX1304/MAX1305/MAX1306).... 6V
CH0–CH7, I.C. to AGND (MAX1308/MAX1309/MAX1310).. 16.5V
CH0–CH7, I.C. to AGND (MAX1312/MAX1313/MAX1314).. 16.5V
D0–D11 to DGND ....................................-0.3V to (DV + 0.3V)
EOC, EOLC, RD, WR, CS to DGND.........-0.3V to (DV + 0.3V)
Continuous Power Dissipation (T = +70°C)
A
TQFP (derate 22.7mW/°C above +70°C)................1818.2mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
DD
DD
DD
CONVST, CLK, SHDN, CHSHDN to DGND...-0.3V to (DV + 0.3V)
INTCLK/EXTCLK to AGND.......................-0.3V to (AV + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
REF-
REF+-to-REF-
COM
MSV
lar devices), f
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T = T
to T
,
MAX
CLK
A
MIN
unless otherwise noted. Typical values are at T = +25°C. See Figures 3 and 4.)
A
PARAMETER
STATIC PERFORMANCE (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
N
12
Bits
LSB
LSB
Integral Nonlinearity
INL
DNL
(Note 2)
0.5
0.3
3
1.0
0.9
16
16
20
20
Differential Nonlinearity
No missing codes (Note 2)
Unipolar, 0x000 to 0x001
Bipolar, 0xFFF to 0x000
Offset Error
LSB
LSB
3
Unipolar, between all channels
Bipolar, between all channels
Unipolar, 0x000 to 0x001
Bipolar, 0xFFF to 0x000
9
Offset-Error Matching
Offset-Error Temperature Drift
9
7
ppm/°C
7
Gain Error
2
16
14
LSB
LSB
Gain-Error Matching
Gain-Error Temperature Drift
Between all channels
3
4
ppm/°C
DYNAMIC PERFORMANCE at f = 500kHz, A = -0.4dBFS (Note 2)
IN
IN
Signal-to-Noise Ratio
SNR
SINAD
THD
68
68
71
71
-86
84
86
dB
dB
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Isolation
-80
dBc
dBc
dB
SFDR
80
ANALOG INPUTS (CH0 through CH7)
MAX1304/MAX1305/MAX1306
0
+5
+5
Input Voltage
V
V
MAX1308/MAX1309/MAX1310
MAX1312/MAX1313/MAX1314
-5
CH
-10
+10
680/2–MAX314
2
_______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
ELECTRICAL CHARACTERISTICS (continued)
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
REF-
REF+-to-REF-
COM
MSV
lar devices), f
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T = T
to T
,
MAX
CLK
A
MIN
unless otherwise noted. Typical values are at T = +25°C. See Figures 3 and 4.)
A
PARAMETER
SYMBOL
CONDITIONS
MAX1304/MAX1305/MAX1306
MAX1308/MAX1309MAX1310
MAX1312/MAX1313/MAX1314
MIN
TYP
7.58
8.66
14.26
0.54
-0.12
0.29
-0.87
0.56
-0.85
15
MAX
UNITS
Input Resistance
R
kΩ
CH
CH
(Note 3)
V
V
V
V
V
V
= +5V
= 0V
0.72
0.39
0.74
CH
CH
CH
CH
CH
CH
MAX1304/MAX1305/MAX1306
MAX1308/MAX1309/MAX1310
MAX1312/MAX1313/MAX1314
-0.157
-1.16
-1.13
= +5V
= -5V
Input Current
(Note 3)
I
mA
pF
= +10V
= -10V
Input Capacitance
C
CH
TRACK/HOLD
One channel selected for conversion
1075
901
680
456
983
821
618
413
20
Two channels selected for conversion
Four channels selected for conversion
Eight channels selected for conversion
One channel selected for conversion
Two channels selected for conversion
Four channels selected for conversion
Eight channels selected for conversion
External-Clock Throughput Rate
(Note 4)
f
TH
ksps
Internal-Clock Throughput Rate
(Note 4, Table 1)
f
ksps
TH
AD
Small-Signal Bandwidth
Full-Power Bandwidth
Aperture Delay
MHz
MHz
ns
20
t
8
Aperture-Delay Matching
Aperture Jitter
100
50
ps
t
ps
RMS
AJ
INTERNAL REFERENCE
REF Output Voltage
V
2.475
2.475
2.500
30
2.525
2.525
V
REF
Reference Output-Voltage
Temperature Drift
ppm/°C
REF
Output Voltage
V
2.500
3.850
2.600
1.350
V
V
V
V
MS
REFMS
REF+ Output Voltage
COM Output Voltage
REF- Output Voltage
V
REF+
V
COM
V
REF-
V
V
-
REF+
Differential Reference Voltage
2.500
V
-
REF
_______________________________________________________________________________________
3
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
ELECTRICAL CHARACTERISTICS (continued)
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
REF-
REF+-to-REF-
COM
MSV
lar devices), f
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T = T
to T
,
MAX
CLK
A
MIN
unless otherwise noted. Typical values are at T = +25°C. See Figures 3 and 4.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EXTERNAL REFERENCE (REF and REF
are externally driven)
MS
REF Input Voltage Range
REF Input Resistance
REF Input Capacitance
V
2.0
2.5
5
3.0
3.0
V
kΩ
pF
V
REF
R
(Note 5)
(Note 6)
REF
15
REF
REF
REF
Input Voltage Range
Input Resistance
V
2.0
2.5
MS
MS
MS
REFMS
R
5
kΩ
pF
V
REFMS
Input Capacitance
15
REF+ Output Voltage
COM Output Voltage
REF- Output Voltage
V
V
V
V
= +2.5V
= +2.5V
= +2.5V
3.850
2.600
1.350
REF+
REF
REF
REF
V
V
COM
V
V
REF-
V
V
-
REF+
Differential Reference Voltage
V
= +2.5V
2.500
V
REF
-
REF
DIGITAL INPUTS (D0–D7, RD, WR, CS, CLK, SHDN, CHSHDN, CONVST)
Input-Voltage High
Input-Voltage Low
Input Hysteresis
Input Capacitance
Input Current
V
0.7 x DV
V
V
IH
DD
V
0.3 x DV
DD
IL
20
15
mV
pF
µA
C
IN
I
V
= 0 or DV
0.02
1
IN
IN
DD
CLOCK-SELECT INPUT (INTCLK/EXTCLK)
Input-Voltage High
Input-Voltage Low
V
0.7 x AV
V
V
IH
DD
V
0.3 x AV
DD
IL
DIGITAL OUTPUTS (D0–D11, EOC, EOLC)
Output-Voltage High
V
I
I
= 0.8mA, Figure 1
DV - 0.6
DD
V
V
OH
SOURCE
Output-Voltage Low
V
= 1.6mA, Figure 1
SINK
0.4
1
OL
D0–D11 Tri-State Leakage Current
RD = high or CS = high
0.06
15
µA
D0–D11 Tri-State Output
Capacitance
RD = high or CS = high
pF
POWER SUPPLIES
Analog Supply Voltage
Digital Supply Voltage
AV
DV
4.75
2.70
5.25
5.25
V
V
DD
DD
MAX1304/MAX1305/MAX1306,
all channels selected
55
54
54
60
60
60
MAX1308/MAX1309/MAX1310,
all channels selected
Analog Supply Current
I
mA
AVDD
MAX1312/MAX1313/MAX1314,
all channels selected
680/2–MAX314
4
_______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
ELECTRICAL CHARACTERISTICS (continued)
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
REF-
REF+-to-REF-
COM
MSV
lar devices), f
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T = T
to T
,
MAX
CLK
A
MIN
unless otherwise noted. Typical values are at T = +25°C. See Figures 3 and 4.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1304/MAX1305/MAX1306,
all channels selected
1.3
2.6
2.6
2.6
Digital Supply Current
(C = 100pF) (Note 7)
MAX1308/MAX1309/MAX1310,
all channels selected
I
1.3
1.3
mA
DVDD
LOAD
MAX1312/MAX1313/MAX1314,
all channels selected
I
SHDN = DV , V
= float
0.6
0.02
50
10
1
AVDD
DD CH
Shutdown Current
(Note 8)
µA
dB
I
SHDN = DV , RD = WR = high
DD
DVDD
Power-Supply Rejection Ratio
PSRR
AV
= +4.75V to +5.25V
DD
TIMING CHARACTERISTICS (Figure 1)
Internal clock, Figure 7
External clock, Figure 8
Internal clock, Figure 7
External clock, Figure 8
800
12
900
225
ns
Time to First Conversion Result
Time to Subsequent Conversions
t
CONV
CLK
Cycles
200
3
ns
t
NEXT
CLK
Cycles
CONVST Pulse-Width Low
(Acquisition Time)
t
(Note 9) Figures 6–10
0.1
1000.0
µs
ACQ
CS Pulse Width
RD Pulse-Width Low
RD Pulse-Width High
WR Pulse-Width Low
CS to WR
t
Figure 6
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
CS
t
Figures 7, 8, 9
Figures 7, 8, 9
Figure 6
RDL
RDH
WRL
CTW
WTC
t
t
t
t
Figure 6
(Note 10)
(Note 10)
(Note 10)
(Note 10)
WR to CS
Figure 6
CS to RD
t
t
Figures 7, 8, 9
Figures 7, 8, 9
CTR
RTC
RD to CS
Data Access Time
(RD Low to Valid Data)
t
Figures 7, 8, 9
30
30
ns
ACC
Bus Relinquish Time (RD High)
CLK Rise to EOC Delay
t
Figures 7, 8, 9
Figure 8
5
ns
ns
ns
ns
ns
REQ
t
20
20
20
EOCD
CLK Rise to EOLC Fall Delay
t
Figure 8
EOLCD
CONVST Fall to EOLC Rise Delay
t
Figures 7, 8, 9
Internal clock, Figure 7
CVEOLCD
50
EOC Pulse Width
t
EOC
CLK
Cycle
External clock, Figure 8
1
_______________________________________________________________________________________
5
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
ELECTRICAL CHARACTERISTICS (continued)
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
REF-
REF+-to-REF-
COM
MSV
lar devices), f
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T = T
to T
,
MAX
CLK
A
MIN
unless otherwise noted. Typical values are at T = +25°C. See Figures 3 and 4.)
A
PARAMETER
Input-Data Setup Time
Input-Data Hold Time
External CLK Period
SYMBOL
CONDITIONS
MIN
10
TYP
MAX
UNITS
ns
t
t
Figure 6
DTW
WTD
Figure 6
10
ns
t
Figures 8, 9
0.05
10.00
µs
CLK
Logic sensitive to rising edges,
Figures 8, 9
External CLK High Period
External CLK Low Period
t
20
ns
ns
CLKH
Logic sensitive to rising edges,
Figures 8, 9
t
20
CLKL
External Clock Frequency
Internal Clock Frequency
CONVST High to CLK Edge
f
(Note 11)
0.1
20
MHz
MHz
ns
CLK
f
15
INT
t
Figures 8, 9
20
CNTC
Note 1: For the MAX1304/MAX1305/MAX1306, V = 0 to +5V. For the MAX1308/MAX1309/MAX1310, V = -5V to +5V. For the
IN
IN
MAX1312/MAX1313/MAX1314, V = -10V to +10V.
IN
Note 2: All channel performance is guaranteed by correlation to a single channel test.
Note 3: The analog input resistance is terminated to an internal bias point (Figure 5). Calculate the analog input current using:
V
− V
CH_
BIAS
I
=
CH_
R
CH_
for V
within the input voltage range.
CH
Note 4: Throughput rate is given per channel. Throughput rate is a function of clock frequency (f
). The external clock through-
CLK
put rate is specified with f
= 16.67MHz and the internal clock throughput rate is specified with f
= 15MHz. See the
CLK
CLK
Data Throughput section for more information.
Note 5: The REF input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF input current using:
VREF − 2.5V
IREF
for V
=
RREF
within the input voltage range.
REF
Note 6: The REF input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF input current using:
MS
MS
VREFMS − 2.5V
IREFMS
=
RREFMS
for V
within the input voltage range.
REFMS
Note 7: All analog inputs are driven with a -0.4dBFS 500kHz sine wave.
Note 8: Shutdown current is measured with the analog input floating. The large amplitude of the maximum shutdown current speci-
fication is due to automated test equipment limitations.
Note 9: CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor droop.
Note 10: CS to WR and CS to RD are internally AND together. Setup and hold times do not apply.
Note 11: Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CONVST
and the falling edge of EOLC to a maximum of 1ms.
680/2–MAX314
6
_______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
Typical Operating Characteristics
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
REF-
REF+-to-REF-
COM
MSV
devices), f
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), f = 500kHz, A = -0.4dBFS. T = +25°C,
CLK
IN IN A
unless otherwise noted.) (Figures 3 and 4)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
OFFSET ERROR
vs. TEMPERATURE
1.0
0.8
16
12
8
0.6
0.4
4
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-4
-8
-12
-16
4.7
4.8
4.9
5.0
AV (V)
5.1
5.2
5.3
-40
-15
10
35
60
85
°
DD
TEMPERATURE ( C)
GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
GAIN ERROR
vs. TEMPERATURE
1
0
16
12
8
-1
4
-2
-3
-4
-5
0
-4
-8
-12
-16
4.7
4.8
4.9
5.0
AV (V)
5.1
5.2
5.3
-40
-15
10
35
60
85
°
TEMPERATURE ( C)
DD
_______________________________________________________________________________________
7
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
Typical Operating Characteristics (continued)
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
REF-
REF+-to-REF-
COM
MSV
devices), f
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), f = 500kHz, A = -0.4dBFS. T = +25°C,
CLK
IN IN A
unless otherwise noted.) (Figures 3 and 4)
SMALL-SIGNAL BANDWIDTH
vs. ANALOG INPUT FREQUENCY
LARGE-SIGNAL BANDWIDTH
vs. ANALOG INPUT FREQUENCY
2
0
2
0
A
= -20dBFS
A = -0.5dBFS
IN
IN
-2
-2
-4
-4
-6
-6
-8
-8
-10
-12
-10
-12
0.1
1
10
100
0.1
1
10
100
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(2048-POINT DATA RECORD)
OUTPUT HISTOGRAM (DC INPUT)
6000
5000
4000
3000
2000
1000
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
5497
f
f
A
= 1.04167Msps
= 500kHz
TH
IN
= -0.05dBFS
IN
SNR = 70.7dB
SINAD = 70.6dB
THD = -87.5dBc
SFDR = 87.1dBc
1611
1084
0
0
2044
2045
2046
2047
2048
0
100
200
300
400
500
DIGITAL OUTPUT CODE
FREQUENCY (kHz)
680/2–MAX314
8
_______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
Typical Operating Characteristics (continued)
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
REF-
REF+-to-REF-
COM
MSV
devices), f
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), f = 500kHz, A = -0.4dBFS. T = +25°C,
CLK
IN IN A
unless otherwise noted.) (Figures 3 and 4)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. CLOCK FREQUENCY
SIGNAL-TO-NOISE RATIO
vs. CLOCK FREQUENCY
80
78
76
74
72
70
68
66
64
62
60
80
78
76
74
72
70
68
66
64
62
60
0
5
10
f
15
(MHz)
20
25
0
5
10
f
15
(MHz)
20
25
CLK
CLK
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK FREQUENCY
TOTAL HARMONIC DISTORTION
vs. CLOCK FREQUENCY
100
95
90
85
80
75
70
65
60
-60
-65
-70
-75
-80
-85
-90
-95
-100
0
5
10
15
(MHz)
20
25
0
5
10
15
(MHz)
20
25
f
f
CLK
CLK
_______________________________________________________________________________________
9
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
Typical Operating Characteristics (continued)
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
REF-
REF+-to-REF-
COM
MSV
devices), f
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), f = 500kHz, A = -0.4dBFS. T = +25°C,
CLK
IN IN A
unless otherwise noted.) (Figures 3 and 4)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. REFERENCE VOLTAGE
SIGNAL-TO-NOISE RATIO
vs. REFERENCE VOLTAGE
75
74
73
72
71
70
69
68
67
66
65
75
74
73
72
71
70
69
68
67
66
65
2.0
2.2
2.4
2.6
(V)
2.8
3.0
2.0
2.2
2.4
2.6
(V)
2.8
3.0
V
V
REF
REF
TOTAL HARMONIC DISTORTION
vs. REFERENCE VOLTAGE
SPURIOUS-FREE DYNAMIC RANGE
vs. REFERENCE VOLTAGE
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
-90
100
95
90
85
80
75
70
2.0
2.2
2.4
2.6
(V)
2.8
3.0
2.0
2.2
2.4
2.6
(V)
2.8
3.0
V
REF
V
REF
680/2–MAX314
10 ______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
Typical Operating Characteristics (continued)
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
REF-
REF+-to-REF-
COM
MSV
devices), f
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), f = 500kHz, A = -0.4dBFS. T = +25°C,
CLK
IN IN A
unless otherwise noted.) (Figures 3 and 4)
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
57
C
= 50pF
LOAD
T
= +85°C
A
T
T
= +85°C
A
A
56
55
54
53
52
51
T
= +25°C
A
= +25°C
= -40°C
T
= -40°C
A
T
A
2.5
3.0
3.5
4.0
DV (V)
4.5
5.0
5.5
4.7
4.8
4.9
5.0
5.1
5.2
5.3
DD
AV (V)
DD
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
DIGITAL SHUTDOWN CURRENT
vs. DIGITAL SUPPLY VOLTAGE
700
680
660
640
620
600
580
560
540
520
500
22
20
18
16
14
12
10
4.7
4.8
4.9
5.0
AV (V)
5.1
5.2
5.3
2.5
3.0
3.5
4.0
DV (V)
4.5
5.0
5.5
DD
DD
DIGITAL SUPPLY CURRENT
vs. NUMBER OF CHANNELS SELECTED
ANALOG SUPPLY CURRENT
vs. NUMBER OF CHANNELS SELECTED
1.0
60
55
50
45
40
35
30
CHSHDN = 0
CHSHDN = 0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
NUMBER OF CHANNELS SELECTED
NUMBER OF CHANNELS SELECTED
______________________________________________________________________________________ 11
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
Typical Operating Characteristics (continued)
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
REF-
REF+-to-REF-
COM
MSV
devices), f
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), f = 500kHz, A = -0.4dBFS. T = +25°C,
CLK
IN IN A
unless otherwise noted.) (Figures 3 and 4)
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.5004
2.5003
2.5002
2.5001
2.5000
2.4999
2.4998
2.4997
2.4996
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
4.7
4.8
4.9
5.0
5.1
5.2
5.3
-40
-15
10
35
60
85
AV (V)
DD
TEMPERATURE (°C)
INTERNAL CLOCK CONVERSION TIME
vs. ANALOG SUPPLY VOLTAGE
INTERNAL CLOCK CONVERSION TIME
vs. TEMPERATURE
900
800
700
600
500
400
300
200
100
0
820
800
780
t
CONV
t
CONV
t
NEXT
t
NEXT
200
180
160
4.7
4.8
4.9
5.0
AV (V)
5.1
5.2
5.3
-40
-15
10
35
60
85
DD
TEMPERATURE (°C)
ANALOG INPUT CHANNEL CURRENT
vs. ANALOG INPUT CHANNEL VOLTAGE
ANALOG INPUT CHANNEL CURRENT
vs. ANALOG INPUT CHANNEL VOLTAGE
ANALOG INPUT CHANNEL CURRENT
vs. ANALOG INPUT CHANNEL VOLTAGE
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
3.0
MAX1304/MAX1305/MAX1306
MAX1308/MAX1309/MAX1310
MAX1312/MAX1313/MAX1314
2.5
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
-6
-4
-2
0
2
4
6
-20 -15 -10 -5
0
5
10 15 20
-20 -15 -10 -5
0
5
10 15 20
680/2–MAX314
V
(V)
CH_
V
(V)
V
(V)
CH_
CH_
12 ______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
Pin Description
PIN
MAX1304
MAX1308
MAX1312
MAX1305
MAX1309
MAX1313
MAX1306
MAX1310
MAX1314
NAME
FUNCTION
Analog Power Input. AV
is the power input for the analog section of the
DD
converter. Apply +5V to AV . Connect all AV
pins together. See the Layout,
DD
1, 15, 17
1, 15, 17
1, 15, 17
AV
DD
DD
Grounding, and Bypassing section for additional information.
2, 3, 14,
16, 23
2, 3, 14,
16, 23
2, 3, 14,
16, 23
Analog Ground. AGND is the power return for AV . Connect all AGND
DD
pins together.
AGND
4
5
4
5
4
5
CH0
CH1
Channel 0 Analog Input
Channel 1 Analog Input
Midscale Voltage Bypass. For the unipolar MAX1304/MAX1305/MAX1306,
connect a 2.2µF and a 0.1µF capacitor from MSV to AGND. For the bipolar
MAX1308/MAX1309/MAX1310/MAX1312/MAX1313/MAX1314, connect
MSV to AGND.
6
6
6
MSV
7
8
7
—
—
—
—
—
—
CH2
CH3
CH4
CH5
CH6
CH7
Channel 2 Analog Input
Channel 3 Analog Input
Channel 4 Analog Input
Channel 5 Analog Input
Channel 6 Analog Input
Channel 7 Analog Input
8
9
—
—
—
—
10
11
12
Clock-Mode Select Input. Connect INTCLK/EXTCLK to AV
internal clock. Connect INTCLK/EXTCLK to AGND to use an external clock
connected to CLK.
to select the
DD
INTCLK/
EXTCLK
13
18
13
13
Midscale Reference Bypass or Input. REF
the internal +2.5V bandgap reference buffer.
For the MAX1304/MAX1305/MAX1306 unipolar devices, V
the unity-gain buffer that drives MSV. MSV sets the midpoint of the input voltage
range. For internal reference operation, bypass REF with a ≥0.01µF
capacitor to AGND. For external reference operation, drive REF
connects through a 5kΩ resistor to
MS
is the input to
REFMS
MS
18
18
REF
with an
MS
MS
external voltage from +2V to +3V.
For the MAX1308/MAX1309/MAX1310/MAX1312/MAX1313/MAX1314 bipolar
devices, connect REF to REF. For internal reference operation, bypass the
MS
REF /REF node with a ≥0.01µF capacitor to AGND. For external reference
MS
operation, drive the REF /REF node with an external voltage from +2V to +3V.
MS
ADC Reference Bypass or Input. REF connects through a 5kΩ resistor to the
internal +2.5V bandgap reference buffer.
For internal reference operation, bypass REF with a ≥0.01µF capacitor.
For external reference operation with the MAX1304/MAX1305/MAX1306
unipolar devices, drive REF with an external voltage from +2V to +3V.
For external reference operation with the MAX1308/MAX1309/MAX1310/
19
19
19
REF
MAX1312/MAX1313/MAX1314 bipolar devices, connect REF
to REF and
MS
drive the REF /REF node with an external voltage from +2V to +3V.
MS
______________________________________________________________________________________ 13
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
Pin Description (continued)
PIN
MAX1304
MAX1308
MAX1312
MAX1305
MAX1309
MAX1313
MAX1306
MAX1310
MAX1314
NAME
FUNCTION
Positive Reference Bypass. Bypass REF+ with a 0.1µF capacitor to AGND. Also
bypass REF+ to REF- with a 2.2µF and a 0.1µF capacitor.
20
21
20
21
20
21
REF+
COM
REF-
V
= V
+ V
/ 2.
REF
REF+
COM
Reference Common Bypass. Bypass COM to AGND with a 2.2µF and a 0.1µF
capacitor. V = 13 / 25 x AV
.
DD
COM
Negative Reference Bypass. Bypass REF- with a 0.1µF capacitor to AGND.
Also bypass REF- to REF+ with a 2.2µF and a 0.1µF capacitor.
22
22
22
V
= V
- V
/ 2.
REF+
COM
REF
Digital Ground. DGND is the power return for DV . Connect all DGND
DD
pins together.
24, 39
25, 38
24, 39
25, 38
24, 39
25, 38
DGND
Digital Power Input. DV
powers the digital section of the converter, including
DD
DV
the parallel interface. Apply +2.7V to +5.25V to DV . Bypass DV
to DGND
DD
DD
DD
with a 0.1µF capacitor. Connect all DV
pins together.
DD
26
27
28
29
30
31
32
33
26
27
28
29
30
31
32
33
26
27
28
29
30
31
32
33
D0
Digital I/O 0 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital I/O 1 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital I/O 2 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital I/O 3 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital I/O 4 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital I/O 5 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital I/O 6 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital I/O 7 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
D1
D2
D3
D4
D5
D6
D7
Digital Output 8 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or
CS = 1.
34
35
36
37
40
34
35
36
37
40
34
35
36
37
40
D8
D9
Digital Output 9 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or
CS = 1.
Digital Output 10 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or
CS = 1.
D10
D11
EOC
Digital Output 11 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or
CS = 1.
End-of-Conversion Output. EOC goes low to indicate the end of a conversion. It
returns high on the next rising CLK edge or the falling CONVST edge.
End-of-Last-Conversion Output. EOLC goes low to indicate the end of the
41
41
41
EOLC last conversion. It returns high when CONVST goes low for the next
conversion sequence.
42
43
42
43
42
43
RD
Read Input. Pulling RD low initiates a read command of the parallel data bus.
Write Input. Pulling WR low initiates a write command for configuring the device
with D0–D7.
WR
680/2–MAX314
14 ______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
Pin Description (continued)
PIN
MAX1304
MAX1308
MAX1312
MAX1305
MAX1309
MAX1313
MAX1306
MAX1310
MAX1314
NAME
FUNCTION
Chip-Select Input. Pulling CS low activates the digital interface. Forcing CS high
places D0–D11 in high-impedance mode.
44
45
44
45
44
45
CS
Conversion Start Input. Driving CONVST high initiates the conversion process.
The analog inputs are sampled on the rising edge of CONVST.
CONVST
External Clock Input. For external clock operation, connect INTCLK/EXTCLK to
DGND and drive CLK with an external clock signal from 100kHz to 20MHz. For
46
47
46
47
46
47
CLK
internal clock operation, connect INTCLK/EXTCLK to DV
and connect CLK to
DD
DGND.
Shutdown Input. Driving SHDN high initiates device shutdown. Connect SHDN
to DGND for normal operation.
SHDN
Active-Low Analog-Input Channel-Shutdown Input. Drive CHSHDN low to
power down analog inputs that are not selected for conversion in the
configuration register. Drive CHSHDN high to power up all analog input
channels regardless of whether they are selected for conversion in the
configuration register. See the Channel Shutdown (CHSHDN) section for more
information.
48
—
48
48
CHSHDN
9, 10,
11, 12
7, 8, 9,
10, 11, 12
I.C.
Internally connected. Connect I.C. to AGND.
Detailed Description
The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–
MAX1314 are 12-bit ADCs. The devices offer 8, 4, or 2
independently selectable input channels, each with
dedicated T/H circuitry. Simultaneous sampling of all
active channels preserves relative phase information
making these devices ideal for motor control and power
monitoring. Three input ranges are available, 0 to +5V,
5V and 10V. The 0 to +5V devices provide 6V fault-
tolerant inputs. The 5V and 10V devices provide
V
DD
I
OL
= 1.6mA
1.6V
DEVICE PIN
16.5V fault-tolerant inputs. Two-channel conversion
results are available in 0.9µs. Conversion results from
all eight channels are available in 1.98µs. The 8-chan-
nel throughput is 456ksps per channel. Internal or
external reference and clock capability offer great flexi-
bility, and ease of use. A write-only configuration regis-
ter can mask out unused channels and a shutdown
feature reduces power. A 20MHz, 12-bit, parallel data
bus outputs the conversion results. Figure 2 shows the
functional diagram of these ADCs.
100pF
I
= 0.8mA
OH
Figure 1. Digital Load Test Circuit
______________________________________________________________________________________ 15
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
DV
DD
AV
DD
D11
D8
CH0
T/H
T/H
8 x 12
SRAM
OUTPUT
DRIVERS
12-BIT
ADC
8 x 1
MUX
D7
CH7
D0
MSV
CONFIGURATION
REGISTER
WR
*
CS
REF+
COM
REF-
RD
INTERFACE
AND
CONTROL
CONVST
SHDN
5kΩ
5kΩ
INTCLK/EXTCLK
REF
CLK
CHSHDN
REF
MS
EOC
2.500V
EOLC
DGND
AGND
*SWITCH CLOSED ON UNIPOLAR DEVICES, OPEN ON BIPOLAR DEVICES
Figure 2. Functional Diagram
680/2–MAX314
16 ______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
25, 38
+5V
+2.7V TO +5.25V
DV
DD
0.1µF
0.1µF
0.1µF
1
15
17
0.1µF
AV
AV
AV
DD
DD
DD
24, 39
48
DGND
GND
CHSHDN
SHDN
CLK
47
46
45
44
43
42
41
40
6
18
19
MSV
BIPOLAR
CONFIGURATION
0.01µF
REF
REF
MS
CONVST
CS
DIGITAL
INTERFACE
AND
MAX1308
MAX1312
CONTROL
WR
0.1µF
20
REF+
REF-
RD
0.1µF
2.2µF
EOLC
EOC
22
0.1µF
2.2µF
0.1µF
37
36
35
34
33
32
31
30
29
28
27
26
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
21
COM
2, 3, 14, 16, 23
GND
AGND
12
11
10
9
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
PARALLEL
DIGITAL
OUTPUT
BIPOLAR
ANALOG
INPUTS
8
7
5
4
13
INTCLK/EXTCLK
Figure 3. Typical Bipolar Operating Circuit
______________________________________________________________________________________ 17
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
+5V
0.1µF
25, 38
1
15
17
+2.7V TO +5.25V
DV
DD
AV
AV
AV
DD
DD
DD
0.1µF
0.1µF
0.1µF
24, 39
48
DGND
GND
2.2µF
0.1µF
CHSHDN
SHDN
CLK
6
MSV
REF
47
46
45
44
43
42
41
40
0.01µF
0.01µF
UNIPOLAR
CONFIGURATION
18
19
CONVST
CS
MS
DIGITAL
INTERFACE
AND
MAX1304
REF
CONTROL
WR
0.1µF
RD
20
REF+
REF-
EOLC
EOC
0.1µF
2.2µF
22
0.1µF
37
36
35
34
33
32
31
30
29
28
27
26
2.2µF
0.1µF
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
21
COM
2, 3, 14, 16, 23
GND
AGND
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
12
11
10
9
PARALLEL
DIGITAL
OUTPUT
UNIPOLAR
ANALOG
INPUTS
8
7
5
4
13
INTCLK/EXTCLK
Figure 4. Typical Unipolar Operating Circuit
680/2–MAX314
18 ______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
acquisition time must be limited to 1ms. Accuracy with
conversion times longer than 1ms cannot be guaran-
teed due to capacitor droop in the input circuitry.
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
Due to the analog input resistive divider formed by R1
and R2 in Figure 5, any significant analog input source
AV
resistance (R
more, R
) results in gain error. Further-
DD
SOURCE
C
HOLD
causes distortion due to nonlinear
OVERVOLTAGE
PROTECTION
CLAMP
SOURCE
analog input currents. Limit R
of 100Ω.
to a maximum
SOURCE
2.5pF
*R
SOURCE
R1
CH_
Selecting an Input Buffer
To improve the input signal bandwidth under AC condi-
tions, drive the input with a wideband buffer (>50MHz)
that can drive the ADC’s input capacitance (15pF) and
settle quickly. For example, the MAX4431 or the
MAX4265 can be used for the 0 to +5V unipolar devices,
or the MAX4350 can be used for 5V bipolar inputs.
C
SAMPLE
ANALOG
SIGNAL
SOURCE
UNDERVOLTAGE
PROTECTION
CLAMP
R2
V
BIAS
*MINIMIZE R
TO AVOID GAIN ERROR AND DISTORTION.
SOURCE
Most applications require an input buffer to achieve 12-bit
accuracy. Although slew rate and bandwidth are impor-
tant, the most critical input buffer specification is settling
time. The simultaneous sampling of multiple channels
requires an acquisition time of 100ns. At the beginning of
the acquisition, the ADC internal sampling capacitor array
connects to the analog inputs, causing some distur-
bance. Ensure the amplifier is capable of settling to at
least 12-bit accuracy during this interval. Use a low-noise,
low-distortion, wideband amplifier that settles quickly and
is stable with the ADC’s 15pF input capacitance.
PART INPUT RANGE (V) R1 (kΩ) R2 (kΩ)
V
(V)
BIAS
MAX1304
MAX1305
MAX1306
0 TO +5
3.33
6.67
5.00
2.86
2.35
0.90
2.50
2.06
MAX1308
MAX1309
MAX1310
5
MAX1312
MAX1313
MAX1314
10
13.33
R1 | | R2 = 2kΩ
See the Maxim website at www.maxim-ic.com for appli-
cation notes on how to choose the optimum buffer
amplifier for your ADC application.
Figure 5. Single-Channel, Equivalent Analog Input T/H Circuit
Analog Inputs
Input Bandwidth
The input-tracking circuitry has a 20MHz small-signal
bandwidth, making it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Track and Hold (T/H)
To preserve phase information across the multichannel
MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–
MAX1314, all input channels have dedicated T/H ampli-
fiers. Figure 5 shows the equivalent analog input T/H
circuit for one channel.
The input T/H circuit is controlled by the CONVST input.
When CONVST is low, the T/H circuit tracks the analog
input. When CONVST is high the T/H circuit holds the
analog input. The rising edge of CONVST is the analog
Input Range and Protection
The MAX1304/MAX1305/MAX1306 provide a 0 to +5V
input voltage range with fault protection of 6V. The
MAX1308/MAX1309/MAX1310 provide a 5V input volt-
age range with fault protection of 16.5V. The
MAX1312/MAX1313/MAX1314 provide a 10V input
voltage range with fault protection of 16.5V. Figure 5
shows the single-channel equivalent input circuit.
input sampling instant. There is an aperture delay (t
)
AD
of 8ns and a 50ps
aperture jitter (t ). The aperture
RMS
AJ
delay of each dedicated T/H input is matched within
100ps of each other.
To settle the charge on C
to 12-bit accuracy,
SAMPLE
use a minimum acquisition time (t
) of 100ns.
ACQ
Therefore, CONVST must be low for at least 100ns.
Although longer acquisition times allow the analog input
to settle to its final value more accurately, the maximum
______________________________________________________________________________________ 19
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
Data Throughput
Clock Modes
The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–
MAX1314 provide a 15MHz internal conversion clock.
Alternatively, an external clock can be used.
The data throughput (f ) of the MAX1304–MAX1306/
TH
MAX1308–MAX1310/MAX1312–MAX1314 is a function
of the clock speed (f
). In internal clock mode, f
=
CLK
CLK
15MHz (typ). In external clock mode, 100kHz ≤ f
≤
CLK
Internal Clock
Internal clock mode frees the microprocessor from the
burden of running the ADC conversion clock. For inter-
20MHz. When reading during conversion (Figures 7 and
8), calculate f as follows:
TH
1
nal clock operation, connect INTCLK/EXTCLK to AV
DD
fTH
=
12 + 3 x (N−1) + 1
and connect CLK to DGND. Note that INTCLK/EXTCLK
is referenced to AV , not DV
tACQ + tQUIET
+
.
DD
fCLK
DD
where N is the number of active channels and t
is
External Clock
QUIET
the period of bus inactivity before the rising edge of
CONVST. See the Starting a Conversion section for
more information.
For external clock operation, connect INTCLK/EXTCLK
to AGND and connect an external clock source to CLK.
Note that INTCLK/EXTCLK is referenced to AV , not
DD
DV . The external clock frequency can be up to
DD
Table 1 uses the above equation and shows the total
throughput as a function of the number of channels
selected for conversion.
20MHz. Linearity is not guaranteed with clock frequen-
cies below 100kHz due to droop in the T/H circuits.
Table 1. Throughput vs. Channels Sampled: f
= 15MHz, t
= 100ns, t
= 50ns
CLK
ACQ
QUIET
CHANNELS
SAMPLED
(N)
CLOCK CYCLES
UNTIL
CLOCK CYCLE
FOR READING
TOTAL
TOTAL
THROUGHPUT
PER CHANNEL
CONVERSION
TIME (ns)
THROUGHPUT
(ksps)
LAST RESULT
LAST CONVERSION
(f
TH
)
1
2
3
4
5
6
7
8
12
15
18
21
24
27
30
33
1
1
1
1
1
1
1
1
800
983
983
821
705
618
550
495
451
413
1000
1200
1400
1600
1800
2000
2200
1643
2117
2474
2752
2975
3157
3310
680/2–MAX314
20 ______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
However, the new configuration does not take effect
until the next CONVST falling edge. At power-up all
Applications Information
Digital Interface
The bidirectional parallel digital interface allows for setting
the 8-bit configuration register (see the Configuration
Register section) and reading the 12-bit conversion
result. The interface includes the following control signals:
chip select (CS), read (RD), write (WR), end of conversion
(EOC), end of last conversion (EOLC), conversion start
(CONVST), shutdown (SHDN), channel shutdown
(CHSHDN), internal clock select (INTCLK/EXTCLK), and
external clock input (CLK). Figures 6, 7, 8, 9, Table 2, and
the Timing Characteristics show the operation of the inter-
face. D0–D7 are bidirectional, and D8–D11 are output
only. D0–D11 go high impedance when RD = 1 or CS = 1.
channels default active. Shutdown does not change the
configuration register. The configuration register may
be written to in shutdown. See the Channel Shutdown
(CHSHDN) section for information about using the con-
figuration register for power saving.
CONVST
CONFIGURATION
REGISTER UPDATES
RD
t
CS
Configuration Register
Enable channels as active by writing to the configura-
tion register through I/O lines D0–D7 (Table 2). The bits
in the configuration register map directly to the chan-
nels, with D0 controlling channel zero, and D7 control-
ling channel seven. Setting any bit high activates the
corresponding input channel, while resetting any bit
low deactivates the corresponding channel. On the
devices with less than eight channels, some of the bits
have no function (Table 2).
CS
t
WRL
t
t
WTC
CTW
WR
t
DTW
D0–D7
To write to the configuration register, pull CS and WR
low, load bits D0 through D7 onto the parallel bus, and
force WR high. The data are latched on the rising edge
of WR (Figure 6). Write to the configuration register at
any point during the conversion sequence. At power-
up, write to the configuration register to select the
active channels before beginning a conversion.
DATA-IN
t
WTD
Figure 6. Write Timing
Table 2. Configuration Register
BIT/CHANNEL
PART
STATE
NUMBER
D0/CH0
D1/CH1
D2/CH2
D3/CH3
D4/CH4
D5/CH5
D6/CH6
D7/CH7
MAX1304
MAX1308
MAX1312
MAX1305
MAX1309
MAX1313
MAX1306
MAX1310
MAX1314
ON
OFF
ON
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
1
0
1
0
X
X
1
0
X
X
X
X
1
0
X
X
X
X
1
0
X
X
X
X
1
0
X
X
X
X
OFF
ON
OFF
X = Don’t care (must be 1 or 0).
______________________________________________________________________________________ 21
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
SAMPLE
INSTANT
t
ACQ
CONVST
HOLD
TRACK
TRACK
t
t
CONV
NEXT
EOC
t
EOC
t
CVEOLCD
EOLC
t
≥ 50ns
QUIET
CS*
t
t
t
CTR
RDH
RTC
RD
t
t
RDL
ACC
CH0
CH1
D0–D11
t
REQ
*CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD.
Figure 7. Read During Conversion—Channel 0 and Channel 1 Selected, Internal Clock
the first CLK pulse must occur within 10µs from the
rising edge of CONVST. Additionally, the external clock
frequency must be greater than 100kHz to avoid T/H
droop-degrading accuracy. The first conversion result
is available for read when EOC goes low on the rising
edge of the 13th clock cycle. Subsequent conversion
results are available after every third clock cycle there-
after (Figures 8 and 9).
Starting a Conversion
To start a conversion using internal clock mode, pull
CONVST low for the acquisition time (t
). The T/H
ACQ
acquires the signal while CONVST is low, and conver-
sion begins on the rising edge of CONVST. The end-of-
conversion signal (EOC) pulses low whenever a
conversion result becomes available for read. The end-
of-last-conversion signal (EOLC) goes low when the last
conversion result is available (Figure 7).
In both internal and external clock modes, hold
CONVST high until the last conversion result is read. If
CONVST goes low in the middle of a conversion, the
current conversion is aborted and a new conversion is
initiated. Furthermore, there must be a period of bus
To start a conversion using external clock mode, pull
CONVST low for the acquisition time (t
). The T/H
ACQ
acquires the signal while CONVST is low. The rising
edge of CONVST is the sampling instant. Apply an
external clock to CLK to start the conversion. To avoid
T/H droop degrading the sampled analog input signals,
inactivity (t
) for 50ns or longer before the falling
QUIET
edge of CONVST for the specified ADC performance.
680/2–MAX314
22 ______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
SAMPLE
INSTANT
t
ACQ
HOLD
13
CONVST
CLK
TRACK
TRACK
t
t
t
CLKL
CLK
CLKH
t
CNTC
1
2
3
12
14
15
16
17
18
19
1
t
t
EOCD
t
NEXT
EOCD
EOC
t
t
CONV
EOC
t
t
CVEOLCD
EOLCD
EOLC
CS*
t
≥ 50ns
QUIET
t
t
t
RTC
CTR
RDH
RD
t
t
RDL
ACC
CH3
CH7
D0–D11
t
REQ
*CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD.
Figure 8. Read During Conversion—Channel 3 and Channel 7 Selected, External Clock
high to release the digital bus. In internal clock mode,
the next EOC falling edge occurs within 225ns. In exter-
nal clock mode, the next EOC falling edge occurs in
three CLK cycles. When the last result is available
EOLC goes low.
Reading a Conversion Result
Reading During a Conversion
Figures 7 and 8 show the interface signals to initiate a
read operation during a conversion cycle. These figures
show two channels selected for conversion. If more
channels are selected, the results are available succes-
sively at every EOC falling edge. CS can be low at all
times, low during the RD cycles, or the same as RD.
Reading After Conversion
Figure 9 shows the interface signals for a read operation
after a conversion with all eight channels enabled. At
the falling of EOLC, driving CS and RD low places the
first conversion result onto the parallel bus. Successive
low pulses of RD place the successive conversion
results onto the bus. When the last conversion results in
the sequence are read, additional read pulses wrap the
pointer back to the first converted result.
After initiating a conversion by bringing CONVST high,
wait for EOC to go low. In internal clock mode, EOC
goes low within 900ns. In external clock mode, EOC
goes low on the rising edge of the 13th CLK cycle. To
read the conversion result, drive CS and RD low to
latch data to the parallel digital output bus. Bring RD
______________________________________________________________________________________ 23
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
CONVST
EOC
ONLY LAST PULSE SHOWN
t
CVEOLCD
t
EOC
EOLC
CS*
t
RTC
t
CTR
t
t
RDH
t
= 50ns
RDL
QUIET1
RD
D0–D11
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
t
t
REQ
ACC
* CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD.
Figure 9. Read After Conversion—Eight Channels Selected, External Clock
Exiting shutdown (falling edge of SHDN) starts a con-
version in the same way as the rising edge of CONVST.
After coming out of shutdown, initiate a dummy conver-
sion and discard the results. After the dummy conver-
sion, allow the 1ms wake-up time to expire before
initiating the first accurate conversion.
Power-Up Reset
At power-up, all channels are selected for conversion
(see the Configuration Register section). After applying
power, allow the 1ms wake-up time to elapse and then
initiate a dummy conversion and discard the results.
After the dummy conversion is complete, accurate con-
versions can be obtained.
Channel Shutdown (CHSHDN)
The channel-shutdown feature allows analog input
channels to be powered down when they are not
selected for conversion. Powering down channels that
are not selected for conversion reduces the analog
supply current by 2.9mA per channel. To power down
channels that are not selected for conversion, pull
CHSHDN low. See the Configuration Register section
for information on selecting and deselecting channels
for conversion.
Power-Saving Modes
Shutdown Mode
During shutdown the internal reference and analog
circuits in the device shutdown and the analog supply
current drops to 0.6µA (typ). Select shutdown mode
using the SHDN input. Set SHDN high to enter shut-
down mode. SHDN takes precedence over CHSHDN.
Entering and exiting shutdown mode does not change
the configuration byte. However, a new configuration
byte can be written while in shutdown mode by follow-
ing the standard write procedure shown in Figure 6.
The drawback of powering down analog inputs that are
not selected for conversion is that it takes time to power
them up. Figure 10 shows how a dummy conversion is
used to power up an analog input in external clock
mode. After selecting a new channel in the configura-
tion register, initiate a dummy conversion and discard
the results. After the dummy conversion, allow the 1ms
EOC and EOLC are high when the MAX1304–MAX1306/
MAX1308–MAX1310/MAX1312–MAX1314 are shut down.
The state of the digital outputs D0–D11 is independent
of the state of SHDN. If CS and RD are low, the digital
outputs D0–D11 are active regardless of SHDN. The
digital outputs only go high impedance when CS or RD
is high. When the digital outputs are powered down, the
digital supply current drops to 20nA.
wake-up time (t
) to expire before initiating the first
WAKE
accurate conversion.
680/2–MAX314
24 ______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
CS*
t
t
ACQ
ACQ
CONVST
WR
CONFIGURATION
REGISTER
DUMMY
CONVERSION
START
FIRST ACCURATE
CONVERSION
START
UPDATES
CONFIGURATION REGISTER
POWERS UP ONE OR
MORE CHANNELS
DATA
IN
D0–D7
t
≥ 1ms
WAKE
1
2
3
4
5
12
13
1
CLK
EOC
EOLC
*CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD.
Figure 10. Powering Up an Analog Input Channel with a Dummy Conversion and Wake-Up Time (CHSHDN = 0, External-Clock
Mode, One Channel Selected)
CS*
t
t
ACQ
ACQ
CONVST
WR
CONFIGURATION
REGISTER
FIRST ACCURATE
CONVERSION START
SECOND ACCURATE
CONVERSION START
UPDATES
CONFIGURATION REGISTER
POWERS UP ONE OR
MORE CHANNELS
DATA
IN
D0–D7
1
2
3
4
5
12
13
1
CLK
EOC
EOLC
*CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD.
Figure 11. Powering Up an Analog Input Channel Directly (CHSHDN = 1, External-Clock Mode, One Channel Selected)
______________________________________________________________________________________ 25
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
To avoid the timing requirements associated with pow-
ering up an analog channel, force CHSHDN high. With
CHSHDN high, each analog input is powered up
regardless of whether it is selected for conversion in
the configuration register. Note that shutdown mode
takes precedence over the CHSHDN mode.
erence voltage by driving REF with a +2.0V to +3.0V
external reference. As shown in Figure 2, the REF input
impedance is 5kΩ. For more information about using
external references see the Transfer Functions section.
Midscale ꢀoltage (MSꢀ)
The voltage at MSV (V
) sets the midpoint of the ADC
MSV
Reference
transfer functions. For the 0 to +5V input range (unipolar
devices), the midpoint of the transfer function is +2.5V.
For the 5V and 10V input range devices, the midpoint
of the transfer function is zero.
Internal Reference
The internal reference circuits provide for analog input
voltages of 0 to +5V for the unipolar MAX1304/
MAX1305/MAX1306, 5V for the bipolar MAX1308/
MAX1309/MAX1310 or 10V for the bipolar MAX1312/
MAX1313/MAX1314. Install external capacitors for ref-
erence stability, as indicated in Table 3 and shown in
Figures 3 and 4.
As shown in Figure 2, there is a unity-gain buffer
between REF
and MSV in the unipolar MAX1304/
MS
MAX1305/MAX1306. This midscale buffer sets the mid-
point of the unipolar transfer functions to either the inter-
nal +2.5V reference or an externally applied voltage at
REF . V
follows V
within 3mV.
MS MSV
REFMS
As illustrated in Figure 2, the internal reference voltage
The midscale buffer is not active for the bipolar
devices. For these devices, MSV must be connected to
is 2.5V (V
). This 2.5V is internally buffered to create
REF
the voltages at REF+ and REF-. Table 4 shows the volt-
ages at COM, REF+, and REF-.
AGND or externally driven. REF
must be bypassed
MS
with a 0.01µF capacitor to AGND.
External Reference
External reference operation is achieved by overriding
the internal reference voltage. Override the internal ref-
See the Transfer Functions section for more information
about MSV.
Table 3. Reference Bypass Capacitors
INPUT VOLTAGE RANGE
LOCATION
UNIPOLAR (µF)
BIPOLAR (µF)
N/A
MSV Bypass Capacitor to AGND
2.2 || 0.1
0.01
REF
Bypass Capacitor to AGND
0.01
MS
REF Bypass Capacitor to AGND
REF+ Bypass Capacitor to AGND
REF+ to REF- Capacitor
0.01
0.01
0.1
0.1
2.2 || 0.1
0.1
2.2 || 0.1
0.1
REF- Bypass Capacitor to AGND
COM Bypass Capacitor to AGND
2.2 || 0.1
2.2 || 0.1
N/A = Not applicable. Connect MSV directly to AGND.
Table 4. Reference Voltages
CALCULATED VALUE (V) CALCULATED VALUE (V) CALCULATED VALUE (V)
= 2.000V, = 2.500V, = 3.000V,
V
REF
V
REF
V
REF
PARAMETER
EQUATION
(
(
)
(
)
)
AV = 5.0V
DD
AV = 5.0V
DD
AV = 5.0V
DD
V
V
= 13 / 25 x AV
DD
2.600
3.600
1.600
2.000
2.600
3.850
1.350
2.500
2.600
4.100
1.100
3.000
COM
COM
V
V
= V
= V
+ V
/ 2
REF
REF+
REF+
COM
COM
V
V
- V
/ 2
REF-
REF-
REF
680/2–MAX314
V
- V
V
- V = V
REF+ REF
REF+
REF-
REF-
26 ______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
The input range is centered about V
, internally set
Transfer Functions
MSV
to +2.5V. For a custom midscale voltage, drive REF
MS
Unipolar 0 to +5V Devices
Table 5 and Figure 12 show the offset binary transfer
function for the MAX1304/MAX1305/MAX1306 with a 0
to +5V input range. The full-scale input range (FSR) is
two times the voltage at REF. The internal +2.5V refer-
ence gives a +5V FSR, while an external +2V to +3V
reference allows an FSR of +4V to +6V, respectively.
Calculate the LSB size using:
with an external voltage source and MSV will follow
REF . Noise present on MSV or REF directly cou-
ples into the ADC result. Use a precision, low-drift volt-
age reference with adequate bypassing to prevent MSV
from degrading ADC performance. For maximum FSR,
do not violate the absolute maximum voltage ratings of
the analog inputs when choosing MSV.
MS
MS
Determine the input voltage as a function of V
MSV
,
REF
V
, and the output code in decimal using:
2 x V
REF
1 LSB =
12
2
V
CH_
= LSB x CODE + V
- 2.500V
10
MSV
which equals 1.22mV when using a 2.5V reference.
Table 5. 0 to 5V Unipolar Code Table
DECIMAL
INPUT VOLTAGE
EQUIVALENT
DIGITAL OUTPUT
CODE
BINARY
DIGITAL
OUTPUT CODE
(V)
2 x V
REF
V
= +2.5V
= +2.5V
REF
0xFFF
0xFFE
0xFFD
0xFFC
(
)
V
REFMS
(CODE
)
10
1111 1111 1111
= 0xFFF
4095
4094
2049
2048
2047
1
+4.9994 0.5 LSB
+4.9982 0.5 LSB
+2.5018 0.5 LSB
+2.5006 0.5 LSB
+2.4994 0.5 LSB
+0.0018 0.5 LSB
+0.0006 0.5 LSB
0x801
0x800
0x7FF
1111 1111 1110
= 0xFFE
1000 0000 0001
= 0x801
1000 0000 0000
= 0x800
0x0003
0x0002
0x0001
0x0000
2 x V
212
REF
1 LSB =
0111 1111 1111
= 0x7FF
0000 0000 0001
= 0x001
0
1
2
2046 2048 2050
(MSV)
4093 4095
3
INPUT VOLTAGE (LSBs)
0000 0000 0000
= 0x000
0
Figure 12. 0 to +5V Unipolar Transfer Function
______________________________________________________________________________________ 27
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
Bipolar 5V Devices
Table 6 and Figure 13 show the two’s complement trans-
fer function for the 5V input range MAX1308/MAX1309/
MAX1310. The FSR is four times the voltage at REF. The
internal +2.5V reference gives a +10V FSR, while an
external +2V to +3V reference allows an FSR of +8V to
+12V respectively. Calculate the LSB size using:
The input range is centered about V
. Normally,
MSV
MSV = AGND, and the input is symmetrical about zero.
For a custom midscale voltage, drive MSV with an
external voltage source. Noise present on MSV directly
couples into the ADC result. Use a precision, low-drift
voltage reference with adequate bypassing to prevent
MSV from degrading ADC performance. For maximum
FSR, do not violate the absolute maximum voltage rat-
ings of the analog inputs when choosing MSV.
4 x V
REF
1 LSB =
12
2
Determine the input voltage as a function of V
,
REF
V
MSV
, and the output code in decimal using:
which equals 2.44mV when using a 2.5V reference.
V
CH_
= LSB x CODE + V
10 MSV
Table 6. 5V Bipolar Code Table
DECIMAL
TWO’s
COMPLEMENT
DIGITAL OUTPUT
CODE
INPUT VOLTAGE
(V)
EQUIVALENT
DIGITAL OUTPUT
CODE
4 x V
REF
0x7FF
0x7FE
0x7FD
0x7FC
V
= +2.5V
REF
V
(
)
= 0
MSV
(CODE
)
10
0111 1111 1111 =
0x7FF
+2047
+2046
+1
+4.9988 0.5 LSB
+4.9963 0.5 LSB
+0.0037 0.5 LSB
+0.0012 0.5 LSB
-0.0012 0.5 LSB
-4.9963 0.5 LSB
-4.9988 0.5 LSB
0x001
0x000
0xFFF
0111 1111 1110 =
0x7FE
0000 0000 0001 =
0x001
0000 0000 0000 =
0x000
0
0x803
0x802
0x801
0x800
4 x V
212
REF
1 LSB =
1111 1111 1111 =
0xFFF
-1
1000 0000 0001 =
0x801
-2048 -2046
-1
(MSV)
INPUT VOLTAGE (V
0
+1
+2045 +2047
IN LSBs)
MSV
-2047
-2048
- V
CH_
1000 0000 0000 =
0x800
Figure 13. 5V Bipolar Transfer Function
680/2–MAX314
28 ______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
Bipolar 10V Devices
Table 7 and Figure 14 show the two’s complement trans-
fer function for the 10V input range MAX1312/
MAX1313/MAX1314. The FSR is eight times the voltage at
REF. The internal +2.5V reference gives a +20V FSR,
while an external +2V to +3V reference allows an FSR of
+16V to +24V, respectively. Calculate the LSB size using:
The input range is centered about V
. Normally,
MSV
MSV = AGND, and the input is symmetrical about zero.
For a custom midscale voltage, drive MSV with an
external voltage source. Noise present on MSV directly
couples into the ADC result. Use a precision, low-drift
voltage reference with adequate bypassing to prevent
MSV from degrading ADC performance. For maximum
FSR, do not violate the absolute maximum voltage rat-
ings of the analog inputs when choosing MSV.
8 x V
REF
1 LSB =
12
2
Determine the input voltage as a function of V
,
REF
V
MSV
, and the output code in decimal using:
which equals 4.88mV with a +2.5V internal reference.
V
CH_
= LSB x CODE + V
10 MSV
Table 7. 10V Bipolar Code Table
DECIMAL
TWO’s
COMPLEMENT
DIGITAL OUTPUT
CODE
INPUT VOLTAGE
(V)
EQUIVALENT
DIGITAL OUTPUT
CODE
8 x V
REF
0x7FF
0x7FE
0x7FD
0x7FC
V
= +2.5V
REF
V
(
)
= 0
MSV
(CODE
)
10
0111 1111 1111 =
0x7FF
+2047
+2046
+1
+9.9976 0.5 LSB
+9.9927 0.5 LSB
+0.0073 0.5 LSB
0.0024 0.5 LSB
-0.0024 0.5 LSB
-9.9927 0.5 LSB
-9.9976 0.5 LSB
0x001
0x000
0xFFF
0111 1111 1110 =
0x7FE
0000 0000 0001 =
0x001
0000 0000 0000 =
0x000
0
0x803
0x802
0x801
0x800
8 x V
212
REF
1 LSB =
1111 1111 1111 =
0xFFF
-1
1000 0000 0001 =
0x801
-2048 -2046
-1
(MSV)
INPUT VOLTAGE (V
0
+1
+2045 +2047
IN LSBs)
MSV
-2047
-2048
- V
CH_
1000 0000 0000 =
0x800
Figure 14. 10V Bipolar Transfer Function
______________________________________________________________________________________ 29
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
rithms that realign sequentially sampled data into a
simultaneous sample set. Additionally, the variety of
input voltage ranges allows for flexibility when choosing
current sensors and position encoders.
3-Phase Motor Controller
The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–
MAX1314 are ideally suited for motor-control systems
(Figure 15). The devices’ simultaneously sampled
inputs eliminate the need for complicated DSP algo-
MAX1308
DSP
12-BIT
ADC
T/H
IGBT CURRENT DRIVERS
I
PHASE1
CURRENT
SENSOR
I
PHASE3
I
PHASE2
3-PHASE ELECTRIC MOTOR
PHASE 1
PHASE 2
PHASE 3
POSITION
ENCODER
Figure 15. 3-Phase Motor Control
680/2–MAX314
30 ______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
ously sampled eight channels eliminate the need for
complicated DSP algorithms that realign sequentially
sampled data into a simultaneous sample set.
3-Phase Power-Monitoring System
The 8-channel devices are well suited for use in
3-phase power monitoring (Figure 16). The simultane-
MAX1312
12-BIT
ADC
T/H
MICROCONTROLLER
BUFFERS
AND INPUT
PROTECTION
V
V
P3
V
P1
V
P2
I
P3
I
P2
I
Pn
I
P1
NEUTRAL
CURRENT
TRANSFORMER
PHASE 1
LOAD
NEUTRAL
POWER
GRID
CURRENT
TRANSFORMER
LOAD
LOAD
CURRENT
TRANSFORMER
PHASE 2
PHASE 3
CURRENT
TRANSFORMER
Figure 16. 3-Phase Power Monitoring
______________________________________________________________________________________ 31
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
Layout, Grounding, and Bypassing
For best performance use PC boards. Board layout must
ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines paral-
lel to one another (especially clock lines), and do not run
digital lines underneath the ADC package.
DIGITAL
GROUND
POINT
ANALOG SUPPLY
+5V RETURN
DIGITAL SUPPLY
RETURN +3V TO +5V
Figure 17 shows the recommended system ground con-
nections. Establish an analog ground point at AGND and
a digital ground point at DGND. Connect all analog
grounds to the analog ground point. Connect all digital
grounds to the digital ground point. For lowest noise
operation, make the power-supply ground returns as low
impedance and as short as possible. Connect the analog
ground point to the digital ground point at one location.
ANALOG
GROUND
POINT
OPTIONAL
FERRITE
BEAD
High-frequency noise in the power supplies degrades
the ADC’s performance. Bypass the analog power
plane to the analog ground plane with a 2.2µF capaci-
AV
DD
DGND
AGND
DV
DGND
DV
DD
DD
DIGITAL
CIRCUITRY
DATA
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
tor within one inch of the device. Bypass each AV
to
DD
AGND pair of pins with a 0.1µF capacitor as close to
the device as possible. AV to AGND pairs are pin 1
DD
to pin 2, pin 14 to pin 15, and pin 16 to pin 17.
Likewise, bypass the digital power plane to the digital
ground plane with a 2.2µF capacitor within one inch of
Figure 17. Power-Supply Grounding and Bypassing
the device. Bypass each DV
to DGND pair of pins
DD
with a 0.1µF capacitor as close to the device as possi-
ble. DV to DGND pairs are pin 24 to pin 25, and pin
38 to pin 39. If a supply is very noisy use a ferrite bead
as a lowpass filter as shown in Figure 17.
DD
Offset Error
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Typically the point at which
offset error is specified is either at or near the zero-
scale point of the transfer function or at or near the mid-
scale point of the transfer function.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. For these devices, this
straight line is drawn between the endpoints of the
transfer function, once offset and gain errors have
been nullified.
For the unipolar devices (MAX1304/MAX1305/
MAX1306), the ideal zero-scale transition from 0x000 to
0x001 occurs at 1 LSB above AGND (Figure 12, Table 5).
Unipolar offset error is the amount of deviation between
the measured zero-scale transition point and the ideal
zero-scale transition point.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. For these devices, the DNL of
each digital output code is measured and the worst-
case value is reported in the electrical characteristics
table. A DNL error specification of less than 1 LSB
guarantees no missing codes and a monotonic
transfer function.
For the bipolar devices (MAX1308/MAX1309/MAX1310/
MAX1312/MAX1313/MAX1314), the ideal midscale tran-
sition from 0xFFF to 0x000 occurs at MSV (Figures 14
and 13, Tables 7 and 6). The bipolar offset error is the
amount of deviation between the measured midscale
transition point and the ideal midscale transition point.
680/2–MAX314
32 ______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
Gain Error
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope
of the ideal transfer function. For the MAX1304–
MAX1306/MAX1308–MAX1310/MAX1312–MAX1314, the
gain error is the difference of the measured full-scale
and zero-scale transition points minus the difference of
the ideal full-scale and zero-scale transition points.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed as:
−
SINAD 1.76
ENOB =
6.02
For the unipolar devices (MAX1304/MAX1305/
MAX1306), the full-scale transition point is from 0xFFE
to 0xFFF and the zero-scale transition point is from
0x000 to 0x001.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first five harmon-
ics to the fundamental itself. This is expressed as:
For the bipolar devices (MAX1308/MAX1309/MAX1310/
MAX1312/MAX1313/MAX1314), the full-scale transition
point is from 0x7FE to 0x7FF and the zero-scale transi-
tion point is from 0x800 to 0x801.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
2
2
2
2
2
V
+ V + V + V + V
3 5 6
4
2
=
THD 20 x log
V
1
where V is the fundamental amplitude, and V through
6
order harmonics.
1
2
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
V
are the amplitudes of the 2nd- through 6th-
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the fundamen-
tal (maximum signal component) to the RMS value of the
next largest spurious component, excluding DC offset.
SFDR is specified in decibels relative to the carrier (dBc).
SNR
= 6.02 × N + 1.76
dB dB
dB[max]
Channel-to-Channel Isolation
Channel-to-channel isolation indicates how well each
analog input is isolated from the others. The channel-to-
channel isolation for these devices is measured by
applying DC to channel 1 through channel 7 while an
AC 500kHz, -0.4dBFS sine wave is applied to channel
0. An FFT is taken for channel 0 and channel 1 and the
difference (in dB) of the 500kHz magnitudes is reported
as the channel-to-channel isolation.
In reality, there are other noise sources such as thermal
noise, reference noise, and clock jitter.
For these devices, SNR is computed by taking the ratio
of the RMS signal to the RMS noise. RMS noise
includes all spectral components to the Nyquist fre-
quency excluding the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal
to the RMS noise plus distortion. RMS noise plus distor-
tion includes all spectral components to the Nyquist fre-
quency excluding the fundamental and the DC offset.
Aperature Delay
Aperture delay (t ) is the time delay from the CONVST
AD
rising edge to the instant when an actual sample is taken.
⎛
⎞
SIGNAL
(NOISE + DISTORTION)
RMS
SINAD(dB) = 20 x log
⎜
⎟
⎝
⎠
RMS
______________________________________________________________________________________ 33
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
Aperture Jitter
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC so that the signal’s slew rate does not limit the
ADC’s performance. The input frequency is then swept
up to the point where the amplitude of the digitized
conversion result has decreased by -3dB.
Aperture Jitter (t ) is the sample-to-sample variation in
AJ
aperture delay.
Jitter is a concern when considering an ADC’s dynamic
performance, e.g., SNR. To reconstruct an analog input
from the ADC digital outputs, it is critical to know the
time at which each sample was taken. Typical applica-
tions use an accurate sampling clock signal that has
low jitter from sampling edge to sampling edge. For a
system with a perfect sampling clock signal, with no
clock jitter, the SNR performance of an ADC is limited
by the ADC’s internal aperture jitter as follows:
Full-Power Bandwidth
A large, -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
⎛
⎞
1
DC Power-Supply Rejection (PSRR)
DC PSRR is defined as the change in the positive full-
scale transfer function point caused by a 5% variation
=
SNR 20 x log
⎜
⎟
2 x π x f x t
⎝
⎠
IN
AJ
in the analog power-supply voltage (AV ).
DD
where f represents the analog input frequency and
IN
t
AJ
is the time of the aperture jitter.
680/2–MAX314
34 ______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
Pin Configurations
TOP VIEW
AVDD
AGND
AGND
CH0
1
2
36 D10
35 D9
34 D8
33 D7
32 D6
31 D5
30 D4
29 D3
AV
1
2
36 D10
35 D9
34 D8
33 D7
32 D6
31 D5
30 D4
29 D3
DD
AGND
AGND
CH0
CH1
MSV
CH2
CH3
I.C.
3
3
4
4
CH1
5
5
MSV
CH2
6
6
MAX1304
MAX1308
MAX1312
MAX1305
MAX1309
MAX1313
7
7
CH3
8
8
CH4
D2
D1
D0
DV
D2
D1
D0
DV
9
28
27
26
25
9
28
27
26
25
CH5
I.C.
10
11
12
10
11
12
CH6
I.C.
CH7
I.C.
DD
DD
8-CHANNEL TQFP
4-CHANNEL TQFP
AVDD
AGND
AGND
CH0
CH1
MSV
I.C.
1
2
36 D10
35 D9
34 D8
33 D7
32 D6
31 D5
30 D4
29 D3
3
4
5
6
MAX1306
MAX1310
MAX1314
7
I.C.
8
I.C.
D2
D1
D0
9
28
27
26
25
I.C.
10
11
12
I.C.
I.C.
DVDD
2-CHANNEL TQFP
______________________________________________________________________________________ 35
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
Package Information
Chip Information
For the latest package outline information and land patterns, go
TRANSISTOR COUNT: 50,000
to www.maxim-ic.com/packages.
PROCESS: 0.6µm BiCMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
48 TQFP
C48+6
21-0054
680/2–MAX314
36 ______________________________________________________________________________________
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10ꢀ, ±±ꢀ, and 0 to +±ꢀ Analog Input Ranges
680/2–MAX314
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
4
8/09
Added automotive part numbers
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 37
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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