MAX1295ACEI [MAXIM]
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface; 265ksps ，+ 3V ， 6 / 2通道，12位ADC，带有+ 2.5V电压基准及并行接口
| 型号： | MAX1295ACEI |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface |
| 文件： | 总20页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1530; Rev 0; 9/99
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
5/MAX1297
General Description
Features
The MAX1295/MAX1297 low-power, 12-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2µs), on-chip clock, +2.5V internal reference, and
high-speed 12-bit parallel interface. They operate with
a single +2.7V to +3.6V analog supply.
♦ 12-Bit Resolution, ±0.5LSB Linearity
♦ +3V Single-Supply Operation
♦ Internal +2.5V Reference
♦ Software-Configurable Analog Input Multiplexer
6-Channel Single-Ended/
Power consumption is only 5.4mW at the maximum
sampling rate of 265ksps. Two software-selectable
power-down modes enable the MAX1295/MAX1297 to
be shut down between conversions; accessing the par-
allel interface returns them to normal operation.
Powering down between conversions can reduce sup-
ply current below 10µA at lower sampling rates.
3-Channel Pseudo-Differential (MAX1295)
2-Channel Single-Ended/
1-Channel Pseudo-Differential (MAX1297)
♦ Software-Configurable Unipolar/Bipolar
Analog Inputs
♦ Low Current
1.8mA (265ksps)
1.0mA (100ksps)
400µA (10ksps)
2µA (shutdown)
Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differen-
tial operation. In single-ended mode, the MAX1295 has
six input channels and the MAX1297 has two (three
input channels and one input channel, respectively,
when in pseudo-differential mode).
♦ Internal 3MHz Full-Power Bandwidth Track/Hold
♦ Parallel 12-Bit Interface
Excellent dynamic performance and low power combined
with ease of use and small package size make these con-
verters ideal for battery-powered and data-acquisition
applications or for other circuits with demanding power-
consumption and space requirements. The MAX1295 is
offered in a 28-pin QSOP package, while the MAX1297
comes in a 24-pin QSOP. For pin-compatible +5V, 12-bit
versions, refer to the MAX1294/MAX1296 data sheet.
♦ Small Footprint
28-Pin QSOP (MAX1295)
24-Pin QSOP (MAX1297)
Pin Configurations
TOP VIEW
D9
D8
D7
D6
D5
D4
D3
D2
D1
1
2
3
4
5
6
7
8
9
28 D10
27 D11
Applications
Industrial Control Systems Data Logging
26
V
DD
Energy Management
Patient Monitoring
Touchscreens
25 REF
24 REFADJ
23 GND
22 COM
21 CH0
20 CH1
19 CH2
18 CH3
17 CH4
16 CH5
15 CS
Data-Acquisition Systems
MAX1295
Ordering Information
INL
TEMP. RANGE PIN-PACKAGE
(LSB)
PART
D0 10
INT 11
RD 12
WR 13
CLK 14
MAX1295ACEI
0°C to +70°C 28 QSOP
0°C to +70°C 28 QSOP
0.5
1
MAX1295BCEI
MAX1295AEEI -40°C to +85°C 28 QSOP
MAX1295BEEI -40°C to +85°C 28 QSOP
0.5
1
MAX1297ACEG
0°C to +70°C 24 QSOP
0°C to +70°C 24 QSOP
0.5
1
MAX1297BCEG
QSOP
MAX1297AEEG -40°C to +85°C 24 QSOP
MAX1297BEEG -40°C to +85°C 24 QSOP
0.5
1
Pin Configurations continued at end of data sheet.
Typical Operating Circuits appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ABSOLUTE MAXIMUM RATINGS
V
to GND..............................................................-0.3V to +6V
28-Pin QSOP (derate 8.00mW/°C above +70°C)........667mW
Operating Temperature Ranges
MAX1295_C_ _ /MAX1297_C_ _ ........................0°C to +70°C
MAX1295_E_ _ /MAX1297_E_ _ ......................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
DD
CH0–CH5, COM to GND............................-0.3V to (V
REF, REFADJ to GND.................................-0.3V to (V
Digital Inputs to GND ...............................................-0.3V to +6V
Digital Outputs (D0–D11, INT) to GND.......-0.3V to (V + 0.3V)
Continuous Power Dissipation (T = +70°C)
+ 0.3V)
+ 0.3V)
DD
DD
DD
A
24-Pin QSOP (derate 9.5mW/°C above +70°C)..........762mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= +2.7V to +3.6V, COM = GND, REFADJ = V , V
= +2.5V, 4.7µF capacitor at REF pin, f
= 4.8MHz (50% duty cycle),
DD REF
CLK
T
A
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
5/MAX1297
Resolution
RES
INL
12
Bits
MAX129_A
MAX129_B
No missing codes over temperature
0.5
1
Relative Accuracy (Note 2)
LSB
Differential Nonlinearity
Offset Error
DNL
1
LSB
LSB
4
Gain Error (Note 3)
Gain Temperature Coefficient
4
LSB
2.0
0.2
ppm/°C
Channel-to-Channel Offset
Matching
LSB
DYNAMIC SPECIFICATIONS (f
= 50kHz, V = 2.5Vp-p, 265ksps, external f
= 4.8MHz, bipolar input mode)
IN(sine-wave)
IN
CLK
Signal-to-Noise Plus Distortion
SINAD
67
80
70
dB
dB
Total Harmonic Distortion
(including 5th-order harmonic)
THD
-78
Spurious-Free Dynamic Range
Intermodulation Distortion
Channel-to-Channel Crosstalk
Full-Linear Bandwidth
SFDR
IMD
dB
dB
f
f
= 49kHz, f
= 52kHz
76
-78
250
3
IN1
IN2
= 125kHz (Note 4)
dB
IN
SINAD > 68dB
-3dB rolloff
kHz
MHz
Full-Power Bandwidth
CONVERSION RATE
External clock mode
3.3
2.5
3.2
Conversion Time (Note 5)
t
External acquisition/internal clock mode
Internal acquisition/internal clock mode
3.0
3.6
3.5
4.1
µs
CONV
Track/Hold Acquisition Time
Aperture Delay
t
625
ns
ns
ACQ
External acquisition or external clock mode
External acquisition or external clock mode
Internal acquisition/internal clock mode
50
<50
<200
Aperture Jitter
ps
External Clock Frequency
Duty Cycle
f
0.1
30
4.8
70
MHz
%
CLK
2
_______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
5/MAX1297
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +3.6V, COM = GND, REFADJ = V , V
= +2.5V, 4.7µF capacitor at REF pin, f
= 4.8MHz (50% duty cycle),
DD REF
CLK
T
A
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOGINPUTS
Unipolar, V
= 0
0
V
REF
COM
Analog Input Voltage Range
Single-Ended and Differential
(Note 6)
V
IN
V
Bipolar, V
= V
/2
-V
/2
+V /2
REF
COM
REF
REF
Multiplexer Leakage Current
Input Capacitance
On/off-leakage-current, V = 0 or V
IN
0.01
12
1
µA
pF
DD
C
IN
INTERNAL REFERENCE
REF Output Voltage
2.49
2.5
15
2.51
V
mA
REF Short-Circuit Current
REF Temperature Coefficient
REFADJ Input Range
TC
20
ppm/°C
mV
REF
For small adjustments
100
REFADJ High Threshold
Load Regulation (Note 7)
Capacitive Bypass at REFADJ
Capacitive Bypass at REF
EXTERNAL REFERENCE AT REF
To power down the internal reference
0 to 0.5mA output load
V
- 1
V
DD
0.2
0.5
1
mV/mA
µF
0.01
4.7
10
µF
V
+
DD
REF Input Voltage Range
REF Input Current
V
V
REF
1.0
2.0
50mV
V
= 2.5V, f
= 265ksps
200
300
2
REF
SAMPLE
I
µA
REF
Shutdown mode
DIGITAL INPUTS AND OUTPUTS
Input Voltage High
V
V
V
IH
Input Voltage Low
V
0.8
1
IL
Input Hysteresis
V
HYS
200
0.1
15
mV
µA
pF
V
Input Leakage Current
Input Capacitance
I
V
IN
= 0 or V
DD
IN
C
IN
OL
OH
Output Voltage Low
Output Voltage High
V
I
I
= 1.6mA
0.4
1
SINK
V
= 1mA
V
- 0.5
V
SOURCE
DD
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage
I
0.1
15
µA
pF
CS = V
CS = V
LEAKAGE
DD
DD
C
OUT
V
2.7
3.6
2.6
2.3
1.2
0.8
10
V
DD
Internal reference
External reference
Internal reference
External reference
2.3
1.9
0.9
0.5
2
Operating mode,
= 265ksps
f
SAMPLE
mA
Positive Supply Current
Power-Supply Rejection
I
DD
Standby mode
Shutdown mode
µA
PSR
V
DD
= 2.7V to 3.6V, full-scale input
0.4
0.7
mV
_______________________________________________________________________________________
3
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
TIMING CHARACTERISTICS
(V
DD
= +2.7V to +3.6V, COM = GND, REFADJ = V , V
= +2.5V, 4.7µF capacitor at REF pin, f
= 4.8MHz (50% duty cycle),
DD REF
CLK
T
A
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ns
CLK Period
t
208
40
40
40
0
CP
CLK Pulse Width High
t
ns
CH
CLK Pulse Width Low
t
CL
ns
t
t
ns
Data Valid to WR Rise Time
WR Rise to Data Valid Hold Time
WR to CLK Fall Setup Time
CLK Fall to WR Hold Time
CS to CLK or WR Setup Time
CLK or WR to CS Hold Time
CS Pulse Width
DS
ns
DH
t
t
40
40
60
0
ns
CWS
ns
CWH
t
ns
CSWS
t
ns
CSWH
t
100
60
20
20
20
ns
CS
t
ns
WR Pulse Width (Note 8)
CS Rise to Output Disable
RD Rise to Output Disable
RD Fall to Output Data Valid
RD Fall to INT High Delay
CS Fall to Output Data Valid
WR
5/MAX1297
t
TC
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
= 20pF, Figure 1
100
70
ns
t
TR
= 20pF, Figure 1
= 20pF, Figure 1
= 20pF, Figure 1
= 20pF, Figure 1
ns
t
70
ns
DO
t
100
110
ns
INT1
t
ns
DO2
Note 1: Tested at V
= +3V, COM = GND, unipolar single-ended input mode.
DD
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to V
Note 7: External load should not change during conversion for specified accuracy.
.
DD
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
V
DD
3k
DOUT
DOUT
C
20pF
LOAD
C
LOAD
6k
20pF
GND
b) HIGH-Z TO V AND V TO V
OL
GND
a) HIGH-Z TO V AND V TO V
OH
OH
OL
OL
OH
Figure 1. Load Circuits for Enable/Disable Times
4
_______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
5/MAX1297
Typical Operating Characteristics
(V
DD
= +3V, V
= +2.500V, f
= 4.8MHz, C = 20pF, T = +25°C, unless otherwise noted.)
REF
CLK
L
A
SUPPLY CURRENT
vs. SAMPLE FREQUENCY
INTEGRAL NONLINEARITY vs.
DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY vs.
DIGITAL OUTPUT CODE
0.5
10,000
1000
100
10
0.5
0.4
0.4
0.3
WITH INTERNAL REFERENCE
0.3
0.2
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
WITH EXTERNAL REFERENCE
0
1k
1
10k 100k 1M
0.1
10
100
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
5000
f
(Hz)
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
SAMPLE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
STANDBY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
2.10
2.05
2.00
1.95
1.90
1.85
1.80
930
920
910
900
890
880
2.2
2.1
2.0
1.9
1.8
1.7
1.6
R = ∞
CODE = 101010100000
R = ∞
CODE = 101010100000
L
L
2.7
3.0
3.3
3.6
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
V
DD
(V)
V
DD
(V)
TEMPERATURE (°C)
POWER-DOWN CURRENT
vs. SUPPLY VOLTAGE
POWER-DOWN CURRENT
vs. TEMPERATURE
STANDBY CURRENT vs. TEMPERATURE
1.50
1.25
1.00
1.2
1.1
1.0
0.9
0.8
930
920
910
900
890
880
0.75
0.50
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
-40
-15
10
35
60
85
V
DD
(V)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Characteristics (continued)
(V
DD
= +3V, V
= +2.500V, f
= 4.8MHz, C = 20pF, T = +25°C, unless otherwise noted.)
REF
CLK
L
A
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE vs.
SUPPLY VOLTAGE
OFFSET ERROR vs. SUPPLY VOLTAGE
2.53
0
-0.5
-1.0
-1.5
-2.0
-2.5
2.53
2.52
2.51
2.50
2.49
2.48
2.52
2.51
2.50
2.49
2.48
2
-40
-15
10
TEMPERATURE (°C)
60
85
3.0
3.3
35
2.7
3.0
3.3
3.6
2.7
3.6
V
DD
(V)
V
DD
(V)
OFFSET ERROR vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
0.5
0
1.0
0
0.5
0
-0.5
-1.0
-1.5
-2.0
-2.5
-0.5
-1.0
-1.5
-2.0
-1.0
-2.0
-3.0
-40
-15
10
35
60
85
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
TEMPERATURE (°C)
V
DD
(V)
TEMPERATURE (°C)
FFT PLOT
20
0
V
f
= 3V
= 50kHz
DD
IN
f
= 250ksps
SAMPLE
-20
-40
-60
-80
-100
-120
-140
0
200
400
600
800
1000
FREQUENCY (kHz)
6
_______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
5/MAX1297
Pin Description
PIN
NAME
FUNCTION
MAX1295
MAX1297
1
2
1
2
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
INT
Three-State Digital Output (D9)
Three-State Digital Output (D8)
Three-State Digital I/O Line (D7)
Three-State Digital I/O Line (D6)
Three-State Digital I/O Line (D5)
Three-State Digital I/O Line (D4)
Three-State Digital I/O Line (D3)
Three-State Digital I/O Line (D2)
Three-State Digital I/O Line (D1)
Three-State Digital I/O Line (D0)
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
10
11
INT goes low when the conversion is complete and output data is ready.
Active-Low Read Select. If CS is low, a falling edge on RD will enable the read oper-
ation on the data bus.
12
12
RD
Active-Low Write Select. When CS is low in the internal acquisition mode, a rising
edge on WR latches in configuration data and starts an acquisition plus a conver-
sion cycle. When CS is low in external acquisition mode, the first rising edge on WR
ends acquisition and starts a conversion.
13
13
WR
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock.
14
15
14
15
CLK
In internal clock mode, connect this pin to either V
or GND.
DD
Active-Low Chip Select. When CS is high, digital outputs (INT, D11–D0) are high
impedance.
CS
16
17
18
19
20
21
—
—
—
—
16
17
CH5
CH4
CH3
CH2
CH1
CH0
Analog Input Channel 5
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode
and must be stable to 0.5LSB during conversion.
22
23
18
19
COM
GND
Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with
24
20
REFADJ
a 0.01µF capacitor. When using an external reference, connect REFADJ to V
to
DD
disable the internal bandgap reference.
_______________________________________________________________________________________
7
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description (continued)
PIN
NAME
FUNCTION
MAX1295
MAX1297
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor
to GND when using the internal reference.
25
21
REF
26
27
28
22
23
24
V
Analog +2.7V to +3.6V Power Supply. Bypass with a 0.1µF capacitor to GND.
Three-State Digital Output (D11)
DD
D11
D10
Three-State Digital Output (D10)
REF
T/H
REFADJ
17k
1.22V
REFERENCE
A =
V
2.05
2
(CH5)
(CH4)
(CH3)
(CH2)
CH1
ANALOG
INPUT
MULTIPLEXER
CHARGE REDISTRIBUTION
12-BIT DAC
COMP
CH0
12
SUCCESSIVE-
COM
APPROXIMATION
REGISTER
CLK
CLOCK
CS
WR
RD
CONTROL LOGIC
&
MAX1295
MAX1297
LATCHES
INT
V
DD
12
THREE-STATE, BIDIRECTIONAL
I/O INTERFACE
GND
D0–D11
12-BIT DATA BUS
( ) ARE FOR MAX1295 ONLY.
Figure 2. Simplified Functional Diagram of 6-/2-Channel MAX1295/MAX1297
Single-Ended and
_______________Detailed Description
Pseudo-Differential Operation
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH5 for the MAX1295
(Figure 3a) and to CH0–CH1 for the MAX1297 (Figure
3b), while IN- is switched to COM (Table 2). In differen-
tial mode, IN+ and IN- are selected from analog input
pairs (Table 3) and are internally switched to either of
Converter Operation
The MAX1295/MAX1297 ADCs use a successive-
approximation (SAR) conversion technique and an input
track/hold (T/H) stage to convert an analog input signal
to a 12-bit digital output. This output format provides an
easy interface to standard microprocessors (µPs). Figure
2 shows the simplified internal architecture of the
MAX1295/MAX1297.
8
_______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
5/MAX1297
the analog inputs. This configuration is pseudo-differ-
ential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within 0.5LSB
( 0.1LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
end of the acquisition interval, the T/H switch opens,
retaining charge on C
at IN+.
as a sample of the signal
HOLD
The conversion interval begins with the input multiplex-
er switching C from the positive input (IN+) to the
HOLD
negative input (IN-). This unbalances node ZERO at
the comparator’s positive input. The capacitive digital-
to-analog converter (DAC) adjusts during the remain-
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C . At the
HOLD
12-BIT CAPACITIVE DAC
12-BIT CAPACITIVE DAC
V
REF
V
REF
COMPARATOR
INPUT
MUX
COMPARATOR
INPUT
MUX
C
HOLD
C
HOLD
ZERO
–
+
ZERO
–
+
CH0
CH0
CH1
12pF
12pF
R
IN
CH1
CH2
CH3
CH4
CH5
R
IN
800Ω
800Ω
C
SWITCH
C
SWITCH
HOLD
HOLD
TRACK
TRACK
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
T/H
SWITCH
T/H
SWITCH
COM
COM
SINGLE-ENDED MODE: IN+ = CH0–CH5, IN- = COM
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1 AND CH2/CH3, AND CH4/CH5
SINGLE-ENDED MODE: IN+ = CH0–CH1, IN- = COM
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR
CH0/CH1
Figure 3a. MAX1295 Simplified Input Structure
Figure 3b. MAX1297 Simplified Input Structure
Table 1. Control-Byte Functional Description
BIT
NAME
FUNCTIONAL DESCRIPTION
PD1 and PD0 select the various clock and power-down modes.
0
0
1
1
0
1
0
1
Full Power-Down Mode. Clock mode is unaffected.
D7, D6
PD1, PD0
Standby Power-Down Mode. Clock mode is unaffected.
Normal Operation Mode. Internal clock mode selected.
Normal Operation Mode. External clock mode selected.
ACQMOD = 0: Internal Acquisition Mode
ACQMOD = 1: External Acquisition Mode
D5
D4
ACQMOD
SGL/DIF = 0: Pseudo-Differential Analog Input Mode
SGL/DIF = 1: Single-Ended Analog Input Mode
In single-ended mode, input signals are referred to COM. In differential mode, the voltage difference
between two channels is measured (Tables 2, 4).
SGL/DIF
UNI/BIP = 0: Bipolar Mode
UNI/BIP = 1: Unipolar Mode
In unipolar mode, an analog input signal from 0V to V
D3
UNI/BIP
can be converted; in bipolar mode, the
REF
signal can range from -V /2 to +V /2.
REF REF
Address bits A2, A1, A0 select which of the 6/2 (MAX1295/MAX1297) channels is to be converted
(Tables 2, 3).
D2, D1, D0
A2, A1, A0
_______________________________________________________________________________________
9
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Table 2. Channel Selection for Single-Ended Operation (SGL/DIF = 1)
A2
A1
A0
CH0
CH1
CH2*
CH3*
CH4*
CH5*
COM
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
+
-
-
-
-
-
-
+
+
+
+
+
*Channels CH2–CH5 apply to MAX1295 only.
Table 3. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)
A2
0
A1
0
A0
0
CH0
CH1
CH2*
CH3*
CH4*
CH5*
+
-
-
0
0
1
+
5/MAX1297
0
1
0
+
-
-
0
1
1
+
1
0
0
+
-
-
1
0
1
+
*Channels CH2–CH5 apply to MAX1295 only.
der of the conversion cycle to restore node ZERO to 0V
within the limits of 12-bit resolution. This action is equiv-
In single-ended operation, IN- is connected to COM
and the converter samples the positive “+” input. In
pseudo-differential operation, IN- connects to the nega-
alent to transferring a 12pF (V
- V ) charge from
IN-
IN+
C
HOLD
to the binary-weighted capacitive DAC, which in
tive input “-”, and the difference of (IN+) - (IN-) is sam-
| |
turn forms a digital representation of the analog input
signal.
pled. At the beginning of the next conversion, the
positive input connects back to IN+ and CHOLD
charges to the input signal.
Analog Input Protection
Internal protection diodes, which clamp the analog
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
input to V
and GND, allow each input channel to
DD
swing within (GND - 300mV) to (V
+ 300mV) without
DD
damage. However, for accurate conversions near full
scale, both inputs must not exceed (V
less than (GND - 50mV).
+ 50mV) or be
DD
t , is the maximum time the device takes to acquire
ACQ
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation:
If an analog input voltage exceeds the supplies by
more than 50mV, limit the forward-bias input current
to 4mA.
t
= 9 (R + R ) C
S IN IN
ACQ
Track/Hold
The MAX1295/MAX1297 T/H stage enters its tracking
mode on WR’s rising edge. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that in internal clock
mode this is approximately 1µs after writing the control
byte.
where R is the source impedance of the input signal,
S
R
(800Ω) is the input resistance, and C (12pF) is
IN
IN
the input capacitance of the ADC. Source impedances
below 3kΩ have no significant impact on the MAX1295/
MAX1297’s AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
10 ______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
5/MAX1297
t
CS
CS
t
ACQ
t
CONV
t
t
CSWH
CSWS
t
WR
WR
t
DH
t
DS
CONTROL
BYTE
D11–D0
ACQMOD ="0"
t
INT1
INT
RD
t
TR
t
D0
HIGH-Z
HIGH-Z
VALID DATA
DOUT
Figure 4. Conversion Timing Using Internal Acquisition Mode
Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.
for acquiring the signal: an internal and an external
acquisition. The conversion period lasts for 13 clock
cycles in either the internal or external clock or acquisi-
tion mode. Writing a new control byte during a conver-
sion cycle will abort the conversion and start a new
acquisition interval.
Input Bandwidth
The MAX1295/MAX1297 T/H stage offers a 250kHz full-
linear and a 3MHz full-power bandwidth. This makes it
possible to digitize high-speed transients and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended.
Internal Acquisition
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this acquisition interval (three external clock
cycles or approximately 1µs in internal clock mode)
ends (Figure 4). Note that when the internal acquisition
is combined with the internal clock, the aperture jitter
can be as high as 200ps. Internal clock users wishing
to achieve the 50ps jitter specification should always
use external acquisition mode.
Starting a Conversion
Initiate a conversion by writing a control byte that selects
the multiplexer channel and configures the MAX1295/
MAX1297 for either unipolar or bipolar operation. A
write pulse (WR + CS) can either start an acquisition
interval or initiate a combined acquisition plus conver-
sion. The sampling interval occurs at the end of the
acquisition interval. The acquisition mode (ACQMOD)
bit in the input control byte (Table 1) offers two options
______________________________________________________________________________________ 11
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
t
CS
CS
t
t
t
CONV
CSWS
ACQ
t
WR
t
t
CSWH
WR
DH
t
DS
CONTROL
BYTE
ACQMOD = "1"
CONTROL
BYTE
ACQMOD = "0"
D11–D0
INT
t
INT1
RD
5/MAX1297
t
D0
t
TR
HIGH-Z
HIGH-Z
VALID DATA
DOUT
Figure 5. Conversion Timing Using External Acquisition Mode
External Acquisition
Use external acquisition mode for precise control of the
sampling aperture and/or dependent control of acquisi-
tion and conversion times. The user controls acquisition
and start-of-conversion with two separate write pulses.
The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0 (all other bits in
control byte unchanged), terminates acquisition and
starts conversion on WR rising edge (Figure 5).
when the conversion is complete and the output data is
ready (Figures 4, 5). It returns high on the first read
cycle or if a new control byte is written.
Selecting Clock Mode
The MAX1295/MAX1297 operate with either an internal
or an external clock. Control bits D6 and D7 select
either internal or external clock mode. The part retains
the last requested clock mode if a power-down mode is
selected in the current input word. For both internal and
external clock mode, internal or external acquisition
can be used. At power-up, the MAX1295/MAX1297
enter the default external clock mode.
The address bits for the input multiplexer must have the
same values on the first and second write pulse.
Power-down mode bits (PD0, PD1) can assume new
values on the second write pulse (see Power-Down
Modes section). Changing other bits in the control byte
will corrupt the conversion.
Internal Clock Mode
Select internal clock mode to release the µP from the
burden of running the SAR conversion clock. Bits D6
and D7 of the control byte must be set to 1; the internal
clock frequency is then selected, resulting in a conver-
sion time of 3.6µs. When using the internal clock mode,
tie the CLK pin either high or low to prevent the pin
from floating.
Reading a Conversion
A standard interrupt signal INT is provided to allow the
MAX1295/MAX1297 to flag the µP when the conversion
has ended and a valid result is available. INT goes low
12 ______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
5/MAX1297
ACQUISITION STARTS
CONVERSION STARTS
ACQUISITION ENDS
t
CP
CLK
WR
t
t
CH
t
CWS
CL
WR GOES HIGH WHEN CLK IS HIGH.
ACQMOD = "0"
ACQUISITION STARTS
t
CWH
CONVERSION STARTS
ACQUISITION ENDS
CLK
WR
ACQMOD = "0"
WR GOES HIGH WHEN CLK IS LOW.
Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
t
CWS
t
DH
WR
ACQMOD = "0"
ACQMOD = "1"
WR GOES HIGH WHEN CLK IS HIGH
ACQUISITION ENDS
ACQUISITION STARTS
CONVERSION STARTS
CLK
WR
t
CWH
t
DH
ACQMOD = "1"
WR GOES HIGH WHEN CLK IS LOW
ACQMOD = "0"
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
External Clock Mode
To select the external clock mode, bits D6 and D7 of
the control byte must be set to zero. Figure 6 shows the
clock and WR timing relationship for internal (Figure 6a)
and external (Figure 6b) acquisition modes with an
external clock. For proper operation, a 100kHz to
4.8MHz clock frequency with 30% to 70% duty cycle is
recommended. Operating the MAX1295/MAX1297 with
clock frequencies lower than 100kHz is not recommend-
ed because the resulting voltage droop across the hold
capacitor in the T/H stage will degrade performance.
Digital Interface
The input and output data are multiplexed on a three-
state parallel interface (I/O) that can easily be inter-
faced with standard µPs. The signals CS, WR, and RD
control the write and read operations. CS represents
______________________________________________________________________________________ 13
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Table 4. Control-Byte Format
D7
(MSB)
D0
(LSB)
D6
D5
D4
D3
D2
D1
PD1
PD0
ACQMOD
A2
A1
A0
SGL/DIF
UNI/BIP
An internal buffer is designed to provide +2.5V at REF for
both the MAX1295 and MAX1297. The internally trimmed
+1.22V reference is buffered with a +2.05V/V gain.
V
= +3V
DD
50k
50k
Internal Reference
The full-scale range with the internal reference is +2.5V
with unipolar inputs and 1.25V with bipolar inputs. The
internal reference buffer allows for small adjustments
( 100mV) in the reference voltage (Figure 7).
MAX1295
MAX1297
330k
REFADJ
REF
4.7µF
GND
0.01µF
Note: The reference buffer must be compensated with
an external capacitor (4.7µF min) connected between
REF and GND to reduce reference noise and switching
spikes from the ADC. To further minimize noise on the
reference, connect a 0.01µF capacitor between REFADJ
and GND.
GND
5/MAX1297
Figure 7. Reference Adjustment with External Potentiometer
the chip-select signal, which enables a µP to address
the MAX1295/MAX1297 as an I/O port. When high, CS
disables the CLK, WR, and RD inputs and forces the
interface into a high-impedance (high-Z) state.
External Reference
With both the MAX1295 and MAX1297, an external refer-
ence can be placed at either the input (REFADJ) or the
output (REF) of the internal reference buffer amplifier.
Input Format
The control bit sequence is latched into the device on
pins D7–D0 during a write command. Table 4 shows
the control-byte format.
Using the REFADJ input makes buffering the external
reference unnecessary. The REFADJ input impedance
is typically 17kΩ.
When applying an external reference to REF, disable
the internal reference buffer by connecting REFADJ to
DD
Therefore, an external reference at REF must deliver up
to 200µA DC load current during a conversion and
have an output impedance less than 10Ω. If the refer-
ence has higher output impedance or is noisy, bypass
it close to the REF pin with a 4.7µF capacitor.
Output Data Format
The 12-bit-wide output format for both the MAX1295/
MAX1297 is binary in unipolar mode and two’s comple-
ment in bipolar mode. CS, RD, WR, INT, and the 12 bits
of output data can interface directly to a 16-bit data bus.
When reading the output data, CS and RD must be low.
V
. The DC input resistance at REF is 25kΩ.
__________Applications Information
Power-Down Modes
To save power, place the converter in a low-current
shutdown state between conversions. Select standby
mode or shutdown mode through bits D6 and D7 of the
control byte (Tables 1, 4). In both software power-down
modes the parallel interface remains active, but the
ADC does not convert.
Power-On Reset
When power is first applied, internal power-on reset cir-
cuitry activates the MAX1295/MAX1297 in external clock
mode and sets INT high. After the power supplies stabi-
lize, the internal reset time is 10µs; no conversions
should be attempted during this phase. When using the
internal reference, 500µs is required for V
to stabilize.
REF
Standby Mode
While in standby mode, the supply current is typically
850µA. The part will power up on the next rising edge
of WR and be ready to perform conversions. This quick
turn-on time allows the user to realize significantly
reduced power consumption for conversion rates
below 265ksps.
Internal and External Reference
The MAX1295/MAX1297 can be used with an internal
or external reference voltage. An external reference
can be connected directly to REF or REFADJ.
14 ______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
5/MAX1297
Table 5. Full-Scale and Zero-Scale for Unipolar and Bipolar Operation
UNIPOLAR MODE
BIPOLAR MODE
Positive Full Scale
Full Scale
Zero Scale
—
V
REF
+ COM
V
/2 + COM
COM
REF
COM
Zero Scale
—
Negative Full Scale
-V
/2 + COM
REF
OUTPUT CODE
REF
OUTPUT CODE
FULL-SCALE
TRANSITION
FS
=
+ COM
+ COM
011 . . . 111
2
FS = REF + COM
ZS = COM
111 . . . 111
011 . . . 110
ZS = COM
111 . . . 110
-REF
2
-FS =
000 . . . 010
000 . . . 001
000 . . . 000
100 . . . 010
100 . . . 001
100 . . . 000
REF
4096
1LSB =
REF
4096
1LSB =
111 . . . 111
111 . . . 110
111 . . . 101
011 . . . 111
011 . . . 110
011 . . . 101
100 . . . 001
100 . . . 000
000 . . . 001
000 . . . 000
COM*
INPUT VOLTAGE (LSB)
- FS
+FS - 1LSB
0
1
2
FS
2048
INPUT VOLTAGE (LSB)
(COM)
FS - 3/2LSB
≤
*COM
V
/2
REF
Figure 8. Unipolar Transfer Function
Figure 9. Bipolar Transfer Function
Shutdown Mode
Transfer Function
Shutdown mode turns off all chip functions that draw qui-
escent current, reducing the typical supply current to
2µA immediately after the current conversion is complet-
ed. A rising edge on WR causes the MAX1295/MAX1297
to exit shutdown mode and return to normal operation.
To achieve full 12-bit accuracy with a 4.7µF reference
bypass capacitor, 50µs is required after power-up.
Waiting this 50µs in standby mode instead of in full-
power mode can reduce power consumption by a factor
of 3 or more. When using an external reference, only
50µs is required after power-up. Enter standby mode by
performing a dummy conversion with the control byte
specifying standby mode.
Table 5 shows the full-scale voltage ranges for unipolar
and bipolar modes. Figure 8 depicts the nominal unipo-
lar input/output (I/O) transfer function, and Figure 9
shows the bipolar I/O transfer function. Code transitions
occur halfway between successive-integer LSB values.
Output coding is binary, with 1LSB = (V
/4096).
REF
Maximum Sampling Rate/
Achieving 300ksps
When running at the maximum clock frequency of
4.8MHz, the specified throughput of 265ksps is achieved
by completing a conversion every 18 clock cycles: 1
write cycle, 3 acquisition cycles, 13 conversion cycles,
and 1 read cycle. This assumes that the results of the
last conversion are read before the next control byte is
written. It is possible to achieve higher throughputs, up
to 300ksps, by first writing a control byte to begin the
Note: Bypass capacitors larger than 4.7µF between
REF and GND will result in longer power-up delays.
______________________________________________________________________________________ 15
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
WR
RD
D11–D0
CONTROL
WORD
D11–
D0
CONTROL WORD
CONVERSION
D7–D0
STATE
ACQUISITION
ACQUISITION
5/MAX1297
SAMPLING INSTANT
Figure 10. Timing Diagram for Fastest Conversion
ing of the data bus during acquisition or conversion can
cause additional supply noise, which may make it diffi-
cult to achieve true 12-bit performance.
SUPPLIES
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and don’t lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one “star point” (Figure 11) connecting the two ground
systems (analog and digital). For lowest noise opera-
tion, ensure the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.
+3V
+3V
GND
4.7µF
0.1µF
*R = 5Ω
V
GND
COM
+3V
DGND
DD
DIGITAL
CIRCUITRY
MAX1295
MAX1297
*OPTIONAL
High-frequency noise in the power supply, V , could
DD
impair operation of the ADC’s fast comparator. Bypass
Figure 11. Power-Supply and Grounding Connections
V
to the star ground with a network of two parallel
DD
capacitors, 0.1µF and 4.7µF, located as close as to the
MAX1295/MAX1297’s power-supply pin as possible.
Minimize capacitor lead length for best supply-noise
rejection and add an attenuation resistor (5Ω) if the
power supply is extremely noisy.
acquisition cycle of the next conversion, and then read-
ing the results of the previous conversion from the bus.
This technique (Figure 10) allows a conversion to be
completed every 16 clock cycles. Note that the switch-
16 ______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
5/MAX1297
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
_________________________Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1295/MAX1297 is measured using the end-
point method.
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals:
SINAD (dB) = 20 · log (Signal
/ Noise
)
RMS
RMS
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
Aperture Delay
Aperture delay (t ) is the time between the rising
AD
edge of the sampling clock and the instant when an
actual sample is taken.
2
2
2
2
THD = 20 log
V
+ V + V + V
/V
1
2
3
4
5
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum
analog-to-digital noise is caused by quantization error
only and results directly from the ADC’s resolution,
(N Bits):
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component.
SNR = (6.02 · N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
Chip Information
TRANSISTOR COUNT: 5781
SUBSTRATE CONNECTED TO GND
______________________________________________________________________________________ 17
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Circuits
CLK
CLK
+3V
+3V
MAX1297
V
MAX1295
V
DD
DD
+2.5V
+2.5V
CS
WR
RD
REF
CS
WR
RD
REF
µP
CONTROL
INPUTS
µP
CONTROL
INPUTS
0.1µF
0.1µF
REFADJ
REFADJ
INT
4.7µF
4.7µF
INT
OUTPUT STATUS
OUTPUT STATUS
D11
D10
D9
D11
D10
D9
D8
D8
D7
D6
D7
D6
CH5
CH4
D5
D4
D3
D5
D4
D3
5/MAX1297
CH3
CH2
CH1
ANALOG
INPUTS
CH1
D2
D2
ANALOG
INPUTS
CH0
CH0
D1
D0
D1
D0
COM
COM
GND
GND
µP DATA BUS
µP DATA BUS
18 ______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
5/MAX1297
Pin Configurations (continued)
TOP VIEW
D9
D8
D7
D6
D5
D4
D3
D2
D1
1
2
3
4
5
6
7
8
9
24 D10
23 D11
22
V
DD
21 REF
20 REFADJ
19 GND
18 COM
17 CH0
16 CH1
15 CS
MAX1297
D0 10
INT 11
RD 12
14 CLK
13 WR
QSOP
______________________________________________________________________________________ 19
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Package Information
5/MAX1297
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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MAXIM
MAX1295AEEI
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
MAXIM
MAX1295AEEI+
ADC, Successive Approximation, 12-Bit, 1 Func, 6 Channel, Parallel, Word Access, PDSO28, 0.150 INCH, QSOP-28
MAXIM
MAX1295BCEI
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
MAXIM
MAX1295BCEI+
ADC, Successive Approximation, 12-Bit, 1 Func, 6 Channel, Parallel, Word Access, PDSO28, 0.150 INCH, QSOP-28
MAXIM
MAX1295BCEI-T
ADC, Successive Approximation, 12-Bit, 1 Func, 6 Channel, Parallel, Word Access, PDSO28, 0.150 INCH, QSOP-28
MAXIM
MAX1295BEEI
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
MAXIM
MAX1295BEEI+T
ADC, Successive Approximation, 12-Bit, 1 Func, 6 Channel, Parallel, Word Access, PDSO28, 0.150 INCH, QSOP-28
MAXIM
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