MAX1282AEEE [MAXIM]
ADC, Successive Approximation, 12-Bit, 1 Func, 4 Channel, Serial Access, BICMOS, PDSO16, 4.40 MM, 0.65 MM PITCH, MO-153AC, TSSOP-16;
| 型号： | MAX1282AEEE |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 12-Bit, 1 Func, 4 Channel, Serial Access, BICMOS, PDSO16, 4.40 MM, 0.65 MM PITCH, MO-153AC, TSSOP-16 信息通信管理 光电二极管 转换器 |
| 文件： | 总23页 (文件大小：348K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1688; Rev 0; 5/00
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
General Description
Features
The MAX1282/MAX1283 12-bit analog-to-digital convert-
ers (ADCs) combine a 4-channel analog-input multiplexer,
high-bandwidth track/hold (T/H), and serial interface with
high conversion speed and low power consumption. The
MAX1282 operates from a single +4.5V to +5.5V supply;
the MAX1283 operates from a single +2.7V to +3.6V sup-
ply. Both devices’ analog inputs are software configurable
for unipolar/bipolar and single-ended/pseudo-differential
operation.
♦ 4-Channel Single-Ended or 2-Channel
Pseudo-Differential Inputs
♦ Internal Multiplexer and Track/Hold
♦ Single-Supply Operation
+4.5V to +5.5V (MAX1282)
+2.7V to +3.6V (MAX1283)
♦ Internal +2.5V Reference
The 4-wire serial interface connects directly to
SPI™/QSPI™/MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1282/
MAX1283 use an external serial-interface clock to perform
successive-approximation analog-to-digital conversions.
The devices feature an internal +2.5V reference and a ref-
erence-buffer amplifier with a 1.5ꢀ voltage-adꢁustment
♦ 400kHz Sampling Rate (MAX1282)
♦ Low Power: 2.5mA (400ksps)
1.3mA (REDP)
0.9mA (FASTPD)
2µA (FULLPD)
♦ SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire
Serial Interface
range. An external reference with a 1V to V
also be used.
range may
DD
♦ Software-Configurable Unipolar or Bipolar Inputs
♦ 16-Pin TSSOP Package
The MAX1282/MAX1283 provide a hardwired SHDN pin
and four software-selectable power modes (normal opera-
tion, reduced power (REDP), fast power-down (FASTPD),
and full power-down (FULLPD)). These devices can be
programmed to automatically shut down at the end of a
conversion or to operate with reduced power. When using
the power-down modes, accessing the serial interface
automatically powers up the devices, and the quick turn-
on time allows them to be shut down between all conver-
sions.
Ordering Information
TEMP.
RANGE
PIN-
PACKAGE
INL
(LSB)
PART
MAX1282BCUE
0°C to +70°C
16 TSSOP
16 TSSOP
16 TSSOP
16 TSSOP
1
1
1
1
MAX1282BEUE -40°C to +85°C
MAX1283BCUE 0°C to +70°C
MAX1283BEUE -40°C to +85°C
The MAX1282/MAX1283 are available in 16-pin TSSOP
packages.
Pin Configuration
Applications
Portable Data Logging
Data Acquisition
TOP VIEW
V
1
2
3
4
5
6
7
8
16
15 SCLK
CS
V
DD1
DD2
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
CH0
CH1
14
13 DIN
CH2
MAX1282/
MAX1283
Process Control
SSTRB
CH3
12
COM
SHDN
REF
11 DOUT
10 GND
9
REFADJ
Typical Operating Circuit appears at end of data sheet.
TSSOP
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
ABSOLUTE MAXIMUM RATINGS
V
V
_ to GND ........................................................... -0.3V to +6V
Continuous Power Dissipation (T = +70°C)
16-Pin TSSOP (derate 6.7mW/°C above +70°C) ........ 535mW
Operating Temperature Ranges
DD
DD1
A
to V
....................................................... -0.3V to +0.3V
DD2
CH0–CH3, COM to GND .......................... -0.3V to (V _ +0.3V)
DD
REF, REFADJ to GND................................ -0.3V to V _ +0.3V)
Digital Inputs to GND .............................................. -0.3V to +6V
MAX1282BCUE/MAX1283BCUE ....................... 0°C to +70°C
MAX1282BEUE/MAX1283BEUE..................... -40°C to +85°C
Storage Temperature Range............................ -60°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
DD
Digital Outputs to GND............................. -0.3V to (V _ +0.3V)
DD
Digital Output Sink Current .................................................25mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX1282
(V
= V
= +4.5V to +5.5V, COM = GND, f
= 6.4MHz, 50ꢀ duty cycle, 16 clocks/conversion cycle (400ksps), external
DD1
DD2
OSC
+2.5V at REF, REFADJ = V
, T = T
DD1
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
12
Bits
LSB
LSB
LSB
LSB
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
INL
1.0
1.0
6.0
6.0
DNL
No missing codes over temperature
Gain Error (Note 3)
Gain-Error Temperature
Coefficient
1.6
0.2
ppm/°C
LSB
Channel-to-Channel Offset-Error
Matching
DYNAMIC SPECIFICATIONS (100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode)
Signal-to-Noise plus Distortion
Ratio
SINAD
70
dB
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
THD
SFDR
IMD
Up to the 5th harmonic
= 99kHz, f =102kHz
-81
80
76
dB
dB
dB
f
IN1
IN2
Channel-to-Channel Crosstalk
(Note 4)
200kHz, V = 2.5Vp-p
IN
-78
dB
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Conversion Time (Note 5)
Track/Hold Acquisition Time
Aperture Delay
-3dB point
6
MHz
kHz
SINAD > 68dB
350
t
2.5
µs
ns
CONV
t
400
ACQ
10
ns
Aperture Jitter
<50
ps
Serial Clock Frequency
Duty Cycle
f
0.5
40
6.4
60
MHz
ꢀ
SCLK
2
_______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1282 (continued)
(V
= V
= +4.5V to +5.5V, COM = GND, f
= 6.4MHz, 50ꢀ duty cycle, 16 clocks/conversion cycle (400ksps), external
DD1
DD2
OSC
+2.5V at REF, REFADJ = V
, T = T
DD1
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS (CH3–CH0, COM)
Unipolar, V
= 0
V
REF
COM
Input Voltage Range, Single-
Ended and Differential (Note 6)
V
CH_
V
Bipolar, V
or V
= V
/2, referenced
REF
COM
CH_
V
/2
REF
to COM or CH_
On/off leakage current, V
, V
= 0 or
COM CH_
Multiplexer Leakage Current
µA
pF
0.001
18
1
V
DD1
Input Capacitance
INTERNAL REFERENCE
REF Output Voltage
V
REF
T
A
= +25°C
2.480
2.500 2.520
15
V
REF Short-Circuit Current
mA
REF Output Temperature
Coefficient
TC V
15
ppm/°C
REF
Load Regulation (Note 7)
Capacitive Bypass at REF
Capacitive Bypass at REFADJ
REFADJ Output Voltage
REFADJ Input Range
0 to 1mA output load
0.05
2.0
10
10
mV/mA
µF
4.7
0.01
µF
1.22
100
V
For small adꢁustments, from 1.22V
To power down the internal reference
mV
REFADJ Buffer Disable
Threshold
1.4
1.0
V
- 1.0
V
DD1
Buffer Voltage Gain
+2.05
200
V/V
EXTERNAL REFERENCE (reference buffer disabled, reference applied to REF)
V
+
DD1
50mV
REF Input Voltage Range
(Note 8)
V
V
V
= 2.500V, f
= 2.500V, f
= f
MAX
350
320
5
REF
SCLK
REF Input Current
= 0
µA
REF
SCLK
In full power-down mode, f
= 0
SCLK
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Leakage
V
3.0
V
V
INH
V
0.8
1
INL
V
0.2
15
V
HYST
I
V
IN
= 0 or V
DD2
µA
pF
IN
Input Capacitance
C
IN
DIGITAL OUTPUTS (DOUT, SSTRB)
Output Voltage Low
V
I
I
= 5mA
0.4
10
V
V
OL
SINK
Output Voltage High
V
OH
= 1mA
SOURCE
4
Three-State Leakage Current
I
µA
pF
CS = V
CS = V
L
DD2
DD2
Three-State Output Capacitance
C
15
OUT
_______________________________________________________________________________________
3
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1282 (continued)
(V
= V
= +4.5V to +5.5V, COM = GND, f
= 6.4MHz, 50ꢀ duty cycle, 16 clocks/conversion cycle (400ksps), external
DD1
DD2
OSC
+2.5V at REF, REFADJ = V
, T = T
DD1
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
POWER SUPPLY
Positive Supply Voltage
(Note 9)
V
DD1,
4.5
5.5
V
DD2
Normal operating mode (Note 10)
Reduced-power mode (Note 11)
Fast power-down mode (Note 11)
Full power-down mode (Note 11)
2.5
1.3
0.9
2.0
0.5
4.0
2.0
1.5
10
V
V
5.5V
=
=
DD1
DD2
mA
IV
IV
+
DD2
DD1
Supply Current
µA
Power-Supply Reꢁection
PSR
V
= V
= 5V 10ꢀ, midscale input
DD2
2.0
mV
DD1
ELECTRICAL CHARACTERISTICS—MAX1283
(V
= V
= +2.7V to +3.6V, COM = GND, f
= 4.8MHz, 50ꢀ duty cycle, 16 clocks/conversion cycle (300ksps), external
DD1
DD2
OSC
+2.5V at REF, REFADJ = V
, T = T
DD1
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
12
Bits
LSB
LSB
LSB
LSB
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
INL
1.0
1.0
6.0
6.0
DNL
No missing codes over temperature
Gain Error (Note 3)
Gain-Error Temperature
Coefficient
1.6
0.2
ppm/°C
LSB
Channel-to-Channel Offset-Error
Matching
DYNAMIC SPECIFICATIONS (100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode)
Signal-to-Noise plus Distortion
Ratio
SINAD
70
dB
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
THD
SFDR
IMD
Up to the 5th harmonic
= 73kHz, f = 77kHz
-70
72
76
dB
dB
dB
f
IN1
IN2
Channel-to-Channel Crosstalk
(Note 4)
f = 150kHz, V = 2.5Vp-p
IN
-78
dB
Full-Power Bandwidth
Full-Linear Bandwidth
-3dB point
3
MHz
kHz
SINAD > 68dB
250
4
_______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1283 (continued)
(V
= V
= +2.7V to +3.6V, COM = GND, f
= 4.8MHz, 50ꢀ duty cycle, 16 clocks/conversion cycle (300ksps), external
DD1
DD2
OSC
+2.5V at REF, REFADJ = V
, T = T
DD1
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
CONVERSION RATE
Conversion Time (Note 5)
SYMBOL
CONDITIONS
Normal operating mode
MIN
TYP
MAX
UNITS
t
3.3
µs
ns
CONV
Track/Hold Acquisition Time
Aperture Delay
t
Normal operating mode
625
ACQ
10
ns
Aperture Jitter
<50
ps
Serial Clock Frequency
Duty Cycle
f
Normal operating mode
0.5
40
4.8
60
MHz
ꢀ
SCLK
ANALOG INPUTS (CH3–CH0, COM)
Unipolar, V
= 0
V
REF
COM
Input Voltage Range, Single
Ended and Differential (Note 6)
V
V
CH_
Bipolar, V
or V
= V
REF
/2,
COM
CH_
V
REF
/2
referenced to COM or CH_
Multiplexer Leakage Current
Input Capacitance
On/off leakage current, V
= 0 or V
µA
pF
0.001
18
1
CH_
DD1
INTERNAL REFERENCE
REF Output Voltage
V
T
A
= +25°C
2.480
2.500 2.520
15
V
REF
REF Short-Circuit Current
mA
REF Output Temperature
Coefficient
TC V
15
ppm/°C
REF
Load Regulation (Note 7)
Capacitive Bypass at REF
Capacitive Bypass at REFADJ
REFADJ Output Voltage
REFADJ Input Range
0 to 0.75mA output load
0.1
2.0
10
10
mV/mA
µF
4.7
0.01
µF
1.22
100
V
For small adꢁustments, from 1.22V
To power down the internal reference
mV
REFADJ Buffer Disable
Threshold
1.4
1.0
V
- 1.0
V
DD1
Buffer Voltage Gain
2.05
V/V
EXTERNALREFERENCE (reference buffer disabled, reference applied to REF)
V
+
DD1
50mV
REF Input Voltage Range
(Note 8)
V
V
V
= 2.500V, f
= 2.500V, f
= f
MAX
200
350
320
5
REF
REF
SCLK
REF Input Current
= 0
µA
SCLK
In full power-down mode, f
= 0
SCLK
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Leakage
V
2.0
V
V
INH
V
0.8
1
INL
V
0.2
15
V
HYST
I
V
= 0 or V
DD2
µA
pF
IN
IN
Input Capacitance
C
IN
_______________________________________________________________________________________
5
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1283 (continued)
(V
= V
= +2.7V to +3.6V, COM = GND, f
= 4.8MHz, 50ꢀ duty cycle, 16 clocks/conversion cycle (300ksps), external
DD1
DD2
OSC
+2.5V at REF, REFADJ = V
, T = T
DD1
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.4
UNITS
DIGITAL OUTPUTS (DOUT, SSTRB)
Output Voltage Low
V
I
I
= 5mA
V
V
OL
SINK
Output Voltage High
V
= 0.5mA
V
- 0.5V
DD2
OH
SOURCE
Three-State Leakage Current
I
10
µA
pF
CS = V
CS = V
L
DD2
DD2
Three-State Output Capacitance
C
15
OUT
POWER SUPPLY
Positive Supply Voltage
(Note 9)
V
DD1,
2.7
3.6
V
V
DD2
Normal operating mode (Note 10)
Reduced-power mode (Note 11)
Fast power-down mode (Note 11)
Full power-down mode (Note 11)
2.5
1.3
0.9
2.0
0.5
3.5
2.0
1.5
10
V
V
3.6V
=
=
DD1
DD2
mA
Supply Current
IV
DD1 +
IV
DD2
µA
Power-Supply Reꢁection
PSR
V
= V
= 2.7V to 3.6V, midscale input
DD2
2.0
mV
DD1
TIMING CHARACTERISTICS—MAX1282
(Figures 1, 2, 5, 6; V
= V
= +4.5V to +5.5V, T = T
A
to T
, unless otherwise noted.)
MAX
DD1
DD2
MIN
PARAMETER
SCLK Period
SYMBOL
CONDITIONS
MIN
156
62
62
35
0
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CP
CH
SCLK Pulse Width High
SCLK Pulse Width Low
DIN to SCLK Setup
DIN to SCLK Hold
t
t
CL
DS
DH
t
t
t
t
35
0
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Rise to CS Fall Ignore
CS Rise to SCLK Rise Ignore
SCLK Rise to DOUT Hold
SCLK Rise to SSTRB Hold
SCLK Rise to DOUT Valid
SCLK Rise to SSTRB Valid
CS Rise to DOUT Disable
CS Rise to SSTRB Disable
CS Fall to DOUT Enable
CS Fall to SSTRB Enable
CS Pulse Width High
CSS
CSH
CSO
t
35
35
10
10
t
CS1
t
t
t
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
20
20
DOH
t
STH
80
80
65
65
65
65
DOV
t
STV
10
10
DOD
t
STD
t
DOE
t
STE
t
100
CSW
6
_______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
TIMING CHARACTERISTICS—MAX1283
(Figures 1, 2, 5, 6; V
= V
= +2.7V to +3.6V, T = T
A
to T
, unless otherwise noted.)
MAX
DD1
DD2
MIN
PARAMETER
SCLK Period
SYMBOL
CONDITIONS
MIN
208
83
83
45
0
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CP
CH
SCLK Pulse Width High
SCLK Pulse Width Low
DIN to SCLK Setup
DIN to SCLK Hold
t
t
CL
DS
DH
t
t
t
t
45
0
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Rise to CS Fall Ignore
CS Rise to SCLK Rise Ignore
SCLK Rise to DOUT Hold
SCLK Rise to SSTRB Hold
SCLK Rise to DOUT Valid
SCLK Rise to SSTRB Valid
CS Rise to DOUT Disable
CS Rise to SSTRB Disable
CS Fall to DOUT Enable
CS Fall to SSTRB Enable
CS Pulse Width High
CSS
CSH
CSO
t
45
45
13
13
t
CS1
t
t
t
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
20
20
DOH
t
STH
100
100
85
DOV
t
STV
13
13
DOD
t
85
STD
t
85
DOE
t
85
STE
t
100
CSW
Note 1: Tested at V
= V
= V
, COM = GND, unipolar single-ended input mode.
DD(MIN)
DD1
DD2
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Offset nulled.
Note 4: Ground the “on” channel; sine wave is applied to all “off” channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50ꢀ duty cycle.
Note 6: The common-mode range for the analog inputs (CH3–CH0 and COM) is from GND to V
Note 7: External load should not change during conversion for specified accuracy.
.
DD1
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p. An external reference below 2.5V compro-
mises the performance of the ADC.
Note 9: Electrical characteristics are guaranteed from V
= V
to V
= V
. For operations beyond
DD2(MIN)
DD1(MIN)
DD2(MIN)
DD1(MAX)
this range, see Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory.
Note 10: AIN = midscale, unipolar mode. MAX1282 tested with 20pF on DOUT, 20pF on SSTRB, and f = 6.4MHz, 0 to 5V.
SCLK
MAX1283 tested with same loads, f
= 4.8MHz, 0 to 3V.
SCLK
Note 11: SCLK = DIN = GND, CS = V
.
DD1
_______________________________________________________________________________________
7
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Typical Operating Characteristics
(MAX1282: V
= V
= 5.0V, f
= 6.4MHz; MAX1283: V
= V
= 3.0V, f
= 4.8MHz; C
= 20pF, 4.7µF capacitor
LOAD
DD1
DD2
SCLK
DD1
DD2
SCLK
at REF, 0.01µF capacitor at REFADJ, T = +25°C, unless otherwise noted.)
A
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
SUPPLY CURRENT vs. SUPPLY
VOLTAGE (CONVERTING)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.4
0.3
0.5
0.4
0.3
0.2
0.1
0
3.5
3.0
2.5
2.0
0.2
0.1
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
-0.4
-0.4
-0.5
1.5
2.5
0
500 1000 1500 2000 2500 3000 3500 4000 4500
DIGITAL OUTPUT CODE
3.0
3.5
4.0
4.5
5.0
5.5
0
500 1000 1500 2000 2500 3000 3500 4000 4500
DIGITAL OUTPUT CODE
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY
VOLTAGE (STATIC)
SUPPLY CURRENT vs. TEMPERATURE
(STATIC)
SUPPLY CURRENT vs. TEMPERATURE
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
3.2
3.0
2.8
2.6
2.4
2.2
2.0
MAX1282 (PD1 = 1, PD0 = 1)
MAX1283 (PD1 = 1, PD0 = 1)
MAX1282 (PD1 = 1, PD0 = 0)
MAX1283 (PD1 = 1, PD0 = 0)
NORMAL OPERATION (PD1 = PD0 = 1)
REDP (PD1 = 1, PD0 = 0)
MAX1282
FASTDP (PD1 = 0, PD0 = 1)
MAX1283
MAX1282 (PD1 = 0, PD0 = 1)
MAX1283 (PD1 = 0, PD0 = 1)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
2.5
2.0
1.5
1.0
0.5
0
5
4
3
2
1
0
2.5005
2.5003
2.5001
2.4999
2.4997
2.4995
(PD1 = PD0 = 0)
MAX1282
(PD1 = PD0 = 0)
MAX1283
-40 -20
0
20
40
60
80 100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
8
_______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Typical Operating Characteristics (continued)
(MAX1282: V
= V
= 5.0V, f
= 6.4MHz; MAX1283: V
= V
= 3.0V, f
= 4.8MHz; C
= 20pF, 4.7µF capacitor
LOAD
DD1
DD2
SCLK
DD1
DD2
SCLK
at REF, 0.01µF capacitor at REFADJ, T = +25°C, unless otherwise noted.)
A
REFERENCE VOLTAGE
vs. TEMPERATURE
OFFSET ERROR vs. SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
2.0
1.5
0.5
0
2.5002
2.5000
2.4998
2.4996
2.4994
2.4992
2.4990
2.4988
MAX1282
MAX1283
1.0
0.5
-0.5
-1.0
-1.5
-2.0
-2.5
0
-0.5
-1.0
-1.5
-2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
-40 -20
0
20
40
60
80 100
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
GAIN ERROR vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
0.5
0
1.0
0.8
0.6
0.4
0.2
0
-0.5
-1.0
-1.5
-2.0
-0.2
-0.4
-0.6
-0.8
-1.0
-40
-15
10
35
60
85
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
9
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Pin Description
PIN
1
NAME
FUNCTION
V
Positive Supply Voltage
Sampling Analog Inputs
DD1
2–5
CH0–CH3
COM
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to 0.5LSB.
6
7
SHDN
Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2µA (typ).
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
internal reference mode, the reference buffer provides a 2.500V nominal output, externally adꢁustable at
8
REF
REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to V
.
DD1
9
REFADJ
GND
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, connect REFADJ to V
.
DD1
10
11
Ground
DOUT
Serial-Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high.
Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High impedance
when CS is high.
12
13
14
SSTRB
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT and
SSTRB are high impedance.
CS
Serial-Clock Input. Clocks data in and out of serial interface and sets the conversion speed. (Duty cycle
must be 40ꢀ to 60ꢀ.)
15
16
SCLK
V
Positive Supply Voltage
DD2
V
DD2
V
DD2
3k
3k
DOUT
DOUT
DOUT
DOUT
C
70pF
C
LOAD
20pF
LOAD
C
50pF
C
LOAD
50pF
LOAD
3k
3k
GND
GND
GND
a) High-Z to V and V to V
OH
GND
b) High-Z to V and V to V
OL
a) V to High-Z
OH
b) V to High-Z
OL
OH
OL
OL
OH
Figure 1. Load Circuits for Enable Time
10 ______________________________________________________________________________________
Figure 2. Load Circuits for Disable Time
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
sinusoidal signal at IN-, the input voltage is determined
Detailed Description
by:
The MAX1282/MAX1283 ADCs use a successive-
approximation conversion technique and input T/H cir-
ν
− = V − sin(2πft)
IN
(
)
cuitry to convert an analog signal to a 12-bit digital out-
put. A flexible serial interface provides easy interface to
microprocessors (µPs). Figure 3 shows a functional dia-
gram of the MAX1282/MAX1283.
IN
The maximum voltage variation is determined by:
d ν
−
(
)
= V − 2πf ≤
1LSB
t
CONV
V
REF
IN
max
=
IN
12
dt
Pseudo-Differential Input
The equivalent circuit of Figure 4 shows the MAX1282/
MAX1283’s input architecture, which is composed of a
T/H, input multiplexer, input comparator, switched-
capacitor DAC, and reference.
2
t
CONV
A 0.65Vp-p, 60Hz signal at IN- will generate a 0.5LSB
error when using a +2.5V reference voltage and a
2.5µs conversion time (15 / f
). When a DC refer-
SCLK
ence voltage is used at IN-, connect a 0.1µF capacitor
to GND to minimize noise at the input.
In single-ended mode, the positive input (IN+) is con-
nected to the selected input channel and the negative
input (IN-) is set to COM. In differential mode, IN+ and
IN- are selected from the following pairs: CH0/CH1 and
CH2/CH3. Configure the channels according to Tables
1 and 2.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
. The
HOLD
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit has been entered. At the end of the acquisition
interval, the T/H switch opens, retaining charge on
The MAX1282/MAX1283 input configuration is pseudo-
differential because only the signal at IN+ is sampled.
The return side (IN-) is connected to the sampling
capacitor while converting and must remain stable
within 0.5LSB ( 0.1LSB for best results) with respect
to GND during a conversion.
C
as a sample of the signal at IN+. The conver-
HOLD
sion interval begins with the input multiplexer switching
from IN+ to IN-. This unbalances node ZERO at
C
HOLD
the comparator’s input. The capacitive DAC adꢁusts
during the remainder of the conversion cycle to restore
If a varying signal is applied to the selected IN-, its
amplitude and frequency must be limited to maintain
accuracy. The following equations express the relation-
ship between the maximum signal amplitude and its
frequency to maintain 0.5LSB accuracy. Assuming a
node ZERO to V
/ 2 within the limits of 12-bit resolu-
DD1
tion. This action is equivalent to transferring a
✕
12pF (V + - V -) charge from C
to the binary-
IN
IN
HOLD
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
14
15
GND
CS
SCLK
CAPACITIVE
DAC
REF
INPUT
MUX
INPUT
SHIFT
REGISTER
INT
CLOCK
13
7
DIN
CONTROL
LOGIC
C
12pF
HOLD
CH0
CH1
SHDN
COMPARATOR
ZERO
2
3
4
5
11
12
CH2
CH3
CH0
CH1
CH2
CH3
OUTPUT
SHIFT
DOUT
C
*
SWITCH
R
IN
800Ω
REGISTER
SSTRB
COM
6pF
ANALOG
INPUT
MUX
T/H
TRACK
CLOCK
HOLD
IN
AT THE SAMPLING INSTANT,
12-BIT
SAR ADC
THE MUX INPUT SWITCHES FROM
THE SELECTED IN+ CHANNEL TO
THE SELECTED IN- CHANNEL.
OUT
1
REF
V
V
DD1
DD2
6
COM
16
≈
A
2.05
V
/2
DD1
+1.22V
REFERENCE
17k
SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM.
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM
PAIRS OF CH0/CH1 AND CH2/CH3.
10
GND
9
8
REFADJ
REF
MAX1282
MAX1283
+2.500V
*INCLUDES ALL INPUT PARASITICS
Figure 3. Functional Diagram
Figure 4. Equivalent Input Circuit
______________________________________________________________________________________ 11
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Table 1. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
COM
0
0
1
+
–
1
0
1
0
1
1
1
0
0
+
–
–
–
+
+
Table 2. Channel Selection in Pseudo-Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
0
0
1
1
0
1
0
1
1
0
1
0
+
–
+
–
–
+
–
+
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using under-
sampling techniques. To avoid high-frequency signals
being aliased into the frequency band of interest, anti-
alias filtering is recommended.
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, the difference of IN+) - (IN-) is con-
Analog Input Protection
Internal protection diodes, which clamp the analog input
to V
and GND, allow the channel input pins to swing
DD1
[(
]
from GND - 0.3V to V
+ 0.3V without damage.
DD1
verted. At the end of the conversion, the positive input
However, for accurate conversions near full scale, the
inputs must not exceed V
lower than GND by 50mV.
connects back to IN+ and C
signal.
charges to the input
HOLD
by more than 50mV or be
DD1
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
If the analog input exceeds 50mV beyond the sup-
plies, do not allow the input current to exceed 2mA.
Starting a Conversion
Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX1282/MAX1283’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 3 shows the control-byte format.
t
, is the maximum time the device takes to acquire
ACQ
the signal and the minimum time needed for the signal
to be acquired. It is calculated by the following equa-
tion:
✕
✕
t
= 9 (R + R ) 18pF
S IN
ACQ
where R = 800Ω and R = the source impedance of
IN
S
the input signal; t
is never less than 400ns
The MAX1282/MAX1283 are compatible with SPI/
QSPI/MICROWIRE devices. For SPI, select the correct
clock polarity and sampling edge in the SPI control reg-
isters: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI,
and QSPI all transmit a byte and receive a byte at the
same time. Using the Typical Operating Circuit, the sim-
plest software interface requires only three 8-bit transfers
to perform a conversion (one 8-bit transfer to configure
the ADC, and two more 8-bit transfers to clock out the
ACQ
(MAX1282) or 625ns (MAX1283). Note that source
impedances below 2kΩ do not significantly affect the
ADC’s AC performance.
Input Bandwidth
The ADC’s input tracking circuitry has a 6MHz
(MAX1282) or 3MHz (MAX1283) small-signal band-
width, so it is possible to digitize high-speed transient
12 ______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
conversion result). (See Figure 16 for MAX1282/
MAX1283 QSPI connections.)
Data Framing
The falling edge of CS does not start a conversion.
The first logic high clocked into DIN is interpreted as a
start bit and defines the first bit of the control byte. A
conversion starts on SCLK’s falling edge, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as follows:
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 500kHz to 6.4MHz (MAX1282) or
4.8MHz (MAX1283).
The first high bit clocked into DIN with CS low any
1) Set up the control byte and call it TB1. TB1 should
be in the format: 1XXXXXXX binary, where the Xs
denote the particular channel, selected conversion
mode, and power mode.
time the converter is idle, e.g., after V
are applied.
and V
DD2
DD1
or
The first high bit clocked into DIN after B6 of a con-
version in progress is clocked onto the DOUT pin
(Figure 7).
2) Use a general-purpose I/O line on the CPU to pull
CS low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
Once a start bit has been recognized, the current conver-
sion may only be terminated by pulling SHDN low.
4) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.
The fastest the MAX1282/MAX1283 can run with CS held
low between conversions is 16 clocks per conversion.
Figure 7 shows the serial-interface timing necessary to
perform a conversion every 16 SCLK cycles. If CS is tied
low and SCLK is continuous, guarantee a start bit by first
clocking in 16 zeros.
5) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.
6) Pull CS high.
Figure 5 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with three leading zeros, and one trailing zero. The total
conversion time is a function of the serial-clock fre-
quency and the amount of idle time between 8-bit
transfers. To avoid excessive T/H droop, make sure the
total conversion time does not exceed 120µs.
___________Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1282/MAX1283 in normal operating mode, ready to
convert with SSTRB = low. After the power supplies sta-
bilize, the internal reset time is 10µs, and no conver-
sions should be performed during this phase. If CS is
low, the first logic 1 on DIN is interpreted as a start bit.
Until a conversion takes place, DOUT shifts out zeros.
Additionally, wait for the reference to stabilize when
using the internal reference.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 13). For bipolar input mode, the output is two’s
complement (Figure 14). Data is clocked out on the ris-
ing edge of SCLK in MSB-first format.
Serial Clock
The external clock not only shifts data in and out, but it
also drives the analog-to-digital conversion steps.
SSTRB pulses high for one clock period after the last bit
of the control byte. Successive-approximation bit deci-
sions are made and appear at DOUT on each of the
next 12 SCLK rising edges, MSB first (Figure 5). SSTRB
and DOUT go into a high-impedance state when CS
goes high; after the next CS falling edge, SSTRB out-
puts a logic low. Figure 6 shows the detailed serial-inter-
face timings.
Power Modes
Save power by placing the converter in one of two low-
current operating modes or in full power-down between
conversions. Select the power-down mode through bit
1 and bit 0 of the DIN control byte (Tables 3 and 4), or
force the converter into hardware shutdown by driving
SHDN to GND.
The software power-down modes take effect after the
conversion is completed; SHDN overrides any software
power mode and immediately stops any conversion in
progress. In software power-down mode, the serial
interface remains active while waiting for a new control
byte to start conversion and switch to full-power mode.
The conversion must complete in 120µs or less, or
droop on the sample-and-hold capacitors may degrade
conversion results.
______________________________________________________________________________________ 13
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Table 3. Control-Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
BIT
NAME
DESCRIPTION
7(MSB)
START
The first logic 1 bit after CS goes low defines the beginning of the control byte.
6
5
4
SEL2
SEL1
SEL0
These three bits select which of the eight channels are used for the conversion (Tables 1 and 2).
3
UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0 to V
can be converted; in bipolar mode, the differential signal can
REF
range from -V /2 to +V /2.
REF REF
2
SGL/DIF
1 = single ended, 0 = pseudo-differential. Selects single-ended or pseudo-differential conver-
sions. In single-ended mode, input signal voltages are referred to COM. In pseudo-differential
mode, the voltage difference between two channels is measured (Tables 1 and 2).
1
PD1
PD0
Select operating mode.
0(LSB)
PD1
PD0
Mode
0
0
1
1
0
1
0
1
Full power-down
Fast power-down
Reduced power
Normal operation
Table 4. Software-Controlled Power Modes
TOTAL SUPPLY CURRENT
CIRCUIT SECTIONS*
PD1/PD0
MODE
CONVERTING
AFTER
INPUT COMPARATOR
REFERENCE
(mA)
CONVERSION
Full Power-Down
(FULLPD)
00
01
2.5
2µA
Off
Off
Fast Power-Down
(FASTPD)
2.5
0.9mA
Reduced Power
On
Reduced-Power
Mode (REDP)
10
11
2.5
2.5
1.3mA
2.0mA
Reduced Power
Full Power
On
On
Normal Operating
*Circuit operation between conversions; during conversion all circuits are fully powered up.
Once conversion is completed, the device goes into the
programmed power mode until a new control byte is
written.
convert after 2µs when using an external reference.
When using the internal reference, wait for the typical
power-up delay from a full power-down (software or
hardware) as shown in Figure 8.
The power-up delay is dependent on the power-down
state. Software low-power modes will be able to start
conversion immediately when running at decreased
clock rates (see Power-Down Sequencing). Upon
power-on reset, when exiting software full power-down
mode, or when exiting hardware shutdown, the device
goes immediately into full-power mode and is ready to
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. When software power-down is
asserted, the ADC completes the conversion in
14 ______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
CS
t
ACQ
SCLK
DIN
1
4
8
9
12
16
20
24
SEL SEL SEL UNI/ SGL/
PD2 PD2
2
1
0
BIP DIF
START
SSTRB
RB1
RB2
B11 B10 B9 B8 B7
RB3
B5 B4 B3 B2 B1 B0
B6
DOUT
IDLE
400ns
(CLK = 6.4MHz)
CONVERSION
IDLE
A/D STATE
Figure 5. Single-Conversion Timing
progress and powers down into the specified low-qui-
escent-current state (2µA, 0.9mA, or 1.3mA).
and power-down modes may attain the lowest power
consumption in other applications.
The first logic 1 on DIN is interpreted as a start bit and
puts the MAX1282/MAX1283 into its full-power mode.
Following the start bit, the data input word or control
byte also determines the next power-down state. For
example, if the DIN word contains PD1 = 0 and PD0 = 1,
a 0.9mA power-down resumes after one conversion.
Table 4 details the four power modes with the corre-
sponding supply current and operating sections.
Using Full Power-Down Mode
Full power-down mode (FULLPD) achieves the lowest
power consumption, up to 1000 conversions per chan-
nel per second. Figure 9a shows the MAX1283’s power
consumption for one- or four-channel conversions utiliz-
ing full power-down mode (PD1 = PD0 = 0), with the
internal reference and conversion controlled at the
maximum clock speed. A 0.01µF bypass capacitor at
REFADJ forms an RC filter with the internal 17kΩ refer-
ence resistor, with a 170µs time constant. To achieve
full 12-bit accuracy, nine time constants or 1.5ms are
required after power-up if the bypass capacitor is fully
discharged between conversions. Waiting this 1.5ms
duration in fast power-down (FASTPD) or reduced-
power (REDP) mode instead of in full power-up can fur-
ther reduce power consumption. This is achieved by
using the sequence shown in Figure 11a.
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down. Unlike software power-down mode, the
conversion is not completed; it stops coincidentally with
SHDN being brought low. When returning to normal
operation—from SHDN, with an external reference—the
MAX1282/MAX1283 can be considered fully powered
up within 2µs of actively pulling SHDN high. When
using the internal reference, the conversion should be
initiated only when the reference has settled; its recov-
ery time is dependent on the external bypass capaci-
tors and the time between conversions.
Figure 9b shows the MAX1283’s power consumption for
one- or four-channel conversions utilizing FULLPD
mode (PD1 = PD0 = 0), with an external reference and
conversion controlled at the maximum clock speed.
One dummy conversion to power up the device is
needed, but no waiting time is necessary to start the
second conversion, thereby achieving lower power
consumption as low as half the full sampling rate.
Power-Down Sequencing
The MAX1282/MAX1283 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. Figures 9 and 10 show the
average supply current as a function of the sampling
rate. The following sections discuss the various power-
down sequences. Other combinations of clock rates
______________________________________________________________________________________ 15
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
CS
t
CSW
t
t
CP
t
CSH
CSS
t
CH
t
t
CS1
t
CL
CSO
#10
SCLK
t
DH
t
DS
t
DOH
DIN
t
t
DOV
DOD
t
DOE
DOUT
t
STH
t
t
STD
STV
t
STE
SSTRB
Figure 6. Detailed Serial-Interface Timing
Using Fast Power-Down
and Reduced-Power Modes
An internal buffer is designed to provide 2.5V at
REF for the MAX1282/MAX1283. The internally trimmed
1.22V reference is buffered with a 2.05 gain.
FASTPD and REDP modes achieve the lowest power
consumption at speeds close to the maximum sampling
rate. Figure 10 shows the MAX1283’s power
consumption in FASTPD mode (PD1 = 0, PD0 = 1),
REDP mode (PD1 = 1, PD0 = 0), and, for comparison,
normal operating mode (PD1 = 1, PD0 = 1). The figure
shows power consumption using the specified power-
down mode, with the internal reference and conversion
controlled at the maximum clock speed. The clock
speed in FASTPD or REDP should be limited to 4.8MHz
for the MAX1282/MAX1283. FULLPD mode may provide
increased power savings in applications where the
MAX1282/MAX1283 are inactive for long periods of time,
but intermittent bursts of high-speed conversions are
required. Figure 11b shows FASTPD and REDP timing.
Internal Reference
The MAX1282/MAX1283’s full-scale range with the inter-
nal reference is 2.5V with unipolar inputs and 1.25V
with bipolar inputs. The internal reference voltage is
adꢁustable by 100mV with the circuit in Figure 12.
External Reference
The MAX1282/MAX1283’s external reference can be
placed at the input (REFADJ) or the output (REF) of the
internal reference-buffer amplifier. The REFADJ input
impedance is typically 17kΩ. At REF, the DC input
resistance is a minimum of 18kΩ. During conversion, an
external reference at REF must deliver up to 350µA DC
load current and have 10Ω or less output impedance. If
the reference has a higher output impedance or is
noisy, bypass it close to the REF pin with a 4.7µF
capacitor.
Internal and External References
The MAX1282/MAX1283 can be used with an internal
or external reference voltage. An external reference
can be connected directly at REF or at the REFADJ pin.
Table 5. Full Scale and Zero Scale
UNIPOLAR MODE
BIPOLAR MODE
Positive
Full Scale
Zero
Scale
Negative
Full Scale
Full Scale
+ V
Zero Scale
V
/ 2
V
/ 2
REF
REF
V
V
COM
V
COM
REF
COM
+ V
+ V
COM
COM
16 ______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
CS
DIN
S
CONTROL BYTE 0
S
CONTROL BYTE 1
S
CONTROL BYTE 2
S
ETC
1
8
12
16 1
5
8
12
16 1
5
8
12
16 1
5
SCLK
B11
B6
CONVERSION RESULT 0
B0
B11
B6
CONVERSION RESULT 1
B0
B11
B6
DOUT
SSTRB
Figure 7. Continuous 16-Clock/Conversion Timing
10k
1.50
1.25
1.00
0.75
0.50
0.25
0
MAX1283, V = V
= 3.0V
DD 2
DD1
C
LOAD
= 20pF
CODE = 101010000000
1k
100
10
4 CHANNELS
1 CHANNEL
1
1
10
100
1k
10k
100k
0.0001 0.001
0.01
0.1
1
10
SAMPLING RATE (sps)
TIME IN SHUTDOWN (s)
Figure 8. Reference Power-Up Delay vs. Time in Shutdown
Figure 9b. Average Supply Current vs. Conversion Rate with
External Reference in FULLPD
1k
2.5
MAX1283, V = V = 3.0V
DD1
DD2
NORMAL OPERATION
C
= 20pF
LOAD
CODE = 101010000000
2.0
100
REDP
FASTPD
1.5
1.0
4 CHANNELS
10
1
1 CHANNEL
MAX1283, V = V = 3.0V
DD1
DD2
C
LOAD
= 20pF
CODE = 101010000000
0.5
50
200
SAMPLING RATE (sps)
0.1
1
10
100
1k
10k
150
250
0
100
300 350
SAMPLING RATE (sps)
Figure 9a. Average Supply Current vs. Conversion Rate with
Internal Reference in FULLPD
Figure 10. Average Supply Current vs. Sampling Rate (in
FASTPD, REDP, and Normal Operation)
______________________________________________________________________________________ 17
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
To use the direct REF input, disable the internal buffer by
Figure 15 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND. Connect all other analog
grounds to the star ground. Connect the digital system
ground to this ground only at this point. For lowest-
noise operation, the ground return to the star ground’s
power supply should be low impedance and as short
as possible.
connecting REFADJ to V
. Using the REFADJ input
DD1
makes buffering the external reference unnecessary.
Transfer Function
Table 5 shows the full-scale voltage ranges for unipolar
and bipolar modes.
Figure 13 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 14 shows the bipolar
I/O transfer function. Code transitions occur halfway
between successive-integer LSB values. Output coding
is binary, with 1LSB = 0.61mV (2.500V / 4096) for unipo-
lar operation, and 1LSB = 0.61mV [(2.500V / 2) / 4096]
for bipolar operation.
High-frequency noise in the V
power supply may
DD1
affect the high-speed comparator in the ADC. Bypass
the supply to the star ground with 0.1µF and 10µF
capacitors close to V
of the MAX1282/MAX1283.
DD1
Minimize capacitor lead lengths for best supply-noise
reꢁection. If the power supply is very noisy, a 10Ω resis-
tor can be connected as a lowpass filter (Figure 15).
Layout, Grounding, and Bypassing
For best performance, use PC boards; wire-wrap
boards are not recommended. Board layout should
ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital (espe-
cially clock) lines parallel to one another, or digital lines
underneath the ADC package.
High-Speed Digital Interfacing with QSPI
The MAX1282/MAX1283 can interface with QSPI using
the circuit in Figure 16 (CPOL = 0, CPHA = 0). This
QSPI circuit can be programmed to do a conversion on
each of the four channels. The result is stored in memory
without taxing the CPU, since QSPI incorporates its own
microsequencer.
WAIT 2ms (10 x RC)
0
0
1
0
0
0
1
1
1
1
DIN
FULLPD
REDP
FULLPD
1.22V
DUMMY CONVERSION
1.22V
2.5V
RE FADJ
0V
0V
γ = RC = 17kΩ x 0.01µF
2.5V
REF
2.5mA
2.5mA
2.5mA
I
+ I
VDD1 VDD2
1.3mA OR 0.9mA
0mA
0mA
Figure 11a. Full Power-Down Timing
1
0
1
0
0
1
1
1
1
DIN
REDP
REDP
FASTPD
2.5mA
2.5V (ALWAYS ON)
2.5mA
REF
2.5mA
1.3mA
0.9mA
0.9mA
IV
+ IV
DD2
DD1
Figure 11b. FASTPD and REDP Timing
18 ______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
+3.3V
OUTPUT CODE
24k
V
REF
2
FS
=
+ V
COM
011 . . . 111
011 . . . 110
MAX1282
MAX1283
ZS = V
-FS =
510k
COM
100k
REFADJ
-V
REF
2
12
+ V
COM
000 . . . 010
000 . . . 001
000 . . . 000
V
REF
1LSB =
0.047µF
4096
111 . . . 111
111 . . . 110
111 . . . 101
Figure 12. MAX1282/MAX1283 Reference-Adjust Circuit
OUTPUT CODE
100 . . . 001
100 . . . 000
FULL-SCALE
TRANSITION
11 . . . 111
COM*
INPUT VOLTAGE (LSB)
- FS
+FS - 1LSB
11 . . . 110
11 . . . 101
≤
V
*V
COM
/ 2
REF
Figure 14. Bipolar Transfer Function, Full Scale (FS) =
/ 2 + V , Zero Scale (ZS) = V
FS = V + V
REF
COM
V
REF
COM
COM
ZS = V
1LSB =
COM
V
REF
4096
2) The MAX1282/MAX1283’s CS pin is driven low by the
TMS320’s XF_ I/O port to enable data to be clocked
into the MAX1282/MAX1283’s DIN pin.
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
3) An 8-bit word (1XXXXX11) should be written to the
MAX1282/MAX1283 to initiate a conversion and
place the device into normal operating mode. See
Table 3 to select the proper XXXXX bit values for your
specific application.
0
1
2
3
FS
(COM)
FS - 3/2LSB
INPUT VOLTAGE (LSB)
Figure 13. Unipolar Transfer Function, Full Scale (FS) =
+ V , Zero Scale (ZS) = V
4) The MAX1282/MAX1283’s SSTRB output is moni-
tored through the TMS320’s FSR input. A falling
edge on the SSTRB output indicates that the conver-
sion is in progress and data is ready to be received
from the device.
V
REF
COM
COM
TMS320LC3x Interface
Figure 17 shows an application circuit to interface the
MAX1282/MAX1283 to the TMS320 in external clock
mode. The timing diagram for this interface circuit is
shown in Figure 18.
5) The TMS320 reads in 1 data bit on each of the next
16 rising edges of SCLK. These data bits represent
the 12-bit conversion result followed by 4 trailing bits,
which should be ignored.
Use the following steps to initiate a conversion in the
MAX1282/MAX1283 and to read the results:
6) Pull CS high to disable the MAX1282/MAX1283 until
the next conversion is initiated.
1) The TMS320 should be configured with CLKX (trans-
mit clock) as an active-high output clock and CLKR
(TMS320 receive clock) as an active-high input clock.
CLKX and CLKR on the TMS320 are connected to
the MAX1282/MAX1283’s SCLK input.
______________________________________________________________________________________ 19
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the SNR is the ratio of the full-scale analog
input (RMS value) to the RMS quantization error (resid-
ual error). The ideal, theoretical minimum analog-to-dig-
ital noise is caused only by quantization error and
results directly from the ADC’s resolution (N bits):
SUPPLIES
+3V
+3V
GND
✕
SNR = (6.02 N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock ꢁitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
*R = 10Ω
V
GND
COM
V
DD2
+3V
DGND
DD1
DIGITAL
CIRCUITRY
Signal-to-Noise Plus
Distortion (SINAD)
SINAD is the ratio of the fundamental input frequency’s
RMS amplitude to RMS equivalent of all other ADC out-
put signals:
MAX1282
MAX1283
*OPTIONAL
Figure 15. Power-Supply Grounding Connection
SINAD (dB) = 20 ✕ log (Signal
/ Noise
)
RMS
RMS
Definitions
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists only of quantization noise. With an
input range equal to the ADC’s full-scale range, calcu-
late ENOB as follows:
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
from a straight line on an actual transfer function. This
straight line can be a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1282/MAX1283
are measured using the best straight-line fit method.
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the input signal’s
first five harmonics to the fundamental itself. This is
expressed as:
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
⎛
⎞
2
2
2
2
2
V
+ V + V + V + V
3 4 4 5
⎜
⎟
2
⎝
⎠
THD = 20 × log
Aperture Width
Aperture width (t ) is the time the T/H circuit requires
AW
V
1
to disconnect the hold capacitor from the input circuit
(for instance, to turn off the sampling bridge, and put
the T/H unit in hold mode).
where V is the fundamental amplitude, and V through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
1
2
Aperture Jitter
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the funda-
mental (maximum signal component) to the RMS value
of the next-largest distortion component.
Aperture ꢁitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
rising edge of the sampling clock and the instant when
an actual sample is taken.
20 ______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
+5V
OR
+3V
+5V
OR
+3V
10µF
0.1µF
V
DD2 16
1
2
3
4
5
V
DD1
0.1µF
10µF
(POWER SUPPLIES)
CH0
CH1
CH2
CH3
SCLK 15
CSB 14
SCK
MAX1282
MAX1283
PCS0
ANALOG
INPUTS
MC683XX
DIN
13
MOSI
SSTRB
12
11
MISO
V
DD1
DOUT
GND
6
7
8
COM
SHDN
10
9
REFADJ
REF
4.7µF
0.01µF
(GND)
Figure 16. QSPI Connections
XF
CS
CLKX
SCLK
TMS320LC3x
MAX1282
MAX1283
CLKR
DX
DR
DIN
DOUT
SSTRB
FSR
Figure 17. MAX1282/MAX1283-to-TMS320 Serial Interface
______________________________________________________________________________________ 21
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
CS
SCLK
START
SEL2
SEL1
SEL0 UNI/BIP SGI/DIF PD1
PD0
DIN
SSTRB
HIGH IMPEDANCE
HIGH IMPEDANCE
DOUT
B10
B1
MSB
B0
Figure 18. MAX1282/MAX1283-to-TMS320 Serial Interface
Chip Information
Typical Operating Circuit
+5V OR
+3V
TRANSISTOR COUNT: 4286
PROCESS: BiCMOS
V
DD
V
V
CH0
DD1
0.1µF
0 TO
+2.5V
DD2
ANALOG
INPUTS
MAX1282
MAX1283
GND
CPU
CH3
COM
CS
I/O
REF
4.7µF
SCLK
DIN
SCK (SK)
MOSI (SO)
MISO (SI)
DOUT
SSTRB
SHDN
REFADJ
0.01µF
V
SS
22 ______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, TSSOP 4.40mm BODY
1
21-0066
I
1
Note: The MAX1282/MAX1283 do not have an exposed die pad.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2000 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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