MAX126AEAX+ [MAXIM]
Analog Circuit, PDSO36, 0.300 INCH, 0.80 MM PITCH, SSOP-36;
| 型号： | MAX126AEAX+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog Circuit, PDSO36, 0.300 INCH, 0.80 MM PITCH, SSOP-36 光电二极管 |
| 文件： | 总16页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1319; Rev 1; 1/98
2 x 4 -Ch a n n e l, S im u lt a n e o u s -S a m p lin g
1 4 -Bit DAS
5/MAX126
________________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
The MAX125/MAX126 are high-speed, multichannel,
14-bit data-acquisition systems (DAS) with simultane-
ous track/holds (T/Hs). These devices contain a 14-bit,
3µs, successive-approximation analog-to-digital con-
verter (ADC), a +2.5V reference, a buffered reference
input, and a bank of four simultaneous-sampling T/H
amplifiers that preserve the relative phase information
of the sampled inputs. The MAX125/MAX126 have two
multiplexed inputs for each T/H, allowing a total of eight
inputs. In addition, the converter is overvoltage tolerant
to ±17V; a fault condition on any channel will not harm
the IC. Available input ranges are ±5V (MAX125) and
±2.5V (MAX126).
♦ Four Simultaneous-Sampling T/H Amplifiers with
Two Multiplexed Inputs (eight single-ended inputs
total)
♦ 3µs Conversion Time per Channel
♦ Throughput: 250ksps (1 channel)
142ksps (2 channels)
100ksps (3 channels)
76ksps (4 channels)
♦ Input Range: ±5V (MAX125)
±2.5V (MAX126)
♦ Fault-Protected Input Multiplexer (±17V)
♦ ±5V Supplies
An on-board sequencer converts one to four channels
per CONVST pulse. In the default mode, one T/H output
(CH1A) is converted. An interrupt signal (INT) is pro-
vided after the last conversion is complete. Convert
two, three, or four channels by reprogramming the
MAX125/MAX126 throug h the b id ire c tiona l p a ra lle l
interface. Once programmed, the MAX125/MAX126
continue to convert the specified number of channels
per CONVST pulse until they are reprogrammed. The
channels are converted sequentially, beginning with
CH1. The INT signal always follows the end of the last
conversion in a conversion sequence. The ADC con-
verts each assigned channel in 3µs and stores the
result in an internal 14x4 RAM. Upon completion of the
conversions, data can be accessed by applying suc-
cessive pulses to the RD pin. Four successive reads
access four data words sequentially.
♦ Internal +2.5V or External Reference Operation
♦ Programmable On-Board Sequencer
♦ High-Speed Parallel DSP Interface
______________Ord e rin g In fo rm a t io n
INL
(LSB)
PART
TEMP. RANGE
PIN-PACKAGE
MAX125ACAX
MAX125BCAX
MAX125CCAX
MAX125AEAX
MAX125BEAX
MAX125CEAX
MAX126ACAX
MAX126BCAX
MAX126CCAX
MAX126AEAX
MAX126BEAX
MAX126CEAX
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
36 SSOP*
36 SSOP*
36 SSOP
36 SSOP*
36 SSOP*
36 SSOP
36 SSOP*
36 SSOP*
36 SSOP
36 SSOP*
36 SSOP*
36 SSOP
±2
±4
±4
±2
±4
±4
±2
±4
±4
±2
±4
±4
The parallel interface’s data-access and bus-release
timing specifications are compatible with most popular
digital signal processors and 16-bit/32-bit microproces-
sors, so the MAX125/MAX126 conversion results can
be accessed without resorting to wait states.
________________________Ap p lic a t io n s
Multiphase Motor Control
Power-Grid Synchronization
Power-Factor Monitoring
*Contact factory for availability.
Digital Signal Processing
Vibration and Waveform Analysis
Typical Operating Circuit appears at end of data sheet.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
2 x 4 -Ch a n n e l, S im u lt a n e o u s -S a m p lin g
1 4 -Bit DAS
ABSOLUTE MAXIMUM RATINGS
AV to AGND ...........................................................-0.3V to 6V
Continuous Power Dissipation (T = +70°C)
A
DD
AV to AGND ............................................................0.3V to -6V
DV to DGND ...........................................................-0.3V to 6V
DD
SSOP (derate 11.8mW/°C above +70°C) .....................941mW
Operating Temperature Ranges
SS
AGND to DGND.......................................................-0.3V to 0.3V
CH_ _ to AGND....................................................................±17V
REFIN, REFOUT to AGND ..........................................-0.3V to 6V
MAX125_CAX/MAX126_CAX...............................0°C to +70°C
MAX125_EAX/MAX126_EAX ............................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec)................................300°C
Digital Inputs/Outputs to DGND ..............-0.3V to (DV + 0.3V)
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= +5V ±5%, AV = -5V ±5%, DV
= +5V ±5%, V
= 2.5V, AGND = DGND = 0V, 4.7µF capacitor from REFOUT to
DD
SS
DD
REFIN
5/MAX126
AGND, 0.1µF capacitor from REFIN to AGND, f
noted.)
= 16MHz, external clock, 50% duty cycle, T = T
to T , unless otherwise
MAX
CLK
A
MIN
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
N
All channels
14
Bits
MAX125A/MAX126A
±2
±4
±1
Integral Nonlinearity
(Note 2)
INL
LSB
MAX12_B/C
±2
MAX12_A/B, guaranteed monotonic to 14 bits
Differential Nonlinearity
DNL
LSB
mV
MAX125C/MAX126C,
guaranteed monotonic to 13 bits
±2
T
A
= +25°C
±5
±15
±25
5
Bipolar Zero Error
T
A
= T to T
MIN MAX
Bipolar Zero-Error Match
Zero-Code Tempco
Between all channels
1.2
±5
±5
mV
ppm/°C
T
A
= +25°C
±10
±15
5
Gain Error
mV
T
A
= T to T
MIN MAX
Gain Error Match
Between all channels
1.2
±5
mV
Gain Error Tempco
ppm/°C
DYNAMIC PERFORMANCE (f
= 16MHz, f = 10.06kHz) (Notes 1, 3)
IN
CLK
MAX125
MAX126
72
70
75
72
Signal-to-Noise Plus
Distortion (Note 4)
Single-channel mode,
channel 1A, 250ksps
SINAD
THD
dB
dB
dB
dB
Total Harmonic
Distortion (Notes 4, 5)
Single-channel mode, channel 1A, 250ksps
Single-channel mode, channel 1A, 250ksps
Single-channel mode, channel 1A, 250ksps
-89
90
-80
Spurious-Free Dynamic
Range (Note 4)
SFDR
80
Channel-to-Channel
Isolation (Note 6)
80
2
_______________________________________________________________________________________
2 x 4 -Ch a n n e l, S im u lt a n e o u s -S a m p lin g
1 4 -Bit DAS
5/MAX126
ELECTRICAL CHARACTERISTICS (continued)
(AV
= +5V ±5%, AV = -5V ±5%, DV
= +5V ±5%, V
= 2.5V, AGND = DGND = 0V, 4.7µF capacitor from REFOUT to
DD
SS
DD
REFIN
AGND, 0.1µF capacitor from REFIN to AGND, f
noted.)
= 16MHz, external clock, 50% duty cycle, T = T
to T , unless otherwise
MAX
CLK
A
MIN
PARAMETER
ANALOG INPUT
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX125
MAX126
±5
Input Voltage Range
Input Current
V
V
IN
±2.5
MAX125, V = ±5V
IN
I
IN
±667
16
µA
MAX126, V = ±2.5V
IN
Input Capacitance
TRACK/HOLD
C
(Note 7)
pF
IN
Acquisition Time
t
1
µs
MHz
MHz
mV/ms
ns
ACQ
Small-Signal Bandwidth
Full-Power Bandwidth
Droop Rate
8
0.5
2
Aperture Delay
5
Aperture Jitter
30
500
psRMS
ps
Aperture-Delay Matching
REFERENCE OUTPUT (Note 8)
Output Voltage
V
T
= +25°C
2.475
2.500
±1
2.525
V
%
REFOUT
A
External Load Regulation
REFOUT Tempco
0mA < I
< 1mA
LOAD
(Note 9)
30
ppm/°C
External Capacitive
Bypass at REFIN
0.1
4.7
µF
µF
External Capacitive
Bypass at REFOUT
22
REFERENCE INPUT
Input Voltage Range
Input Current
2.50 ±10%
10
V
REFIN = 2.5V
(Note 10)
±10
10
µA
kΩ
pF
Input Resistance
Input Capacitance
EXTERNAL CLOCK
External Clock Frequency
(Note 7)
0.1
2.4
16
MHz
DIGITAL INPUTS (CONVST, RD, WR, CS, CLK, A0–A3) (Note 1)
Input High Voltage
Input Low Voltage
V
V
V
IH
V
IL
0.8
±1
CONVST, RD, WR, CS, CLK
Input Current
I
IN
µA
pF
A0–A3
±10
15
Input Capacitance
C
(Note 7)
IN
_______________________________________________________________________________________
3
2 x 4 -Ch a n n e l, S im u lt a n e o u s -S a m p lin g
1 4 -Bit DAS
ELECTRICAL CHARACTERISTICS (continued)
(AV
= +5V ±5%, AV = -5V ±5%, DV
= +5V ±5%, V
= 2.5V, AGND = DGND = 0V, 4.7µF capacitor from REFOUT to
DD
SS
DD
REFIN
AGND, 0.1µF capacitor from REFIN to AGND, f
noted.)
= 16MHz, external clock, 50% duty cycle, T = T
to T , unless otherwise
MAX
CLK
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS (D0–D13, INT) (Note 1)
Output High Voltage
V
I
= 1mA
4
V
V
OH
OUT
Output Low Voltage
V
OL
I
= -1.6mA
0.4
OUT
Three-State Leakage Current
D0–D13
±10
µA
Three-State Output
Capacitance
(Note 7)
10
pF
POWER REQUIREMENTS
Positive Supply Voltage
Negative Supply Voltage
Digital Supply Voltage
AV
4.75
-5.25
4.75
5
-5
5
5.25
-4.75
5.25
25
V
V
DD
AV
SS
5/MAX126
DV
V
DD
Positive Supply Current
Negative Supply Current
Digital Supply Current
I(AV
)
17
-13
3
mA
mA
mA
mA
mA
mA
LSB
LSB
mW
DD
I(AV
)
-17
-1
SS
I(DV
)
5
3
DD
Shutdown Positive Current
Shutdown Negative Current
Shutdown Digital Current
Positive Supply Rejection
Negative Supply Rejection
Power Dissipation
3
PSRR+
PSRR-
(Note 11)
(Note 11)
(Note 12)
±1
±2
±2
250
165
4
_______________________________________________________________________________________
2 x 4 -Ch a n n e l, S im u lt a n e o u s -S a m p lin g
1 4 -Bit DAS
5/MAX126
TIMING CHARACTERISTICS (Figure 4)
(AV = +5V, AV = -5V, DV = +5V, AGND = DGND = 0V, T = T
to T , unless otherwise noted.)
MAX
DD
SS
DD
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
30
0
TYP
MAX
UNITS
ns
t
CONVST Pulse Width
CS to WR Setup Time
CS to WR Hold Time
WR Low Pulse Width
CS to CONVST Delay
Address Setup Time
Address Hold Time
RD to INT Delay
CW
t
ns
CWS
t
0
ns
CWH
t
30
125
30
0
ns
WR
t
ns
CSD
t
ns
AS
t
ns
AH
t
ID
25pF load
30
ns
Delay Time Between Reads
CS to RD Setup Time
CS to RD Hold Time
RD Low Pulse Width
Data-Access Time
t
40
0
ns
RD
t
ns
CRS
CRH
t
0
ns
t
30
ns
RD
t
25pF load (Note 13)
25pF load (Note 14)
Mode 1, 1 channel
Mode 2, 2 channel
Mode 3, 3 channel
Mode 4, 4 channel
Mode 1, 1 channel
Mode 2, 2 channel
Mode 3, 3 channel
Mode 4, 4 channel
Exiting shutdown
30
45
3
ns
DA
DH
Bus-Relinquish Time
t
5
ns
6
Conversion Time
t
µs
CONV
9
12
250
142
100
76
Conversion Rate/Channel
Start-Up Time
ksps
µs
5
Note 1: AV = +5V, AV = -5V, DV = +5V, V
= 2.500V (external), V = ±5V (MAX125) or ±2.5V (MAX126).
IN
DD
SS
DD
REFIN
Note 2: Relative accuracy is the analog value’s deviation at any code from its theoretical value after the full-scale range has been
calibrated.
Note 3: CLK synchronized with CONVST.
Note 4:
f
= 10.06kHz, V = ±5V (MAX125) or ±2.5V (MAX126).
IN IN
Note 5: First five harmonics.
Note 6: All inputs except CH1A driven with ±5V (MAX125) or ±2.5V (MAX126) 10kHz signal; CH1A connected to AGND and digitized.
Note 7: Guaranteed by design. Not production tested.
Note 8: AV = +5V, AV = -5V, DV = +5V, V = 0V (all channels).
DD
SS
DD
IN
Note 9: Temperature drift is defined as the change in output voltage from +25°C to T
TC = [∆REFOUT/REFOUT] / ∆T.
or T . It is calculated as
MAX
MIN
Note 10: See Figure 2.
Note 11: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage. Tested with one input
at full scale and all others at AGND. V = 2.5V (internal).
REFIN
Note 12: Tested with V = AGND on all channels, V
= 2.5V (internal).
IN
REFIN
Note 13: The data-access time is defined as the time required for an output to cross 0.8V or 2.0V. It is measured using the circuit of
Figure 1. The measured number is then extrapolated back to determine the value with a 25pF load.
Note 14: The bus-relinquish time is derived from the measured time taken for the data outputs to change 0.5V when loaded with the
circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging/discharging the 120pF
capacitor. Thus, the time given is the part’s true bus-relinquish time, independent of the external bus loading capacitance.
_______________________________________________________________________________________
5
2 x 4 -Ch a n n e l, S im u lt a n e o u s -S a m p lin g
1 4 -Bit DAS
______________________________________________________________P in De s c rip t io n
PIN
1, 2
3, 4
5
NAME
FUNCTION
Channel 2 Multiplexed Inputs, single-ended
CH2B, CH2A
CH1B, CH1A
Channel 1 Multiplexed Inputs, single-ended
+5V ±5% Analog Supply Voltage
AV
DD
6
REFIN
REFOUT
AGND
External Reference Input/Internal Reference Output. Bypass with a 0.1µF capacitor to AGND.
Reference-Buffer Output. Bypass with a 4.7µF capacitor to AGND.
Analog Ground. Both pins must be tied to ground.
Data Bits. D13 = MSB.
7
8, 36
9–16
17
D13–D6
DV
+5V ±5% Digital Supply Voltage
DD
5/MAX126
18
DGND
D5, D4
D3/A3–D0/A0
CLK
Digital Ground
19, 20
21–24
25
Data Bits
Bidirectional Data Bits/Address Bits. D0/A0 = LSB.
Clock Input (duty cycle must be 30% to 70%).
Chip-Select Input (active-low)
26
CS
27
Write Input (active-low)
WR
28
Read Input (active-low)
RD
29
Conversion-Start Input. Rising edge initiates sampling and conversion sequence.
Interrupt Output. Falling edge indicates the end of a conversion sequence.
-5V ±5% Analog Supply Voltage
CONVST
INT
30
31
AV
SS
32, 33
34, 35
CH4A, CH4B
CH3A, CH3B
Channel 4 Multiplexed Inputs, single-ended
Channel 3 Multiplexed Inputs, single-ended
_______________De t a ile d De s c rip t io n
The MAX125/MAX126 use a successive-approximation
conversion technique and four simultaneous-sampling
track/hold (T/H) amplifiers to convert analog signals into
14-bit digital outputs. Each T/H has two multiplexed
inputs, allowing a total of eight inputs. Each T/H output
is converted and stored in memory to be accessed
sequentially by the parallel interface with successive
re a d c yc le s . The MAX125/MAX126 inte rna l mic ro-
sequencer can be programmed to digitize one, two,
three, or four inputs sampled simultaneously from either
of the two banks of four inputs (see Figure 2).
1.6mA
TO OUTPUT
PIN
1.6V
120pF
1.0mA
The c onve rs ion timing a nd c ontrol s e q ue nc e s a re
derived from a 16MHz external clock, the CONVST
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
6
_______________________________________________________________________________________
2 x 4 -Ch a n n e l, S im u lt a n e o u s -S a m p lin g
1 4 -Bit DAS
5/MAX126
REFIN
AGND
REFOUT
BANDGAP REFERENCE
2.50V
10k
CH1A
CH1B
A
B
MUX
MUX
MUX
MUX
T/H
T/H
CH2A
CH2B
A
B
V
REF
MUX
COMP
CH3A
A
B
T/H
T/H
CH3B
CH4A
14-BIT
DAC
A
B
SAR
CH4B
V
REF
14x4
RAM
D0/A0 (LSB)
D1/A1
AV
DD
AGND
D2/A2
THREE-STATE
OUTPUT
DRIVERS
AV
SS
D3/A3
D13 (MSB)
CONTROL LOGIC
MAX125
MAX126
BUS INTERFACE
CLK
CONVST
INT
CS
RD
WR
DV
DD
DGND
Figure 2. Functional Diagram
_______________________________________________________________________________________
7
2 x 4 -Ch a n n e l, S im u lt a n e o u s -S a m p lin g
1 4 -Bit DAS
HOLD
FROM MICROSEQUENCER
C
7pF
HOLD
BUFFER
TRACK
HOLD
CH_A
5k
S1A
S2A
TRACK
C
IN
5k
S3A
MUX
S1B
S2B
5k
CH_B
5/MAX126
C
IN
5k
S3B
REFOUT
DAC
SAR
MAX125
MAX126
Figure 3. Equivalent Input Circuit
signal, and the programmed mode. The T/H amplifiers
hold the input voltages at the CONVST rising edge.
Additional CONVST pulses are ignored until the last
conversion for the sample is complete. The ADC con-
verts each assigned channel in 3µs and stores the
result in an internal 4x14-bit memory.
An a lo g In p u t Ra n g e a n d In p u t P ro t e c t io n
The MAX125’s input range is ±5V, and the MAX126’s
input range is ±2.5V. The input resistance for both parts
is 10kΩ. An input protection structure allows input volt-
ages to ±17V without harming the IC. This protection is
also active in shutdown mode.
At the end of the last conversion, INT goes low and the
T/H amplifiers begin to track the inputs again. The data
can be accessed by applying successive pulses to the
RD pin. Successive reads access data words sequen-
tially. The memory is not random-access; data from
CH1 is a lwa ys re a d firs t. Afte r a c c e s s ing a ll p ro-
grammed channels, the address pointer selects CH1
again. Additional read pulses cycle through the data
words. CS can be held low during successive reads.
Tra c k /Ho ld s
The MAX125/MAX126 feature four simultaneous T/Hs.
Each T/H has two multiplexed inputs. A T-switch input
configuration provides excellent hold-mode isolation.
Allow 1µs acquisition time for 14-bit accuracy.
The T/H aperture delay is typically 10ns. The 500ps
aperture-delay mismatch between the T/Hs allows the
relative phase information of up to four different inputs
to be preserved. Figure 3 shows the equivalent input
circuit, illustrating the ADC’s sampling architecture.
Only one of four T/H stages with its two multiplexed
inputs (CH_A and CH_B) is shown. All switches are in
track configuration for channel A. An internal buffer
charges the hold capacitor to minimize the required
acquisition time between conversions. The analog input
a pp e a rs a s a 10kΩ re sistor in p a ra lle l with a 16pF
capacitor.
In p u t Ba n d w id t h
The T/H’s input tracking circuitry has an 8MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
us ing und e rs a mp ling te c hniq ue s . To a void hig h-
frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
8
_______________________________________________________________________________________
2 x 4 -Ch a n n e l, S im u lt a n e o u s -S a m p lin g
1 4 -Bit DAS
5/MAX126
t
CW
CONVST
INT
t
t
CONV
ACQ
t
ID
t
CWH
t
t
CSD
CWS
CS
RD
t
CRS
t
CRH
t
RD
t
t
WR
RD
WR
t
DA
t
DH
DATA
CH1
CH2
CH3
CH4
DATA IN
t
AS
t
AH
Figure 4. Timing Diagram
RD inputs and forces the interface into a high-Z state.
Figure 4 details the interface timing.
CS
P ro g ra m m in g Mo d e s
The MAX125/MAX126 have eight conversion modes
plus power-down, which are programmed through a
bidirectional parallel interface. At power-up, the devices
d e fa ult to the mod e Inp ut Mux A/Sing le -Cha nne l
Conversion. The user can select between two banks
(mux inputs A or mux inputs B) of four simultaneous-
sampled input channels, as illustrated in Figure 2. An
internal microsequencer can be programmed to convert
one, two, three, or four channels of the selected bank
per sample. For a single-channel conversion, CH1 is
digitized, and then INT goes low to indicate completion
of the conversion. For multichannel conversions, INT
goes low after the last channel has been digitized.
WR
A0
(LSB)
A1
A2
A3
To input data into the MAX125/MAX126, pull CS low,
program the bidirectional pins A0–A3 (Table 1), and
pulse WR low. Data is latched into the devices on the
WR or CS rising edge. The ADC is now ready to convert.
Once programmed, the ADCs continue operating in the
same mode until they are reprogrammed or until power
is removed. Figure 5 shows an example of program-
ming a four-channel conversion using Input Mux A.
Figure 5. Programming a Four-Channel Conversion, Input Mux A
Between conversions, the buffer input is connected to
channel 1 of the selected track/hold bank. When a
channel is not selected, switches S1, S2, and S3 are
placed in hold mode to improve channel-to-channel
isolation.
Dig it a l In t e rfa c e
Input data (A0–A3) and output data (D0–D13) are multi-
plexed on a three-state bidirectional interface. This par-
allel I/O can easily be interfaced with a microprocessor
(µP) or DSP. CS, WR, and RD control the write and read
operations. CS is the standard chip-select signal, which
enables the controller to address the MAX125/MAX126
as an I/O port. When CS is high, it disables the WR and
Starting a Conversion
After programming the MAX125/MAX126 as outlined in
the Programming Modes section, pulse CONVST low to
initiate a conversion sequence. The analog inputs are
sampled at the CONVST rising edge. Do not start a
new conversion while the conversion is in progress.
Monitor the INT output. A falling edge indicates the end
of a conversion sequence.
_______________________________________________________________________________________
9
2 x 4 -Ch a n n e l, S im u lt a n e o u s -S a m p lin g
1 4 -Bit DAS
Table 1. Modes of Operation
CONVERSION
TIME (µs)
A3
A2
A1
A0
MODE
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
3
6
Input Mux A/Single-Channel Conversion (default at power-up)
Input Mux A/Two-Channel Conversion
Input Mux A/Three-Channel Conversion
Input Mux A/Four-Channel Conversion
Input Mux B/Single-Channel Conversion
Input Mux B/Two-Channel Conversion
Input Mux B/Three-Channel Conversion
Input Mux B/Four-Channel Conversion
Power-Down
9
12
3
6
9
12
—
X = Don’t care
5/MAX126
address pointer is reset to CH_1. For multichannel con-
ve rs ions , up to four RD fa lling e d g e s s e q ue ntia lly
access the data for channels 1 through 4. For n chan-
nels converted (1 < n ≤ 4), the address pointer is reset
to CH_1 after n RD pulses. Do not perform a read oper-
ation during conversion, as it will corrupt the conver-
sion’s accuracy.
REFOUT
7
6
(2.5V)
(2.5V)
TO DAC
4.7µF
A = 1
V
__________Ap p lic a t io n s In fo rm a t io n
REFIN
10k
Ex t e rn a l Clo c k
The MAX125/MAX126 require a TTL-compatible clock
up to 16MHz for p rop e r op e ra tion. The c loc k d uty
cycle’s range is between 30% and 70%.
MAX125
MAX126
0.1µF
In t e rn a l a n d Ex t e rn a l Re fe re n c e
The MAX125/MAX126 can be used with an internal or
external reference voltage. An external reference can
be connected directly at REFIN. An internal buffer with
a gain of +1 provides 2.5V at REFOUT.
2.5V
Internal Reference
The full-scale range with the internal reference is ±5V
for the MAX125 and ±2.5V for the MAX126. Bypass
REFIN with a 0.1µF capacitor to AGND and bypass the
REFOUT pin with a 4.7µF (min) capacitor to AGND
(Figure 6). The maximum value to compensate the ref-
erence buffer is 22µF. Larger values are acceptable if
low-ESR capacitors are used.
Figure 6. Internal Reference
Reading a Conversion
Digitized data from up to four channels are stored in
memory to be read out through the parallel interface.
After receiving an INT signal, the user can access up to
four conversion results by performing up to four read
operations.
External Reference
For operation over a wide temperature range, an exter-
nal 2.5V reference with tighter specifications improves
a c c ura c y. The MAX6325 is a n e xc e lle nt c hoic e
to ma tc h the MAX125/MAX126 a c c ura c y ove r the
commercial and extended temperature ranges with a
With CS low, the c onve rs ion re s ult from CH_1 is
accessed, and INT is reset high on the first RD falling
edge. On the RD rising edge, the internal address
p ointe r is a d va nc e d . If a s ing le c onve rs ion is p ro-
g ra mme d , only one RD p uls e is re q uire d , a nd the
10 ______________________________________________________________________________________
2 x 4 -Ch a n n e l, S im u lt a n e o u s -S a m p lin g
1 4 -Bit DAS
5/MAX126
OUTPUT CODE
REFOUT
7
(2.5V)
011 . . . 111
011 . . . 110
TO DAC
4.7µF
000 . . . 010
000 . . . 001
000 . . . 000
A = 1
V
4V
16384
REFOUT
1LSB =
(2.5V)
REFIN
10k
6
MAX125
MAX126
OUT
111 . . . 111
111 . . . 110
111 . . . 101
MAX6325
100 . . . 001
100 . . . 000
2.5V
ZERO
- FS
+FS - 1LSB
INPUT VOLTAGE (LSB)
FS = 2 x V
(MAX125)
REFOUT
FS = V
(MAX126)
REFOUT
Figure 7. External Reference
Figure 8. Bipolar Transfer Function
1ppm/°C (max) temperature drift. Connect an external
reference at REFIN as shown in Figure 7. The minimum
impedance is 7kΩ for DC currents in both normal oper-
ation and shutdown. Bypass REFOUT with a 4.7µF low-
ESR capacitor.
buffer’s settling time and the bypass capacitor’s value
dominate the power-up delay. With the recommended
4.7µF at REFOUT, the power-up delay is typically 5µs.
Tra n s fe r Fu n c t io n
The MAX125/MAX126 have bipolar input ranges. Fig-
ure 8 shows the bipolar/output transfer function. Code
transitions occur at successive-integer least significant
bit (LSB) values. Output coding is twos-complement
b ina ry with 1LSB = 610µV for the MAX125 a nd
1LSB = 305µV for the MAX126.
P o w e r-On Re s e t
When power is first applied, the internal power-on-reset
c irc uitry a c tiva te s the MAX125/MAX126 with INT =
high, ready to convert. The default conversion mode is
Inp ut Mux A/Sing le -Cha nne l Conve rs ion. Se e the
Programming Modes section if other configurations are
desired.
Ou t p u t De m u lt ip le x e r
An output demultiplexer circuit is useful for isolating
data from one channel in a four-channel conversion
sequence. Figure 9’s circuit uses the external 16MHz
clock and the INT signal to generate four RD pulses
and a latch clock to save data from the desired chan-
nel. CS must be low during the four RD pulses. The
c ha nne l is s e le c te d with the b ina ry c od ing of two
switches. A 16-bit 16373 latch simplifies layout.
After the power supplies have been stabilized, the reset
time is 5µs ; no c onve rs ions s hould b e p e rforme d
during this phase. At power-up, data in memory is
undefined.
S o ft w a re P o w e r-Do w n
Software power-down is activated by setting bit A3 of
the control word high (Table 1). It is asserted after the
WR or CS rising edge, at which point the ADC immedi-
ately powers down to a low quiescent-current state.
Mo t o r-Co n t ro l Ap p lic a t io n s
Vector motor control requires monitoring of the individ-
ual phase currents. In their most basic application, the
MAX125/MAX126 simultaneously sample two currents
(CH1A and CH2A, Figure 10) and preserve the neces-
sary relative phase information. Only two of the three
phase currents have to be digitized, because the third
component can be mathematically derived with a coor-
dinate transformation.
AV
drops to less than 1.5mA, and AV is reduced
DD
SS
to less than 1mA. The ADC blocks and reference buffer
are turned off, but the digital interface and the refer-
ence remain active for fast power-up recovery. Wake
up the MAX125/MAX126 b y writing a c ontrol word
(A0–A3, Table 1). The bidirectional interface interprets
a logic zero at A3 as the start signal and powers up in
the mode selected by A0, A1, and A2. The reference
______________________________________________________________________________________ 11
2 x 4 -Ch a n n e l, S im u lt a n e o u s -S a m p lin g
1 4 -Bit DAS
V
CC
V
CC
HC161
1/2 HC74
Q
PRE
D
CLR
ENP
RD
P = Q
G
Q
ENT
LOAD
HC688
CLR
V
(LSB) 0
1
CC
A
B
C
P0
P1
P2
P3
2
3
INT
D
RCO
P4
P5
P6
P7
5/MAX126
EXTERNAL
CLOCK
V
CC
Q0
Q1
Q2
Q3
LATCH
CLOCK
(TO 16373 LATCH)
10k
Q4
Q5
Q6
Q7
CH1
0
1
0
1
0
0
1
1
EXTERNAL
CLOCK
CH2
CH3
CH4
Figure 9. Output Demultiplexer Circuit
The circuit of Figure 10 shows a typical vector motor-
control application using all available inputs of the
MAX125/MAX126. CH1A a nd CH2A a re c onne c te d
to two isolated Hall-effect current sensors and are a
p a rt of the c urre nt (torq ue ) fe e d b a c k loop . The
MAX125/MAX126 digitize the currents and deliver raw
data to the following DSP and controller stages, where
the vector processing takes place. Sensorless vector
control uses a computer model for the motor and an
algorithm to split each output current into its magnetiz-
ing (stator current) and torque-producing (rotor current)
components.
If a 2- to 3-phase conversion is not practical, three cur-
rents can be sampled simultaneously with the addition
of a third s e ns or (not s hown). Op tiona l volta g e
(position) feedback can be derived by measuring two
phase voltages (CH3A, CH4A). Typically, an isolated
differential amplifier is used between the motor and the
MAX125/MAX126. Again, the third phase voltage can
be derived from the magnitude (phase voltage) and its
relative phase.
For optimum speed control and good load regulation
close to zero speed, additional velocity and position
feedback are derived from an encoder or resolver and
12 ______________________________________________________________________________________
2 x 4 -Ch a n n e l, S im u lt a n e o u s -S a m p lin g
1 4 -Bit DAS
5/MAX126
MAIN DC
RESOLVER/
ENCODER
EXTERNAL
SETPOINTS
AC
MOTOR
POWER
STAGE
CONTROLLER
R/E
A
B
A
B
14
AUX
CH1
CH2
CH3
CH4
DSP
MAX125
MAX126
MAIN DC
TEMP
A
B
A
B
14 BIT ADC +
MICRO-
SEQUENCER
VELOCITY
FEEDBACK
µC
Figure 10. Vector Motor Control
brought to the MAX125/MAX126 at CH4B. The addi-
tional channels can be used to evaluate slower analog
inputs, such as the main DC bus voltage (CH2B), tem-
perature sensors (CH3B), or other analog inputs (AUX,
CH1B).
connect that point to the system analog ground plane
to avoid interference from other digital noise sources. If
DGND is connected to the system digital ground, digi-
tal noise may get through to the ADC’s analog portion.
The AGND pins must be connected directly to a low-
impedance ground plane. Extra impedance between
the pins and the ground plane increases crosstalk and
degrades INL.
P o w e r-S u p p ly Byp a s s in g
a n d Gro u n d Ma n a g e m e n t
For optimum system performance, use printed circuit
b oa rd s with s e p a ra te a na log a nd d ig ita l g round
planes. Wire-wrapped boards are not recommended.
Connect the two ground planes together at the low-
impedance power-supply source. Connect DGND and
AGND together at the IC. For the best ground connec-
tion, connect the DGND and AGND pins together and
Bypass AV and AV with 0.1µF ceramic capacitors
DD
SS
to AGND. Mount them with short leads close to the
device. Ferrite beads may also be used to further iso-
late the analog and digital power supplies. Bypass
DV with a 0.1µF ceramic capacitor to DGND.
DD
______________________________________________________________________________________ 13
2 x 4 -Ch a n n e l, S im u lt a n e o u s -S a m p lin g
1 4 -Bit DAS
__________________P in Co n fig u ra t io n
__________Typ ic a l Op e ra t in g Circ u it
TOP VIEW
CH1A
CH1B
CH2A
CH2B
CH3A
CH3B
CH4A
CH4B
CH2B
CH2A
CH1B
CH1A
1
2
3
4
5
6
7
8
9
36 AGND
35 CH3B
34 CH3A
33 CH4B
32 CH4A
D0/A0
D1/A1
D2/A2
D3/A3
D4
D5
D6
D7
D8
AV
DD
MAX125
MAX126
MAX125
MAX126
REFIN
REFOUT
AGND
31 AV
SS
+5V
AV
DD
30 INT
D9
0.1µF
D10
D11
D12
D13
CONVST
29
AGND
0.1µF
D13 (MSB)
28 RD
5/MAX126
AV
SS
-5V
D12 10
D11 11
D10 12
D9 13
D8 14
D7 15
D6 16
27 WR
26 CS
+5V
REFIN
DV
DD
0.1µF
4.7µF
0.1µF
25 CLK
24 D0/A0 (LSB)
23 D1/A1
22 D2/A2
21 D3/A3
20 D4
REFOUT
DGND
CLK CONVST INT CS RD WR
DV 17
DD
DGND 18
19 D5
16MHz
SSOP
CONTROL INTERFACE
___________________Ch ip In fo rm a t io n
TRANSISTOR COUNT: 4219
SUBSTRATE CONNECTED TO AV
SS
14 ______________________________________________________________________________________
2 x 4 -Ch a n n e l, S im u lt a n e o u s -S a m p lin g
1 4 -Bit DAS
5/MAX126
________________________________________________________P a c k a g e In fo rm a t io n
______________________________________________________________________________________ 15
2 x 4 -Ch a n n e l, S im u lt a n e o u s -S a m p lin g
1 4 -Bit DAS
NOTES
5/MAX126
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1998 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX126CCAX+TD
ADC, Successive Approximation, 14-Bit, 1 Func, 4 Channel, Parallel, Word Access, PDSO36, 0.163 INCH, 0.80 MM PITCH, ROHS COMPLIANT, SSOP-36
MAXIM
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