MAX1257BETM+T [MAXIM]
暂无描述;
| 型号： | MAX1257BETM+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 暂无描述 传感器 温度传感器 先进先出芯片 |
| 文件： | 总43页 (文件大小：561K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3295; Rev 7; 2/12
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
General Description
Features
The MAX1220/MAX1257/MAX1258 integrate a 12-bit,
multichannel, analog-to-digital converter (ADC), and a 12-
bit, octal, digital-to-analog converter (DAC) in a single IC.
These devices also include a temperature sensor and
configurable general-purpose I/O ports (GPIOs) with a
o 12-Bit, 225ksps ADC
Analog Multiplexer with True-Differential
Track/Hold (T/H)
16 Single-Ended Channels or 8 Differential
Channels (Unipolar or Bipolar)
®
(MAX1257/MAX1258)
25MHz SPI-/QSPI™-/MICROWIRE -compatible serial
Eight Single-Ended Channels or Four Differential
Channels (Unipolar or Bipolar) (MAX1220)
Excellent Accuracy: 0ꢀ5 ꢁSB ꢂIꢁ, 0ꢀ5 ꢁSB DIꢁ
interface. The ADC is available in 8 and 16 input-channel
versions. The octal DAC outputs settle within 2.0µs and
the ADC has a 225ksps conversion rate.
o 12-Bit, Octal, 2µs Settling DAC
All devices include an internal reference (2.5V or
4.096V) for both the ADC and DAC. Programmable ref-
erence modes allow the use of an internal reference, an
external reference, or a combination of both. Features
such as an internal 1°C accurate temperature sensor,
FIFO, scan modes, programmable internal or external
clock modes, data averaging, and AutoShutdown™
allow users to minimize power consumption and proces-
sor requirements. The low glitch energy (4nV•s) and low
digital feedthrough (0.5nV•s) of the integrated octal
DACs make these devices ideal for digital control of
fast-response closed-loop systems.
The devices are guaranteed to operate with a supply volt-
age from +2.7V to +3.6V (MAX1257) and from +4.75V to
+5.25V (MAX1220/MAX1258). These devices consume
2.5mA at 225ksps throughput, only 22µA at 1ksps
throughput, and under 0.2µA in the shutdown mode. The
MAX1257/MAX1258 feature 12 GPIOs, while the
MAX1220 offers four GPIOs that can be configured as
inputs or outputs.
Ultra-ꢁow Glitch Energy (4nV•s)
Power-Up Options from Zero Scale or Full Scale
Excellent Accuracy: 0ꢀ5 ꢁSB ꢂIꢁ
o ꢂnternal Reference or External Single-Ended/
Differential Reference
ꢂnternal Reference Voltage 2ꢀ5V or 4ꢀ096V
o ꢂnternal 1ꢃC Accurate Temperature Sensor
o On-Chip FꢂFO Capable of Storing 16 ADC
Conversion Results and One Temperature Result
o On-Chip Channel-Scan Mode and ꢂnternal
Data-Averaging Features
o Analog Single-Supply Operation
+2ꢀ7V to +3ꢀ6V or +4ꢀ75V to +5ꢀ25V
o Digital Supply: +2ꢀ7V to AVDD
o 25MHz, SPꢂ/QSPꢂ/MꢂCROWꢂRE Serial ꢂnterface
o AutoShutdown Between Conversions
o ꢁow-Power ADC
2ꢀ5mA at 225ksps
22µA at 1ksps
The MAX1220 is available in a 36-pin TQFN package.
The MAX1257/MAX1258 are available in 48-pin TQFN
package. All devices are specified over the
-40°C to +85°C temperature range.
0ꢀ2µA at Shutdown
o ꢁow-Power DAC: 1ꢀ5mA
o Evaluation Kit Available (Order MAX1258EVKꢂT)
Applications
Controls for Optical Components
Base-Station Control Loops
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
System Supervision and Control
Data-Acquisition Systems
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
Pin Configurations appear at end of data sheetꢀ
Ordering Information/Selector Guide
REF
VOLTAGE
(V)
ANALOG
SUPPLY
VOLTAGE (V)
RESOLUTION
BITS**
ADC
CHANNELS
DAC
CHANNELS
PART
PIN-PACKAGE
GPIOs
MAX1220BETX+
MAX1257BETM+
MAX1258BETM+
36 Thin QFN-EP*
48 Thin QFN-EP*
48 Thin QFN-EP*
4.096
2.5
4.75 to 5.25
2.7 to 3.6
12
12
12
8
8
8
8
4
16
16
12
12
4.096
4.75 to 5.25
Iote: All devices are specified over the -40°C to +85°C operating range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
**Number of resolution bits refers to both DAC and ADC.
________________________________________________________________ Maxim ꢂntegrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at wwwꢀmaxim-icꢀcomꢀ
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ABSOꢁUTE MAXꢂMUM RATꢂIGS
AVDD to AGND ........................................................-0.3V to +6V
DGND to AGND.....................................................-0.3V to +0.3V
DVDD to AVDD......................................................-3.0V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
Continuous Power Dissipation (multilayer board, T = +70°C)
A
36-Pin TQFN (6mm x 6mm)
(derate 35.7mW/°C above +70°C)......................2857.1mW
48-Pin TQFN (7mm x 7mm)
Digital Outputs to DGND........................-0.3V to (V
Analog Inputs, Analog Outputs and REF_
to AGND .............................................-0.3V to (V
Maximum Current into Any Pin (except AGND, DGND, AVDD,
DVDD, and OUT_)...........................................................50mA
Maximum Current into OUT_.............................................100mA
+ 0.3V)
(derate 40mW/°C above +70°C)............................3200mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature ...................................................+260°C
DVDD
+ 0.3V)
AVDD
Iote: If the package power dissipation is not exceeded, one output at a time may be shorted to AVDD, DVDD, AGND, or DGND
indefinitely.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS
(V
= V
= 2.7V to 3.6V (MAX1257), external reference V
= 2.5V (MAX1257), V
= 4.75V to 5.25V, V = 2.7V to V
DVDD AVDD
AVDD
DVDD
REF
AVDD
(MAX1220/MAX1258), external reference V
unless otherwise noted. Typical values are at V
Outputs are unloaded, unless otherwise noted.)
= 4.096V (MAX1220/MAX1258), f
= 3.6MHz (50% duty cycle), T = -40°C to +85°C,
REF
CLK A
= V
= 3V (MAX1257), V
= V = 5V (MAX1220/MAX1258), T = +25°C.
DVDD A
AVDD
DVDD
AVDD
PARAMETER
SYMBOꢁ
COIDꢂTꢂOIS
ADC
MꢂI
TYP
MAX
UIꢂTS
DC ACCURACY (Iote 1)
Resolution
12
Bits
LSB
07/MAX1258
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
0.5
0.5
1
1.0
1.0
4.0
4.0
DNL
LSB
LSB
Gain Error
(Note 2)
0.1
0.8
0.1
LSB
Gain Temperature Coefficient
Channel-to-Channel Offset
ppm/°C
LSB
DYIAMꢂC SPECꢂFꢂCATꢂOIS (10kHz sine-wave input, V = 2ꢀ5V
(MAX1257), V = 4ꢀ096V (MAX1220/MAX1258),
P-P
ꢂI
P-P
ꢂI
225ksps, f
= 3ꢀ6MHz)
CꢁK
Signal-to-Noise Plus Distortion
SINAD
THD
70
dB
Total Harmonic Distortion
(Up to the Fifth Harmonic)
-76
dBc
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Linear Bandwidth
SFDR
IMD
72
76
100
1
dBc
dBc
kHz
f
= 9.9kHz, f
= 10.2kHz
IN1
IN2
SINAD > 70dB
-3dB point
Full-Power Bandwidth
MHz
COIVERSꢂOI RATE (Iote 3)
External reference
0.8
µs
Conversion
clock
Power-Up Time
t
PU
Internal reference (Note 4)
218
cycles
2
_______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(V
= V
= 2.7V to 3.6V (MAX1257), external reference V
= 2.5V (MAX1257), V
= 4.75V to 5.25V, V = 2.7V to V
DVDD AVDD
AVDD
DVDD
REF
AVDD
(MAX1220/MAX1258), external reference V
unless otherwise noted. Typical values are at V
Outputs are unloaded, unless otherwise noted.)
= 4.096V (MAX1220/MAX1258), f
= 3.6MHz (50% duty cycle), T = -40°C to +85°C,
REF
CLK A
= V
= 3V (MAX1257), V
= V = 5V (MAX1220/MAX1258), T = +25°C.
DVDD A
AVDD
DVDD
AVDD
PARAMETER
Acquisition Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
t
(Note 5)
0.6
µs
ACQ
Internally clocked
Externally clocked
5.5
Conversion Time
t
µs
CONV
3.6
0.1
40
External Clock Frequency
Duty Cycle
f
Externally clocked conversion (Note 5)
3.6
60
MHz
%
CLK
Aperture Delay
30
ns
Aperture Jitter
< 50
ps
ANALOG INPUTS
Unipolar
Bipolar
0
V
REF
REF
1
Input Voltage Range (Note 6)
V
-V
/2
+V
/2
REF
Input Leakage Current
Input Capacitance
0.01
24
µA
pF
INTERNAL TEMPERATURE SENSOR
T
T
= +25°C
0.7
1.0
1/8
A
Measurement Error (Notes 5, 7)
°C
= T
to T
3.0
A
MIN
MAX
Temperature Resolution
°C/LSB
INTERNAL REFERENCE
MAX1257
MAX1220/MAX1258
2.482
4.066
2.50
2.518
4.126
REF1 Output Voltage (Note 8)
V
4.096
REF1 Voltage Temperature
Coefficient
TC
30
ppm/°C
REF
REF1 Output Impedance
6.5
k
V
V
= 2.5V
0.39
0.63
REF
REF1 Short-Circuit Current
EXTERNAL REFERENCE
REF1 Input Voltage Range
mA
= 4.096V
REF
V
AVDD
V
V
REF mode 11 (Note 4)
1
V
V
REF1
+ 0.05
V
AVDD
REF mode 01
REF mode 11
1
0
REF2 Input Voltage Range
(Note 4)
+ 0.05
REF2
1
_______________________________________________________________________________________
3
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(V
= V
= 2.7V to 3.6V (MAX1257), external reference V
= 2.5V (MAX1257), V
= 4.75V to 5.25V, V = 2.7V to V
DVDD AVDD
AVDD
DVDD
REF
AVDD
(MAX1220/MAX1258), external reference V
unless otherwise noted. Typical values are at V
Outputs are unloaded, unless otherwise noted.)
= 4.096V (MAX1220/MAX1258), f
= 3.6MHz (50% duty cycle), T = -40°C to +85°C,
REF
CLK A
= V
= 3V (MAX1257), V
= V = 5V (MAX1220/MAX1258), T = +25°C.
DVDD A
AVDD
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
= 2.5V (MAX1257), f
MIN
TYP
MAX
UNITS
V
REF
=
25
80
SAMPLE
V
= 4.096V (MAX1220/MAX1258),
REF
REF1 Input Current (Note 9)
I
40
80
µA
REF1
REF2
f
= 225ksps
SAMPLE
Acquisition between conversions
0.01
25
1
V
REF
= 2.5V (MAX1257), f
=
80
SAMPLE
V
REF
= 4.096V (MAX1220/MAX1258),
REF2 Input Current
I
40
80
1
µA
f
= 225ksps
SAMPLE
Acquisition between conversions
0.01
DAC
DC ACCURACY (Note 10)
Resolution
12
Bits
LSB
LSB
mV
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
0.5
4
DNL
Guaranteed monotonic
(Note 8)
1.0
10
V
3
10
5
OS
ppm of
FS/°C
Offset-Error Drift
Gain Error
GE
(Note 8)
10
LSB
07/MAX1258
ppm of
FS/°C
Gain Temperature Coefficient
DAC OUTPUT
8
V
V
-
-
AVDD
0.02
No load
0.02
0.1
Output-Voltage Range
V
AVDD
0.1
10k load to either rail
DC Output Impedance
Capacitive Load
0.5
(Note 11)
1
nF
V
= 2.7V, V
= 2.5V (MAX1257),
REF
AVDD
2000
500
gain error < 1%
Resistive Load to AGND
R
L
V
AVDD
= 4.75V, V
= 4.096V
REF
(MAX1220/MAX1258), gain error < 2%
From power-down mode, V
From power-down mode, V
= 5V
25
21
1
AVDD
AVDD
Wake-Up Time (Note 12)
1k Output Termination
100k Output Termination
µs
k
= 2.7V
Programmed in from power-down mode
At wake-up or programmed in
power-down mode
100
k
4
_______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(V
= V
= 2.7V to 3.6V (MAX1257), external reference V
= 2.5V (MAX1257), V
= 4.75V to 5.25V, V = 2.7V to V
DVDD AVDD
AVDD
DVDD
REF
AVDD
(MAX1220/MAX1258), external reference V
unless otherwise noted. Typical values are at V
Outputs are unloaded, unless otherwise noted.)
= 4.096V (MAX1220/MAX1258), f
= 3.6MHz (50% duty cycle), T = -40°C to +85°C,
REF
CLK A
= V
= 3V (MAX1257), V
= V = 5V (MAX1220/MAX1258), T = +25°C.
DVDD A
AVDD
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (Notes 5, 13)
Output-Voltage Slew Rate
SR
Positive and negative
3
V/µs
µs
Output-Voltage Settling Time
t
To 1 LSB, 400 - C00 hex (Note 7)
2
5
S
Code 0, all digital inputs from 0 to
Digital Feedthrough
0.5
nV•s
nV•s
V
DVDD
Major Code Transition Glitch
Impulse
Between codes 2047 and 2048
From V
4
660
720
260
320
REF
Output Noise (0.1Hz to 50MHz)
µV
µV
P-P
P-P
Using internal reference
From V
Output Noise (0.1Hz to
500kHz)
REF
Using internal reference
DAC-to-DAC Transition
Crosstalk
0.5
nV•s
INTERNAL REFERENCE
REF1 Output Voltage (Note 8)
REF1 Temperature Coefficient
REF1 Short-Circuit Current
MAX1257
2.482
4.066
2.5
4.096
30
2.518
4.126
V
MAX1220/MAX1258
TC
ppm/°C
mA
REF
V
V
= 2.5V
0.39
0.63
REF
= 4.096V
REF
EXTERNAL-REFERENCE INPUT
REF1 Input Voltage Range
REF1 Input Impedance
V
R
REF modes 01, 10, and 11 (Note 4)
0.7
70
V
V
REF1
AVDD
100
130
kꢀ
REF1
DIGITAL INTERFACE
DIGITAL INPUTS (SCLK, DIN, CS, CNVST, LDAC)
Input-Voltage High
V
V
DVDD
V
DVDD
V
DVDD
= 2.7V to 5.25V
= 3.6V to 5.25V
= 2.7V to 3.6V
2.4
V
V
IH
0.8
0.6
10
Input-Voltage Low
V
IL
Input Leakage Current
Input Capacitance
I
0.01
15
µA
pF
L
C
IN
DIGITAL OUTPUT (DOUT) (Note 14)
Output-Voltage Low
V
I
I
= 2mA
0.4
10
V
V
OL
SINK
= 2mA
SOURCE
V
DVDD
0.5
-
Output-Voltage High
V
OH
Three-State Leakage Current
µA
pF
Three-State Output
Capacitance
C
15
OUT
_______________________________________________________________________________________
5
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(V
= V
= 2.7V to 3.6V (MAX1257), external reference V
= 2.5V (MAX1257), V
= 4.75V to 5.25V, V = 2.7V to V
DVDD AVDD
AVDD
DVDD
REF
AVDD
(MAX1220/MAX1258), external reference V
unless otherwise noted. Typical values are at V
Outputs are unloaded, unless otherwise noted.)
= 4.096V (MAX1220/MAX1258), f
= 3.6MHz (50% duty cycle), T = -40°C to +85°C,
REF
CLK A
= V
= 3V (MAX1257), V
= V = 5V (MAX1220/MAX1258), T = +25°C.
DVDD A
AVDD
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUT (EOC) (Note 14)
Output-Voltage Low
V
I
I
= 2mA
0.4
V
V
OL
SINK
= 2mA
SOURCE
V
DVDD
0.5
-
Output-Voltage High
V
OH
Three-State Leakage Current
10
µA
pF
Three-State Output
Capacitance
C
15
OUT
DIGITAL OUTPUTS (GPIO_) (Note 14)
I
I
= 2mA
0.4
0.8
GPIOB_, GPIOC_ Output-
Voltage Low
SINK
SINK
V
= 4mA
GPIOB_, GPIOC_ Output-
Voltage High
V
V
-
-
DVDD
0.5
I
I
I
= 2mA
V
V
SOURCE
GPIOA_ Output-Voltage Low
GPIOA_ Output-Voltage High
Three-State Leakage Current
= 15mA
0.8
10
SINK
DVDD
0.8
= 15mA
V
SOURCE
µA
pF
Three-State Output
C
15
OUT
DD
Capacitance
07/MAX1258
POWER REQUIREMENTS (Note 15)
Digital Positive-Supply Voltage
DV
2.7
V
V
AVDD
Idle, all blocks shut down
0.2
1
4
µA
mA
Digital Positive-Supply Current
DI
DD
Only ADC on, external reference
MAX1257
2.7
3.6
5.25
2
Analog Positive-Supply Voltage
Analog Positive-Supply Current
AV
V
DD
MAX1220/MAX1258
4.75
Idle, all blocks shut down
0.2
2.8
2.6
1.5
-77
-80
0.1
µA
f
f
= 225ksps
= 100ksps
4.2
Only ADC on,
external reference
SAMPLE
SAMPLE
AI
DD
mA
dB
All DACs on, no load, internal reference
MAX1257, V = 2.7V
4
REF1 Positive-Supply
Rejection
AVDD
PSRR
PSRD
MAX1220/MAX1258, V
MAX1257, V
= 4.75V
AVDD
= 2.7V to
0.5
0.5
0.5
0.5
AVDD
Output
code =
FFFhex
DAC Positive-Supply Rejection
ADC Positive-Supply Rejection
mV
MAX1220/MAX1258,
= 4.75V to 5.25V
0.1
V
AVDD
MAX1257, V
= 2.7V to
0.06
0.06
AVDD
Full-
PSRA
mV
scale
input
MAX1220/MAX1258,
= 4.75V to 5.25V
V
AVDD
6
_______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(V
= V
= 2.7V to 3.6V (MAX1257), external reference V
= 2.5V (MAX1257), V
= 4.75V to 5.25V, V = 2.7V to V
DVDD AVDD
AVDD
DVDD
REF
AVDD
(MAX1220/MAX1258), external reference V
unless otherwise noted. Typical values are at V
Outputs are unloaded, unless otherwise noted.)
= 4.096V (MAX1220/MAX1258), f
= 3.6MHz (50% duty cycle), T = -40°C to +85°C,
REF
CLK A
= V
= 3V (MAX1257), V
= V = 5V (MAX1220/MAX1258), T = +25°C.
DVDD A
AVDD
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Figures 6–13)
SCLK Clock Period
t
40
16
16
ns
ns
ns
CP
SCLK Pulse-Width High
SCLK Pulse-Width Low
t
40/60 duty cycle
60/40 duty cycle
CH
t
CL
GPIO Output Rise/Fall After
CS Rise
t
C
LOAD
= 20pF
100
ns
GOD
GPIO Input Setup Before CS
Fall
t
0
ns
ns
ns
GSU
LDAC Pulse Width
t
20
1.8
10
1.8
10
10
0
LDACPWL
C
C
C
C
= 20pF, SLOW = 0
= 20pF, SLOW = 1
= 20pF, SLOW = 0
= 20pF, SLOW = 1
12.0
40
SCLK Fall to DOUT Transition
(Note 16)
LOAD
LOAD
LOAD
LOAD
t
t
DOT
12.0
40
SCLK Rise to DOUT Transition
(Notes 16, 17)
ns
DOT
CS Fall to SCLK Fall Setup Time
SCLK Fall to CS Rise Hold Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
CS Pulse-Width High
t
ns
ns
ns
ns
ns
ns
ns
ns
CSS
t
2000
CSH
t
10
0
DS
t
DH
t
50
CSPWH
CS Rise to DOUT Disable
CS Fall to DOUT Enable
EOC Fall to CS Fall
t
C
C
= 20pF
= 20pF
25
DOD
LOAD
t
1.5
30
25.0
DOE
LOAD
t
RDS
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference on
(Note 18)
65
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference
initially off
140
CS or CNVST Rise to EOC
Fall—Internally Clocked
Conversion Time
t
µs
DOV
CKSEL = 01 (voltage conversion)
9
9
CKSEL = 10 (voltage conversion),
internal reference on (Note 18)
CKSEL = 10 (voltage conversion),
internal reference initially off
80
CKSEL = 00, CKSEL = 01 (temp sense)
CKSEL = 01 (voltage conversion)
40
ns
µs
CNVST Pulse Width
t
CSW
1.4
_______________________________________________________________________________________
7
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(V
= V
= 2.7V to 3.6V (MAX1257), external reference V
= 2.5V (MAX1257), V
= 4.75V to 5.25V, V = 2.7V to V
DVDD AVDD
AVDD
DVDD
REF
AVDD
(MAX1220/MAX1258), external reference V
unless otherwise noted. Typical values are at V
Outputs are unloaded, unless otherwise noted.)
= 4.096V (MAX1220/MAX1258), f
= 3.6MHz (50% duty cycle), T = -40°C to +85°C,
REF
CLK A
= V
= 3V (MAX1257), V
= V = 5V (MAX1220/MAX1258), T = +25°C.
DVDD A
AVDD
DVDD
AVDD
Iote 1: Tested at V
= V
= +2.7V (MAX1257), V
= +2.7V, V
= +5.25V (MAX1220/MAX1258).
DVDD
AVDD
DVDD
AVDD
Iote 2: Offset nulled.
Iote 3: No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles multiplied by the
clock period.
Iote 4: See Table 5 for reference-mode details.
Iote 5: Not production tested. Guaranteed by design.
Iote 6: See the ADC/DAC References section.
Iote 7: Fast automated test, excludes self-heating effects.
Iote 8: Specified over the -40°C to +85°C temperature range.
Iote 9: REFSEL[1:0] = 00 and when DACs are not powered up.
Iote 10: DAC linearity, gain, and offset measurements are made between codes 115 and 3981.
Iote 11: The DAC buffers are guaranteed by design to be stable with a 1nF load.
Iote 12: Time required by the DAC output to power up and settle within 1 LSB in the external reference mode.
Iote 13: All DAC dynamic specifications are valid for a load of 100pF and 10kΩ.
Iote 14: Only one digital output (either DOUT, EOC, or the GPIOs) can be indefinitely shorted to either supply at one time.
Iote 15: All digital inputs at either V
or DGND. V
should not exceed V
.
DVDD
DVDD
AVDD
Iote 16: See the Reset Register section and Table 9 for details on programming the SLOW bit.
Iote 17: Clock mode 11 only.
Iote 18: First conversion after reference power-up is always timed as if the internal reference was initially off to ensure the internal
reference has settled. Subsequent conversions are timed as shown.
07/MAX1258
8
_______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
Typical Operating Characteristics
(V
= V
= 3V (MAX1257), external V
= 2.5V (MAX1257), V
= V
= 5V (MAX1220/MAX1258), external V
=
AVDD
DVDD
REF
AVDD
DVDD
REF
4.096V (MAX1220/MAX1258), f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor at REF,
CLK
SAMPLE
LOAD
T
A
= +25°C, unless otherwise noted.)
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
ANALOG SHUTDOWN CURRENT
vs. TEMPERATURE
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
MAX1220/MAX1258
MAX1257
MAX1220/MAX1258
MAX1257
2.7
4.750
4.875
5.000
5.125
5.250
3.0
3.3
3.6
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
MAX1257
1024
MAX1220/MAX1258
MAX1220/MAX1258
1024
0
2048
3072
4096
0
2048
3072
4096
0
1024
2048
3072
4096
OUTPUT CODE
OUTPUT CODE
OUTPUT CODE
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLATGE
1.00
0.75
0.50
0.25
0
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
-0.25
-0.50
-0.75
-1.00
MAX1220/MAX1258
MAX1257
MAX1257
0
1024
2048
3072
4096
4.750
4.875
5.000
5.125
5.250
2.7
3.0
3.3
3.6
OUTPUT CODE
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
9
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(V
= V
= 3V (MAX1257), external V
= 2.5V (MAX1257), V
= V
= 5V (MAX1220/MAX1258), external V
=
AVDD
DVDD
REF
AVDD
DVDD
REF
4.096V (MAX1220/MAX1258), f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor at REF,
CLK
SAMPLE
LOAD
T
A
= +25°C, unless otherwise noted.)
ADC OFFSET ERROR
vs. TEMPERATURE
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
2
1
1.0
0.5
0
1.0
0.5
0
MAX1220/MAX1258
0
MAX1257
-1
-2
-0.5
-1.0
-0.5
-1.0
MAX1220/MAX1258
MAX1257
-40
-15
10
35
60
85
4.750
4.875
5.000
5.125
5.250
2.7
3.0
3.3
3.6
300
85
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
ADC GAIN ERROR
vs. TEMPERATURE
ADC EXTERNAL REFERENCE
INPUT CURRENT vs. SAMPLING RATE
ANALOG SUPPLY CURRENT
vs. SAMPLING RATE
60
50
40
30
20
10
0
3.0
2.5
2.0
1.5
1.0
0.5
0
2
1
MAX1220/MAX1258
MAX1220/MAX1258
MAX1257
MAX1220/MAX1258
07/MAX1258
0
-1
-2
MAX1257
MAX1257
50
-40
-15
10
TEMPERATURE (°C)
35
60
85
0
50
100
SAMPLING RATE (ksps)
150
200
250
300
0
100
150
200
250
SAMPLING RATE (ksps)
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
2.02
2.00
1.98
1.96
1.94
1.92
1.90
1.88
2.04
2.02
2.00
1.98
1.96
1.94
1.92
1.90
2.04
2.02
2.00
1.98
1.96
1.94
1.92
1.90
MAX1220/MAX1258
MAX1257
MAX1220/MAX1258
MAX1257
-40
-15
10
35
60
2.7
3.0
3.3
3.6
4.750
4.875
5.000
5.125
5.250
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
10 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
Typical Operating Characteristics (continued)
(V
= V
= 3V (MAX1257), external V
= 2.5V (MAX1257), V
= V
= 5V (MAX1220/MAX1258), external V
=
AVDD
DVDD
REF
AVDD
DVDD
REF
4.096V (MAX1220/MAX1258), f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor at REF,
CLK
SAMPLE
LOAD
T
A
= +25°C, unless otherwise noted.)
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0.4
0.2
0
1.5
1.0
0.5
0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-0.5
-1.0
-1.5
-0.2
-0.4
MAX1220/MAX1258
MAX1220/MAX1258
MAX1257
1024
2047
2050
2053
2056
2059
2062
3.6
5
0
1024
2048
3072
4096
2062
85
0
2048
3072
4096
5.250
85
OUTPUT CODE
OUTPUT CODE
OUTPUT CODE
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
0.4
0.2
0
1.2
1.0
0.8
0.6
0.4
0.2
1.2
1.0
0.8
0.6
0.4
0.2
-0.2
-0.4
MAX1220/MAX1258
EXTERNAL REFERENCE = 4.096V
MAX1257
EXTERNAL REFERENCE = 2.5V
MAX1257
2047
2050
2053
2056
2059
4.750
4.875
5.000
5.125
2.7
3.0
3.3
OUTPUT CODE
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
DAC FULL-SCALE ERROR
vs. TEMPERATURE
DAC FULL-SCALE ERROR
vs. TEMPERATURE
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
10
8
10
8
1.00
0.75
0.50
0.25
0
INTERNAL
REFERENCE
INTERNAL
REFERENCE
6
6
4
4
2
2
0
0
-0.25
-0.50
-0.75
-1.00
EXTERNAL
REFERENCE = 2.5V
EXTERNAL
REFERENCE = 4.096V
-2
-4
-6
-2
-4
-6
MAX1220/MAX1258
MAX1220/MAX1258
MAX1257
-40
-15
10
35
60
-40
-15
10
35
60
0
1
2
3
4
TEMPERATURE (°C)
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
______________________________________________________________________________________ 11
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(V
= V
= 3V (MAX1257), external V
= 2.5V (MAX1257), V
= V
= 5V (MAX1220/MAX1258), external V
=
AVDD
DVDD
REF
AVDD
DVDD
REF
4.096V (MAX1220/MAX1258), f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor at REF,
CLK
SAMPLE
LOAD
T
A
= +25°C, unless otherwise noted.)
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
5
0
5
0
0
-1
-2
-3
-4
-5
-6
-7
-5
-5
-10
-15
-10
-15
MAX1257
0.5
MAX1220/MAX1258
MAX1257
0.5
0
5
10
15
20
25
30
85
85
0
1.0
1.5
2.0
2.5
3.0
0
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (mA)
LOAD CURRENT (mA)
REFERENCE VOLTAGE (V)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
4.12
4.11
4.10
4.09
4.08
2.52
2.51
2.50
2.49
2.48
24.96
24.94
24.92
24.90
24.88
24.86
24.84
07/MAX1258
MAX1220/MAX1258
MAX1257
MAX1220/MAX1258
-40
-15
10
35
60
85
-40
-15
10
35
60
4.750
4.875
5.000
5.125
5.250
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLATAGE
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
25.1
25.0
24.9
24.8
24.7
25.1
25.0
24.9
24.8
24.7
41.0
40.9
40.8
40.7
40.6
40.5
MAX1220/MAX1258
EXTERNAL REFERENCE = 4.096V
MAX1257, EXTERNAL REFERENCE = 2.5V
MAX1257
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
-40
-15
10
35
60
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
12 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
Typical Operating Characteristics (continued)
(V
= V
= 3V (MAX1257), external V
= 2.5V (MAX1257), V
= V
= 5V (MAX1220/MAX1258), external V
=
AVDD
DVDD
REF
AVDD
DVDD
REF
4.096V (MAX1220/MAX1258), f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor at REF,
CLK
SAMPLE
LOAD
T
A
= +25°C, unless otherwise noted.)
ADC FFT PLOT
ADC IMD PLOT
ADC CROSSTALK PLOT
0
-20
0
-20
0
-20
f
f
f
= 32.768kHz
f
f
f
= 5.24288MHz
= 9.0kHz
= 11.0kHz
= -6dBFS
f
f
f
= 5.24288MHz
= 10.080kHz
= 8.0801kHz
SAMPLE
CLK
IN1
IN2
CLK
IN1
IN2
= 10.080kHz
ANALOG_N
= 5.24288MHz
CLK
SINAD = 71.27dBc
SNR = 71.45dBc
THD = 85.32dBc
SFDR = 87.25dBc
A
SNR = 72.00dBc
THD = 85.24dBc
ENOB = 11.65 BITS
-40
-40
-40
IN
IMD = 82.99dBc
-60
-60
-60
-80
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
-100
-120
-140
-160
0
50
100
150
200
0
50
100
150
200
0
50
100
150
200
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
5
4
3
2
1
0
2.08
2.07
2.06
2.05
2.04
2.03
2.02
2.01
2.00
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
MAX1220/MAX1258
GPIOA0–A3 OUTPUTS
SINKING
SINKING
GPIOB0–B3,
C0–C3 OUTPUTS
SOURCING
SOURCING
DAC OUTPUT = MIDSCALE
MAX1220/MAX1258
DAC OUTPUT = MIDSCALE
MAX1257
0
20
40
60
80
100
-30
0
30
60
90
-30
-20
0
10
20
30
-10
SOURCE CURRENT (mA)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
GPIO OUTPUT VOLTAGE
vs. SINK CURRENT
GPIO OUTPUT VOLTAGE
vs. SINK CURRENT
3.0
2.5
2.0
1.5
1.0
0.5
0
1500
1200
900
600
300
0
1500
1200
900
600
300
0
MAX1257
GPIOA0–A3 OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
GPIOA0–A3 OUTPUTS
MAX1220/MAX1258
GPIOA0–A3 OUTPUTS
MAX1257
50 60
0
20
40
60
80
100
0
20
40
60
80
100
0
10
20
30
40
SOURCE CURRENT (mA)
SINK CURRENT (mA)
SINK CURRENT (mA)
______________________________________________________________________________________ 13
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(V
= V
= 3V (MAX1257), external V
= 2.5V (MAX1257), V
= V
= 5V (MAX1220/MAX1258), external V
=
AVDD
DVDD
REF
AVDD
DVDD
REF
4.096V (MAX1220/MAX1258), f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor at REF,
CLK
SAMPLE
LOAD
T
A
= +25°C, unless otherwise noted.)
DAC-TO-DAC CROSSTALK
= 10kΩ, C = 100pF
DAC-TO-DAC CROSSTALK
R = 10kΩ, C = 100pF
LOAD
TEMPERATURE SENSOR ERROR
vs. TEMPERATURE
R
LOAD
LOAD
LOAD
MAX1220 toc47
MAX1220 toc48
1.00
0.75
0.50
0.25
0
V
OUTA
V
OUTA
1V/div
2V/div
-0.25
-0.50
-0.75
-1.00
V
OUTB
V
OUTB
10mV/div
AC-COUPLED
10mV/div
AC-COUPLED
MAX1257
MAX1220/MAX1258
100µs/div
100µs/div
-40
-15
10
35
60
85
TEMPERATURE (°C)
DYNAMIC RESPONSE RISE TIME
= 10kΩ, C = 100pF
DYNAMIC RESPONSE RISE TIME
= 10kΩ, C = 100pF
DYNAMIC RESPONSE FALL TIME
= 10kΩ, C = 100pF
MAX1220 toc51
R
R
R
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
MAX1220 toc49
MAX1220 toc50
MAX1257
MAX1257
CS
2V/div
V
V
OUT_
OUT_
1V/div
1V/div
07/MAX1258
V
OUT_
CS
1V/div
CS
1V/div
2V/div
MAX1220/MAX1258
1µs/div
1µs/div
1µs/div
DYNAMIC RESPONSE FALL TIME
= 10kΩ, C = 100pF
MAJOR CARRY TRANSITION
= 10kΩ, C = 100pF
MAJOR CARRY TRANSITION
R = 10kΩ, C = 100pF
LOAD
R
R
LOAD
LOAD
LOAD
LOAD
LOAD
MAX1220 toc52
MAX1220 toc53
MAX1220 toc54
CS
2V/div
CS
2V/div
CS
1V/div
V
V
OUT_
20mV/div
AC-COUPLED
OUT_
V
OUT_
10mV/div
AC-COUPLED
2V/div
MAX1257
MAX1220/MAX1258
1µs/div
MAX1220/MAX1258
1µs/div
1µs/div
14 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
Typical Operating Characteristics (continued)
(V
= V
= 3V (MAX1257), external V
= 2.5V (MAX1257), V
= V
= 5V (MAX1220/MAX1258), external V
=
AVDD
DVDD
REF
AVDD
DVDD
REF
4.096V (MAX1220/MAX1258), f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor at REF,
CLK
SAMPLE
LOAD
T
A
= +25°C, unless otherwise noted.)
DAC DIGITAL FEEDTHROUGH R
= 10kΩ,
DAC DIGITAL FEEDTHROUGH R
= 10kΩ,
NEGATIVE FULL-SCALE SETTLING TIME
= 10kΩ, C = 100pF
LOAD
LOAD
C
= 100pF, CS = HIGH, DIN = LOW
C
LOAD
= 100pF, CS = HIGH, DIN = LOW
R
LOAD
LOAD
LOAD
MAX1220 toc55
MAX1220 toc56
MAX1220 toc57
MAX1257
SCLK
2V/div
SCLK
1V/div
V
OUT_
1V/div
V
V
OUT_
OUT_
100mV/div
100mV/div
AC-COUPLED
AC-COUPLED
V
LDAC
1V/div
MAX1257
MAX1220/MAX1258
200ns/div
200ns/div
1µs/div
NEGATIVE FULL-SCALE SETTLING TIME
= 10kΩ, C = 100pF
POSITIVE FULL-SCALE SETTLING TIME
= 10kΩ, C = 100pF
POSITIVE FULL-SCALE SETTLING TIME
= 10kΩ, C = 100pF
MAX1220 toc60
R
R
R
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
MAX1220 toc58
MAX1220 toc59
MAX1257
V
V
LDAC
LDAC
2V/div
2V/div
V
OUT_
1V/div
V
OUT_
V
OUT_
2V/div
2V/div
V
LDAC
1V/div
MAX1220/MAX1258
2µs/div
MAX1220/MAX1258
1µs/div
1µs/div
ADC REFERENCE FEEDTHROUGH
= 10kΩ, C = 100pF
ADC REFERENCE FEEDTHROUGH
= 10kΩ, C = 100pF
R
R
LOAD
LOAD
LOAD
LOAD
MAX1220 toc61
MAX1220 toc62
V
REF2
V
REF2
1V/div
2V/div
V
DAC-OUT
V
DAC-OUT
10mV/div
AC-COUPLED
2mV/div
AC-COUPLED
MAX1257
MAX1220/MAX1258
ADC REFERENCE SWITCHING
ADC REFERENCE SWITCHING
200µs/div
200µs/div
______________________________________________________________________________________ 15
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Pin Description
PIN
NAME
FUNCTION
MAX1257
MAX1258
MAX1220
1, 2
3
—
GPIOA0, GPIOA1 General-Purpose I/O A0, A1. GPIOA0, A1 can sink and source 15mA.
Active-Low End-of-Conversion Output. Data is valid after the falling edge
4
EOC
of EOC.
Digital Positive-Power Input. Bypass DVDD to DGND with a 0.1µF
capacitor.
4
5
7
8
DVDD
DGND
DOUT
Digital Ground. Connect DGND to AGND.
Serial-Data Output. Data is clocked out on the falling edge of the SCLK
clock in modes 00, 01, and 10. Data is clocked out on the rising edge of
the SCLK clock in mode 11. It is high impedance when CS is high.
6
7
9
Serial-Clock Input. Clocks data in and out of the serial interface. (Duty
cycle must be 40% to 60%.) See Table 5 for details on programming the
clock mode.
10
11
SCLK
Serial-Data Input. DIN data is latched into the serial interface on the
falling edge of SCLK.
8
9–12, 16–19
13
DIN
OUT0–OUT7
AVDD
12–15,
22–25
DAC Outputs
Positive Analog Power Input. Bypass AVDD to AGND with a 0.1µF
capacitor.
18
14
19
—
AGND
N.C.
Analog Ground
07/MAX1258
15, 23, 32, 33
No Connection. Not internally connected.
Active-Low Load DAC. LDAC is an asynchronous active-low input that
updates the DAC outputs. Drive LDAC low to make the DAC registers
transparent.
20
21
26
27
LDAC
CS
Active-Low Chip-Select Input. When CS is low, the serial interface is
enabled. When CS is high, DOUT is high impedance.
Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up
the DAC outputs with a 100kꢀ resistor to AGND or set RES_SEL high to
22
28
—
RES_SEL
wake up the DAC outputs with a 100kꢀ resistor to V
high to power up the DAC input register to FFFh. Set RES_SEL low to
power up the DAC input register to 000h.
. Set RES_SEL
REF
24, 25
GPIOC0, GPIOC1 General-Purpose I/O C0, C1. GPIOC0, C1 can sink 4mA and source 2mA.
16 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
Pin Description (continued)
PIN
NAME
FUNCTION
MAX1257
MAX1258
MAX1220
Reference 1 Input. Reference voltage; leave unconnected to use the
internal reference (2.5V for the MAX1257 or 4.096V for the
MAX1220/MAX1258). REF1 is the positive reference in ADC external
differential reference mode. Bypass REF1 to AGND with a 0.1µF
capacitor in external reference mode only. See the ADC/DAC
References section.
26
35
REF1
27–31, 34
35
—
—
AIN0–AIN5
REF2/AIN6
Analog Inputs
Reference 2 Input/Analog Input 6. See Table 5 for details on
programming the setup register. REF2 is the negative reference in the
ADC external differential reference mode.
Active-Low Conversion-Start Input/Analog Input 7. See Table 5 for details
on programming the setup register.
36
—
CNVST/AIN7
CNVST/AIN15
Active-Low Conversion-Start Input/Analog Input 15. See Table 5 for
details on programming the setup register.
—
—
—
1
2, 3, 5, 6
GPIOA0–GPIOA3 General-Purpose I/O A0–A3. GPIOA0–GPIOA3 can sink and source 15mA.
16, 17,
20, 21
General-Purpose I/O B0–B3. GPIOB0–GPIOB3 can sink 4mA and
GPIOB0–GPIOB3
source 2mA.
General-Purpose I/O C0–C3. GPIOC0–GPIOC3 can sink 4mA and
—
—
29–32
GPIOC0–GPIOC3
source 2mA.
33, 34, 36–47
AIN0–AIN13
Analog Inputs
Reference 2 Input/Analog Input 14. See Table 5 for details on
programming the setup register. REF2 is the negative reference in the
ADC external differential reference mode.
—
—
48
—
REF2/AIN14
Exposed Pad. Must be externally connected to AGND. Do not use as a
ground connect.
EP
______________________________________________________________________________________ 17
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
(CPOL) and phase (CPHA) in the µC control registers to
Detailed Description
the same value. The MAX1220/MAX1257/MAX1258
The MAX1220/MAX1257/MAX1258 integrate a 12-bit,
operate with SCLK idling high or low, and thus operate
multichannel, analog-to-digital converter (ADC), and a
with CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS
12-bit, octal, digital-to-analog converter (DAC) in a sin-
low to latch any input data at DIN on the falling edge of
gle IC. These devices also include a temperature sen-
SCLK. Output data at DOUT is updated on the falling
sor and configurable GPIOs with
a 25MHz
edge of SCLK in clock modes 00, 01, and 10. Output
data at DOUT is updated on the rising edge of SCLK in
clock mode 11. See Figures 6–11. Bipolar true-differen-
tial results and temperature-sensor results are available
in two’s complement format, while all other results are in
binary.
SPI-/QSPI-/MICROWIRE-compatible serial interface.
The ADC is available in 8 and 16 input-channel
versions. The octal DAC outputs settle within 2.0µs, and
the ADC has a 225ksps conversion rate.
All devices include an internal reference (2.5V or
4.096V) providing a well-regulated, low-noise reference
for both the ADC and DAC. Programmable reference
modes for the ADC and DAC allow the use of an inter-
nal reference, an external reference, or a combination
of both. Features such as an internal 1°C accurate
temperature sensor, FIFO, scan modes, programmable
internal or external clock modes, data averaging, and
AutoShutdown allow users to minimize both power con-
sumption and processor requirements. The low glitch
energy (4nV•s) and low digital feedthrough (0.5nV•s) of
the integrated octal DACs make these devices ideal for
digital control of fast-response closed-loop systems.
A high-to-low transition on CS initiates the data-input
operation. Serial communications to the ADC always
begin with an 8-bit command byte (MSB first) loaded
from DIN. The command byte and the subsequent data
bytes are clocked from DIN into the serial interface on
the falling edge of SCLK. The serial-interface and fast-
interface circuitry is common to the ADC, DAC, and
GPIO sections. The content of the command byte
determines whether the SPI port should expect 8, 16, or
24 bits and whether the data is intended for the ADC,
DAC, or GPIOs (if applicable). See Table 1. Driving CS
high resets the serial interface.
These devices are guaranteed to operate with a supply
voltage from +2.7V to +3.6V (MAX1257) and from
+4.75V to +5.25V (MAX1220/MAX1258). These devices
consume 2.5mA at 225ksps throughput, only 22µA at
1ksps throughput, and under 0.2µA in the shutdown
mode. The MAX1257/MAX1258 feature 12 GPIOs while
the MAX1220 offers four GPIOs that can be configured
as inputs or outputs.
The conversion register controls ADC channel selec-
tion, ADC scan mode, and temperature-measurement
requests. See Table 4 for information on writing to the
conversion register. The setup register controls the
clock mode, reference, and unipolar/bipolar ADC con-
figuration. Use a second byte, following the first, to
write to the unipolar-mode or bipolar-mode registers.
See Table 5 for details of the setup register and see
Tables 6, 7, and 8 for setting the unipolar- and bipolar-
mode registers. Hold CS low between the command
byte and the second and third byte. The ADC averag-
ing register is specific to the ADC. See Table 9 to
address that register. Table 11 shows the details of the
reset register.
07/MAX1258
Figure 1 shows the MAX1257/MAX1258 functional dia-
gram. The MAX1220 only includes the GPIOA0,
GPIOA1 and GPIOC0, GPIOC1 block. The output-con-
ditioning circuitry takes the internal parallel data bus
and converts it to a serial data format at DOUT, with the
appropriate wake-up timing. The arithmetic logic unit
(ALU) performs the averaging function.
Begin a write to the DAC by writing 0001XXXX as a
command byte. The last 4 bits of this command byte
are don’t-care bits. Write another 2 bytes (holding CS
low) to the DAC interface register following the com-
mand byte to select the appropriate DAC and the data
to be written to it. See the DAC Serial Interface section
and Tables 10, 20, and 21.
SPI-Compatible Serial Interface
The MAX1220/MAX1257/MAX1258 feature a serial inter-
face that is compatible with SPI and MICROWIRE
devices. For SPI, ensure the SPI bus master (typically a
microcontroller (µC)) runs in master mode so that it
generates the serial clock signal. Select the SCLK fre-
quency of 25MHz or less, and set the clock polarity
18 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
DVDD
AVDD
GPIOB0– GPIOC0–
GPIOB3 GPIOC3
GPIOA0–
GPIOA3
MAX1257
MAX1258
GPIO
CONTROL
USER-PROGRAMMABLE
I/O
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
OSCILLATOR
SCLK
CS
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
DIN
SPI
PORT
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
DOUT
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
TEMPERATURE
SENSOR
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
EOC
LOGIC
CONTROL
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
CNVST
AIN0
12-BIT
SAR
ADC
OUTPUT
CONDITIONING
12-BIT
DAC
FIFO AND
ALU
INPUT
REGISTER
DAC
REGISTER
T/H
AIN13
REF2/
AIN14
CNVST/
AIN15
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
REF2
INTERNAL
REFERENCE
REF1
RES_SEL
LDAC
AGND
DGND
Figure 1. MAX1257/MAX1258 Functional Diagram
______________________________________________________________________________________ 19
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 1ꢀ Command Byte (MSB First)
ADDITIONAL
REGISTER
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NO. OF
BYTES
Conversion
Setup
1
0
0
0
0
0
0
0
0
CHSEL3
CHSEL2
CHSEL1
CHSEL0
SCAN1
SCAN0
TEMP
0
1
0
0
0
0
0
0
0
CKSEL1
CKSEL0
REFSEL1 REFSEL0 DIFFSEL1 DIFFSEL0
1
ADC
1
0
0
0
0
0
0
AVGON
NAVG1
NAVG0
NSCAN1
NSCAN0
0
2
DAC Select
Reset
1
0
0
0
0
0
X
1
0
0
0
0
X
X
X
RESET
SLOW
FBGON
0
GPIO Configure
GPIO Write
0
0
0
0
1
1
0
0
1
0
1
0
1 or 2
1 or 2
1 or 2
0
GPIO Read
No Operation
X = Don’t care.
Write to the GPIOs by issuing a command byte to the
appropriate register. Writing to the MAX1220 GPIOs
requires 1 additional byte following the command byte.
Writing to the MAX1257/MAX1258 requires 2 additional
bytes following the command byte. See Tables 12–19
for details on GPIO configuration, writes, and reads.
See the GPIO Command section. Command bytes writ-
ten to the GPIOs on devices without GPIOs are ignored.
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conver-
sion start and use it to request internally timed conver-
sions, without tying up the serial bus. In clock mode 01,
use CNVST to request conversions one channel at a
time, thereby controlling the sampling speed without
tying up the serial bus. Request and start internally
timed conversions through the serial interface by writ-
ing to the conversion register in the default clock mode,
10. Use clock mode 11 with SCLK up to 3.6MHz for
externally timed acquisitions to achieve sampling rates
up to 225ksps. Clock mode 11 disables scanning and
averaging. See Figures 6–9 for timing specifications on
how to begin a conversion.
Power-Up Default State
The MAX1220/MAX1257/MAX1258 power up with all
blocks in shutdown (including the reference). All regis-
ters power up in state 00000000, except for the setup
register and the DAC input register. The setup register
powers up at 0010 1000 with CKSEL1 = 1 and
REFSEL1 = 1. The DAC input register powers up to
FFFh when RES_SEL is high and powers up to 000h
when RES_SEL is low.
07/MAX1258
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the last
requested operation and is waiting for the next com-
mand byte. EOC goes high when CS or CNVST go low.
EOC is always high in clock mode 11.
12-Bit ADC
The MAX1220/MAX1257/MAX1258 ADCs use a fully
differential successive-approximation register (SAR)
conversion technique and on-chip track-and-hold (T/H)
circuitry to convert temperature and voltage signals into
12-bit digital results. The analog inputs accept both sin-
gle-ended and differential input signals. Single-ended
signals are converted using a unipolar transfer function,
and differential signals are converted using a selec-
table bipolar or unipolar transfer function. See the ADC
Transfer Functions section for more data.
Single-Ended or Differential Conversions
The MAX1220/MAX1257/MAX1258 use a fully differen-
tial ADC for all conversions. When a pair of inputs are
connected as a differential pair, each input is connect-
ed to the ADC. When configured in single-ended mode,
the positive input is the single-ended channel and the
negative input is referred to AGND. See Figure 2.
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from the
following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13,
AIN14/AIN15. AIN0–AIN7 are available on all devices.
AIN0–AIN15 are available on the MAX1257/MAX1258.
ADC Clock Modes
When addressing the setup, register bits 5 and 4 of the
command byte (CKSEL1 and CKSEL0, respectively)
control the ADC clock modes. See Table 5. Choose
between four different clock modes for various ways to
20 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
See Tables 5–8 for more details on configuring the
inputs. For the inputs that are configurable as CNVST,
REF2, and an analog input, only one function can be
used at a time.
AIN5–AIN15 (only negative inputs) in differential mode.
For external T/H timing, use clock mode 01. After the
T/H enters hold mode, the difference between the sam-
pled positive and negative input voltages is converted.
The input capacitance charging rate determines the
time required for the T/H to acquire an input signal. If
the input signal’s source impedance is high, the
required acquisition time lengthens.
Unipolar or Bipolar Conversions
Address the unipolar- and bipolar-mode registers
through the setup register (bits 1 and 0). See Table 5 for
the setup register. See Figures 3 and 4 for the transfer-
function graphs. Program a pair of analog inputs for dif-
ferential operation by writing a one to the appropriate bit
of the bipolar- or unipolar-mode register. Unipolar mode
Any source impedance below 300Ω does not signifi-
cantly affect the ADC’s AC performance. A high-imped-
ance source can be accommodated either by
lengthening t
(only in clock mode 01) or by placing
ACQ
sets the differential input range from 0 to V
A nega-
REF1.
a 1µF capacitor between the positive and negative ana-
log inputs. The combination of the analog-input source
impedance and the capacitance at the analog input cre-
ates an RC filter that limits the analog input bandwidth.
tive differential analog input in unipolar mode causes the
digital output code to be zero. Selecting bipolar mode
sets the differential input range to
V
REF1
/ 2. The digital
output code is binary in unipolar mode and two’s com-
plement in bipolar mode.
ꢂnput Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, making it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequen-
cy signals aliasing into the frequency band
of interest.
In single-ended mode, the MAX1220/MAX1257/
MAX1258 always operate in unipolar mode. The analog
inputs are internally referenced to AGND with a full-scale
input range from 0 to the selected reference voltage.
Analog ꢂnput (T/H)
The equivalent circuit of Figure 2 shows the ADC input
architecture of the MAX1220/MAX1257/MAX1258. In
track mode, a positive input capacitor is connected to
AIN0–AIN15 in single-ended mode and AIN0, AIN2,
and AIN4–AIN14 (only positive inputs) in differential
mode. A negative input capacitor is connected to
AGND in single-ended mode or AIN1, AIN3, and
Analog ꢂnput Protection
Internal electrostatic-discharge (ESD) protection diodes
clamp all analog inputs to AVDD and AGND, allowing
the inputs to swing from (AGND - 0.3V) to (AVDD +
0.3V) without damage. However, for accurate conver-
sions near full scale, the inputs must not exceed AVDD
by more than 50mV or be lower than AGND by 50mV. If
an analog input voltage exceeds the supplies, limit the
input current to 2mA.
AIN0–AIN15
(SINGLE-ENDED),
AIN0, AIN2,
REF1
DAC
ACQ
AGND
AIN4–AIN14
(DIFFERENTIAL)
CIN+
ꢂnternal FꢂFO
The MAX1220/MAX1257/MAX1258 contain a first-
in/first-out (FIFO) buffer that holds up to 16 ADC results
plus one temperature result. The internal FIFO allows
the ADC to process and store multiple internally
clocked conversions and a temperature measurement
without being serviced by the serial bus.
COMPARATOR
HOLD
CIN-
AGND
(SINGLE-ENDED),
AIN1, AIN3,
AIN5–AIN15
(DIFFERENTIAL)
If the FIFO is filled and further conversions are request-
ed without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading zeros. After each falling edge of CS, the oldest
available pair of bytes of data is available at DOUT,
MSB first. When the FIFO is empty, DOUT is zero.
ACQ
ACQ
HOLD
HOLD
AV / 2
DD
Figure 2. Equivalent Input Circuit
______________________________________________________________________________________ 21
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
The first 2 bytes of data read out after a temperature
measurement always contain the 12-bit temperature
result, preceded by four leading zeros, MSB first. If
another temperature measurement is performed before
the first temperature result is read out, the old measure-
ment is overwritten by the new result. Temperature
results are in degrees Celsius (two’s complement), at a
resolution of 8 LSB per degree. See the Temperature
Measurements section for details on converting the dig-
ital code to a temperature.
The MAX1257 internal reference is 2.5V. The
MAX1220/MAX1258 internal reference is 4.096V. When
using an external reference on any of these devices,
the voltage range is 0.7V to V
.
AVDD
DAC Transfer Function
See Table 2 for various analog outputs from the DAC.
DAC Power-On Wake-Up Modes
The state of the RES_SEL input determines the wake-up
state of the DAC outputs. Connect RES_SEL to AVDD
or AGND upon power-up to be sure the DAC outputs
wake up to a known state. Connect RES_SEL to AGND
to wake up all DAC outputs at 000h. While RES_SEL is
low, the 100kΩ internal resistor pulls the DAC outputs to
AGND and the output buffers are powered down.
Connect RES_SEL to AVDD to wake up all DAC outputs
at FFFh. While RES_SEL is high, the 100kΩ pullup
12-Bit DAC
In addition to the 12-bit ADC, the MAX1220/
MAX1257/MAX1258 also include eight voltage-output,
12-bit, monotonic DACs with less than 4 LSB integral
nonlinearity error and less than 1 LSB differential nonlin-
earity error. Each DAC has a 2µs settling time and ultra-
low glitch energy (4nV•s). The 12-bit DAC code is
resistor pulls the DAC outputs to V
buffers are powered down.
and the output
REF1
unipolar binary with 1 LSB = V
/4096.
REF
DAC Digital ꢂnterface
DAC Power-Up Modes
See Table 21 for a description of the DAC power-up
and power-down modes.
Figure 1 shows the functional diagram of the MAX1257/
MAX1258. The shift register converts a serial 16-bit word
to parallel data for each input register operating with a
clock rate up to 25MHz. The SPI-compatible digital inter-
face to the shift register consists of CS, SCLK, DIN, and
DOUT. Serial data at DIN is loaded on the falling edge
of SCLK. Pull CS low to begin a write sequence. Begin a
write to the DAC by writing 0001XXXX as a command
byte. The last 4 bits of the DAC select register are don’t-
care bits. See Table 10. Write another 2 bytes to the
DAC interface register following the command byte to
select the appropriate DAC and the data to be written to
it. See Tables 20 and 21.
GPIOs
In addition to the internal ADC and DAC, the
MAX1257/MAX1258 also provide 12 general-purpose
input/output channels, GPIOA0–GPIOA3, GPIOB0–
07/MAX1258
Table 2ꢀ DAC Output Code Table
DAC COITEITS
AIAꢁOG OUTPUT
MSB
ꢁSB
The eight double-buffered DACs include an input and a
DAC register. The input registers are directly connect-
ed to the shift register and hold the result of the most
recent write operation. The eight 12-bit DAC registers
hold the current output code for the respective DAC.
Data can be transferred from the input registers to the
DAC registers by pulling LDAC low or by writing the
appropriate DAC command sequence at DIN. See
Table 20. The outputs of the DACs are buffered through
eight rail-to-rail op amps.
4095
4096
⎛
⎞
1111
1111
0000
0000
0111
1111
+V
REF
⎜
⎝
⎟
⎠
2049
4096
⎛
⎞
1000
1000
0111
0001
0000
0111
+V
REF
⎜
⎝
⎟
⎠
2048
4096
+V
REF
⎛
⎞
⎛
⎞
+V
=
REF
⎜
⎝
⎟
⎠
⎜
⎝
⎟
⎠
2
The MAX1220/MAX1257/MAX1258 DAC output voltage
range is based on the internal reference or an external
reference. Write to the setup register (see Table 5) to
program the reference. If using an external voltage ref-
erence, bypass REF1 with a 0.1µF capacitor to AGND.
2047
4096
⎛
⎞
+V
REF
⎜
⎝
⎟
⎠
1
⎛
⎞
0000
0000
0000
0000
0001
0000
+V
REF
⎜
⎝
⎟
⎠
4096
0
22 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
GPIOB3, and GPIOC0–GPIOC3. The MAX1220 includes
four GPIO channels (GPIOA0, GPIOA1, GPIOC0,
GPIOC1). Read and write to the GPIOs as detailed in
Table 1 and Tables 12–19. Also, see the GPIO Command
section. See Figures 11 and 12 for GPIO timing.
mode, connect a 0.1µF capacitor to AGND. Set
REFSEL[1:0] = 01 to program the ADC and DAC for
external-reference mode. The DAC uses REF1 as its
external reference, while the ADC uses REF2 as its
external reference. Set REFSEL[1:0] = 11 to program
the ADC for external differential reference mode. REF1
is the positive reference and REF2 is the negative refer-
ence in the ADC external differential mode.
Write to the GPIOs by writing a command byte to the
GPIO command register. Write a single data byte to the
MAX1220 following the command byte. Write 2 bytes to
the MAX1257/MAX1258 following the command byte.
When REFSEL[1:0] = 00 or 10, REF2/AIN_ functions as
an analog input channel. When REFSEL[1:0] = 01 or 11,
REF2/AIN_ functions as the device’s negative reference.
The GPIOs can sink and source current. The
MAX1257/MAX1258 GPIOA0–GPIOA3 can sink and
source up to 15mA. GPIOB0–GPIOB3 and GPIOC0–
GPIOC3 can sink 4mA and source 2mA. The MAX1220
GPIOA0 and GPIOA1 can sink and source up to 15mA.
The MAX1220 GPIOC0 and GPIOC1 can sink 4mA and
source 2mA. See Table 3.
Temperature Measurements
Issue a command byte setting bit 0 of the conversion
register to one to take a temperature measurement.
See Table 4. The MAX1220/MAX1257/MAX1258 perform
temperature measurements with an internal diode-con-
nected transistor. The diode bias current changes from
68µA to 4µA to produce a temperature-dependent bias
voltage difference. The second conversion result at 4µA
is subtracted from the first at 68µA to calculate a digital
value that is proportional to absolute temperature. The
output data appearing at DOUT is the digital code
above, minus an offset to adjust from Kelvin to Celsius.
Clock Modes
ꢂnternal Clock
The MAX1220/MAX1257/MAX1258 can operate from an
internal oscillator. The internal oscillator is active in
clock modes 00, 01, and 10. Figures 6, 7, and 8 show
how to start an ADC conversion in the three internally
timed conversion modes.
The reference voltage used for the temperature mea-
surements is always derived from the internal reference
source to ensure that 1 LSB corresponds to 1/8 of a
degree Celsius. On every scan where a temperature
measurement is requested, the temperature conversion
is carried out first. The first 2 bytes of data read from
the FIFO contain the result of the temperature measure-
ment. If another temperature measurement is per-
formed before the first temperature result is read out,
the old measurement is overwritten by the new result.
Temperature results are in degrees Celsius (two’s com-
plement). See the Applications Information section for
information on how to perform temperature measure-
ments in each clock mode.
Read out the data at clock speeds up to 25MHz
through the SPI interface.
External Clock
Set CKSEL1 and CKSEL0 in the setup register to 11 to
set up the interface for external clock mode 11. See
Table 5. Pulse SCLK at speeds from 0.1MHz to
3.6MHz. Write to SCLK with a 40% to 60% duty cycle.
The SCLK frequency controls the conversion timing.
See Figures 9a and 9b for clock mode 11 timing. See
the ADC Conversions in Clock Mode 11 section.
ADC/DAC References
Address the reference through the setup register, bits 3
and 2. See Table 5. Following a wake-up delay, set
REFSEL[1:0] = 00 to program both the ADC and DAC
for internal reference use. Set REFSEL[1:0] = 10 to pro-
gram the ADC for internal reference. Set REFSEL[1:0] =
10 to program the DAC for external reference, REF1.
When using REF1 or REF2/AIN_ in external-reference
Register Descriptions
The MAX1220/MAX1257/MAX1258 communicate
between the internal registers and the external circuitry
through the SPI-compatible serial interface. Table 1
details the command byte, the registers, and the bit
Table 3ꢀ GPꢂO Maximum Sink/Source Current
MAX1257/MAX1258 (mA)
CURREIT
MAX1220 (mA)
GPꢂOA0–GPꢂOA3
GPꢂOB0–GPꢂOB3
GPꢂOC0–GPꢂOC3
GPꢂOA0, GPꢂOA1
GPꢂOC0, GPꢂOC1
Sink
15
15
4
2
4
2
15
15
4
2
Source
______________________________________________________________________________________ 23
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
names. Tables 4–12 show the various functions within
Table 4ꢀ Conversion Register*
the conversion register, setup register, unipolar-mode
BIT
BIT
FUNCTION
register, bipolar-mode register, ADC averaging regis-
ter, DAC select register, reset register, and GPIO com-
mand register, respectively.
NAME
—
7 (MSB)
Set to one to select conversion register.
Analog-input channel select.
Analog-input channel select.
Analog-input channel select.
Analog-input channel select.
Scan-mode select.
CHSEL3
CHSEL2
CHSEL1
CHSEL0
SCAN1
SCAN0
6
5
4
3
2
1
Conversion Register
Select active analog input channels, scan modes, and
a single temperature measurement per scan by issuing
a command byte to the conversion register. Table 4
details channel selection, the four scan modes, and
how to request a temperature measurement. Start a
scan by writing to the conversion register when in clock
mode 10 or 11, or by applying a low pulse to the
CNVST pin when in clock mode 00 or 01. See Figures 6
and 7 for timing specifications for starting a scan with
CNVST.
Scan-mode select.
Set to one to take a single temp-
erature measurement. The first
conversion result of a scan contains
temperature information.
TEMP
0 (LSB)
*See below for bit details.
A conversion is not performed if it is requested on a
channel or one of the channel pairs that has been con-
figured as CNVST or REF2. For channels configured as
differential pairs, the CHSEL0 bit is ignored and the two
pins are treated as a single differential channel.
SELECTED
CHANNEL
(N)
CHSEL3
CHSEL2
CHSEL1
CHSEL0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN0
Select scan mode 00 or 01 to return one result per sin-
gle-ended channel and one result per differential pair
within the selected scanning range (set by bits 2 and 1,
SCAN1 and SCAN0), plus one temperature result, if
selected. Select scan mode 10 to scan a single input
channel numerous times, depending on NSCAN1 and
NSCAN0 in the ADC averaging register (Table 9).
Select scan mode 11 to return only one result from a
single channel.
AIN1
AIN2
AIN3
AIN4
AIN5
07/MAX1258
AIN6
AIN7
AIN8
Setup Register
Issue a command byte to the setup register to config-
ure the clock, reference, power-down modes, and ADC
single-ended/differential modes. Table 5 details the bits
in the setup-register command byte. Bits 5 and 4
(CKSEL1 and CKSEL0) control the clock mode, acqui-
sition and sampling, and the conversion start. Bits 3
and 2 (REFSEL1 and REFSEL0) set the device for either
internal or external reference. Bits 1 and 0 (DIFFSEL1
and DIFFSEL0) address the ADC unipolar-mode and
bipolar-mode registers and configure the analog input
channels for differential operation.
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
SCAN MODE
SCAN1 SCAN0
(CHANNEL N IS SELECTED BY
BITS CHSEL3–CHSEL0)
0
0
0
1
Scans channels 0 through N.
Scans channels N through the highest
numbered channel.
Scans channel N repeatedly. The ADC
averaging register sets the number of
results.
1
1
0
1
No scan. Converts channel N once only.
24 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
Table 5ꢀ Setup Register*
BꢂT IAME
—
BꢂT
FUICTꢂOI
7 (MSB)
Set to zero to select setup register.
Set to one to select setup register.
—
6
CKSEL1
CKSEL0
REFSEL1
REFSEL0
DIFFSEL1
DIFFSEL0
5
Clock mode and CNVST configuration; resets to one at power-up.
Clock mode and CNVST configuration.
4
3
Reference-mode configuration.
2
1
Reference-mode configuration.
Unipolar-/bipolar-mode register configuration for differential mode.
Unipolar-/bipolar-mode register configuration for differential mode.
0 (LSB)
*See below for bit details.
Table 5aꢀ Clock Modes*
CKSEꢁ1
CKSEꢁ0
COIVERSꢂOI CꢁOCK
ACQUꢂSꢂTꢂOI/SAMPꢁꢂIG
Internally timed.
CNVST COIFꢂGURATꢂOI
0
0
1
1
0
1
0
1
Internal
Internal
CNVST
CNVST
Externally timed by CNVST.
Internally timed.
Internal
AIN15/AIN7
AIN15/AIN7
External (3.6MHz max)
Externally timed by SCLK.
*See the Clock Modes section.
Table 5bꢀ Clock Modes 00, 01, and 10
VOꢁTAGE
REFEREICE COIDꢂTꢂOIS
OVERRꢂDE
REF2
COIFꢂGURATꢂOI
REFSEꢁ1 REFSEꢁ0
AUTOSHUTDOWI
Internal reference turns off after scan is complete. If
internal reference is turned off, there is a programmed
delay of 218 internal-conversion clock cycles.
AIN
Internal (DAC
and ADC)
0
0
0
1
AIN14/AIN6
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
AIN
Internal reference not used.
External single-
ended (REF1
for DAC and
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
REF2
REF2 for ADC)
Default reference mode. Internal reference turns off
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 internal-
AIN
Internal (ADC)
and external
REF1 (DAC)
conversion clock cycles.
1
1
0
1
AIN14/AIN6
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
AIN
Internal reference not used.
External
differential
(ADC), external
REF1 (DAC)
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
REF2
______________________________________________________________________________________ 25
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
The ADC reference is always on if any of the following
conditions are true:
3) At least one DAC is powered down through the
100kΩ to VREF and REFSEL[1:0] = 00.
1) The FBGON bit is set to one in the reset register.
If any of the above conditions exist, the ADC reference
is always on, but there is a 188 clock-cycle delay
before temperature-sensor measurements begin, if
requested.
2) At least one DAC output is powered up and
REFSEL[1:0] (in the setup register) = 00.
Table 5cꢀ Clock Mode 11
VOꢁTAGE
REFEREICE COIDꢂTꢂOIS
OVERRꢂDE
REF2
AUTOSHUTDOWI
REFSEꢁ1 REFSEꢁ0
COIFꢂGURATꢂOI
Internal reference turns off after scan is complete. If
internal reference is turned off, there is a programmed
delay of 218 external conversion clock cycles.
AIN
Internal (DAC
and ADC)
0
0
0
1
AIN14/AIN6
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Temperature
AIN
External single-
Internal reference not used.
Internal reference required. There is a programmed
ended (REF1
for DAC and
REF2 for ADC)
REF2
AIN14/AIN6
REF2
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Temperature
Default reference mode. Internal reference turns off
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 external
conversion clock cycles.
07/MAX1258
AIN
Internal (ADC)
and external
REF1 (DAC)
1
1
0
1
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Temperature
AIN
Internal reference not used.
External
differential
(ADC), external
REF1 (DAC)
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Temperature
Table 5dꢀ Differential Select Modes
DꢂFFSEꢁ1 DꢂFFSEꢁ0
FUICTꢂOI
0
0
1
1
0
1
0
1
No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
1 byte of data follows the command setup byte and is written to the unipolar-mode register.
1 byte of data follows the command setup byte and is written to the bipolar-mode register.
26 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
Table 6ꢀ Unipolar-Mode Register (Addressed Through the Setup Register)
BꢂT IAME
UCH0/1
BꢂT
FUICTꢂOI
Configure AIN0 and AIN1 for unipolar differential conversion.
Configure AIN2 and AIN3 for unipolar differential conversion.
Configure AIN4 and AIN5 for unipolar differential conversion.
Configure AIN6 and AIN7 for unipolar differential conversion.
Configure AIN8 and AIN9 for unipolar differential conversion.
Configure AIN10 and AIN11 for unipolar differential conversion.
Configure AIN12 and AIN13 for unipolar differential conversion.
Configure AIN14 and AIN15 for unipolar differential conversion.
7 (MSB)
UCH2/3
6
UCH4/5
5
UCH6/7
4
UCH8/9
3
UCH10/11
UCH12/13
UCH14/15
2
1
0 (LSB)
Table 7ꢀ Bipolar-Mode Register (Addressed Through the Setup Register)
BꢂT IAME
BꢂT
FUICTꢂOI
Set to one to configure AIN0 and AIN1 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN0 and AIN1 for unipolar
single-ended conversion.
BCH0/1
7 (MSB)
Set to one to configure AIN2 and AIN3 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN2 and AIN3 for unipolar
single-ended conversion.
BCH2/3
BCH4/5
6
Set to one to configure AIN4 and AIN5 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN4 and AIN5 for unipolar
single-ended conversion.
5
Set to one to configure AIN6 and AIN7 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN6 and AIN7 for unipolar
single-ended conversion.
BCH6/7
4
Set to one to configure AIN8 and AIN9 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN8 and AIN9 for unipolar
single-ended conversion.
BCH8/9
3
Set to one to configure AIN10 and AIN11 for bipolar differential conversion. Set the corresponding
bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN10 and AIN11 for
unipolar single-ended conversion.
BCH10/11
BCH12/13
BCH14/15
2
1
Set to one to configure AIN12 and AIN13 for bipolar differential conversion. Set the corresponding
bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN12 and AIN13 for
unipolar single-ended conversion.
Set to one to configure AIN14 and AIN15 for bipolar differential conversion. Set the corresponding
bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN14 and AIN15 for
unipolar single-ended conversion.
0 (LSB)
______________________________________________________________________________________ 27
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Unipolar/Bipolar Registers
The final 2 bits (LSBs) of the setup register control the
unipolar-/bipolar-mode address registers. Set
DIFFSEL[1:0] = 10 to write to the unipolar-mode regis-
ter. Set bits DIFFSEL[1:0] = 11 to write to the bipolar-
mode register. In both cases, the setup command byte
must be followed by 1 byte of data that is written to the
unipolar-mode register or bipolar-mode register. Hold
CS low and run 16 SCLK cycles before pulling CS high.
If the last 2 bits of the setup register are 00 or 01, nei-
ther the unipolar-mode register nor the bipolar-mode
register is written. Any subsequent byte is recognized
as a new command byte. See Tables 6, 7, and 8 to pro-
gram the unipolar- and bipolar-mode registers.
Both registers power up at all zeros to set the inputs as
16 unipolar single-ended channels. To configure a
channel pair as single-ended unipolar, bipolar differen-
tial, or unipolar differential, see Table 8.
In unipolar mode, AIN+ can exceed AIN- by up to
REF
bipolar mode, either input can exceed the other by up
Table 8ꢀ Unipolar/Bipolar Channel Function
V
. The output format in unipolar mode is binary. In
UIꢂPOꢁAR-
to V
/ 2. The output format in bipolar mode is two’s
REF
BꢂPOꢁAR-MODE
REGꢂSTER BꢂT
CHAIIEꢁ PAꢂR
FUICTꢂOI
MODE
complement (see the ADC Transfer Functions section).
REGꢂSTER BꢂT
ADC Averaging Register
Write a command byte to the ADC averaging register to
configure the ADC to average up to 32 samples for
each requested result, and to independently control the
number of results requested for single-channel scans.
0
0
1
1
0
1
0
1
Unipolar single-ended
Bipolar differential
Unipolar differential
Unipolar differential
Table 9ꢀ ADC Averaging Register*
BꢂT IAME
—
BꢂT
FUICTꢂOI
7 (MSB)
Set to zero to select ADC averaging register.
—
6
Set to zero to select ADC averaging register.
—
5
Set to one to select ADC averaging register.
07/MAX1258
AVGON
NAVG1
NAVG0
NSCAN1
NSCAN0
4
Set to one to turn averaging on. Set to zero to turn averaging off.
Configures the number of conversions for single-channel scans.
Configures the number of conversions for single-channel scans.
Single-channel scan count. (Scan mode 10 only.)
Single-channel scan count. (Scan mode 10 only.)
3
2
1
0 (LSB)
*See below for bit details.
FUICTꢂOI
AVGOI
IAVG1
IAVG0
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Performs one conversion for each requested result.
Performs four conversions and returns the average for each requested result.
Performs eight conversions and returns the average for each requested result.
Performs 16 conversions and returns the average for each requested result.
Performs 32 conversions and returns the average for each requested result.
ISCAI1
ISCAI0
FUICTꢂOI (APPꢁꢂES OIꢁY ꢂF SCAI MODE 10 ꢂS SEꢁECTED)
Scans channel N and returns four results.
0
0
1
1
0
1
0
1
Scans channel N and returns eight results.
Scans channel N and returns 12 results.
Scans channel N and returns 16 results.
28 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
Table 9 details the four scan modes available in the
ADC conversion register. All four scan modes allow
averaging as long as the AVGON bit, bit 4 in the
averaging register, is set to 1. Select scan mode 10 to
scan the same channel multiple times. Clock mode 11
disables averaging. For example, if AVGON = 1,
NAVG[1:0] = 00, NSCAN[1:0] = 11, and SCAN[1:0] =
10, 16 results are written to the FIFO, with each result
being the average of four conversions of channel N.
byte controls the DAC serial interface. See Table 20
and the DAC Serial Interface section.
Reset Register
Write to the reset register (as shown in Table 11) to
clear the FIFO or reset all registers (excluding the DAC
and GPIO registers) to their default states. When the
RESET bit in the reset register is set to 0, the FIFO is
cleared. Set the RESET bit to one to return all the
device registers to their default power-up state. All reg-
isters power up in state 00000000, except for the setup
register that powers up in clock mode 10 (CKSEL1 = 1
and REFSEL1 = 1). The DAC and GPIO registers are
not reset by writing to the reset register. Set the SLOW
bit to one to add a 15ns delay in the DOUT signal path
to provide a longer hold time. Writing a one to the
SLOW bit also clears the contents of the FIFO. Set the
FBGON bit to one to force the bias block and bandgap
reference to power up regardless of the state of the
DAC and activity of the ADC block. Setting the FBGON
bit high also removes the programmed wake-up delay
between conversions in clock modes 01 and 11.
Setting the FBGON bit high also clears the FIFO.
DAC Select Register
Write a command byte 0001XXXX to the DAC select
register (as shown in Table 10) to set up the DAC inter-
face and indicate that another word will follow. The last
4 bits of the DAC select register are don’t-care bits. The
word that follows the DAC select-register command
Table 10ꢀ DAC Select Register
BꢂT
IAME
BꢂT
FUICTꢂOI
—
—
—
—
X
7 (MSB) Set to zero to select DAC select register.
6
5
4
3
2
1
0
Set to zero to select DAC select register.
Set to zero to select DAC select register.
Set to one to select DAC select register.
Don’t care.
Table 12ꢀ GPꢂO Command Register
X
Don’t care.
BꢂT IAME
BꢂT
FUICTꢂOI
X
Don’t care.
—
7 (MSB)
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
GPIO configuration bit.
X
Don’t care.
—
6
—
5
Table 11ꢀ Reset Register
—
—
4
3
BꢂT
BꢂT
FUICTꢂOI
—
2
1
IAME
GPIOSEL1
GPIOSEL2
—
—
—
—
—
7 (MSB) Set to zero to select ADC reset register.
0 (LSB)
GPIO write bit.
6
5
4
3
Set to zero to select ADC reset register.
Set to zero to select ADC reset register.
Set to zero to select ADC reset register.
Set to one to select ADC reset register.
GPꢂOSEꢁ1 GPꢂOSEꢁ2
FUICTꢂOI
GPIO configuration; written data is
entered in the GPIO configuration
register.
1
1
0
1
0
1
Set to zero to clear the FIFO only. Set to
one to set the device in its power-on
condition.
RESET
SLOW
2
1
GPIO write; written data is entered
in the GPIO write register.
Set to one to turn on slow mode.
GPIO read; the next 8/16 SCLK
cycles transfer the state of all GPIO
drivers into DOUT.
Set to one to force internal bias block and
bandgap reference to be always powered
up.
FBGON 0 (LSB)
______________________________________________________________________________________ 29
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
GPꢂO Command
Write a command byte to the GPIO command register
to configure, write, or read the GPIOs, as detailed in
Table 12.
ration register in the MAX1257/MAX1258. See Tables
13 and 14. The register bits are updated after the last
CS rising edge. All GPIOs default to inputs upon power-
up.
Write the command byte 00000011 to configure the
GPIOs. The eight SCLK cycles following the command
byte load data from DIN to the GPIO configuration reg-
ister in the MAX1220. The 16 SCLK cycles following the
command byte load data from DIN to the GPIO configu-
The data in the register controls the function of each
GPIO, as shown in Tables 13–19.
Table 13ꢀ MAX1220 GPꢂO Configuration
DATA PꢂI
DꢂI
DOUT
GPꢂO COMMAID BYTE
DATA BYTE
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
GPIOC1
0
GPIOC0
0
GPIOA1
0
GPIOA0
0
X
0
X
0
X
0
X
0
Table 14ꢀ MAX1257/MAX1258 GPꢂO Configuration
DATA PIN
GPIO COMMAND BYTE
DATA BYTE 1
DATA BYTE 2
DIN
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
X
0
X
X
X
0
DOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
07/MAX1258
Table 15ꢀ MAX1220 GPꢂO Write
DATA PꢂI
DꢂI
GPꢂO COMMAID BYTE
DATA BYTE
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
GPIOC1
0
GPIOC0
0
GPIOA1
0
GPIOA0
0
X
0
X
0
X
X
0
DOUT
0
Table 16ꢀ MAX1257/MAX1258 GPꢂO Write
DATA PIN
GPIO COMMAND BYTE
DATA BYTE 1
DATA BYTE 2
DIN
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
X
0
X
X
X
0
DOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
30 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
GPꢂO Write
Write the command byte 00000010 to indicate a GPIO
write operation. The eight SCLK cycles following the
command byte load data from DIN into the GPIO write
register in the MAX1220. The 16 SCLK cycles following
the command byte load data from DIN into the GPIO
write register in the MAX1257/MAX1258. See Tables 15
and 16. The register bits are updated after the last CS
rising edge.
GPꢂO Read
Write the command byte 00000001 to indicate a GPIO
read operation. The eight SCLK cycles following the
command byte transfer the state of the GPIOs to DOUT
in the MAX1220. The 16 SCLK cycles following the com-
mand byte transfer the state of the GPIOs to DOUT in the
MAX1257/MAX1258. See Tables 18 and 19.
DAC Serial ꢂnterface
Write a command byte 0001XXXX to the DAC select
register to indicate the word to follow is written to the
DAC serial interface, as detailed in Tables 1, 10, 20, and
21. Write the next 16 bits to the DAC interface register,
as shown in Tables 20 and 21. Following the high-to-low
transition of CS, the data is shifted synchronously and
latched into the input register on each falling edge of
SCLK. Each word is 16 bits. The first 4 bits are the con-
trol bits followed by 12 data bits (MSB first) and 2 don’t-
care sub-bits. See Figures 10–12 for DAC timing
specifications.
Table 17ꢀ GPꢂO-Mode Control
CONFIGURATION
BIT
WRITE
BIT
OUTPUT
STATE
GPIO
FUNCTION
1
1
0
1
0
1
1
Output
Output
Input
0
Three-state
Pulldown
(open drain)
0
0
0
Table 18ꢀ MAX1220 GPꢂO Read
DATA PꢂI
DꢂI
GPꢂO COMMAID BYTE
DATA BYTE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
X
0
X
0
X
0
X
0
X
X
X
X
DOUT
GPIOC1
GPIOC0
GPIOA1
GPIOA0
Table 19ꢀ MAX1257/MAX1258 GPꢂO Read
DATA PꢂI
DꢂI
GPꢂO COMMAID BYTE
DATA BYTE 1
DATA BYTE 2
0
0
0
0
0
0
0
0
1
0
X
0
X
0
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
DOUT
0
0
0
0
0
0
0
______________________________________________________________________________________ 31
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 20ꢀ DAC Serial-ꢂnterface Configuration
16-BꢂT SERꢂAꢁ WORD
MSB
COITROꢁ
BꢂTS
C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ꢁSB
DESCRꢂPTꢂOI
FUICTꢂOI
DATA BꢂTS
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
NOP
No operation.
Reset all internal registers to 000h and
leave output buffers in their present state.
0
0
0
1
0
X
0
X
X
X
X
X
X
X
X
X
RESET
Preset all internal registers to FFFh and
leave output buffers in their present state.
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1
X
1
X
X
X
X
X
X
X
X
X
Pull-High
DAC0
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
D11–D0 to input register 0,
DAC output unchanged.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D11–D0 to input register 1,
DAC output unchanged.
D11–D0 to input register 2,
DAC output unchanged.
D11–D0 to input register 3,
DAC output unchanged.
D11–D0 to input register 4,
DAC output unchanged.
D11–D0 to input register 5,
DAC output unchanged.
07/MAX1258
D11–D0 to input register 6,
DAC output unchanged.
D11–D0 to input register 7,
DAC output unchanged.
D11–D0 to input registers 0–3 and DAC
registers 0–3. DAC outputs updated
(write-through).
1
1
0
0
1
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DAC0–DAC3
D11–D0 to input registers 4–7 and DAC
DAC4–DAC7 registers 4–7. DAC outputs updated
(write-through).
D11–D0 to input registers 0–7 and DAC
registers 0–7. DAC outputs updated
(write-through).
1
1
1
1
0
0
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DAC0–DAC7
DAC0–DAC7
D11–D0 to input registers 0–7.
DAC outputs unchanged.
Input registers to DAC registers indicated
by ones, DAC outputs updated,
equivalent to software LDAC.
1
1
1
0
X
X
X
X
DAC0–DAC7
(No effect on DACs indicated by zeros.)
32 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
Table 21ꢀ DAC Power-Up and Power-Down Commands
COITROꢁ
DATA BꢂTS
BꢂTS
DESCRꢂPTꢂOI
FUICTꢂOI
C3 C2 C1 C0
D3 D2 D1 D0
Power up individual DAC buffers indicated by data
in DAC0 through DAC7. A one indicates the DAC
output is connected and active. A zero does not
affect the DAC’s present state.
1
1
1
1
1
1
1
1
— — — — — — — —
0
0
0
1
1
0
X
X
Power-Up
Power down individual DAC buffers indicated by
data in DAC0 through DAC7. A one indicates the
DAC output is disconnected and high impedance.
A zero does not affect the DAC’s present state.
— — — — — — — —
Power-Down 1
Power down individual DAC buffers indicated by
data in DAC0 through DAC7. A one indicates the
DAC output is disconnected and pulled to AGND
with a 1kΩ resistor. A zero does not affect the DAC’s
present state.
1
1
1
1
1
1
1
1
1
1
1
1
— — — — — — — —
— — — — — — — —
— — — — — — — —
1
0
1
0
0
1
0
0
1
X
X
X
Power-Down 2
Power down individual DAC buffers indicated by
data in DAC0 through DAC7. A one indicates the
Power-Down 3 DAC output is disconnected and pulled to AGND
with a 100kΩ resistor. A zero does not affect the
DAC’s present state.
Power down individual DAC buffers indicated by
data in DAC0 through DAC7. A one indicates the
Power-Down 4 DAC output is disconnected and pulled to REF1 with
a 100kΩ resistor. A zero does not affect the DAC’s
present state.
two’s complement for bipolar mode and temperature
results. See Figures 3, 4, and 5 for input/output and
temperature-transfer functions.
If CS goes high prior to completing 16 SCLK cycles, the
command is discarded. To initiate a new transfer, drive
CS low again.
For example, writing the DAC serial interface word 1111
0000 and 1111 0100 disconnects DAC outputs 4
through 7 and forces them to a high-impedance state.
DAC outputs 0 through 3 remain in their previous state.
ADC Transfer Functions
Figure 3 shows the unipolar transfer function for single-
ended or differential inputs. Figure 4 shows the bipolar
transfer function for differential inputs. Code transitions
occur halfway between successive-integer LSB values.
Output-Data Format
Figures 6–9 illustrate the conversion timing for the
MAX1220/MAX1257/MAX1258. All 12-bit conversion
results are output in 2-byte format, MSB first, with four
leading zeros. Data appears on DOUT on the falling
edges of SCLK. Data is binary for unipolar mode and
Output coding is binary, with 1 LSB = V
/4096
REF1
(MAX1257) and 1 LSB = V
/4096 (MAX1220/
REF1
MAX1258) for unipolar and bipolar operation, and 1
LSB = +0.125°C for temperature measurements.
Bipolar true-differential results and temperature-sensor
______________________________________________________________________________________ 33
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
results are available in two’s complement format, while
all others are in binary. See Tables 6, 7, and 8 for
details on which setting (unipolar or bipolar) takes
precedence.
and performed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 6 for clock mode 00 timing after a
command byte is issued. See Table 5 for details on
programming the clock mode in the setup register.
In unipolar mode, AIN+ can exceed AIN- by up to
V
. In bipolar mode, either input can exceed the
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX1220/MAX1257/
MAX1258 then wake up, scan all requested channels,
store the results in the FIFO, and shut down. After the
REF1
other by up to V
/2.
REF1
Partial Reads and Partial Writes
If the 1st byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the remaining bits are lost for that byte. The next byte of
data that is read out contains the next 8 bits. If the first
byte of an entry in the FIFO is read out fully, but the
second byte is read out partially, the rest of that byte is
lost. The remaining data in the FIFO is unaffected and
can be read out normally after taking CS low again, as
long as the 4 leading bits (normally zeros) are ignored.
If CS is pulled low before EOC goes low, a conversion
may not be completed and the FIFO data may not be
correct. Incorrect writes (pulling CS high before com-
pleting eight SCLK cycles) are ignored and the register
remains unchanged.
V
= V - V
REF+ REF-
REF
V
V
REF
REF
011....111
011....110
011....101
FS = V /2 + V
REF
COM
ZS = COM
-FS = -V /2
REF
V
REF
1 LSB = V /4096
REF
000....001
000....000
111....111
(COM)
V
REF
100....011
100....010
100....001
100....000
Applications Information
Internally Timed Acquisitions and
Conversions Using CNVST
-FS
-1 0 +1
(COM)
+FS - 1 LSB
ADC Conversions in Clock Mode 00
In clock mode 00, the wake-up, acquisition, conversion,
and shutdown sequence is initiated through CNVST
07/MAX1258
INPUT VOLTAGE (LSB)
Figure 4. Bipolar Transfer Function—Full Scale ( FS) =
V /2
REF
OUTPUT CODE
FULL-SCALE
TRANSITION
111....111
111....110
111....101
011....111
011....110
FS = V
REF
1 LSB = V /4096
REF
000....010
000....001
000....000
111....111
111....110
111....101
000....011
000....010
000....001
000....000
100....001
100....000
0
1
2
3
FS
FS - 3/2 LSB
INPUT VOLTAGE (LSB)
0
-256
+255.5
TEMPERATURE (°C)
Figure 5. Temperature Transfer Function
Figure 3. Unipolar Transfer Function—Full Scale (FS) = V
REF
34 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
CNVST
CS
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
SCLK
DOUT
LSB1
MSB2
MSB1
t
RDS
EOC
Figure 6. Clock Mode 00—After writing a command byte, set CNVST low for at least 40ns to begin a conversion.
t
CSW
CNVST
(CONVERSION 2)
(ACQUISITION 1)
(ACQUISITION 2)
CS
t
DOV
SCLK
(CONVERSION 1)
DOUT
EOC
LSB1
MSB2
MSB1
Figure 7. Clock Mode 01—After writing a command byte, request multiple conversions by setting CNVST low for each conversion.
Externally Timed Acquisitions and
scan is complete, EOC is pulled low and the results are
available in the FIFO. Wait until EOC goes low before
pulling CS low to communicate with the serial interface.
EOC stays low until CS or CNVST is pulled low again. A
temperature-conversion result, if requested, precedes
all other FIFO results.
Internally Timed Conversions with CNVST
ADC Conversions in Clock Mode 01
In clock mode 01, conversions are requested one at a
time using CNVST and performed automatically using
the internal oscillator. See Figure 7 for clock mode 01
timing after a command byte is issued.
Do not issue a second CNVST signal before EOC goes
low; otherwise, the FIFO can be corrupted. Wait until all
conversions are complete before reading the FIFO. SPI
communications to the DAC and GPIO registers are per-
mitted during conversion. However, coupled noise may
result in degraded ADC signal-to-noise ratio (SNR).
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for
at least 1.4µs to complete the acquisition. If reference
mode 00 or 10 is selected, an additional 45µs is
required for the internal reference to power up. If a tem-
perature measurement is being requested, reference
power-up and temperature measurement is internally
timed. In this case, hold CNVST low for at least 40ns.
______________________________________________________________________________________ 35
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
CONVERSION BYTE
DIN
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
MSB1
LSB1
MSB2
t
DOV
EOC
Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (CNVST is not required).
Initiate a scan by writing a command byte to the conver-
sion register. The MAX1220/MAX1257/MAX1258 then
power up, scan all requested channels, store the results
in the FIFO, and shut down. After the scan is complete,
EOC is pulled low and the results are available in the
FIFO. If a temperature measurement is requested, the
temperature result precedes all other FIFO results. EOC
stays low until CS is pulled low again. Wait until all con-
versions are complete before reading the FIFO. SPI
communications to the DAC and GPIO registers are per-
mitted during conversion. However, coupled noise may
result in degraded ADC SNR.
Set CNVST high to begin a conversion. Sampling is
completed approximately 500ns after CNVST goes
high. After the conversion is complete, the ADC shuts
down and pulls EOC low. EOC stays low until CS or
CNVST is pulled low again. Wait until EOC goes low
before pulling CS or CNVST low. The number of CNVST
signals must equal the number of conversions request-
ed by the scan and averaging registers to correctly
update the FIFO. Wait until all conversions are com-
plete before reading the FIFO. SPI communications to
the DAC and GPIO registers are permitted during
conversion. However, coupled noise may result in
degraded ADC SNR.
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
If averaging is turned on, multiple CNVST pulses need to
be performed before a result is written to the FIFO. Once
the proper number of conversions has been performed
to generate an averaged FIFO result (as specified to the
averaging register), the scan logic automatically switch-
es the analog input multiplexer to the next requested
channel. If a temperature measurement is programmed,
it is performed after the first rising edge of CNVST follow-
ing the command byte written to the conversion register.
The temperature-conversion result is available on DOUT
once EOC has been pulled low.
07/MAX1258
ADC Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing a command byte to the conversion
register and are performed one at a time using SCLK
as the conversion clock. Scanning, averaging and the
FIFO are disabled, and the conversion result is avail-
able at DOUT during the conversion. Output data is
updated on the rising edge of SCLK in clock mode 11.
See Figures 9a and 9b for clock mode 11 timing.
Initiate a conversion by writing a command byte to the
conversion register followed by 16 SCLK cycles. If CS
is pulsed high between the eighth and ninth cycles, the
pulse width must be less than 100µs. To continuously
convert at 16 cycles per conversion, alternate 1 byte of
zeros (NOP byte) between each conversion byte. If 2
NOP bytes follow a conversion byte, the analog cells
power down at the end of the second NOP. Set the
FBGON bit to one in the reset register to keep the inter-
nal bias block powered.
Internally Timed Acquisitions and
Conversions Using the Serial Interface
ADC Conversions in Clock Mode 10
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequence is initiated by writing a com-
mand byte to the conversion register, and is performed
automatically using the internal oscillator. This is the
default clock mode upon power-up. See Figure 8 for
clock mode 10 timing.
36 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
CONVERSION BYTE #1
NOP
CONVERSION BYTE #2
NOP
CONVERSION
DIN
ACQUISITION #1
ACQUISITION #2
CONVERSION #1
CONVERSION #2
CS
SCLK
DOUT
MSB1
LSB1
MSB2
EOC
Figure 9a. Clock Mode 11—Externally Timed Acquisition, Sampling and Conversion without CNVST for Maximum ADC Throughput
CONVERSION BYTE
NOP
NOP
DIN
ACQUISITION
CONVERSION
CS
SCLK
DOUT
EOC
MSB1
LSB1
Figure 9b. Clock Mode 11—Externally Timed Acquisition, Sampling and Conversion without CNVST to Reduce Analog Power
Dissipation
If reference mode 00 is requested, or if an external ref-
erence is selected but a temperature measurement is
being requested, wait 45µs with CS high after writing
the conversion byte to extend the acquisition and allow
the internal reference to power up. To perform a tem-
perature measurement, write 24 bytes (192 cycles) of
zeros after the conversion byte using 8-bit NOP com-
mands each framed by CS (to match production test
method; other length NOP sequences are not produc-
tion tested). The temperature result appears on DOUT
during the last 2 bytes of the 192 cycles. For tempera-
ture conversion in clock mode 11 with the TEMP bit set
in the conversion register, no scanning of AIN0 to
AIN15 is performed. Therefore, the CHSEL[3:0] bits are
don’t cares. These bits can be set to 0000b. When the
conversion is complete, only the temperature data is
available.
sion in clock mode 00 and 10 (see the Electrical
Characteristics, as applicable):
Total conversion time =
t
x n
x n
+ t + t
CONV
AVG
SCAN TS INT-REF,SU
where:
t
= t
, where t
is dependent on the clock
DOV
CONV
DOV
mode and the reference mode selected
n
AVG
= samples per result (amount of averaging)
n
= number of times each channel is scanned; set
SCAN
to one unless [SCAN1, SCAN0] = 10
t
= time required for temperature measurement
TS
(53.1µs); set to zero if temperature measurement is not
requested
t
= t
(external-reference wake-up); if a
WU
INT-REF,SU
conversion using the external reference is requested
In clock mode 01, the total conversion time depends on
how long CNVST is held low or high. Conversion time in
externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set of eight SCLK cycles. In clock
mode 01, the total conversion time does not include the
time required to turn on the internal reference.
Conversion-Time Calculations
The conversion time for each scan is based on a num-
ber of different factors: conversion time per sample,
samples per result, results per scan, if a temperature
measurement is requested, and if the external refer-
ence is in use. Use the following formula to calculate
the total conversion time for an internally timed conver-
______________________________________________________________________________________ 37
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
t
CH
t
CL
32
16
8
SCLK
DIN
5
1
2
3
4
t
DH
t
DS
Dn-3
Dn-4
Dn-5
Dn-1
Dn-2
D1
D0
t
DOT
t
DOD
t
DOE
D15
D7
D14
D6
D12
D4
D13
D5
DOUT
D1
D0
t
CSS
t
CSPWH
t
CSH
CS
NOTE: FOR THE MAX1220 GPIO WRITES, n = 16; FOR ALL DAC WRITES AND GPIO WRITES ON THE MAX1257/MAX1258, n = 24.
Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10)
07/MAX1258
DAC/GPꢂO Timing
Figures 10–13 detail the timing diagrams for writing to
the DAC and GPIOs. Figure 10 shows the timing speci-
fications for clock modes 00, 01, and 10. Figure 11
shows the timing specifications for clock mode 11.
Figure 12 details the timing specifications for the DAC
input select register and 2 bytes to follow. Output data
is updated on the rising edge of SCLK in clock mode
11. Figure 13 shows the GPIO timing. Figure 14 shows
the timing details of a hardware LDAC command DAC-
register update. For a software-command DAC-register
update, t is valid from the rising edge of CS, which fol-
S
lows the last data bit in the software command word.
38 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
t
CH
t
CL
32
16
8
SCLK
5
1
2
3
4
t
DH
t
DS
Dn-1
Dn-2
Dn-3
Dn-4
Dn-5
D1
D0
DIN
DOUT
CS
t
t
DOT
DOE
t
DOD
D15
D7
D14
D6
D13
D5
D12
D4
D1
D0
t
CSS
t
CSPWH
t
CSH
NOTE: FOR THE MAX1220 GPIO WRITES, n = 16; FOR ALL DAC WRITES AND GPIO WRITES ON THE MAX1257/MAX1258, n = 24.
Figure 11. DAC/GPIO Serial-Interface Timing (Clock Mode 11)
SCLK
10
24
1
2
8
9
DIN
BIT 7 (MSB)
BIT 6
BIT 0 (LSB)
BIT 15
BIT 14
BIT 1
BIT 0
DOUT
CS
THE COMMAND BYTE
INITIALIZES THE DAC SELECT
REGISTER
THE NEXT 16 BITS SELECT THE DAC
AND THE DATA WRITTEN TO IT
Figure 12. DAC-Select Register Byte and DAC Serial-Interface Word
______________________________________________________________________________________ 39
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
CS
t
GOD
t
GSU
GPIO INPUT/OUTPUT
Figure 13. GPIO Timing
t
LDACPWL
LDAC
t
S
1 LSB
OUT_
07/MAX1258
Figure 14. LDAC Functionality
The MAX1220/MAX1257/MAX1258 thin QFN packages
contain an exposed pad on the underside of the device.
Connect this exposed pad to AGND. Refer to the
MAX1258EVKIT for an example of proper layout.
LDAC Functionality
Drive LDAC low to transfer the content of the input reg-
isters to the DAC registers. Drive LDAC permanently
low to make the DAC register transparent. The DAC
output typically settles from zero to full scale within
LSB after 2µs. See Figure 14.
1
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1220/MAX1257/MAX1258 is measured using
the end-point method.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Ensure that digi-
tal and analog signal lines are separated from each
other. Do not run analog and digital signals parallel to
one another (especially clock signals) or do not run digi-
tal lines underneath the MAX1220/MAX1257/
MAX1258 package. High-frequency noise in the AVDD
power supply may affect performance. Bypass the
AVDD supply with a 0.1µF capacitor to AGND, close to
the AVDD pin. Bypass the DVDD supply with a 0.1µF
capacitor to DGND, close to the DVDD pin. Minimize
capacitor lead lengths for best supply-noise rejection. If
the power supply is very noisy, connect a 10Ω resistor in
series with the supply to improve power-supply filtering.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
40 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
Unipolar ADC Offset Error
For an ideal converter, the first transition occurs at 0.5
LSB, above zero. Offset error is the amount of deviation
between the measured first transition point and the
ideal first transition point.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD(dB) = 20 x log (Signal
/ Noise
)
RMS
RMS
Bipolar ADC Offset Error
While in bipolar mode, the ADC’s ideal midscale transi-
tion occurs at AGND -0.5 LSB. Bipolar offset error is the
measured deviation from this ideal value.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the ENOB as follows:
ADC Gain Error
Gain error is defined as the amount of deviation
between the ideal transfer function and the measured
transfer function, with the offset error removed and with
a full-scale analog input voltage applied to the ADC,
resulting in all ones at DOUT.
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
DAC Offset Error
DAC offset error is determined by loading a code of all
zeros into the DAC and measuring the analog output
voltage.
⎡
⎤
2
2
2
2
2
THD = 20 x log
V
+ V
+ V
+ V
+ V
/ V
1
(
)
2
3
4
5
6
⎢
⎣
⎥
⎦
DAC Gain Error
DAC gain error is defined as the amount of deviation
between the ideal transfer function and the measured
transfer function, with the offset error removed, when
loading a code of all ones into the DAC.
where V is the fundamental amplitude, and V through
6
1
2
V are the amplitudes of the first five harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest distortion
component.
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
ADC Channel-to-Channel Crosstalk
Bias the ON channel to midscale. Apply a full-scale sine
wave test tone to all OFF channels. Perform an FFT on
the ON channel. ADC channel-to-channel crosstalk is
expressed in dB as the amplitude of the FFT spur at the
frequency associated with the OFF channel test tone.
Aperture Delay
Aperture delay (t ) is the time between the rising
AD
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-
to-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1 and
f2, are present at the inputs. The intermodulation prod-
ucts are (f1 f2), (2 x f1), (2 x f2), (2 x f1 f2), (2 x f2
f1). The individual input tone levels are at -7dBFS.
SNR = (6.02 x N + 1.76)dB
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC so the signal’s slew rate does not limit the ADC’s
performance. The input frequency is then swept up to
the point where the amplitude of the digitized conver-
sion result has decreased by -3dB. Note that the T/H
performance is usually the limiting factor for the small-
signal input bandwidth.
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise. RMS noise
includes all spectral components to the Nyquist fre-
quency excluding the fundamental, the first five har-
monics, and the DC offset.
______________________________________________________________________________________ 41
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Pin Configurations
TOP VIEW
+
36
35
34
33
32
31
30
29
28
27
26
25
CNVST/AIN15
GPIOA0
GPIOA1
EOC
1
2
3
4
5
6
7
8
9
AIN2
+
REF1
GPIOA0
GPIOA1
EOC
1
2
3
4
5
6
7
8
9
27 AIN0
AIN1
26 REF1
25 GPIOC1
24 GPIOC0
23 N.C.
AIN0
GPIOA2
GPIOA3
DVDD
GPIOC3
GPIOC2
GPIOC1
GPIOC0
RES_SEL
CS
DVDD
DGND
DOUT
SCLK
DIN
MAX1257
MAX1258
MAX1220
22 RES_SEL
21 CS
DGND
DOUT
LDAC
20
SCLK 10
DIN 11
OUT0
19 OUT7
LDAC
OUT7
OUT0 12
TQFN
TQFN
07/MAX1258
Full-Power Bandwidth
Chip Information
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
PROCESS: BiCMOS
Package Information
DAC Digital Feedthrough
DAC digital feedthrough is the amount of noise that
appears on the DAC output when the DAC digital con-
trol lines are toggled.
For the latest package outline information and land patterns
(footprints), go to wwwꢀmaxim-icꢀcom/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
ADC Power-Supply Rejection
ADC power-supply rejection (PSR) is defined as the
shift in offset error when the power supply is moved
from the minimum operating voltage to the maximum
operating voltage.
ꢁAID
PATTERI IOꢀ
PACKAGE
TYPE
PACKAGE
CODE
OUTꢁꢂIE IOꢀ
90-0050
90-0132
36 TQFN-EP
48 TQFN-EP
T3666+3
T4877+6
21-0141
21-0144
DAC Power-Supply Rejection
DAC PSR is the amount of change in the converter’s
value at full-scale as the power-supply voltage changes
from its nominal value. PSR assumes the converter’s lin-
earity is unaffected by changes in the power-supply
voltage.
42 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
07/MAX1258
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
5
12/07
Changed timing characteristic specification.
Changed the Ordering Information table to show lead(Pb)-free packages.
Added Note 18 to the Electrical Characteristics table (t spec).
7
1
7, 8
20
DOV
Added the ADDITIONAL NO. OF BYTES column to Table 1.
6
7
1/10
2/12
Corrected Figure 8, replaced Figure 9 with Figures 9a and 9b, and modified Figures
10 and 11.
36–39
Updated the ADC Conversions in Clock Mode 11 section.
36
8
Clarified Note 9.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
43 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2012 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
©2020 ICPDF网 联系我们和版权申明