MAX12558ETK-D [MAXIM]
ADC, Proprietary Method, 14-Bit, 2 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.80 MM HEIGHT, MO-220WNND-2, TQFN-68;
| 型号： | MAX12558ETK-D |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Proprietary Method, 14-Bit, 2 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.80 MM HEIGHT, MO-220WNND-2, TQFN-68 转换器 |
| 文件： | 总30页 (文件大小：455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3842; Rev 0; 10/05
Dual, 80Msps, 14-Bit, IF/Baseband ADC
General Description
Features
The MAX12558 is a dual, 3.3V, 14-bit analog-to-digital
converter (ADC) featuring fully differential wideband
track-and-hold (T/H) inputs, driving internal quantizers.
The MAX12558 is optimized for low power, small size,
and high dynamic performance in intermediate frequen-
cy (IF) and baseband sampling applications. This dual
ADC operates from a single 3.3V supply, consuming
only 756mW while delivering a typical 71.7dB signal-to-
noise ratio (SNR) performance at a 175MHz input fre-
quency. The T/H input stages accept single-ended or
differential inputs up to 400MHz. In addition to low oper-
ating power, the MAX12558 features a 330µW power-
down mode to conserve power during idle periods.
♦ Direct IF Sampling Up to 400MHz
♦ Excellent Dynamic Performance
74.4dB/71.7dB SNR at f = 70MHz/175MHz
84.2dBc/79dBc SFDR at f = 70MHz/175MHz
IN
IN
♦ 3.3V Low-Power Operation
789mW (Differential Clock Mode)
756mW (Single-Ended Clock Mode)
♦ Fully Differential or Single-Ended Analog Input
♦ Adjustable Differential Analog Input Voltage
♦ 750MHz Input Bandwidth
♦ Adjustable, Internal or External, Shared Reference
♦ Differential or Single-Ended Clock
♦ Accepts 25% to 75% Clock Duty Cycle
♦ User-Selectable DIV2 and DIV4 Clock Modes
♦ Power-Down Mode
A flexible reference structure allows the MAX12558 to
use the internal 2.048V bandgap reference or accept
an externally applied reference and allows the refer-
ence to be shared between the two ADCs. The refer-
ence structure allows the full-scale analog input range
to be adjusted from 0.35V to 1.15V. The MAX12558
provides a common-mode reference to simplify design
and reduce external component count in differential
analog input circuits.
♦ CMOS Outputs in Two’s Complement or Gray
Code
♦ Out-of-Range and Data-Valid Indicators
♦ Small, 68-Pin Thin QFN Package
(10mm x 10mm x 0.8mm)
♦ 12-Bit, Pin-Compatible Version Available
The MAX12558 supports either a single-ended or differ-
ential input clock. User-selectable divide-by-two (DIV2)
and divide-by-four (DIV4) modes allow for design flexibil-
ity and help to reduce the negative effects of clock jitter.
Wide variations in the clock duty cycle are compensated
with the ADC’s internal duty-cycle equalizer (DCE).
(MAX12528)
♦ Evaluation Kit Available (Order MAX12558EVKIT)
Ordering Information
PKG
CODE
The MAX12558 features two parallel, 14-bit-wide,
CMOS-compatible outputs. The digital output format is
pin-selectable to be either two’s complement or Gray
code. A separate power-supply input for the digital out-
puts accepts a 1.7V to 3.6V voltage for flexible interfac-
ing with various logic levels. The MAX12558 is available
in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package
with exposed paddle (EP), and is specified for the
extended (-40°C to +85°C) temperature range.
PART
TEMP RANGE PIN-PACKAGE
MAX12558ETK -40°C to +85°C 68 Thin QFN-EP* T6800-2
MAX12558ETK+ -40°C to +85°C 68 Thin QFN-EP* T6800-2
*EP = Exposed paddle.
+Denotes lead-free package.
Selector Guide
For a 12-bit, pin-compatible version of this ADC, refer to
the MAX12528 data sheet. See the Selector Guide for
more selections.
SAMPLING RATE
(Msps)
RESOLUTION
(Bits)
PART
Applications
IF and Baseband Communication Receivers
Cellular, LMDS, Point-to-Point Microwave,
MMDS, HFC, WLAN
MAX12559**
MAX12558
MAX12557
MAX12529**
MAX12528
MAX12527
95
80
65
95
80
65
14
14
14
12
12
12
I/Q Receivers
Ultrasound and Medical Imaging
Portable Instrumentation
Digital Set-Top Boxes
**Future product—contact factory for availability.
Low-Power Data Acquisition
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual, 80Msps, 14-Bit, IF/Baseband ADC
ABSOLUTE MAXIMUM RATINGS
DD
V
to GND ................................................................-0.3V to +3.6V
DIFFCLK/SECLK, G/T, PD, SHREF, DIV2,
DIV4 to GND .........-0.3V to the lower of (V + 0.3V) and +3.6V
D0A–D13A, D0B–D13B, DAV,
DORA, DORB to GND..............................-0.3V to (OV + 0.3V)
Continuous Power Dissipation (T = +70°C)
A
68-Pin Thin QFN, 10mm x 10mm x 0.8mm
(derate 70mW/°C above +70°C) ....................................4000mW
Operating Temperature Range................................-40°C to +85°C
Junction Temperature...........................................................+150°C
Storage Temperature Range .................................-65°C to +150°C
Lead Temperature (soldering 10s).......................................+300°C
OV to GND............-0.3V to the lower of (V + 0.3V) and +3.6V
DD
DD
DD
INAP, INAN to GND ...-0.3V to the lower of (V + 0.3V) and +3.6V
DD
INBP, INBN to GND ...-0.3V to the lower of (V + 0.3V) and +3.6V
DD
CLKP, CLKN to
DD
GND........................-0.3V to the lower of (V + 0.3V) and +3.6V
DD
REFIN, REFOUT
to GND ..................-0.3V to the lower of (V + 0.3V) and +3.6V
DD
REFAP, REFAN,
COMA to GND ......-0.3V to the lower of (V + 0.3V) and +3.6V
DD
REFBP, REFBN,
COMB to GND ......-0.3V to the lower of (V + 0.3V) and +3.6V
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -1dBFS (differential),
DD
DD
L
IN
DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
= 80MHz (50% duty cycle), T =
DD
CLK
A
-40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
14
Bits
Integral Nonlinearity
INL
f
f
= 3MHz
1.4
0.6
LSB
IN
= 3MHz, no missing codes over
IN
Differential Nonlinearity
DNL
-1.0
+1.2
LSB
temperature (Note 2)
Offset Error
Gain Error
0.1
0.1
0.7
4.6
%FSR
%FSR
External reference, V
= 2.048V
REFIN
ANALOG INPUT (INAP, INAN, INBP, INBN)
Differential Input Voltage Range
Common-Mode Input Voltage
Analog Input Resistance
V
Differential or single-ended inputs
Each input, Figure 3
1.024
V
V
DIFF
V
/ 2
DD
R
2.8
kΩ
IN
Fixed capacitance to ground,
each input, Figure 3
C
2
PAR
Analog Input Capacitance
pF
Switched capacitance,
each input, Figure 3
C
4.5
SAMPLE
CONVERSION RATE
Maximum Clock Frequency
Minimum Clock Frequency
f
80
MHz
MHz
CLK
5
Clock
Cycles
Data Latency
Figure 5
8
DYNAMIC CHARACTERISTICS
Small-Signal Noise Floor
SSNF
SNR
Input at -35dBFS
75.4
72.7
76.8
75.2
74.7
74.4
71.7
dBFS
dB
f
IN
f
IN
f
IN
f
IN
= 3MHz
= 40MHz
= 70MHz
= 175MHz
Signal-to-Noise Ratio
69.9
2
_______________________________________________________________________________________
Dual, 80Msps, 14-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -1dBFS (differential),
DD
DD
L
IN
DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
= 80MHz (50% duty cycle), T =
DD
CLK
A
-40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
74.8
73.5
73.7
70.6
86.9
81.9
84.2
79
MAX
UNITS
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
= 3MHz
71.1
= 40MHz
= 70MHz
= 175MHz
= 3MHz
Signal-to-Noise Plus Distortion
SINAD
dB
68.6
73.8
= 40MHz
= 70MHz
= 175MHz
= 3MHz
Spurious-Free Dynamic Range
Total Harmonic Distortion
Second Harmonic
SFDR
THD
HD2
HD3
dBc
dBc
dBc
dBc
72.8
-85.3
-79.7
-81.7
-77.1
-87.3
-84.8
-86.7
-79.9
-91.4
-81.9
-84.3
-81.3
-72.9
-71.3
= 40MHz
= 70MHz
= 175MHz
= 3MHz
= 40MHz
= 70MHz
= 175MHz
= 3MHz
= 40MHz
= 70MHz
= 175MHz
Third Harmonic
f
f
= 68.5MHz at -7dBFS
= 71.5MHz at -7dBFS
IN1
IN2
-86.5
-87.1
3rd-Order Intermodulation
Distortion
IM3
dBc
f
f
= 172.5MHz at -7dBFS
= 177.5MHz at -7dBFS
IN1
IN2
MHz
ns
Full-Power Bandwidth
Aperture Delay
FPBW
Input at -0.2dBFS, -3dB rolloff
Figure 5
750
1.2
t
AD
ps
RMS
Aperture Jitter
t
AJ
< 0.1
INAP = INAN = COMA
INBP = INBN = COMB
Output Noise
n
0.91
LSB
RMS
OUT
_______________________________________________________________________________________
3
Dual, 80Msps, 14-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -1dBFS (differential),
DD
DD
L
IN
DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
= 80MHz (50% duty cycle), T =
DD
CLK
A
-40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
10% beyond full scale
MIN
TYP
MAX
UNITS
Clock
Cycle
Overdrive Recovery Time
1
INTERCHANNEL CHARACTERISTICS
f
f
or f
or f
= 70MHz at -1dBFS
= 175MHz at -1dBFS
95
INA
INB
INB
Crosstalk Rejection
dB
87
INA
Gain Matching
0.01
0.01
0.1
dB
Offset Matching
%FSR
INTERNAL REFERENCE (REFOUT)
REFOUT Output Voltage
V
2.000
2.048
35
2.080
V
REFOUT
REFOUT Load Regulation
REFOUT Temperature Coefficient
-1mA < I
< +1mA
mV/mA
ppm/°C
REFOUT
TC
50
REF
Short to V —sinking
DD
0.24
2.1
REFOUT Short-Circuit Current
mA
Short to GND—sourcing
BUFFERED REFERENCE MODE (REFIN is driven by REFOUT or an external 2.048V single-ended reference source;
/V /V and V /V /V are generated internally)
V
REFAP REFAN COMA
REFBP REFBN COMB
REFIN Input Voltage
V
R
2.048
> 50
V
REFIN
REFIN Input Resistance
MΩ
REFIN
V
V
COMA
COMB
COM_ Output Voltage
REF_P Output Voltage
REF_N Output Voltage
V
V
V
V
= V
/ 2
1.60
1.65
2.418
0.882
1.536
25
1.70
V
COM_
REF_P
REF_N
DD
V
V
REFAP
REFBP
= V
/ 2 + (V
x 3/8)
x 3/8)
V
DD
REFIN
V
V
REFAN
REFBN
= V
/ 2 - (V
V
V
DD
REFIN
V
V
REFA
REFB
Differential Reference Voltage
= V
- V
REF_N
1.456
1.595
REF_
REF_P
Differential Reference
Temperature Coefficient
TC
ppm/°C
REF
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, V
/V
/V
and V
/V
/V
are applied
REFAP REFAN COMA
REFBP REFBN COMB
externally, V
= V
= V
/ 2)
COMA
COMB
DD
V
V
REFAP
REFBP
REF_P Input Voltage
V
- V
+0.768
V
REF_P
COM_
V
V
REFAN
REFBN
REF_N Input Voltage
COM_ Input Voltage
V
V
V
- V
-0.768
1.65
V
V
V
REF_N
COM_
COM_
V
= V
/ 2
DD
COM_
V
V
REFA
REFB
Differential Reference Voltage
= V
- V
= V x 3/4
REFIN
1.536
REF_
REF_P
REF_N
4
_______________________________________________________________________________________
Dual, 80Msps, 14-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -1dBFS (differential),
DD
DD
L
IN
DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
= 80MHz (50% duty cycle), T
=
DD
CLK
A
-40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
REF_P Sink Current
SYMBOL
CONDITIONS
= 2.418V
MIN
TYP
MAX
UNITS
I
I
REFAP
V
V
V
1.2
mA
REF_P
REF_N
COM_
REFBP
I
I
REFAN
REF_N Source Current
COM_ Sink Current
= 0.882V
= 1.65V
0.85
0.85
mA
mA
REFBN
I
I
COMA
COMB
C
C
,
REF_P
REF_P, REF_N Capacitance
13
6
pF
pF
REF_N
COM_ Capacitance
C
COM_
CLOCK INPUTS (CLKP, CLKN)
Single-Ended Input High
Threshold
Single-Ended Input Low
Threshold
0.8 x
V
DIFFCLK/SECLK = GND, CLKN = GND
DIFFCLK/SECLK = GND, CLKN = GND
V
V
IH
V
DD
0.2 x
V
IL
V
DD
Minimum Differential Clock Input
Voltage Swing
DIFFCLK/SECLK = OV
0.2
V
DD
P-P
V
Differential Input Common-Mode
Voltage
DIFFCLK/SECLK = OV
V
/ 2
DD
DD
CLKP, CLKN Input Resistance
CLKP, CLKN Input Capacitance
R
Each input, Figure 4
5
2
kΩ
CLK
CLK
C
pF
DIGITAL INPUTS (DIFFCLK/SECLK, G/T, PD, DIV2, DIV4, SHREF)
0.8 x
OV
Input High Threshold
Input Low Threshold
V
V
V
IH
DD
0.2 x
V
IL
OV
DD
5
OV
applied to input
DD
Input Leakage Current
µA
pF
Input connected to ground
5
Digital Input Capacitance
C
5
DIN
DIGITAL OUTPUTS (D0A–D13A, D0B–D13B, DORA, DORB, DAV)
D0A–D13A, D0B–D13B, DORA, DORB:
0.2
I
= 200µA
Output-Voltage Low
Output-Voltage High
V
V
SINK
OL
DAV: I
= 600µA
0.2
SINK
D0A–D13A, D0B–D13B, DORA, DORB:
= 200µA
OV
0.2
-
DD
I
SOURCE
V
V
OH
OV
-
DD
DAV: I
= 600µA
SOURCE
0.2
OV
applied to input
5
5
Tri-State Leakage Current
(Note 3)
DD
I
µA
LEAK
Input connected to ground
_______________________________________________________________________________________
5
Dual, 80Msps, 14-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -1dBFS (differential),
DD
DD
L
IN
DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
= 80MHz (50% duty cycle), T =
DD
CLK
A
-40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
D0A–D13A, DORA,
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
D0B–D13B, and DORB Tri-State
Output Capacitance (Note 3)
C
3
pF
OUT
DAV
DAV Tri-State Output
Capacitance (Note 3)
C
6
pF
POWER REQUIREMENTS
Analog Supply Voltage
V
3.15
1.70
3.30
2.0
3.60
V
V
DD
Digital Output Supply Voltage
OV
V
DD
DD
Normal operating mode
= 175MHz
single-ended clock
f
IN
229
(DIFFCLK/SECLK = GND)
Normal operating mode
Analog Supply Current
I
mA
VDD
f
IN
= 175MHz
239
0.1
273
differential clock
(DIFFCLK/SECLK = OV
)
DD
Power-down mode (PD = OV
clock idle
)
DD
Normal operating mode
f
= 175MHz
IN
756
single-ended clock
(DIFFCLK/SECLK = GND)
Normal operating mode
Analog Power Dissipation
P
mW
VDD
f
IN
= 175MHz
789
900
differential clock
(DIFFCLK/SECLK = OV
)
DD
Power-down mode (PD = OV
clock idle
)
)
DD
0.33
22.6
Normal operating mode
f
IN
= 175MHz, C
L ≈ 10pF
Digital Output Supply Current
I
mA
OVDD
Power-down mode (PD = OV
clock idle
DD
0.004
6
_______________________________________________________________________________________
Dual, 80Msps, 14-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -1dBFS (differential),
DD
DD
L
IN
DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
= 80MHz (50% duty cycle), T =
DD
CLK
A
-40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Figure 5)
Clock Pulse-Width High
Clock Pulse-Width Low
Data-Valid Delay
t
6.2
6.2
5.8
ns
ns
ns
CH
t
CL
t
(Note 4)
DAV
Data Setup Time Before Rising
Edge of DAV
t
(Notes 4, 5), OV
(Notes 4, 5), OV
= 1.8V
= 1.8V
5.5
5.5
ns
SETUP
DD
DD
Data Hold Time After Rising Edge
of DAV
t
ns
HOLD
Wake-Up Time from Power-Down
t
V
= 2.048V
10
ms
WAKE
REFIN
Note 1: Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization.
Note 2: Guaranteed by design and characterization. Device tested for performance during production test.
Note 3: During power-down, D0A–D13A, D0B–D13B, DORA, DORB, and DAV are high impedance.
Note 4: Data outputs settle to V or V .
IH
IL
Note 5: Guaranteed by design and characterization.
Typical Operating Characteristics
(V
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 5pF at digital outputs, V = -1dBFS (differential),
IN
DD L
DD
DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f
= 80MHz (50% duty cycle), T = +25°C, unless otherwise noted.)
DD
CLK
A
FFT PLOT (32,768-POINT DATA RECORD)
FFT PLOT (32,768-POINT DATA RECORD)
FFT PLOT (32,768-POINT DATA RECORD)
0
0
0
f
f
A
= 80MHz
= 3.00883MHz
= -1.013dBFS
f
f
A
= 80MHz
CLK
= 39.50928MHz
IN
= -1.024dBFS
IN
f
f
A
= 80MHz
= 70.09846MHz
= -1.03dBFS
CLK
IN
IN
CLK
IN
IN
-10
-20
-30
-40
-50
-60
-70
-10
-20
-30
-40
-50
-60
-70
-10
-20
-30
-40
-50
-60
-70
SNR = 75.3dB
SNR = 74.4dB
SNR = 74.2dB
SINAD = 75.1dB
THD = -90.1dBc
SFDR = 91.8dBc
HD2 = -91.8dBc
HD3 = -102dBc
SINAD = 73.5dB
THD = -80.8dBc
SFDR = 83.3dBc
HD2 = -85.5dBc
HD3 = -82.6dBc
SINAD = 73.7dB
THD = -83.3dBc
SFDR = 85.8dBc
HD2 = -88.7dBc
HD3 = -85.8dBc
HD3
HD2
HD2
HD3
-80
-90
-80
-90
-80
-90
HD3
HD2
-100
-100
-100
-110
-120
-110
-120
-110
-120
0
5
10 15 20 25 30 35 40
ANALOG INPUT FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40
ANALOG INPUT FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
7
Dual, 80Msps, 14-Bit, IF/Baseband ADC
Typical Operating Characteristics (continued)
(V
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 5pF at digital outputs, V = -1dBFS (differential),
IN
DD L
DD
DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f
= 80MHz (50% duty cycle), T = +25°C, unless otherwise noted.)
DD
CLK
A
TWO-TONE IMD PLOT
(32,768-POINT DATA RECORD)
TWO-TONE IMD PLOT
(32,768-POINT DATA RECORD)
FFT PLOT (32,768-POINT DATA RECORD)
0
-20
0
0
-20
f
f
f
= 80MHz
f
f
f
= 80MHz
f
f
= 80MHz
= 174.97827MHz
= -1.093dBFS
CLK
IN1
IN2
CLK
IN1
IN2
CLK
IN
-10
-20
-30
-40
-50
-60
-70
= 68.50117MHz
= 71.49933MHz
= A = -7dBFS
= 172.499299MHz
= 177.499492MHz
= A = -7dBFS
A
f
IN
IN2
A
A
SNR = 71.8dB
IN1
IN2
IN1
IN2
f
IN2
f
IN1
IM3 = -94.7dBc
IM3 = -87.5dBc
SINAD = 70.9dB
THD = -78.2dBc
SFDR = 79.4dBc
HD2 = -102.3dBc
HD3 = -79.4dBc
-40
f
IN1
-40
-60
-60
2f + f
IN1 IN2
f
- f
IN2 IN1
HD3
f
- f
IN2 IN1
f
+ f
2f - f
IN2 IN1
IN1 IN2
2f - f
2f + f
IN2 IN1
IN1 IN2
-80
-80
-80
-90
HD2
-100
-120
-100
-100
-120
-110
-120
0
5
10 15 20 25 30 35
ANALOG INPUT FREQUENCY (MHz)
0
5
10 15 20 25 30 35
0
5
10 15 20 25 30 35 40
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SNR, SINAD vs. ANALOG INPUT FREQUENCY
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
(f
CLK
= 80MHz, A = -1dBFS)
IN
80
75
70
65
60
55
50
45
40
1.00
0.75
0.50
0.25
0
2.0
1.6
SNR
1.2
0.8
0.4
SINAD
0
-0.4
-0.8
-1.2
-1.6
-2.0
-0.25
-0.50
-0.75
-1.00
0
50 100 150 200 250 300 350 400
(MHz)
0
2048 4096 6144 8192 10,240 12,288 14,336 16,384
DIGITAL OUTPUT CODE
0
2048 4096 6144 8192 10,240 12,288 14,336 16,384
DIGITAL OUTPUT CODE
f
IN
SNR, SINAD vs. ANALOG INPUT AMPLITUDE
-THD, SFDR vs. ANALOG INPUT AMPLITUDE
-THD, SFDR vs. ANALOG INPUT FREQUENCY
(f
CLK
= 80MHz, f = 70MHz)
(f = 80MHz, f = 70MHz)
CLK IN
(f
CLK
= 80MHz, A = -1dBFS)
IN
IN
80
70
60
50
40
30
20
10
95
85
75
65
55
45
35
95
90
85
80
75
70
65
60
55
50
SNR
SFDR
SFDR
SINAD
-THD
-THD
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
(dBFS)
0
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
(dBFS)
0
0
50 100 150 200 250 300 350 400
(MHz)
A
A
IN
f
IN
IN
8
_______________________________________________________________________________________
Dual, 80Msps, 14-Bit, IF/Baseband ADC
Typical Operating Characteristics (continued)
(V
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 5pF at digital outputs, V = -1dBFS (differential),
IN
DD L
DD
DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f
= 80MHz (50% duty cycle), T = +25°C, unless otherwise noted.)
DD
CLK
A
SNR, SINAD vs. CLOCK SPEED
(f = 70MHz, A = -1dBFS)
SNR, SINAD vs. ANALOG INPUT AMPLITUDE
-THD, SFDR vs. ANALOG INPUT AMPLITUDE
(f
CLK
= 80MHz, f = 175MHz)
(f = 80MHz, f = 175MHz)
CLK IN
IN
IN
IN
95
85
75
65
55
45
35
80
76
72
68
64
60
75
65
55
45
35
25
15
SNR
SNR
SFDR
SINAD
SINAD
-THD
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
(dBFS)
0
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
(dBFS)
0
30
40
50
60
(MHz)
70
80
A
A
f
CLK
IN
IN
-THD, SFDR vs. CLOCK SPEED
SNR, SINAD vs. CLOCK SPEED
-THD, SFDR vs. CLOCK SPEED
(f = 70MHz, A = -1dBFS)
(f = 175MHz, A = -1dBFS)
(f = 175MHz, A = -1dBFS)
IN
IN
IN
IN
IN
IN
100
95
90
85
80
75
70
65
60
55
50
80
75
70
65
60
55
50
90
85
80
75
70
65
SFDR
SFDR
SNR
-THD
SINAD
-THD
60
55
50
30
40
50
60
(MHz)
70
80
30
40
50
60
70
80
30
40
50
60
(MHz)
70
80
f
f
(MHz)
f
CLK
CLK
CLK
-THD, SFDR vs. ANALOG SUPPLY VOLTAGE
SNR, SINAD vs. ANALOG SUPPLY VOLTAGE
SNR, SINAD vs. ANALOG SUPPLY VOLTAGE
(f = 80MHz, f = 175MHz)
(f
CLK
= 80MHz, f = 70MHz)
IN
(f
CLK
= 80MHz, f = 70MHz)
IN
CLK
IN
95
90
85
80
75
70
65
60
55
80
75
70
65
60
55
50
75
70
65
60
55
50
SNR
SNR
SFDR
SINAD
SINAD
-THD
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
V
V
DD
V
DD
DD
_______________________________________________________________________________________
9
Dual, 80Msps, 14-Bit, IF/Baseband ADC
Typical Operating Characteristics (continued)
(V
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 5pF at digital outputs, V = -1dBFS (differential),
IN
DD L
DD
DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f
= 80MHz (50% duty cycle), T = +25°C, unless otherwise noted.)
DD
CLK
A
-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE
-THD, SFDR vs. ANALOG SUPPLY VOLTAGE
SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE
(f
CLK
= 80MHz, f = 70MHz)
(f
CLK
= 80MHz, f = 175MHz)
(f = 80MHz, f = 70MHz)
CLK IN
IN
IN
95
90
85
80
75
70
65
60
55
85
80
75
70
65
60
80
75
70
65
60
55
50
SNR
SFDR
SFDR
SINAD
-THD
-THD
3.6
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
OV (V)
V
OV (V)
DD
DD
DD
-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE
P
(ANALOG), I
vs. ANALOG SUPPLY VOLTAGE
SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE
DISS
VDD
(f
CLK
= 80MHz, f = 175MHz)
(f
CLK
= 80MHz, f = 175MHz)
(f
CLK
= 80MHz, f = 175MHz)
IN
IN
(ANALOG)
IN
80
75
70
65
60
55
50
1000
900
800
700
600
500
400
300
200
100
85
81
77
73
69
65
P
DISS
SNR
SFDR
-THD
SINAD
I
VDD
3.6
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
OV (V)
DD
V
OV (V)
DD
DD
P
(DIGITAL), I
OVDD
DISS
vs. DIGITAL SUPPLY VOLTAGE
SNR, SINAD vs. CLOCK DUTY CYCLE
-THD, SFDR vs. CLOCK DUTY CYCLE
(f
= 80MHz, f = 175MHz)
(f = 70MHz, A = -1dBFS)
(f = 70MHz, A = -1dBFS)
CLK
IN
IN
IN
IN
IN
80
70
60
50
40
30
20
10
0
75
70
65
60
55
50
90
85
80
75
70
65
60
SFDR
SNR
SINAD
P
(DIGITAL)
DISS
-THD
I
OVDD
SINGLE-ENDED CLOCK DRIVE
SINGLE-ENDED CLOCK DRIVE
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
25
35
45
55
65
75
25
35
45
55
65
75
OV (V)
DD
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
10 ______________________________________________________________________________________
Dual, 80Msps, 14-Bit, IF/Baseband ADC
Typical Operating Characteristics (continued)
(V
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 5pF at digital outputs, V = -1dBFS (differential),
IN
DD L
DD
DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f
= 80MHz (50% duty cycle), T = +25°C, unless otherwise noted.)
DD
CLK
A
SNR, SINAD vs. TEMPERATURE
(f = 175MHz, A = -1dBFS)
-THD, SFDR vs. TEMPERATURE
(f = 175MHz, A = -1dBFS)
IN
IN
IN
IN
75
72
69
66
63
60
100
95
90
85
80
75
70
65
60
SNR
SFDR
SINAD
-THD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
GAIN ERROR vs. TEMPERATURE
(V
REFIN
= 2.048V)
OFFSET ERROR vs. TEMPERATURE
1.0
0.6
0.3
0.2
0.1
0
0.2
-0.2
-0.6
-1.0
-0.1
-0.2
-0.3
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
______________________________________________________________________________________ 11
Dual, 80Msps, 14-Bit, IF/Baseband ADC
Pin Description
PIN
NAME
FUNCTION
1, 4, 5, 9,
13, 14, 17
GND
Converter Ground. Connect all ground pins and the exposed paddle (EP) together.
2
3
6
INAP
INAN
Channel A Positive Analog Input
Channel A Negative Analog Input
COMA
Channel A Common-Mode Voltage I/O. Bypass COMA to GND with a 0.1µF capacitor.
Channel A Positive Reference I/O. Channel A conversion range is 2/3 x (V
- V
). Bypass
REFAP
REFAN
REFAP with a 0.1µF capacitor to GND. Connect a 4.7µF and a 0.1µF bypass capacitor between REFAP
and REFAN. Place the 0.1µF REFAP-to-REFAN capacitor as close to the device as possible on the
same side of the PC board.
7
8
REFAP
REFAN
REFBN
REFBP
Channel A Negative Reference I/O. Channel A conversion range is 2/3 x (V
- V
). Bypass
REFAP
REFAN
REFAN with a 0.1µF capacitor to GND. Connect a 4.7µF and a 0.1µF bypass capacitor between REFAP
and REFAN. Place the 0.1µF REFAP-to-REFAN capacitor as close to the device as possible on the
same side of the PC board.
Channel B Negative Reference I/O. Channel B conversion range is 2/3 x (V
- V
). Bypass
REFBP
REFBN
REFBN with a 0.1µF capacitor to GND. Connect a 4.7µF and a 0.1µF bypass capacitor between REFBP
and REFBN. Place the 0.1µF REFBP-to-REFBN capacitor as close to the device as possible on the
same side of the PC board.
10
11
Channel B Positive Reference I/O. Channel B conversion range is 2/3 x (V
- V
). Bypass
REFBP
REFBN
REFBP with a 0.1µF capacitor to GND. Connect a 4.7µF and a 0.1µF bypass capacitor between REFBP
and REFBN. Place the 0.1µF REFBP-to-REFBN capacitor as close to the device as possible on the
same side of the PC board.
12
15
16
COMB
INBN
INBP
Channel B Common-Mode Voltage I/O. Bypass COMB to GND with a 0.1µF capacitor.
Channel B Negative Analog Input
Channel B Positive Analog Input
Differential/Single-Ended Input Clock Drive. This input selects between single-ended or differential clock
DIFFCLK/ input drives.
18
SECLK
CLKN
CLKP
DIFFCLK/SECLK = GND: Selects single-ended clock input drive.
DIFFCLK/SECLK = OV : Selects differential clock input drive.
DD
Negative Clock Input. In differential clock input mode (DIFFCLK/SECLK = OV ), connect a differential
clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply
the clock signal to CLKP and connect CLKN to GND.
Positive Clock Input. In differential clock input mode (DIFFCLK/SECLK = OV ), connect a differential
clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply
the single-ended clock signal to CLKP and connect CLKN to GND.
DD
19
20
DD
21
22
DIV2
DIV4
Divide-by-Two Clock-Divider Digital Control Input. See Table 2 for details.
Divide-by-Four Clock-Divider Digital Control Input. See Table 2 for details.
23–26, 61,
62, 63
Analog Power Input. Connect V
capacitor combination of ≥ 10µF and 0.1µF. Connect all V
to a 3.15V to 3.60V power supply. Bypass V
to GND with a parallel
DD
DD
V
DD
pins to the same potential.
DD
Output-Driver Power Input. Connect OV
parallel capacitor combination of ≥ 10µF and 0.1µF.
to a 1.7V to V
power supply. Bypass OV
to GND with a
DD
DD
DD
27, 43, 60
OV
DD
12 ______________________________________________________________________________________
Dual, 80Msps, 14-Bit, IF/Baseband ADC
Pin Description (continued)
PIN
28
29
30
31
32
33
34
35
36
37
38
39
40
41
NAME
D0B
FUNCTION
Channel B CMOS Digital Output, Bit 0 (LSB)
Channel B CMOS Digital Output, Bit 1
Channel B CMOS Digital Output, Bit 2
Channel B CMOS Digital Output, Bit 3
Channel B CMOS Digital Output, Bit 4
Channel B CMOS Digital Output, Bit 5
Channel B CMOS Digital Output, Bit 6
Channel B CMOS Digital Output, Bit 7
Channel B CMOS Digital Output, Bit 8
Channel B CMOS Digital Output, Bit 9
Channel B CMOS Digital Output, Bit 10
Channel B CMOS Digital Output, Bit 11
Channel B CMOS Digital Output, Bit 12
Channel B CMOS Digital Output, Bit 13 (MSB)
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
D10B
D11B
D12B
D13B
Channel B Data Out-of-Range Indicator. The DORB digital output indicates when the channel B analog
input voltage is out of range.
DORB = 1: Digital outputs exceed full-scale range.
42
DORB
DORB = 0: Digital outputs are within full-scale range.
Data-Valid Digital Output. The rising edge of DAV indicates that data is present on the digital outputs.
The MAX12558 evaluation kit utilizes DAV to latch data into any external back-end digital logic.
44
DAV
45
46
47
48
49
50
51
52
53
54
55
56
57
58
D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
D9A
D10A
D11A
D12A
D13A
Channel A CMOS Digital Output, Bit 0 (LSB)
Channel A CMOS Digital Output, Bit 1
Channel A CMOS Digital Output, Bit 2
Channel A CMOS Digital Output, Bit 3
Channel A CMOS Digital Output, Bit 4
Channel A CMOS Digital Output, Bit 5
Channel A CMOS Digital Output, Bit 6
Channel A CMOS Digital Output, Bit 7
Channel A CMOS Digital Output, Bit 8
Channel A CMOS Digital Output, Bit 9
Channel A CMOS Digital Output, Bit 10
Channel A CMOS Digital Output, Bit 11
Channel A CMOS Digital Output, Bit 12
Channel A CMOS Digital Output, Bit 13 (MSB)
Channel A Data Out-of-Range Indicator. The DORA digital output indicates when the channel A analog
input voltage is out of range.
DORA = 1: Digital outputs exceed full-scale range.
DORA = 0: Digital outputs are within full-scale range.
Output Format Select Digital Input.
59
64
DORA
G/T
G/T = GND: Two’s-complement output format selected.
G/T = OV : Gray-code output format selected.
DD
______________________________________________________________________________________ 13
Dual, 80Msps, 14-Bit, IF/Baseband ADC
Pin Description (continued)
PIN
NAME
FUNCTION
Power-Down Digital Input.
65
PD
PD = GND: ADCs are fully operational.
PD = OV : ADCs are powered down.
DD
Shared Reference Digital Input.
SHREF = V : Shared reference enabled.
DD
SHREF = GND: Shared reference disabled.
When sharing the reference, externally connect REFAP and REFBP together to ensure that V
66
67
SHREF
=
REFAP
V
. Similarly, when sharing the reference, externally connect REFAN to REFBN together to ensure
REFBP
that V
= V
.
REFBN
REFAN
Internal Reference Voltage Output. The REFOUT output voltage is 2.048V and REFOUT can deliver 1mA.
For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from
REFOUT REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a ≥ 0.1µF capacitor.
For external reference operation, REFOUT is not required and must be bypassed to GND with a ≥ 0.1µF
capacitor.
Single-Ended Reference Analog Input. For internal reference and buffered external reference operation,
apply a 0.7V to 2.3V DC reference voltage to REFIN. Bypass REFIN to GND with a 4.7µF capacitor.
Within its specified operating voltage, REFIN has a > 50MΩ input impedance, and the differential
68
—
REFIN
reference voltage (V
- V
) is generated from REFIN. For unbuffered external reference
REF_N
REF_P
operation, connect REFIN to GND. In this mode, REF_P, REF_N, and COM_ are high-impedance inputs
that accept the external reference voltages.
Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve the
specified dynamic performance.
EP
+
x2
Σ
MAX12558
−
FLASH
DAC
ADC
IN_P
STAGE 10
END OF PIPELINE
STAGE 1
STAGE 2
STAGE 9
IN_N
DIGITAL ERROR CORRECTION
D0_ THROUGH D13_
Figure 1. Pipeline Architecture—Stage Blocks
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital out-
put code is multiplied and passed on to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX12558 functional diagram.
Detailed Description
The MAX12558 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
From input to output the total latency is 8 clock cycles.
14 ______________________________________________________________________________________
Dual, 80Msps, 14-Bit, IF/Baseband ADC
CLOCK
14-BIT
PIPELINE
ADC
D0A TO D13A
DORA
DIGITAL
ERROR
CORRECTION
INAP
INAN
OUTPUT
DRIVERS
DATA
FORMAT
T/H
REFAP
COMA
REFAN
CHANNEL A
REFERENCE
SYSTEM
MAX12558
G/T
REFIN
REFOUT
SHREF
INTERNAL
REFERENCE
GENERATOR
DAV
OV
DD
REFBP
COMB
REFBN
CHANNEL B
REFERENCE
SYSTEM
14-BIT
PIPELINE
ADC
INBP
INBN
D0B TO D13B
DORB
DIGITAL
ERROR
CORRECTION
OUTPUT
DRIVERS
DATA
FORMAT
T/H
CLOCK
V
DD
DIFFCLK/SECLK
CLOCK
POWER
CONTROL
AND
CLKP
CLKN
CLOCK
DIVIDER
DUTY-CYCLE
EQUALIZER
PD
BIAS CIRCUITS
GND
DIV2
DIV4
Figure 2. Functional Diagram
______________________________________________________________________________________ 15
Dual, 80Msps, 14-Bit, IF/Baseband ADC
Table 1. Reference Modes
V
DD
BOND WIRE
INDUCTANCE
1.5nH
V
REFIN
REFERENCE MODE
MAX12558
Internal Reference Mode. REFIN is driven by
REFOUT either through a direct short or a
resistive divider.
IN_P
IN_N
35% V
REFOUT
*C
C
2pF
SAMPLE
PAR
4.5pF
to 100%
V
V
V
= V
= V
= V
/ 2
COM_
REF_P
REF_N
DD
V
REFOUT
/ 2 + 3/8 x V
REFIN
/ 2 - 3/8 x V
REFIN
DD
V
DD
BOND WIRE
INDUCTANCE
1.5nH
DD
Buffered External Reference Mode. An
external 0.7V to 2.3V reference voltage is
applied to REFIN.
*C
C
2pF
SAMPLE
PAR
4.5pF
0.7V to 2.3V
V
V
V
= V
= V
= V
/ 2
COM_
REF_P
REF_N
DD
/ 2 + 3/8 x V
/ 2 - 3/8 x V
DD
REFIN
SAMPLING
CLOCK
DD
REFIN
Unbuffered External Reference Mode. REF_P,
REF_N, and COM_ are driven by external
reference sources. The full-scale analog input
*THE EFFECTIVE RESISTANCE OF THE
SWITCHED SAMPLING CAPACITORS IS: R
1
=
IN
<0.5V
f
x C
SAMPLE
CLK
range is (V
- V ) x 2/3.
REF_N
REF_P
Figure 3. Internal T/H Circuit
Analog Inputs and Input Track-and-Hold
(T/H) Amplifier
Reference Output
An internal bandgap reference is the basis for all the
internal voltages and bias currents used in the
MAX12558. The power-down logic input (PD) enables
and disables the reference circuit. REFOUT has approxi-
mately 17kΩ to GND when the MAX12558 is powered
down. The reference circuit requires 10ms to power up
and settle to its final value when power is first applied to
the MAX12558 or when PD (power-down control line)
transitions from high to low.
Figure 3 displays a simplified functional diagram of the
input T/H circuit. This input T/H circuit allows for high
analog input frequencies (high IF) of 175MHz and
beyond and supports a V
voltage.
/ 2 common-mode input
DD
The MAX12558 sampling clock controls the switched-
capacitor input T/H architecture (Figure 3) allowing the
analog input signals to be stored as charge on the
sampling capacitors. These switches are closed (track
mode) when the sampling clock is high and open (hold
mode) when the sampling clock is low (Figure 4). The
analog input signal source must be able to provide the
dynamic currents necessary to charge and discharge
the sampling capacitors. To avoid signal degradation,
these capacitors must be charged to one-half LSB
accuracy within one-half of a clock cycle. The analog
input of the MAX12558 supports differential or single-
ended input drive. For optimum performance with dif-
ferential inputs, balance the input impedance of IN_P
and IN_N and set the common-mode voltage to mid-
The internal bandgap reference produces a buffered
reference voltage of 2.048V 1% at the REFOUT pin
with a 50ppm/°C temperature coefficient. Connect an
external ≥ 0.1µF bypass capacitor from REFOUT to
GND for stability. REFOUT sources up to 1mA and
sinks up to 0.1mA for external circuits with a 35mV/mA
load regulation. Short-circuit protection limits I
REFOUT
to a 2.1mA source current when shorted to GND and a
0.24mA sink current when shorted to V . Similar to
DD
REFOUT, REFIN should be bypassed with a 4.7µF
capacitor to GND.
Reference Configurations
The MAX12558 full-scale analog input range is 2/3 x
supply (V
/ 2). The MAX12558 provides the optimum
DD
common-mode voltage of V
/ 2 through the COM
DD
V
V
with a V
/ 2 0.5V common-mode input range.
is the voltage difference between REFAP (REFBP)
REF
REF
DD
output when operating in internal reference mode and
buffered external reference mode. This COM output
voltage can be used to bias the input network as shown
in Figures 9, 10, and 11.
and REFAN (REFBN). The MAX12558 provides three
modes of reference operation. Setting the voltage at
REFIN (V
(Table 1).
) selects the reference operation mode
REFIN
16 ______________________________________________________________________________________
Dual, 80Msps, 14-Bit, IF/Baseband ADC
Connect REFOUT to REFIN either with a direct short or
through a resistive divider for internal reference mode.
COM_, REF_P, and REF_N are low-impedance outputs
Clock Duty-Cycle Equalizer
The MAX12558 has an internal clock duty-cycle equaliz-
er, which makes the converter insensitive to the duty
cycle of the signal applied to CLKP and CLKN. The con-
verters allow clock duty-cycle variations from 25% to 75%
without negatively impacting the dynamic performance.
with V
and V
= V
/ 2, V
DD
= V
/ 2 + 3/8 x V
,
COM_
REF_N
DD
= V
REFP
/ 2 - 3/8 x V
DD
REFIN
. Bypass REF_P,
REFIN
REF_N, and COM_ each with a 0.1µF capacitor to GND.
Bypass REF_P to REF_N with a 10µF capacitor. Bypass
REFIN and REFOUT to GND with a 0.1µF capacitor. The
REFIN input impedance is very large (> 50MΩ). When
driving REFIN through a resistive divider, use resistances
≥ 10kΩ to avoid loading REFOUT.
The clock duty-cycle equalizer uses a delay-locked
loop (DLL) to create internal timing signals that are
duty-cycle independent. Due to this DLL, the
MAX12558 requires approximately 100 clock cycles to
acquire and lock to new clock frequencies.
Buffered external reference mode is virtually identical to
the internal reference mode except that the reference
source is derived from an external reference and not the
MAX12558’s internal bandgap reference. In buffered
external reference mode, apply a stable reference volt-
age source between 0.7V to 2.3V at REFIN. Pins COM_,
REF_P, and REF_N are low-impedance outputs with
Clock Input and Clock Control Lines
The MAX12558 accepts both differential and single-
ended clock inputs with a wide 25% to 75% input clock
duty cycle. For single-ended clock input operation,
connect DIFFCLK/SECLK and CLKN to GND. Apply an
external single-ended clock signal to CLKP. To reduce
clock jitter, the external single-ended clock must have
sharp falling edges. For differential clock input opera-
V
V
= V
/ 2, V
= V
/ 2 + 3/8 x V
, and
COM_
REF_N
DD
REF_P
/ 2 - 3/8 x V
DD
REFIN
= V
. Bypass REF_P, REF_N,
REFIN
DD
tion, connect DIFFCLK/SECLK to OV . Apply an
DD
and COM_ each with a 0.1µF capacitor to GND. Bypass
REF_P to REF_N with a 4.7µF capacitor.
external differential clock signal to CLKP and CLKN.
Consider the clock input as an analog input and route it
away from any other analog inputs and digital signal
lines. CLKP and CLKN enter high impedance when the
MAX12558 is powered down (Figure 4).
Connect REFIN to GND to enter unbuffered external ref-
erence mode. Connecting REFIN to GND deactivates
the on-chip reference buffers for COM_, REF_P, and
REF_N. With their buffers deactivated, COM_, REF_P,
and REF_N become high-impedance inputs and must
be driven with separate, external reference sources.
Low clock jitter is required for the specified SNR perfor-
mance of the MAX12558. The analog inputs are sam-
pled on the falling (rising) edge of CLKP (CLKN),
requiring this edge to have the lowest possible jitter.
Jitter limits the maximum SNR performance of any ADC
according to the following relationship:
Drive V
to V
COM_
/ 2 5%, and drive REF_P and
DD
COM_
REF_N so V
= (V
+ V
) / 2. The analog
REF_P_
REF_N_
) x 2/3. Bypass
REF_N
input range is (V
- V
REF_P_
REF_P, REF_N, and COM_ each with a 0.1µF capacitor
to GND. Bypass REF_P to REF_N with a 4.7µF capacitor.
⎛
⎞
1
SNR = 20 × log
For all reference modes, bypass REFOUT with a 0.1µF
and REFIN with a 4.7µF capacitor to GND.
⎜
⎟
2 × π × f × t
⎝
⎠
IN
J
The MAX12558 also features a shared reference mode,
in which the user can achieve better channel-to-chan-
nel matching. When sharing the reference (SHREF =
where f represents the analog input frequency and t
IN
J
is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For instance,
assuming that clock jitter is the only noise source, to
obtain the specified 71.7dB of SNR with an input fre-
quency of 175MHz the system must have less than
0.24ps of clock jitter. However, in reality there are other
noise sources such as thermal noise and quantization
noise that contribute to the system noise requiring the
clock jitter to be less than 0.17ps to obtain the speci-
fied 71.7dB of SNR at 175MHz.
V
), externally connect REFAP and REFBP together to
DD
ensure that V
= V . Similarly, when sharing
REFBP
REFAP
the reference, externally connect REFAN to REFBN
together to ensure that V = V
.
REFBN
REFAN
Connect SHREF to GND to disable the shared refer-
ence mode of the MAX12558. In this independent refer-
ence mode, a better channel-to-channel isolation is
achieved.
For detailed circuit suggestions and how to drive the
ADC in buffered/unbuffered external reference mode,
see the Applications Information section.
Clock-Divider Control Inputs (DIV2, DIV4)
The MAX12558 features three different modes of sam-
pling/clock operation (see Table 2). Pulling both control
lines low, the clock-divider function is disabled and the
converters sample at full clock speed. Pulling DIV4 low
______________________________________________________________________________________ 17
Dual, 80Msps, 14-Bit, IF/Baseband ADC
Table 2. Clock-Divider Control Inputs
V
DD
DIV4
DIV2
FUNCTION
S
1H
Clock Divider Disabled
MAX12558
0
0
f
= f
CLK
SAMPLE
10kΩ
Divide-by-Two Clock Divider
= f / 2
0
1
f
SAMPLE
CLK
CLKP
Divide-by-Four Clock Divider
= f / 4
1
1
0
1
10kΩ
f
SAMPLE
CLK
DUTY-CYCLE
EQUALIZER
S
2H
Not Allowed
S
1L
10kΩ
pled on the falling (rising) edge of CLKP (CLKN) and
the resulting data appears at the digital outputs 8 clock
cycles later.
CLKN
10kΩ
SWITCHES S AND S ARE OPEN
DURING POWER-DOWN, MAKING
CLKP AND CLKN HIGH IMPEDANCE.
The DAV indicator is synchronized with the digital out-
put and optimized for use in latching data into digital
back-end circuitry. Alternatively, digital back-end cir-
cuitry can be latched with the rising edge of the con-
version clock (CLKP - CLKN).
1_
2_
S
2L
SWITCHES S ARE OPEN IN
2_
GND
SINGLE-ENDED CLOCK MODE.
Data-Valid Output
DAV is a single-ended version of the input clock that is
compensated to correct for any input clock duty-cycle
variations. The MAX12558 output data changes on the
falling edge of DAV, and DAV rises once the output
data is valid. The falling edge of DAV is synchronized
to have a 5.4ns delay from the falling edge of the input
clock. Output data at D0A/B–D13A/B and DORA/B are
valid from 7ns before the rising edge of DAV to 7ns
after the rising edge of DAV.
Figure 4. Simplified Clock Input Circuit
and DIV2 high enables the divide-by-two feature, which
sets the sampling speed to one-half the selected clock
frequency. In divide-by-four mode, the converter sam-
pling speed is set to one-fourth the clock speed of the
MAX12558. Divide-by-four mode is achieved by applying
a high level to DIV4 and a low level to DIV2. The option to
select either one-half or one-fourth of the clock speed for
sampling provides design flexibility, relaxes clock
requirements, and can minimize clock jitter.
DAV enters high impedance when the MAX12558 is
powered down (PD = OV ). DAV enters its high-
DD
System Timing Requirements
Figure 5 shows the timing relationship between the
clock, analog inputs, DAV indicator, DOR_ indicators,
and the resulting output data. The analog input is sam-
impedance state 10ns after the rising edge of PD and
becomes active again 10ns after PD transitions low.
DAV can sink and source 600µA and has three times the
driving capabilities of D0A/B–D13A/B and DORA/B. DAV
N + 4
DIFFERENTIAL ANALOG INPUT (IN_P–IN_N)
N + 5
N + 3
N + 6
(V
(V
- V
- V
) x 2/3
) x 2/3
REF_P
REF_N
N - 3
N - 2
N +2
N + 7
N + 9
N - 1
N
N + 1
N + 8
REF_N
REF_P
t
AD
CLKN
CLKP
t
CL
t
CH
t
DAV
DAV
t
t
HOLD
SETUP
D0_–D13_
DOR
N - 3 N - 2 N - 1
8.0 CLOCK-CYCLE DATA LATENCY
N
N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9
t
SETUP
t
HOLD
Figure 5. System Timing Diagram
18 ______________________________________________________________________________________
Dual, 80Msps, 14-Bit, IF/Baseband ADC
is typically used to latch the MAX12558 output data into
MAX12558 is in power-down (PD = high). DOR_ enters
a high-impedance state within 10ns after the rising edge
of PD and becomes active 10ns after PD’s falling edge.
an external digital back-end circuit. Keep the capacitive
load on DAV as low as possible (< 15pF) to avoid large
digital currents feeding back into the analog portion of
the MAX12558, thereby degrading its dynamic perfor-
mance. Buffering DAV externally isolates it from heavy
capacitive loads. Refer to the MAX12558 EV kit schemat-
ic for recommendations of how to drive the DAV signal
through an external buffer.
Digital Output Data and Output Format Selection
The MAX12558 provides two 14-bit, parallel, tri-state
output buses. D0A/B–D13A/B and DORA/B update on
the falling edge of DAV and are valid on the rising edge
of DAV.
The MAX12558 output data format is either Gray code
or two’s complement depending on the logic input G/T.
With G/T high, the output data format is Gray code.
With G/T low, the output data format is set to two’s com-
plement. See Figure 8 for a binary-to-Gray and Gray-to-
binary code conversion example.
Data Out-of-Range Indicator
The DORA and DORB digital outputs indicate when the
analog input voltage is out of range. When DOR_ is high,
the analog input is out of range. When DOR_ is low, the
analog input is within range. The valid differential input
range is from (V
- V
) x 2/3 to (V
-
REF_N
REF_P
REF_N
The following equations, Table 3, Figure 6, and Figure 7
define the relationship between the digital output and
the analog input.
V
) x 2/3. Signals outside of this valid differential
range cause DOR_ to assert high as shown in Table 1.
REF_P
DOR is synchronized with DAV and transitions along
with the output data D13–D0. There is an 8 clock-cycle
latency in the DOR function as is with the output data
(Figure 5). DOR_ is high impedance when the
Gray Code (G/T = 1):
V
IN_P
- V
= 2/3 x (V
- V
) x 2 x
REF_N
IN_N
REF_P
(CODE - 8192) / 16,384
10
Table 3. Output Codes vs. Input Voltage
GRAY-CODE OUTPUT CODE
TWO’S-COMPLEMENT OUTPUT CODE
(G/T = 1)
(G/T = 0)
DECIMAL
HEXADECIMAL
DECIMAL
EQUIVALENT
OF
D13A–D0A
D13B–D0B
(CODE )
10
V
- V
IN_N
= 2.418V
= 0.882V
IN_P
HEXADECIMAL
EQUIVALENT
DOR OF
EQUIVALENT
V
V
REF_P
REF_N
BINARY
D13A–D0A
D13B–D0B
EQUIVALENT
OF
D13A–D0A
D13B–D0B
BINARY
D13A–D0A
D13B–D0B
OF
D13A–D0A
D13B–D0B
DOR
D13A–D0A
D13B–D0B
(CODE
)
10
> +1.023875V
(DATA OUT OF
RANGE)
10 0000 0000 0000
1
0x2000
+16,383
01 1111 1111 1111
1
0x1FFF
+8191
10 0000 0000 0000
10 0000 0000 0001
0
0
0x2000
0x2001
+16,383
+16,382
01 1111 1111 1111
01 1111 1111 1110
0
0
0x1FFF
0x1FFE
+8191
+8190
+1.023875V
+1.023750V
11 0000 0000 0011
11 0000 0000 0001
11 0000 0000 0000
01 0000 0000 0000
01 0000 0000 0001
0
0
0
0
0
0x3003
0x3001
0x3000
0x1000
0x1001
+8194
+8193
+8192
+8191
+8190
00 0000 0000 0010
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
0
0
0
0
0
0x0002
0x0001
0x0000
0x3FFF
0x3FFE
+2
+1
0
+0.000250V
+0.000125V
+0.000000V
-0.000125V
-0.000250V
-1
-2
00 0000 0000 0001
00 0000 0000 0000
0
0
0x0001
0x0000
+1
0
10 0000 0000 0001
10 0000 0000 0000
0
0
0x2001
0x2000
-8191
-8192
-1.023875V
-1.024000V
< -1.024000V
(DATA OUT OF
RANGE)
00 0000 0000 0000
1
0x0000
0
10 0000 0000 0000
1
0x2000
-8192
______________________________________________________________________________________ 19
Dual, 80Msps, 14-Bit, IF/Baseband ADC
1 LSB = 4/3 x (V
- V
) / 16,384
REFN
1 LSB = 4/3 x (V
- V
) / 16,384
REFN
REFP
REFP
2/3 x (V
- V
)
2/3 x (V
- V
)
REFN
2/3 x (V
- V
)
2/3 x (V
- V
)
REFN
REFP
REFN
REFP
REFP
REFN
REFP
0x2000
0x2001
0x2003
0x1FFF
0x1FFE
0x1FFD
0x3001
0x3000
0x1000
0x0001
0x0000
0x3FFF
0x0002
0x0003
0x0001
0x0000
0x2003
0x2002
0x2001
0x2000
-8191 -8189
-1
0
+1
+8189 +8191
-8191 -8189
-1
0
+1
+8189 +8191
DIFFERENTIAL INPUT VOLTAGE (LSB)
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 6. Two’s-Complement Transfer Function (G/T = 0)
Two’s Complement (G/T = 0):
Figure 7. Gray-Code Transfer Function (G/T = 1)
low, the converter is in its normal operating mode. With
PD high, the MAX12558 is in power-down mode.
V
IN_P
- V
= 2/3 x (V
- V
) x 2 x
REF_N
IN_N
REF_P
CODE / 16,384
The power-down mode allows the MAX12558 to effi-
ciently use power by transitioning to a low-power state
when conversions are not required. Additionally, the
MAX12558 parallel output bus goes high impedance in
power-down mode, allowing other devices on the bus
to be accessed.
10
where CODE is the decimal equivalent of the digital
10
output code as shown in Table 3.
The digital outputs D0A/B–D13A/B are high impedance
when the MAX12558 is in power-down (PD = 1) mode.
D0A/B–D13A/B enter this state 10ns after the rising
edge of PD and become active again 10ns after PD
transitions low.
In power-down mode all internal circuits are off, the
analog supply current reduces to less than 50µA, and
the digital supply current reduces to 1µA. The following
list shows the state of the analog inputs and digital out-
puts in power-down mode.
Keep the capacitive load on the MAX12558 digital out-
puts D0A/B–D13A/B as low as possible (< 15pF) to
avoid large digital currents feeding back into the ana-
log portion of the converter and degrading its dynamic
performance. Adding external digital buffers on the dig-
ital outputs helps isolate the MAX12558 from heavy
capacitive loads. To improve the dynamic performance
of the MAX12558, add 220Ω resistors in series with the
digital outputs close to the MAX12558. Refer to the
MAX12558 EV kit schematic for guidelines of how to
drive the digital outputs through 220Ω series resistors
and external digital output buffers.
1) INAP/B, INAN/B analog inputs are disconnected
from the internal input amplifier (Figure 3).
2) REFOUT has approximately 17kΩ to GND.
3) REFAP/B, COMA/B, REFAN/B enter a high-imped-
ance state with respect to V
and GND, but there
DD
is an internal 4kΩ resistor between REFAP/B and
COMA/B as well as an internal 4kΩ resistor
between REFAN/B and COMA/B.
4) D0A–D13A, D0B–D13B, DORA, and DORB enter a
high-impedance state.
Power-Down Input
The MAX12558 has two power modes that are con-
trolled with a power-down digital input (PD). With PD
5) DAV enters a high-impedance state.
6) CLKP, CLKN clock inputs enter a high-impedance
state (Figure 4).
20 ______________________________________________________________________________________
Dual, 80Msps, 14-Bit, IF/Baseband ADC
BINARY-TO-GRAY CODE CONVERSION
GRAY-TO-BINARY CODE CONVERSION
1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME
AS THE MOST SIGNIFICANT BINARY BIT.
1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE
MOST SIGNIFICANT GRAY-CODE BIT.
D13
D7
D3
D0
0
BIT POSITION
BINARY
BIT POSITION
GRAY CODE
D11
1
D13
0
D7
1
D3
1
D0
0
D11
0
1
1
1
1
0
1
0
0
1
0
0
1
1
0
1
0
1
1
0
0
1
0
GRAY CODE
0
BINARY
2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING
TO THE FOLLOWING EQUATION:
2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO
THE FOLLOWING EQUATION:
+
GRAY = BINARY
BINARY
BINARY = BINARY
+
GRAY
X
X
X + 1
X
X+1 X
+
+
WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION:
WHERE
IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION:
+
GRAY = BINARY
BINARY
BINARY = BINARY
+
GRAY
12
12
13
12
13 12
+
0
BINARY = 0
+
1
1
GRAY = 1
12
12
GRAY = 1
12
BINARY = 1
12
BIT POSITION
BINARY
BIT POSITION
GRAY CODE
D13
0
D7
D3
1
D0
D11
D13
0
D7
D3
1
D0
0
D11
+
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
1
0
0
1
0
+
0
GRAY CODE
0
BINARY
3) REPEAT STEP 2 UNTIL COMPLETE:
3) REPEAT STEP 2 UNTIL COMPLETE:
+
GRAY = BINARY
BINARY
12
11
11
+
BINARY = BINARY
GRAY
11
11
12
+
GRAY = 1
1
11
+
BINARY = 1
0
11
GRAY = 0
11
BINARY = 1
11
D13
0
D7
D3
1
D0
0
D11
BIT POSITION
BINARY
BIT POSITION
GRAY CODE
D13
0
D7
0
D3
1
D0
0
D11
1
1
+
1
0
0
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
1
1
0
0
1
+
0
GRAY CODE
0
BINARY
4) THE FINAL GRAY-CODE CONVERSION IS:
4) THE FINAL BINARY CONVERSION IS:
BIT POSITION
BINARY
D13
0
D7
1
D3
1
D0
0
BIT POSITION
GRAY CODE
D11
0
D13
0
D7
0
D3
1
D0
0
D11
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
0
1
0
0
1
0
0
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
0
GRAY CODE
0
1
0
1
0
BINARY
EXCLUSIVE OR TRUTH TABLE
FIGURE 8 SHOWS THE GRAY-TO-BINARY AND BINARY-TO-GRAY
CODE CONVERSION IN OFFSET BINARY FORMAT. THE OUTPUT
FORMAT OF THE MAX12558 IS TWO'S-COMPLEMENT BINARY,
HENCE EACH MSB OF THE TWO'S-COMPLEMENT OUTPUT CODE
MUST BE INVERTED TO REFLECT TRUE OFFSET BINARY FORMAT.
A
B
Y
=
A
+
B
0
0
1
1
0
1
0
1
0
1
1
0
Figure 8. Binary-to-Gray and Gray-to-Binary Code Conversion
______________________________________________________________________________________ 21
Dual, 80Msps, 14-Bit, IF/Baseband ADC
The wake-up time from power-down mode is dominated
Applications Information
by the time required to charge the capacitors at REF_P,
REF_N, and COM_. In internal reference mode and
buffered external reference mode the wake-up time is
typically 10ms. When operating in the unbuffered exter-
nal reference mode the wake-up time is dependent on
the external reference drivers.
Using Transformer Coupling
In general, the MAX12558 provides better SFDR and
THD with fully differential input signals than single-
ended input drive, especially for input frequencies
above 125MHz. In differential input mode, even-order
harmonics are lower as both inputs are balanced, and
each of the ADC inputs only requires half the signal
swing compared to single-ended input mode.
An RF transformer (Figure 9) provides an excellent
solution to convert a single-ended input source signal
to a fully differential signal, required by the MAX12558
for optimum performance. Connecting the center tap of
IN_P
5.6pF
49.9Ω
24.9Ω
0.5%
0.1µF
the transformer to COM provides a V
/ 2 DC level
DD
1
5
3
6
2
4
MAX12558
V
IN
T1
shift to the input. Although a 1:1 transformer is shown, a
step-up transformer can be selected to reduce the
drive requirements. A reduced signal swing from the
input driver, such as an op amp, can also improve the
overall distortion. The configuration of Figure 9 is good
COM_
N.C.
N.C.
0.1µF
49.9Ω
0.5%
MINI-CIRCUITS
ADT1-1WT
for frequencies up to Nyquist (f
/ 2).
CLK
The circuit of Figure 10 converts a single-ended input
signal to fully differential just as Figure 9. However,
Figure 10 utilizes an additional transformer to improve
the common-mode rejection allowing high-frequency
signals beyond the Nyquist frequency. A set of 75Ω
and 110Ω termination resistors provide an equivalent
50Ω termination to the signal source. The second set of
termination resistors connects to COM_ providing the
correct input common-mode voltage. Two 0Ω resistors
in series with the analog inputs allow high-IF input fre-
quencies. These 0Ω resistors can be replaced with low-
value resistors to limit the input bandwidth.
IN_N
5.6pF
24.9Ω
Figure 9. Transformer-Coupled Input Drive for Input Frequencies
Up to Nyquist
0Ω*
IN_P
C
IN
0.1µF
110Ω
R
IN
1
5
3
1
5
3
6
2
4
6
2
4
75Ω
0.5%
V
IN
T1
T2
0.5%
MAX12558
COM_
IN_N
N.C.
N.C.
N.C.
N.C.
0.1µF
75Ω
0.5%
110Ω
0.5%
MINI-CIRCUITS
ADT1-1WT
MINI-CIRCUITS
ADT1-1WT
0Ω*
C
IN
*0Ω RESISTORS CAN BE REPLACED WITH
LOW-VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH.
R
IN
Figure 10. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist
22 ______________________________________________________________________________________
Dual, 80Msps, 14-Bit, IF/Baseband ADC
The input network in Figure 10 can be modified to enhance
the frequency-range-specific AC performance of the
MAX12558 by simply replacing the input capacitance with
V
IN
0.1µF
0Ω
a series network of resistor (R ) and capacitor (C ).
IN
IN
IN_P
MAX4108
Table 4 displays a selection of resistors and capacitors
that are recommended to help improve the already
excellent performance of this ADC for specific applica-
tions requiring only a certain range of input frequencies.
5.6pF
0.1µF
5.6pF
24.9Ω
100Ω
100Ω
MAX12558
COM_
24.9Ω
Table 4. Component Selection to
Enhance the Frequency-Range-Specific
AC Performance
IN_N
INPUT
FREQUENCY
RANGE
C
R
IN
IN
COMPONENT
VALUES
COMPONENT
VALUES
Figure 11. Single-Ended, AC-Coupled Input Drive
< 10MHz
12pF to 22pF
12pF
0Ω
50Ω
0Ω
Unbuffered External Reference Drives
Multiple ADCs
10MHz to 125MHz
> 125MHz
The unbuffered external reference mode allows for pre-
cise control over the MAX12558 reference and allows
multiple converters to use a common reference.
Connecting REFIN to GND disables the internal refer-
ence, allowing REF_P, REF_N, and COM_ to be driven
directly by a set of external reference sources.
5.6pF
Single-Ended AC-Coupled Input Signal
Figure 11 shows an AC-coupled, single-ended input
application. The MAX4108 provides high speed, high
bandwidth, low noise, and low distortion to maintain the
input signal integrity.
Figure 13 uses a MAX6029 precision 3.000V bandgap
reference as a common reference for multiple convert-
ers. A seven-component resistive divider chain follows
the MAX6029 voltage reference. The 0.47µF capacitor
along this chain creates a 10Hz LP filter. Three
MAX4230 amplifiers buffer taps along this resistor
chain providing 2.413V, 1.647V, and 0.880V to the
MAX12558 REF_P, REF_N, and COM_ reference inputs.
The feedback around the MAX4230 op amps provides
additional 10Hz LP filtering. Reference voltages 2.413V
and 0.880V set the full-scale analog input range for the
Buffered External Reference Drives
Multiple ADCs
The buffered external reference mode allows for more
control over the MAX12558 reference voltage and
allows multiple converters to use a common reference.
The REFIN input impedance is > 50MΩ.
Figure 12 shows the MAX6029 precision 2.048V bandgap
reference used as a common reference for multiple con-
verters. The 2.048V output of the MAX6029 passes
through a single-pole 10Hz LP filter to the MAX4230.
converter to 1.022V ( ꢀV
- V ] x 2/3).
REF_N
REF_P
Note that one single power supply for all active circuit
components removes any concern regarding power-
supply sequencing when powering up or down.
The MAX4250 buffers the 2.048V reference and pro-
vides additional 10Hz LP filtering before its output is
applied to the REFIN input of the MAX12558.
______________________________________________________________________________________ 23
Dual, 80Msps, 14-Bit, IF/Baseband ADC
3.3V
0.1µF
2.2µF
V
DD
REF_P
REFIN
2.048V
0.1µF
0.1µF
47Ω
0.1µF
1
16.2kΩ
1µF
10µF
0.1µF
3
4
5
MAX12558
5
300µF
6V
1
REF_N
COM_
MAX4230
MAX6029
(EUK21)
0.1µF
0.1µF
2
2
REFOUT
1.47kΩ
GND
0.1µF
NOTE: ONE FRONT-END REFERENCE CIRCUIT
CAN SOURCE UP TO 15mA AND SINK UP TO
30mA OF OUTPUT CURRENT.
3.3V
0.1µF
2.2µF
V
DD
REF_P
REFIN
0.1µF
10µF
0.1µF
MAX12558
REF_N
COM_
0.1µF
0.1µF
REFOUT
GND
0.1µF
Figure 12. External Buffered (MAX4230) Reference Drive Using a MAX6029 Bandgap Reference
24 ______________________________________________________________________________________
Dual, 80Msps, 14-Bit, IF/Baseband ADC
3.3V
3V
0.1µF
2.2µF
0.1µF
1
5
20kΩ
1%
V
DD
REF_P
MAX6029
(EUK30)
REFOUT
0.1µF
0.1µF
0.1µF
0.1µF
20kΩ
10µF
0.1µF
1%
2
MAX12558
2.413V
1
3
REF_N
47Ω
1.47kΩ
47Ω
4
4
4
MAX4230
MAX4230
MAX4230
0.47µF
10µF
330µF
6V
6V
52.3kΩ
1%
COM_
REFIN
GND
1.647V
1
3
3.3V
10µF
6V
330µF
6V
52.3kΩ
1%
1.47kΩ
47Ω
0.1µF
2.2µF
0.880V
1
3
V
DD
REF_P
20kΩ
1%
REFOUT
0.1µF
0.1µF
0.1µF
0.1µF
10µF
6V
330µF
6V
10µF
0.1µF
MAX12558
1.47kΩ
20kΩ
1%
REF_N
20kΩ
1%
COM_
REFIN
GND
Figure 13. External Unbuffered Reference Driving Multiple ADCs
______________________________________________________________________________________ 25
Dual, 80Msps, 14-Bit, IF/Baseband ADC
Offset Error
Grounding, Bypassing, and
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Ideally the midscale
MAX12558 transition occurs at 0.5 LSB above mid-
scale. The offset error is the amount of deviation
between the measured midscale transition point and
the ideal midscale transition point.
Board Layout
The MAX12558 requires high-speed board layout
design techniques. Refer to the MAX12558 EV kit data
sheet for a board layout reference. Locate all bypass
capacitors as close to the device as possible, prefer-
ably on the same side as the ADC, using surface-
mount devices for minimum inductance. Bypass V
to
DD
GND with a 220µF ceramic capacitor in parallel with at
least one 10µF, one 4.7µF, and one 0.1µF ceramic
Gain Error
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope of
the ideal transfer function. The slope of the actual transfer
function is measured between two data points: positive
full scale and negative full scale. Ideally, the positive full-
scale MAX12558 transition occurs at 1.5 LSBs below pos-
itive full scale, and the negative full-scale transition
occurs at 0.5 LSB above negative full scale. The gain
error is the difference of the measured transition points
minus the difference of the ideal transition points.
capacitor. Bypass OV
to GND with a 220µF ceramic
DD
capacitor in parallel with at least one 10µF, one 4.7µF,
and one 0.1µF ceramic capacitor. High-frequency
bypassing/decoupling capacitors should be located as
close as possible to the converter supply pins.
Multilayer boards with ample ground and power planes
produce the highest level of signal integrity. All grounds
and the exposed backside paddle of the MAX12558
must be connected to the same ground plane. The
MAX12558 relies on the exposed backside paddle con-
nection for a low-inductance ground connection. Isolate
the ground plane from any noisy digital system ground
planes such as a DSP or output buffer ground.
Small-Signal Noise Floor (SSNF)
SSNF is the integrated noise and distortion power in the
Nyquist band for small-signal inputs. The DC offset is
excluded from this noise calculation. For this converter,
a small signal is defined as a single tone with a -35dBFS
amplitude. This parameter captures the thermal and
quantization noise characteristics of the data converter
and can be used to help calculate the overall noise fig-
ure of a digital receiver signal path.
Route high-speed digital signal traces away from the
sensitive analog traces. Keep all signal lines short and
free of 90° turns.
Ensure that the differential, analog input network layout
is symmetric and that all parasitic components are bal-
anced equally. Refer to the MAX12558 EV kit data
sheet for an example of symmetric input layout.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
Parameter Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. For the MAX12558, this
straight line is between the endpoints of the transfer
function, once offset and gain errors have been nullified.
INL deviations are measured at every step of the transfer
function and the worst-case deviation is reported in the
Electrical Characteristics table.
SNR
= 6.02 × N + 1.76
ꢀmax]
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spec-
tral components to the Nyquist frequency excluding the
fundamental, the first six harmonics (HD2 through
HD7), and the DC offset.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. A DNL error specification of
less than 1 LSB guarantees no missing codes and a
monotonic transfer function. For the MAX12558, DNL
deviations are measured at every step of the transfer
function and the worst-case deviation is reported in the
Electrical Characteristics table.
SNR = 20 x log (SIGNAL
/ NOISE
)
RMS
RMS
26 ______________________________________________________________________________________
Dual, 80Msps, 14-Bit, IF/Baseband ADC
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise plus distortion. RMS noise plus
distortion includes all spectral components to the
Nyquist frequency excluding the fundamental and the
DC offset.
CLKN
CLKP
t
AD
ANALOG
INPUT
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmon-
ics of the input signal to the fundamental itself. This is
expressed as:
t
AJ
SAMPLED
DATA
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
2
2
2
2
2
2
V
+ V + V + V + V + V
3 4 5 6 7
2
THD = 20 × log
HOLD
TRACK
HOLD
T/H
V
1
where V is the fundamental amplitude, and V through
1
2
V
are the amplitudes of the 2nd- through 7th-order
harmonics (HD2 through HD7).
7
Figure 14. T/H Aperture Timing
1024k data points are collected. n
taking the RMS value of the collected data points after
the mean is removed.
is computed by
OUT
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
Overdrive Recovery Time
Overdrive recovery time is the time required for the
ADC to recover from an input transient that exceeds the
full-scale limits. The MAX12558 specifies overdrive
recovery time using an input transient that exceeds the
full-scale limits by 10%. The MAX12558 requires one
clock cycle to recover from the overdrive condition.
3rd-Order Intermodulation (IM3)
IM3 is the power of the 3rd-order intermodulation prod-
uct relative to the input power of either of the input tones
f
and f . The individual input tone power levels are
IN2
IN1
set to -7dBFS for the MAX12558. The 3rd-order inter-
modulation products are 2 x f - f and 2 x f - f
.
IN2 IN1
IN1 IN2
Crosstalk
Crosstalk indicates how well each channel is isolated
from the other channel. In case of the MAX12558,
crosstalk specifies the coupling onto one channel
being driven by a (-0.5dBFS) signal when the adjacent
interfering channel is driven by a full-scale signal.
Measurement includes all spurs resulting from both
direct coupling and mixing components.
Aperture Jitter
Figure 14 shows the aperture jitter (t ), which is the
AJ
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 14).
Gain Matching
Gain matching is a figure of merit that indicates how
well the gains between the two channels are matched
to each other. The same input signal is applied to both
channels and the maximum deviation in gain is report-
ed (typically in dB) as gain matching.
Full-Power Bandwidth
A large -0.2dBFS analog input signal is applied to an
ADC and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as the
full-power input bandwidth frequency.
Offset Matching
Like gain matching, offset matching is a figure of merit
that indicates how well the offsets between the two chan-
nels are matched to each other. The same input signal is
applied to both channels and the maximum deviation in
offset is reported (typically in %FSR) as offset matching.
Output Noise (n
)
OUT
The output noise (n
) parameter is similar to thermal
OUT
plus quantization noise and is an indication of the con-
verter’s overall noise performance.
No fundamental input tone is used to test for n
.
OUT
IN_P, IN_N, and COM_ are connected together and
______________________________________________________________________________________ 27
Dual, 80Msps, 14-Bit, IF/Baseband ADC
Pin Configuration
TOP VIEW
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
D7A 52
D8A 53
34 D6B
33 D5B
32 D4B
31 D3B
30 D2B
29 D1B
28 D0B
54
55
D9A
D10A
D11A 56
57
58
59
60
61
62
63
D12A
D13A
DORA
27 OV
DD
OV
DD
26
25
24
23
V
V
V
V
DD
MAX12558
V
DD
V
DD
V
DD
DD
DD
DD
G/T 64
22 DIV4
65
66
21 DIV2
PD
20 CLKP
SHREF
EXPOSED PADDLE (GND)
REFOUT 67
19 CLKN
68
18 DIFFCLK/SECLK
REFIN
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
THIN QFN
28 ______________________________________________________________________________________
Dual, 80Msps, 14-Bit, IF/Baseband ADC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
68L THIN QFN, 10x10x0.8mm
1
D
21-0142
2
______________________________________________________________________________________ 29
Dual, 80Msps, 14-Bit, IF/Baseband ADC
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
68L THIN QFN, 10x10x0.8mm
2
D
21-0142
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
Heaney
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