MAX1248BCPE+_技术文档

19-1072; Rev 2; 5/98

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

8/MAX1249

_______________Ge n e ra l De s c rip t io n

____________________________Fe a t u re s

The MAX1248/MAX1249 10-bit data-acquisition sys-

tems combine a 4-channel multiplexer, high-bandwidth

track/hold, and serial interface with high conversion

speed and low power consumption. They operate from

a s ing le +2.7V to +5.25V s up p ly, a nd the ir a na log

inputs are software configurable for unipolar/bipolar

and single-ended/differential operation.

♦ 4-Channel Single-Ended or 2-Channel

Differential Inputs

♦ Single +2.7V to +5.25V Operation

♦ Internal 2.5V Reference (MAX1248)

♦ Low Power: 1.2mA (133ksps, +3V supply)

54µA (1ksps, +3V supply)

The 4-wire serial interface connects directly to SPI™/

QSPI™ and MICROWIRE™ devices without external

logic. A serial strobe output allows direct connection

to TMS320-fa mily d ig ita l s ig na l p roc e s s ors . The

MAX1248/MAX1249 use either the internal clock or an

external serial-interface clock to perform successive-

approximation analog-to-digital conversions.

1µA (power-down mode)

♦ SPI/QSPI/MICROWIRE/TMS320-Compatible

4-Wire Serial Interface

♦ Software-Configurable Unipolar or Bipolar Inputs

♦ 16-Pin QSOP Package (same area as 8-pin SO)

The MAX1248 has an internal 2.5V reference, while the

MAX1249 requires an external reference. Both parts

have a reference-buffer amplifier with a ±1.5% voltage

adjustment range.

_____________Ord e rin g In fo rm a t io n

These devices provide a hard-wired SHDN pin and a

s oftwa re -s e le c ta b le p owe r-d own, a nd c a n b e p ro-

grammed to automatically shut down at the end of a

conversion. Accessing the serial interface automatically

p owe rs up the MAX1248/MAX1249, a nd the q uic k

turn-on time allows them to be shut down between all

conversions. This technique can cut supply current to

under 60µA at reduced sampling rates.

INL

(LSB)

PART^†

TEMP. RANGE PIN-PACKAGE

MAX1248ACPE 0°C to +70°C

16 Plastic DIP

16 QSOP

±1/2

±1

MAX1248BCPE

MAX1248ACEE

MAX1248BCEE

0°C to +70°C

±1/2

±1

16 QSOP

The MAX1248/MAX1249 are available in a 16-pin DIP

and a very small QSOP that occupies the same board

area as an 8-pin SO.

Ordering Information continued at end of data sheet.

†

Contact factory for availability of alternate surface-mount

packages.

For 8-c ha nne l ve rs ions of the s e d e vic e s , s e e the

MAX148/MAX149 data sheet.

________________________Ap p lic a t io n s

__________Typ ic a l Op e ra t in g Circ u it

Portable Data Logging

Medical Instruments

Pen Digitizers

Data Acquisition

+3V

Battery-Powered Instruments

System Supervision

V

DD

V

CH0

DD

C3

0.1µF

0V TO

+2.5V

ANALOG

INPUTS

DGND

MAX1248

CH3

AGND

COM

CPU

I/O

CS

Pin Configuration appears at end of data sheet.

SCLK

SCK (SK)

MOSI (SO)

MISO (SI)

VREF

DIN

C1

4.7µF

DOUT

SSTRB

SHDN

REFADJ

V

SS

C2

0.01µF

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

________________________________________________________________ Maxim Integrated Products

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.

For small orders, phone 408-737-7600 ext. 3468.

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

ABSOLUTE MAXIMUM RATINGS

V

to AGND, DGND .............................................. -0.3V to +6V

QSOP (derate 8.30mW/°C above +70°C)................... 667mW

CERDIP (derate 10.00mW/°C above +70°C).............. 800mW

Operating Temperature Ranges

DD

AGND to DGND.................................................... -0.3V to +0.3V

CH0–CH3, COM to AGND, DGND ............ -0.3V to (V + 0.3V)

DD

VREF to AGND........................................... -0.3V to (V + 0.3V)

Digital Inputs to DGND............................................ -0.3V to +6V

MAX1248_C_E/MAX1249_C_E .......................... 0°C to +70°C

MAX1248_E_E/MAX1249_E_E........................ -40°C to +85°C

MAX1248_MJE/MAX1249_MJE .................... -55°C to +125°C

Storage Temperature Range ............................ -60°C to +150°C

Lead Temperature (soldering, 10sec) ............................ +300°C

DD

Digital Outputs to DGND ........................... -0.3V to (V + 0.3V)

DD

Digital Output Sink Current .................................................25mA

Continuous Power Dissipation (T = +70°C)

A

Plastic DIP (derate 10.53mW/°C above +70°C) ......... 842mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V = +2.7V to +5.25V; COM = 0V; f

= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);

DD

SCLK

MAX1248—4.7µF capacitor at VREF pin; MAX1249—external reference, VREF = 2.500V applied to VREF pin; T = T

to T

,

A

MIN

MAX

unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

8/MAX1249

DC ACCURACY (Note 1)

Resolution

10

Bits

MAX124_A

MAX124_B

±0.5

LSB

±1.0

Relative Accuracy (Note 2)

Differential Nonlinearity

Offset Error

INL

DNL

No missing codes over temperature

MAX124_A

±1

±2

±1

±2

LSB

MAX124_B

MAX124_A

Gain Error (Note 3)

LSB

ppm/°C

LSB

MAX124_B

Gain Temperature Coefficient

±0.25

±0.05

Channel-to-Channel Offset

Matching

DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)

Signal-to-Noise + Distortion Ratio

Total Harmonic Distortion

Spurious-Free Dynamic Range

Channel-to-Channel Crosstalk

Small-Signal Bandwidth

SINAD

THD

66

-70

70

dB

Up to the 5th harmonic

SFDR

dB

65kHz, 2.500Vp-p (Note 4)

-3dB rolloff

-75

2.25

1.0

dB

MHz

Full-Power Bandwidth

CONVERSION RATE

5.5

35

6

7.5

65

Internal clock, SHDN = FLOAT

Conversion Time (Note 5)

t

µs

Internal clock, SHDN = V

CONV

DD

External clock = 2MHz, 12 clocks/conversion

Track/Hold Acquisition Time

Aperture Delay

t

1.5

µs

ns

ps

ACQ

30

<50

1.8

Aperture Jitter

SHDN = FLOAT

Internal Clock Frequency

External Clock Frequency

MHz

0.225

SHDN = V

DD

0.1

0

2.0

Data transfer only

2

_______________________________________________________________________________________

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

8/MAX1249

ELECTRICAL CHARACTERISTICS (continued)

(V = +2.7V to +5.25V; COM = 0V; f

= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);

DD

SCLK

MAX1248—4.7µF capacitor at VREF pin; MAX1249—external reference, VREF = 2.500V applied to VREF pin; T = T

to T

,

A

MIN

MAX

unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

ANALOG/COM INPUTS

Unipolar, COM = 0V

Bipolar, COM = VREF / 2

On/off leakage current, V

0 to VREF

Input Voltage Range, Single-

Ended and Differential (Note 6)

V

±VREF / 2

±1

Multiplexer Leakage Current

Input Capacitance

= 0V or V

±0.01

16

µA

pF

CH_

DD

INTERNAL REFERENCE (MAX1248 only, reference buffer enabled)

VREF Output Voltage

T

= +25°C (Note 7)

2.470

2.500

2.530

30

V

mA

A

VREF Short-Circuit Current

VREF Temperature Coefficient

Load Regulation (Note 8)

MAX1248

±30

ppm/°C

mV

0mA to 0.2mA output load

Internal compensation mode

External compensation mode

0.35

0

Capacitive Bypass at VREF

µF

4.7

Capacitive Bypass at REFADJ

REFADJ Adjustment Range

0.01

µF

%

±1.5

EXTERNAL REFERENCE AT VREF (Buffer disabled)

VREF Input Voltage Range

(Note 9)

V

50mV

+

DD

V

1.0

18

VREF Input Current

VREF = 2.500V

100

25

150

µA

kΩ

µA

VREF Input Resistance

Shutdown VREF Input Current

0.01

10

V

0.5

DD -

REFADJ Buffer-Disable Threshold

EXTERNAL REFERENCE AT REFADJ

Capacitive Bypass at VREF

V

Internal compensation mode

External compensation mode

MAX1248

0

µF

V/V

µA

4.7

2.06

2.00

Reference-Buffer Gain

MAX1249

MAX1248

±50

±10

REFADJ Input Current

MAX1249

DIGITAL INPUTS (DIN, SCLK, CS, SHDN)

V

≤ 3.6V

2.0

3.0

DD

V

IH

V

DIN, SCLK, CS Input High Voltage

V

DD

> 3.6V

V

0.8

V

DIN, SCLK, CS Input Low Voltage

DIN, SCLK, CS Input Hysteresis

DIN, SCLK, CS Input Leakage

DIN, SCLK, CS Input Capacitance

SHDN Input High Voltage

IL

V

HYST

0.2

I

IN

V

= 0V or V

DD

±0.01

±1

15

µA

pF

V

IN

C

(Note 10)

IN

V

SH

V

DD

- 0.4

V

SM

1.1

V

DD

- 1.1

V

SHDN Input Mid Voltage

V

SL

0.4

V

SHDN Input Low Voltage

I

S

±4.0

µA

SHDN Input Current

SHDN = 0V or V

DD

_______________________________________________________________________________________

3

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

ELECTRICAL CHARACTERISTICS (continued)

(V = +2.7V to +5.25V; COM = 0V; f

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);

DD

SCLK

MAX1248—4.7µF capacitor at VREF pin; MAX1249—external reference; VREF = 2.500V applied to VREF pin, T = T

to T

,

A

MIN

MAX

unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

V

DD

/ 2

V

SHDN Voltage, Floating

SHDN = FLOAT

FLT

SHDN Maximum Allowed

Leakage, Mid Input

±100

nA

V

DIGITAL OUTPUTS (DOUT, SSTRB)

I

= 5mA

0.4

0.8

SINK

Output Voltage Low

V

OL

I

= 16mA

SINK

Output Voltage High

V

OH

I

= 0.5mA

V

DD

- 0.5

V

SOURCE

Three-State Leakage Current

Three-State Output Capacitance

I

±0.01

±10

15

µA

pF

CS = V

L

DD

C

CS = V (Note 10)

OUT

DD

POWER REQUIREMENTS

2

Positive Supply Voltage

V

2.70

5.25

3.0

2.0

15

V

DD

V

= 5.25V

= 3.6V

= 5.25V

= 3.6V

1.6

1.2

3.5

1.2

30

DD

Operating mode,

full-scale input (Note 11)

mA

V

DD

I

DD

Positive Supply Current

V

DD

Full power-down

µA

V

DD

10

I

DD

Fast power-down (MAX1248) V = 5.25V

70

DD

V

= 2.7V to 5.25V, full-scale input,

DD

Supply Rejection (Note 12)

PSR

±0.3

mV

external reference = 2.500V

4

_______________________________________________________________________________________

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

8/MAX1249

TIMING CHARACTERISTICS

(V = +2.7V to +5.25V, T = T

to T

, unless otherwise noted.)

DD

A

MIN

MAX

PARAMETER

SYMBOL

CONDITIONS

MIN

1.5

TYP

MAX UNITS

Acquisition Time

DIN to SCLK Setup

DIN to SCLK Hold

t

µs

ns

ACQ

t

DS

100

t

0

ns

DH

MAX124__C/E

MAX124__M

20

200

240

SCLK Fall to Output Data Valid

t

Figure 1

ns

DO

t

Figure 1

Figure 2

ns

CS Fall to Output Enable

CS Rise to Output Disable

CS to SCLK Rise Setup

CS to SCLK Rise Hold

SCLK Pulse Width High

SCLK Pulse Width Low

SCLK Fall to SSTRB

DV

t

TR

t

100

0

CSS

CSH

t

200

CH

t

CL

t

Figure 1

240

SSTRB

t

External clock mode only, Figure 1

External clock mode only, Figure 2

Internal clock mode only (Note 10)

CS Fall to SSTRB Output Enable

CS Rise to SSTRB Output Disable

SSTRB Rise to SCLK Rise

SDV

t

STR

t

0

SCK

Note 1: Tested at V = 2.7V; COM = 0V; unipolar single-ended input mode.

DD

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: MAX1248—internal reference, offset nulled; MAX1249 — external reference (VREF = +2.500V), offset nulled.

Note 4: Ground “on” channel; sine wave applied to all “off” channels.

Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 6: The common-mode range for the analog inputs is from AGND to V

.

DD

Note 7 Sample tested to 0.1% AQL.

Note 8: External load should not change during conversion for specified accuracy.

Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.

Note 10 Guaranteed by design. Not subject to production testing.

Note 11: The MAX1249 typically draws 400µA less than the values shown.

|

Note 12: Measured as V (2.7V) - V (5.25V) .

FS

_______________________________________________________________________________________

5

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s

(V = 3.0V, VREF = 2.500V, f

= 2.0MHz, C

= 20pF, T = +25°C, unless otherwise noted.)

A

DD

SCLK

LOAD

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

SHUTDOWN SUPPLY CURRENT

vs. SUPPLY VOLTAGE

2.5025

INTERNAL REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

2.00

1.75

1.50

1.25

1.00

0.75

0.50

4.0

3.5

3.0

2.5

2.0

R = ∞

L

FULL POWER-DOWN

CODE = 10101010

C

LOAD

= 50pF

C

LOAD

= 20pF

MAX1248

MAX1249

2.5000

C

LOAD

= 50pF

1.5

1.0

0.5

0

C

LOAD

= 20pF

2.4975

2.25 2.75 3.25 3.75 4.25 4.75 5.25

2

2.25 2.75 3.25 3.75 4.25 4.75 5.25

SUPPLY VOLTAGE (V)

V

DD

(V)

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

SHUTDOWN CURRENT

vs. TEMPERATURE

SUPPLY CURRENT vs. TEMPERATURE

2.501

2.0

1.3

V

DD

= 5.25V

2.500

2.499

V

= 3.6V

DD

MAX1248

1.6

1.2

0.8

0.4

1.2

1.1

1.0

V

= 2.7V

DD

2.498

2.497

2.496

MAX1249

= ∞

0.9

0.8

2.495

2.494

R

LOAD

CODE = 1010101000

-60 -20 20

TEMPERATURE (°C)

0

-60 -40 -20

0

20 40 60 80 100 120 140

-60

-20

20

60

100

140

60

100

140

TEMPERATURE (°C)

INTEGRAL NONLINEARITY

vs. TEMPERATURE

INTEGRAL NONLINEARITY

vs. CODE

INTERGRAL NONLINEARITY

vs. SUPPLY VOLTAGE

0.100

0.075

0.050

0.025

0

0.30

0.25

0.20

0.15

0.10

0.05

00

V

DD

= 2.7V

0.25

0.20

0.15

0.10

0.05

0

-0.025

-0.050

-0.075

-0.100

MAX1248

MAX1249

MAX1248

MAX1249

-60 -40 -20

0

20 40 60 80 100 120 140

0

256

512

768

1024

2.25 2.75 3.25 3.75 4.25 4.75 5.25

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

CODE

6

_______________________________________________________________________________________

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

8/MAX1249

______________________________________________________________P in De s c rip t io n

1

NAME

FUNCTION

V

DD

Positive Supply Voltage

Sampling Analog Inputs

2–5

CH0–CH3

COM

Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to

±0.5LSB.

6

7

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1248/MAX1249 down; otherwise, the

devices are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compen-

sation mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode.

SHDN

Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In

internal reference mode (MAX1248 only), the reference buffer provides a 2.500V nominal output,

externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling

8

VREF

REFADJ to V

.

DD

9

REFADJ

AGND

DGND

DOUT

Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to V

.

DD

10

11

12

Analog Ground

Digital Ground

Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.

Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1248/MAX1249 begin the

A/D conversion and goes high when the conversion is completed. In external clock mode, SSTRB

pulses high for one clock period before the MSB decision. High impedance when CS is high (external

clock mode).

13

SSTRB

14

15

DIN

Serial Data Input. Data is clocked in at SCLK’s rising edge.

Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is

high impedance.

CS

Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets

the conversion speed. (Duty cycle must be 40% to 60%.)

16

SCLK

V

DD

V

DD

6k

C

DOUT

C

50pF

C

50pF

C

LOAD

50pF

LOAD

6k

50pF

DGND

b) High-Z to V and V to V

OL

a) High-Z to V and V to V

OH

OL

OH

OL

a) V to High-Z

b) V to High-Z

OL

OH

Figure 1. Load Circuits for Enable Time

Figure 2. Load Circuits for Disable Time

_______________________________________________________________________________________

7

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

on the falling SCLK edge after the last bit of the input

control word has been entered. At the end of the acqui-

sition interval, the T/H switch opens, retaining charge

_______________De t a ile d De s c rip t io n

The MAX1248/MAX1249 analog-to-digital converters

(ADCs) use a successive-approximation conversion

technique and input track/hold (T/H) circuitry to convert

an analog signal to a 10-bit digital output. A flexible

serial interface provides easy interface to microproces-

s ors (µPs ). Fig ure 3 is a b loc k d ia g ra m of the

MAX1248/MAX1249.

on C

as a sample of the signal at IN+.

HOLD

The conversion interval begins with the input multiplex-

er switching C from the positive input (IN+) to the

HOLD

negative input (IN-). In single-ended mode, IN- is sim-

ply COM. This unbalances node ZERO at the compara-

tor’s inp ut. The c a p a c itive DAC a d jus ts d uring the

re ma ind e r of the c onve rs ion c yc le to re s tore nod e

ZERO to 0V within the limits of 10-bit resolution. This

action is equivalent to transferring a charge of 16pF x

P s e u d o -Diffe re n t ia l In p u t

The sampling architecture of the ADC’s analog com-

p a ra tor is illus tra te d in the e q uiva le nt inp ut c irc uit

(Fig ure 4). In s ing le -e nd e d mod e , IN+ is inte rna lly

switched to CH0–CH3, and IN- is switched to COM. In

differential mode, IN+ and IN- are selected from two

pairs: CH0/CH1 and CH2/CH3. Configure the channels

with Tables 2 and 3. Please note that the codes for

CH0–CH3 in the MAX1248/MAX1249 correspond to

the c od e s for CH2–CH5 in the e ig ht-c ha nne l

(MAX148/MAX149) versions.

[(V ) - (V -)] from C

to the binary-weighted

IN+

IN

HOLD

capacitive DAC, which in turn forms a digital represen-

tation of the analog input signal.

Tra c k /Ho ld

The T/H enters its tracking mode on the falling clock

edge after the fifth bit of the 8-bit control word has been

shifted in. It enters its hold mode on the falling clock

edge after the eighth bit of the control word has been

shifted in. If the converter is set up for single-ended

inputs, IN- is connected to COM, and the converter

samples the “+” input. If the converter is set up for dif-

ferential inputs, IN- connects to the “-” input, and the

difference of |IN+ - IN-| is sampled. At the end of the

conversion, the positive input connects back to IN+,

8/MAX1249

In differential mode, IN- and IN+ are internally switched

to either of the analog inputs. This configuration is

pseudo-differential to the effect that only the signal at

IN+ is sampled. The return side (IN-) must remain sta-

b le within ± 0.5LSB (± 0.1LSB for b e s t re s ults ) with

respect to AGND during a conversion. To accomplish

this, connect a 0.1µF capacitor from IN- (the selected

analog input) to AGND.

and C

charges to the input signal.

HOLD

The time required for the T/H to acquire an input signal

is a function of how quickly its input capacitance is

charged. If the input signal’s source impedance is high,

During the acquisition interval, the channel selected as

the positive input (IN+) charges capacitor C

. The

HOLD

acquisition interval spans three SCLK cycles and ends

15

16

CS

SCLK

CAPACITIVE DAC

VREF

INPUT

SHIFT

REGISTER

INT

CLOCK

14

7

DIN

COMPARATOR

INPUT

CONTROL

LOGIC

C

HOLD

SHDN

MUX

ZERO

–

+

CH0

CH1

CH2

CH3

COM

2

3

CH0

CH1

CH2

CH3

12

13

16pF

OUTPUT

SHIFT

DOUT

R

9k

IN

REGISTER

SSTRB

C

SWITCH

ANALOG

INPUT

MUX

T/H

4

5

6

HOLD

CLOCK

TRACK

IN

AT THE SAMPLING INSTANT,

THE MUX INPUT SWITCHES

FROM THE SELECTED IN+

CHANNEL TO THE SELECTED

IN- CHANNEL.

SAR

ADC

T/H

SWITCH

OUT

1

REF

V

DD

COM

11

A ≈ 2.06*

+1.21V

DGND

AGND

20k

REFERENCE

(MAX1248)

SINGLE-ENDED MODE: IN+ = CHO–CH3, IN- = COM.

DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF

CH0/CH1 AND CH2/CH3.

10

9

8

REFADJ

VREF

MAX1248

MAX1249

+2.500V

*A ≈ 2.00 (MAX1249)

Figure 3. Block Diagram

Figure 4. Equivalent Input Circuit

8

_______________________________________________________________________________________

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

8/MAX1249

Table 1. Control-Byte Format

BIT 7

(MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(LSB)

START

SEL2

SEL1

SEL0

UNI/BIP

SGL/DIF

PD1

PD0

BIT

NAME

DESCRIPTION

7(MSB)

START

The first logic “1” bit after CS goes low defines the beginning of the control byte.

6

5

4

SEL2

SEL1

SEL0

These three bits select which of the four channels are used for the conversion (Tables 2 and 3).

3

UNI/BIP

1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an

analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range

from -VREF / 2 to +VREF / 2.

2

SGL/DIF

1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-

ended mode, input signal voltages are referred to COM. In differential mode, the voltage

difference between two channels is measured (Tables 2 and 3).

1

PD1

PD0

Selects clock and power-down modes.

0(LSB)

PD1

PD0

Mode

0

1

0

1

0

1

Full power-down

Fast power-down (MAX1248 only)

Internal clock mode

External clock mode

the acquisition time lengthens, and more time must be

allowed between conversions. The acquisition time,

An a lo g In p u t P ro t e c t io n

Internal protection diodes, which clamp the analog input

t

, is the maximum time the device takes to acquire

to V and AGND, allow the channel input pins to swing

ACQ

DD

the signal, and is also the minimum time needed for the

signal to be acquired. It is calculated by:

from AGND - 0.3V to V

However, for accurate conversions near full scale, the

+ 0.3V without d a ma g e .

DD

inputs must not exceed V by more than 50mV or be

lower than AGND by 50mV.

DD

t

= 7.6 x (R + R ) x 16pF

S IN

ACQ

If the analog input exceeds 50mV beyond the sup-

plies, do not forward bias the protection diodes of off

channels over 4mA.

where R = 9kΩ, R = the source impedance of the

IN

S

input signal, and t

is never less than 1.5µs. Note

ACQ

that source impedances below 3kΩ do not significantly

affect the ADC’s AC performance.

Ho w t o S t a rt a Co n ve rs io n

A conversion is started by clocking a control byte into

DIN. With CS low, each rising edge on SCLK clocks a bit

from DIN into the MAX1248/MAX1249’s internal shift reg-

ister. After CS falls, the first arriving logic “1” bit defines

the control byte’s MSB. Until this first “start” bit arrives,

any number of logic “0” bits can be clocked into DIN with

no effect. Table 1 shows the control-byte format.

Higher source impedances can be used if a 0.01µF

capacitor is connected to the individual analog inputs.

Note that the input capacitor forms an RC filter with the

inp ut s ourc e imp e d a nc e , limiting the ADC’s s ig na l

bandwidth.

In p u t Ba n d w id t h

The ADC’s inp ut tra c king c irc uitry ha s a 2.25MHz

small-signal bandwidth, so it is possible to digitize

high-speed transient events and measure periodic sig-

nals with bandwidths exceeding the ADC’s sampling

ra te b y us ing und e rs a mp ling te c hniq ue s . To a void

high-frequency signals being aliased into the frequency

band of interest, anti-alias filtering is recommended.

The MAX1248/MAX1249 are compatible with SPI/QSPI

and MICROWIRE devices. For SPI, select the correct

clock polarity and sampling edge in the SPI control reg-

isters: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI,

and QSPI all transmit a byte and receive a byte at the

same time. Using the Typical Operating Circuit, the sim-

_______________________________________________________________________________________

9

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

DIF

Table 2. Channel Selection in Single-Ended Mode (SGL/

= 1)

SEL2

0

SEL1

0

SEL0

1

CH0

CH1

CH2

CH3

COM

+

–

1

0

1

0

1

0

+

–

+

DIF

Table 3. Channel Selection in Differential Mode (SGL/

= 0)

SEL2

0

SEL1

0

SEL0

1

CH0

CH1

CH2

CH3

+

–

0

1

0

1

0

1

0

+

–

+

–

+

8/MAX1249

plest software interface requires only three 8-bit transfers

to perform a conversion (one 8-bit transfer to configure

the ADC, and two more 8-bit transfers to clock out the

10-bit conversion result). See Figure 19 for MAX1248/

MAX1249 QSPI connections.

serial-clock frequency and the amount of idle time

between 8-bit transfers. To avoid excessive T/H droop,

make sure the total conversion time does not exceed

120µs.

Digital Output

In unipolar input mode, the output is straight binary

(Figure 16). For bipolar inputs, the output is two’s com-

plement (Figure 17). Data is clocked out at the falling

edge of SCLK in MSB-first format.

Simple Software Interface

Make sure the CPU’s serial interface runs in master

mode so the CPU generates the serial clock. Choose a

clock frequency from 100kHz to 2MHz.

1) Set up the control byte for external clock mode and

call it TB1. TB1 should be of the format: 1XXXXX11

Clo c k Mo d e s

The MAX1248/MAX1249 may use either an external

serial clock or the internal clock to perform the succes-

sive-approximation conversion. In both clock modes,

the e xte rna l c loc k s hifts d a ta in a nd out of the

MAX1248/MAX1249. The T/H acquires the input signal

as the last three bits of the control byte are clocked into

DIN. Bits PD1 and PD0 of the control byte program the

clock mode. Figures 6–9 show the timing characteristics

common to both modes.

binary, where the Xs denote the particular channel

and conversion mode selected.

2) Use a general-purpose I/O line on the CPU to pull

CS low.

3) Transmit TB1 and, simultaneously, receive a byte

and call it RB1. Ignore RB1.

4) Transmit a byte of all zeros ($00 hex) and, simulta-

neously, receive byte RB2.

External Clock

In external clock mode, the external clock not only shifts

data in and out, it also drives the analog-to-digital con-

version steps. SSTRB pulses high for one clock period

after the last bit of the control byte. Successive-approxi-

mation bit decisions are made and appear at DOUT on

each of the next 10 SCLK falling edges (Figure 5).

SSTRB and DOUT go into a high-impedance state when

5) Transmit a byte of all zeros ($00 hex) and, simulta-

neously, receive byte RB3.

6) Pull CS high.

Figure 5 shows the timing for this sequence. Bytes RB2

and RB3 contain the result of the conversion padded

with one leading zero, two sub-bits, and three trailing

zeros. The total conversion time is a function of the

10 ______________________________________________________________________________________

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

8/MAX1249

CS

t

ACQ

SCLK

1

4

8

12

16

20

24

UNI/

BIP

SGL/

DIF

SEL2 SEL1 SEL0

PD1 PD0

DIN

SSTRB

DOUT

START

RB2

B6

RB3

RB1

FILLED WITH

ZEROS

B9

MSB

B0

LSB

B8

B7

B5

B4

B3

B2

B1

S1

S0

ACQUISITION

1.5µs

CONVERSION

A/D STATE

IDLE

(f

CLK

= 2MHz)

Figure 5. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with f

≤ 2MHz)

SCLK

• • •

CS

t

CSH

CSS

CH

t

CL

CSH

SCLK

• • •

t

DS

t

DH

DIN

• • •

t

TR

DV

DO

DOUT

• • •

Figure 6. Detailed Serial-Interface Timing

the serial-clock frequency is less than 100kHz, or if

serial-clock interruptions could cause the conversion

interval to exceed 120µs.

CS goes high; after the next CS falling edge, SSTRB will

output a logic low. Figure 7 shows the SSTRB timing in

external clock mode.

The conversion must complete in some minimum time,

or d roop on the s a mp le -a nd -hold c a p a c itors ma y

degrade conversion results. Use internal clock mode if

______________________________________________________________________________________ 11

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

CS

• • •

t

STR

SDV

SSTRB

• • •

t

SSTRB

SCLK

• • •

•

• • • •

PD0 CLOCKED IN

Figure 7. External Clock Mode SSTRB Detailed Timing

8/MAX1249

CS

SCLK

DIN

1

4

8

18

24

2

3

5

6

7

9

10

11

12

19

20

21

22

23

UNI/ SGL/

BIP DIF

SEL2 SEL1 SEL0

PD1 PD0

START

SSTRB

t

CONV

FILLED WITH

ZEROS

B9

MSB

B0

LSB

DOUT

B8

B7

S1

S0

ACQUISITION CONVERSION

A/D STATE

1.5µs

IDLE

7.5µs MAX

(f

SCLK

= 2MHz) (SHDN = FLOAT)

Figure 8. Internal Clock Mode Timing

Internal Clock

MSB of the c onve rs ion a t DOUT, followe d b y the

remaining bits in MSB-first format (Figure 8). CS does

not need to be held low once a conversion is started.

Pulling CS high prevents data from being clocked into

the MAX1248/MAX1249 and three-states DOUT, but it

does not adversely affect an internal clock mode con-

version already in progress. When internal clock mode

is selected, SSTRB does not go into a high-impedance

state when CS goes high.

In internal clock mode, the MAX1248/MAX1249 gener-

ate their own conversion clocks internally. This frees the

µP from the burden of running the SAR conversion clock

and allows the conversion results to be read back at the

processor’s convenience, at any clock rate from 0MHz

to 2MHz. SSTRB goes low at the start of the conversion

and then goes high when the conversion is complete.

SSTRB is low for a maximum of 7.5µs (SHDN = FLOAT),

during which time SCLK should remain low for best

noise performance.

Fig ure 9 s hows the SSTRB timing in inte rna l c loc k

mode. In this mode, data can be shifted in and out of

the MAX1248/MAX1249 a t c loc k ra te s e xc e e d ing

An internal register stores data when the conversion is

in progress. SCLK clocks the data out of this register at

any time after the conversion is complete. After SSTRB

goes high, the next falling clock edge produces the

2.0MHz if the minimum acquisition time, t

above 1.5µs.

, is kept

ACQ

12 ______________________________________________________________________________________

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

8/MAX1249

Most microcontrollers require that conversions occur in

multiples of 8 SCLK clocks; 16 clocks per conversion is

typically the fastest that a microcontroller can drive the

MAX1248/MAX1249. Figure 10b shows the serial-inter-

face timing necessary to perform a conversion every 16

SCLK cycles in external clock mode.

Da t a Fra m in g

The falling edge of CS does not start a conversion. The

first logic high clocked into DIN is interpreted as a start

bit and defines the first bit of the control byte. A conver-

sion starts on the falling edge of SCLK, after the eighth

bit of the control byte (the PD0 bit) is clocked into DIN.

The start bit is defined as:

__________ Ap p lic a t io n s In fo rm a t io n

The first high bit clocked into DIN with CS low any

time the converter is idle; e.g., after V is applied.

DD

P o w e r-On Re s e t

When power is first applied, and if SHDN is not pulled

low, inte rna l p owe r-on re s e t c irc uitry a c tiva te s the

MAX1248/MAX1249 in internal clock mode, ready to

convert with SSTRB = high. After the power supplies

have stabilized, the internal reset time is 10µs, and no

conversions should be performed during this phase.

SSTRB is high on power-up and, if CS is low, the first

logical 1 on DIN is interpreted as a start bit. Until a con-

version takes place, DOUT shifts out zeros (also see

Table 4).

OR

The first high bit clocked into DIN after bit 3 of a con-

version in progress is clocked onto the DOUT pin.

If CS is toggled before the current conversion is com-

plete, the next high bit clocked into DIN is recognized as

a start bit; the current conversion is terminated, and a

new one is started.

The fastest the MAX1248/MAX1249 can run with CS

held low between conversions is 15 clocks per conver-

sion. Figure 10a shows the serial-interface timing nec-

essary to perform a conversion every 15 SCLK cycles

in external clock mode. If CS is tied low and SCLK is

continuous, guarantee a start bit by first clocking in 16

zeros.

Re fe re n c e -Bu ffe r Co m p e n s a t io n

In addition to its shutdown function, SHDN selects inter-

na l or e xte rna l c omp e ns a tion. The c omp e ns a tion

affects both power-up time and maximum conversion

speed. The 100kHz minimum clock rate is limited by

droop on the sample-and-hold, and is independent of

the compensation used.

CS

• • •

t

CONV

t

CSS

t

SCK

CSH

SSTRB

SCLK

• • •

t

SSTRB

• • •

t

DO

PD0 CLOCK IN

DOUT

• • •

NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

Figure 9. Internal Clock Mode SSTRB Detailed Timing

______________________________________________________________________________________ 13

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

CS

1

8

1

8

1

SCLK

DIN

S

CONTROL BYTE 2

S

CONTROL BYTE 0

S

CONTROL BYTE 1

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0

CONVERSION RESULT 0

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0

CONVERSION RESULT 1

DOUT

SSTRB

Figure 10a. External Clock Mode, 15 Clocks/Conversion Timing

• • •

CS

SCLK

8/MAX1249

S

CONTROL BYTE 0

S

CONTROL BYTE 1

DIN

DOUT

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0

CONVERSION RESULT 0

B9 B8 B7 B6

CONVERSION RESULT 1

Figure 10b. External Clock Mode, 16 Clocks/Conversion Timing

Full power-down mode turns off all chip functions that

draw quiescent current, reducing supply current typically

to 2µA. Fast power-down mode turns off all circuitry

except the bandgap reference. With fast power-down

mode, the supply current is 30µA. Power-up time can be

shortened to 5µs in internal compensation mode.

Floa t SHDN to s e le c t e xte rna l c omp e ns a tion. The

Typical Operating Circuit uses a 4.7µF capacitor at

VREF. A value of 4.7µF or greater ensures reference-

buffer stability and allows converter operation at the

2MHz full clock speed. External compensation increas-

es power-up time (see Choosing Power-Down Mode

and Table 4).

Table 4 shows how the choice of reference-buffer com-

pensation and power-down mode affects both power-up

delay and maximum sample rate. In external compensa-

tion mode, power-up time is 20ms with a 4.7µF compen-

sation capacitor when the capacitor is initially fully

discharged. From fast power-down, start-up time can be

eliminated by using low-leakage capacitors that do not

discharge more than 1/2LSB while shut down. In power-

down, leakage currents at VREF cause droop on the ref-

erence bypass capacitor. Figures 11a and 11b show

the various power-down sequences in both external and

internal clock modes.

Pull SHDN hig h to s e le c t inte rna l c omp e ns a tion.

Internal compensation requires no external capacitor at

VREF and allows for the shortest power-up times. The

maximum clock rate is 2MHz in internal clock mode

and 400kHz in external clock mode.

Ch o o s in g P o w e r-Do w n Mo d e

You can save power by placing the converter in a low-

current shutdown state between conversions. Select full

power-down or fast power-down mode via bits 1 and 0

of the DIN c ontrol b yte with SHDN hig h or floa ting

(Tables 1 and 5). In both software power-down modes,

the serial interface remains operational, but the ADC

does not convert. Pull SHDN low at any time to shut

down the converter completely. SHDN overrides bits 1

and 0 of the control byte.

14 ______________________________________________________________________________________

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

8/MAX1249

Table 4. Typical Power-Up Delay Times

REFERENCE-BUFFER

COMPENSATION

MODE

VREF

CAPACITOR

(µF)

POWER-UP

DELAY

(µs)

MAXIMUM

SAMPLING RATE

(ksps)

REFERENCE

BUFFER

POWER-DOWN

MODE

Enabled

Disabled

Internal

External

—

Fast

Full

Fast

Full

Fast

Full

5

26

300

26

4.7

—

See Figure 13c

133

See Figure 13c

2

—

CLOCK

MODE

EXTERNAL

SHDN

DIN

SETS SOFTWARE

POWER-DOWN

SETS EXTERNAL

CLOCK MODE

SETS EXTERNAL

CLOCK MODE

S X X X X X 1 1

S X X X X X 0 0

S X X X X X 1 1

DOUT

MODE

VALID

DATA

INVALID

DATA

10+2 DATA BITS

POWERED UP

10+2 DATA BITS

HARDWARE

POWER-

DOWN

POWERED UP

SOFTWARE

POWER-DOWN

POWERED UP

Figure 11a. Timing Diagram Power-Down Modes, External Clock

CLOCK

MODE

INTERNAL

SETS

POWER-DOWN

SETS INTERNAL

CLOCK MODE

DIN

S X X X X X 1 0

S X X X X X 0 0

S

DOUT

DATA VALID

SSTRB

MODE

CONVERSION

POWER-DOWN

POWERED UP

Figure 11b. Timing Diagram Power-Down Modes, Internal Clock

______________________________________________________________________________________ 15

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

Table 5. Software Power-Down and

Clock Mode

PD1

PD0

DEVICE

10,000

1000

100

10

VREF = V = 3.0V

DD

Full Power-Down

Fast Power-Down

Internal Clock

External Clock

0

1

0

1

0

1

R

LOAD

= ∞

CODE = 1010101000

4 CHANNELS

Table 6. Hardware Power-Down and

Internal Clock Frequency

1 CHANNEL

1

REFERENCE-

BUFFER

COMPENSATION

INTERNAL

CLOCK

FREQUENCY

SHDN

STATE

DEVICE

MODE

0.1

1

10 100 1k 10k 100k 1M

CONVERSION RATE (Hz)

225kHz

1.8MHz

1

Enabled

Internal

External

8/MAX1249

Floating

Figure 12. Average Supply Current vs. Conversion Rate

with External Reference

Power-

Down

0

N/A

This feature eases the settling-time requirement for the

re fe re nc e volta g e . With a n e xte rna l re fe re nc e , the

MAX1248/MAX1249 can be considered fully powered

up within 2µs of actively pulling SHDN high.

Software Power-Down

Software power-down is activated using bits PD1 and PD0

of the control byte. As shown in Table 5, PD1 and PD0

also specify the clock mode. When software shutdown is

asserted, the ADC operates in the last specified clock

mode until the conversion is complete. Then the ADC

powers down into a low quiescent-current state. In internal

clock mode, the interface remains active, and conversion

results may be clocked out after the MAX1248/MAX1249

enter a software power-down.

P o w e r-Do w n S e q u e n c in g

The MAX1248/MAX1249 auto power-down modes can

save considerable power when operating at less than

maximum sample rates. Figures 12, 13a, and 13b show

the average supply current as a function of the sampling

rate. The following discussion illustrates the various

power-down sequences.

Lowest Power at up to 500

Conversions/Channel/Second

The following examples illustrate two different power-

down sequences. Other combinations of clock rates,

compensation modes, and power-down modes may

give lowest power consumption in other applications.

The first logical 1 on DIN is interpreted as a start bit

and powers up the MAX1248/MAX1249. Following the

start bit, the data input word or control byte also deter-

mines clock mode and power-down states. For exam-

ple, if the DIN word contains PD1 = 1, then the chip

remains powered up. If PD0 = PD1 = 0, a power-down

resumes after one conversion.

Hardware Power-Down

Pulling SHDN low places the converter in hardware

power-down (Table 6). Unlike software power-down

mode, the conversion is not completed; it stops coinci-

dentally with SHDN being brought low. SHDN also con-

trols the clock frequency in internal clock mode. Letting

SHDN float sets the internal clock frequency to 1.8MHz.

When returning to normal operation with SHDN floating,

Figure 13a depicts the MAX1248 power consumption

for one or e ig ht c ha nne l c onve rs ions , utilizing full

power-down mode and internal-reference compensa-

tion. A 0.01µF bypass capacitor at REFADJ forms an

RC filter with the internal 20kΩ reference resistor with a

0.2ms time constant. To achieve full 10-bit accuracy, 8

time constants or 1.6ms are required after power-up.

Waiting 1.6ms in FASTPD mode instead of in full power-

up can reduce the power consumption by a factor of 10

or more. This is achieved by using the sequence shown

in Figure 14.

there is a t

delay of approximately 2MΩ x C , where

RC

L

C

is the capacitive loading on the SHDN pin. Pulling

L

SHDN high sets the internal clock frequency to 225kHz.

16 ______________________________________________________________________________________

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

8/MAX1249

100

10

1

10,000

R

= ∞

R

= ∞

LOAD

CODE = 1010101000

1000

100

10

4 CHANNELS

1 CHANNEL

1

0.01

0.1

1

10

100

1k

0.1

1

10 100 1k 10k 100k 1M

CONVERSION RATE (Hz)

Figure 13a. MAX1248 Supply Current vs. Conversion Rate,

FULLPD

Figure 13b. MAX1248 Supply Current vs. Conversion Rate,

FASTPD

Lowest Power at Higher Throughputs

Fig ure 13b s hows the p owe r c ons ump tion with

external-reference compensation in fast power-down,

with one and four channels converted. The external

4.7µF compensation requires a 75µs wait after power-up

with one dummy conversion. This circuit combines fast

multi-channel conversion with lowest power consumption

possible. Full power-down mode may provide increased

p owe r s a ving s in a p p lic a tions whe re the

MAX1248/MAX1249 are inactive for long periods of time,

but where intermittent bursts of high-speed conversions

are required.

3.0

2.5

2.0

1.5

1.0

In t e rn a l a n d Ex t e rn a l Re fe re n c e s

The MAX1248 can be used with an internal or external

reference voltage, whereas an external reference is

required for the MAX1249. An external reference can

be connected directly at VREF or at the REFADJ pin.

0.5

0

0.01

0.1

1

10

TIME IN SHUTDOWN (sec)

An internal buffer is designed to provide 2.5V at VREF

for b oth the MAX1248 a nd the MAX1249. The

MAX1248’s inte rna lly trimme d 1.21V re fe re nc e is

buffered with a gain of 2.06. The MAX1249’s REFADJ

pin is also buffered with a gain of 2.06 to scale an

external 1.25V reference at REFADJ to 2.5V at VREF.

Figure 13c. Typical Reference-Buffer Power-Up Delay vs. Time

in Shutdown

Internal Reference (MAX1248)

The MAX1248’s full-scale range with the internal refer-

ence is 2.5V with unipolar inputs and ±1.25V with bipo-

lar inputs. The internal-reference voltage is adjustable

to ±1.5% with the circuit of Figure 15.

______________________________________________________________________________________ 17

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

COMPLETE CONVERSION SEQUENCE

1.6ms WAIT

0 1

(ZEROS)

CH1

CH7

(ZEROS)

DIN

1

0 0

FULLPD

1.21V

1

1 1

1

0 0

FULLPD

1

0 1

FASTPD

NOPD

REFADJ

VREF

0V

2.50V

0V

τ = RC = 20kΩ x C

REFADJ

t

≈ 75µs

BUFFEN

Figure 14. MAX1248 FULLPD/FASTPD Power-Up Sequence

External Reference

With both the MAX1248 and MAX1249, an external ref-

erence can be placed at either the input (REFADJ) or

the output (VREF) of the internal reference-buffer ampli-

fier. The REFADJ input impedance is typically 20kΩ for

the MAX1248 and higher than 100kΩ for the MAX1249,

where the internal reference is omitted. At VREF, the

DC input resistance is a minimum of 18kΩ. During con-

version, an external reference at VREF must deliver

up to 350µA DC loa d c urre nt a nd ha ve a n outp ut

impedance of 10Ω or less. If the reference has higher

output impedance or is noisy, bypass it close to the

VREF pin with a 4.7µF capacitor.

+3.3V

8/MAX1249

24k

MAX1248

REFADJ

510k

9

100k

0.01µF

Figure 15. MAX1248 Reference-Adjust Circuit

Using the REFADJ input makes buffering the external

reference unnecessary. To use the direct VREF input,

OUTPUT CODE

FULL-SCALE

disable the internal buffer by tying REFADJ to V . In

DD

power-down, the input bias current to REFADJ can be

TRANSITION

11 . . . 111

a s muc h a s 25µA with REFADJ tie d to V . Pull

DD

11 . . . 110

11 . . . 101

REFADJ to AGND to minimize the input bias current in

power-down.

Tra n s fe r Fu n c t io n

Table 7 shows the full-scale voltage ranges for unipolar

and bipolar modes.

FS = VREF + COM

ZS = COM

The external reference must have a temperature coeffi-

cient of 20ppm/°C or less to achieve accuracy to within

1LSB over the commercial temperature range of 0°C to

+70°C.

VREF

1024

1LSB =

00 . . . 011

00 . . . 010

Figure 16 depicts the nominal, unipolar input/output

(I/O) transfer function, and Figure 17 shows the bipolar

input/output transfer function. Code transitions occur

ha lfwa y b e twe e n s uc c e s s ive -inte g e r LSB va lue s .

Output coding is binary, with 1LSB = 2.44mV (2.500V /

1024) for unip ola r op e ra tion a nd 1LSB = 2.44mV

[(2.500V / 2 - -2.500V / 2) / 1024] for bipolar operation.

00 . . . 001

00 . . . 000

0

1

2

3

FS

(COM)

FS - 3/2LSB

INPUT VOLTAGE (LSBs)

Figure 16. Unipolar Transfer Function, Full Scale (FS) = VREF

+ COM, Zero Scale (ZS) = COM

18 ______________________________________________________________________________________

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

8/MAX1249

Table 7. Full Scale and Zero Scale

UNIPOLAR MODE

BIPOLAR MODE

Positive

Zero

Negative

Full Scale

Zero Scale

COM

Full Scale

Scale

VREF / 2

+ COM

-VREF / 2

+ COM

VREF + COM

COM

OUTPUT CODE

VREF

2

FS

=

+ COM

011 . . . 111

011 . . . 110

SUPPLIES

ZS = COM

-VREF

2

-FS =

+ COM

VREF

+3V

GND

000 . . . 010

000 . . . 001

000 . . . 000

1LSB =

1024

R* = 10Ω

111 . . . 111

111 . . . 110

111 . . . 101

V

DD

AGND

COM DGND

+3V DGND

100 . . . 001

100 . . . 000

DIGITAL

CIRCUITRY

MAX1248

MAX1249

COM*

INPUT VOLTAGE (LSB)

- FS

+FS - 1LSB

* OPTIONAL

*COM ≥ VREF / 2

Figure 17. Bipolar Transfer Function, Zero Scale (ZS) = COM,

Full Scale (FS) = VREF / 2 + COM

Figure 18. Power-Supply Grounding Connection

High-frequency noise in the V

power supply may

La yo u t , Gro u n d in g , a n d Byp a s s in g

For b e s t p e rforma nc e , us e p rinte d c irc uit b oa rd s .

Wire-wrap boards are not recommended. Board layout

should ensure that digital and analog signal lines are

separated from each other. Do not run analog and digi-

tal (especially clock) lines parallel to one another, or

digital lines underneath the ADC package.

DD

affect the ADC’s high-speed comparator. Bypass the

supply to the star ground with 0.1µF and 1µF capaci-

tors close to pin 1 of the MAX1248/MAX1249. Minimize

capacitor lead lengths for best supply-noise rejection.

If the +3V power supply is very noisy, a 10Ω resistor

can be connected as a lowpass filter (Figure 18).

Figure 18 shows the recommended system ground

connections. Establish a single-point analog ground

(star ground point) at AGND, separate from the logic

ground. Connect all other analog grounds and DGND

to the star ground. No other digital system ground

should be connected to this ground. For lowest noise

operation, the ground return to the star ground’s power

supply should be low impedance and as short as pos-

sible.

Hig h -S p e e d Dig it a l In t e rfa c in g w it h QS P I

The MAX1248/MAX1249 can interface with QSPI using

the circuit in Figure 19 (f

= 2.0MHz, CPOL = 0,

SCLK

CPHA = 0). This QSPI circuit can be programmed to do a

conversion on each of the four channels. The result is

stored in memory without taxing the CPU, since QSPI

incorporates its own micro-sequencer.

The MAX1248/MAX1249 are QSPI compatible up to their

maximum external clock frequency of 2MHz.

______________________________________________________________________________________ 19

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

+3V

1µF

16

15

14

13

12

11

10

9

SCK

1

2

3

4

5

6

7

8

V

DD

SCLK

CS

0.1µF

PCS0

CH0

MC683XX

MAX1248

MAX1249

CH1

DIN

MOSI

ANALOG

INPUTS

CH2

SSTRB

DOUT

MISO

CH3

COM

SHDN

VREF

DGND

AGND

REFADJ

(GND)

+2.5V

8/MAX1249

CLOCK CONNECTIONS NOT SHOWN

0.1µF

Figure 19. MAX1248/MAX1249 QSPI Connections External Reference

TMS 3 2 0 LC3 x In t e rfa c e

Figure 20 shows an application circuit to interface the

MAX1248/MAX1249 to the TMS320 in external clock

mode. The timing diagram for this interface circuit is

shown in Figure 21.

XF

CLKX

CLKR

DX

CS

Use the following steps to initiate a conversion in the

MAX1248/MAX1249 and to read the results:

SCLK

TMS320LC3x

1) The TMS320 s hould b e c onfig ure d with CLKX

(transmit clock) as an active-high output clock and

CLKR (TMS320 receive clock) as an active-high

input clock. CLKX and CLKR on the TMS320 are

tied together with the MAX1248/MAX1249’s SCLK

input.

MAX1249

DIN

DR

DOUT

SSTRB

2) The MAX1248/MAX1249’s CS pin is driven low by

the TMS320’s XF_ I/O port, to enable data to be

clocked into the MAX1248/MAX1249’s DIN.

FSR

3) An 8-bit word (1XXXXX11) should be written to the

MAX1248/MAX1249 to initiate a conversion and

place the device into external clock mode. Refer to

Table 1 to select the proper XXXXX bit values for

your specific application.

Figure 20. MAX1248/MAX1249-to-TMS320 Serial Interface

5) The TMS320 reads in one data bit on each of the

next 16 rising edges of SCLK. These data bits rep-

resent the 10 + 2-bit conversion result followed by

four trailing bits, which should be ignored.

4) The MAX1248/MAX1249’s SSTRB output is moni-

tored via the TMS320’s FSR input. A falling edge on

the SSTRB output indicates that the conversion is in

progress and data is ready to be received from the

MAX1248/MAX1249.

6) Pull CS high to disable the MAX1248/MAX1249 until

the next conversion is initiated.

20 ______________________________________________________________________________________

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

8/MAX1249

CS

SCLK

DIN

START SEL2

SEL1

SEL0 UNI/BIP SGL/DIF PD1

PD0

HIGH

IMPEDANCE

SSTRB

HIGH

IMPEDANCE

B0

LSB

DOUT

MSB

B8

S1

S0

Figure 21. TMS320 Serial-Interface Timing Diagram

___________________________________________Ord e rin g In fo rm a t io n (c o n t in u e d )

INL

(LSB)

INL

(LSB)

PART^†

TEMP. RANGE

PIN-PACKAGE

PART^†

TEMP. RANGE PIN-PACKAGE

MAX1248AEPE -40°C to +85°C

MAX1248BEPE -40°C to +85°C

MAX1248AEEE -40°C to +85°C

MAX1248BEEE -40°C to +85°C

16 Plastic DIP

16 QSOP

±1/2

±1

MAX1249ACEE

MAX1249BCEE

0°C to +70°C

16 QSOP

±1/2

±1

16 QSOP

MAX1249AEPE -40°C to +85°C

MAX1249BEPE -40°C to +85°C

MAX1249AEEE -40°C to +85°C

MAX1249BEEE -40°C to +85°C

16 Plastic DIP

16 QSOP

±1/2

±1

±1/2

±1

16 QSOP

MAX1248AMJE -55°C to +125°C 16 CERDIP*

MAX1248BMJE -55°C to +125°C 16 CERDIP*

±1/2

±1

±1/2

±1

16 QSOP

MAX1249ACPE

0°C to +70°C

16 Plastic DIP

±1/2

±1

MAX1249AMJE -55°C to +125°C 16 CERDIP*

MAX1249BMJE -55°C to +125°C 16 CERDIP*

±1/2

±1

MAX1249BCPE

†

Contact factory for availability of alternate surface-mount packages.

* Contact factory for availability of CERDIP package, and for processing to MIL-STD-883B.

______________________________________________________________________________________ 21

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

___________________Ch ip In fo rm a t io n

_________________P in Co n fig u ra t io n

TRANSISTOR COUNT: 2554

TOP VIEW

16

15

14

13

12

11

10

9

V

1

2

3

4

5

6

7

8

SCLK

CS

DD

CH0

CH1

DIN

CH2

MAX1248

MAX1249

SSTRB

DOUT

DGND

AGND

REFADJ

CH3

COM

SHDN

VREF

DIP/QSOP

8/MAX1249

________________________________________________________P a c k a g e In fo rm a t io n

22 ______________________________________________________________________________________

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

8/MAX1249

___________________________________________P a c k a g e In fo rm a t io n (c o n t in u e d )

______________________________________________________________________________________ 23

+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 0 -Bit ADCs in QS OP -1 6

NOTES

8/MAX1249

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

24 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX1248BCPE+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	ADC, Successive Approximation, 10-Bit, 1 Func, 4 Channel, Serial Access, CMOS, PDIP16, 0.300 INCH, PLASTIC, MS-001AA, DIP-16
文件：	总24页 (文件大小：243K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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