MAX1240BCSA [MAXIM]
+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO; + 2.7V ，低功耗， 12位串行ADC的8引脚SO
| 型号： | MAX1240BCSA |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | +2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO |
| 文件： | 总16页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1155; Rev 2; 11/98
+2 .7 V, Lo w -P o w e r,
1 2 -Bit S e ria l ADCs in 8 -P in S O
0/MAX241
__________________Ge n e ra l De s c rip t io n
________________________________Fe a t u re s
The MAX1240/MAX1241 are low-power, 12-bit analog-
to-digital converters (ADCs) available in 8-pin pack-
ages. The MAX1240 operates with a single +2.7V to
+3.6V supply, and the MAX1241 operates with a single
+2.7V to +5.25V supply. Both devices feature a 7.5µs
s uc c e s s ive -a p p roxima tion ADC, a fa s t tra c k/hold
(1.5µs), an on-chip clock, and a high-speed, 3-wire ser-
ial interface.
♦ Single-Supply Operation:
+2.7V to +3.6V (MAX1240)
+2.7V to +5.25V (MAX1241)
♦ 12-Bit Resolution
♦ Internal 2.5V Reference (MAX1240)
♦ Small Footprint: 8-Pin DIP/SO Packages
♦ Low Power: 3.7µW (73ksps, MAX1240)
3mW (73ksps, MAX1241)
Power consumption is only 37mW (V
= 3V) at the
DD
73ksps maximum sampling speed. A 2µA shutdown
mode reduces power at slower throughput rates.
66µW (1ksps, MAX1241)
5µW (power-down mode)
The MAX1240 has an internal 2.5V reference, while the
MAX1241 requires an external reference. The MAX1241
♦ Internal Track/Hold
♦ SPI/QSPI/MICROWIRE 3-Wire Serial Interface
♦ Internal Clock
accepts signals from 0V to V
, and the reference
REF
input range includes the positive supply rail. An exter-
na l c loc k a c c e s s e s d a ta from the 3-wire inte rfa c e ,
which connects directly to standard microcontroller I/O
ports. The interface is compatible with SPI™, QSPI™,
and MICROWIRE™.
Ord e rin g In fo rm a t io n
PIN-
PACKAGE
INL
(LSB)
PART
TEMP. RANGE
Excellent AC characteristics and very low power com-
bined with ease of use and small package size make
these converters ideal for remote-sensor and data-
a c q uis ition a p p lic a tions , or for othe r c irc uits with
demanding power consumption and space require-
ments. The MAX1240/MAX1241 are available in 8-pin
DIP and SO packages.
MAX1240ACPA
MAX1240BCPA
MAX1240CCPA
MAX1240ACSA
MAX1240BCSA
MAX1240CCSA
MAX1240BC/D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
8 Plastic DIP
8 Plastic DIP
8 Plastic DIP
8 SO
±1/2
±1
±1
±1/2
8 SO
±1
8 SO
±1
Dice*
±1
Ap p lic a t io n s
Ordering Information continued at end of data sheet.
*Dice are specified at T = +25°C, DC parameters only.
A
Battery-Powered Systems
Portable Data Logging
Isolated Data Acquisition
Process Control
Fu n c t io n a l Dia g ra m
V
DD
1
Instrumentation
7
8
CS
SCLK
P in Co n fig u ra t io n
3
CONTROL
LOGIC
INT
SHDN
CLOCK
TOP VIEW
OUTPUT
SHIFT
6
DOUT
REGISTER
V
DD
SCLK
CS
1
2
3
4
8
7
6
5
12-BIT
SAR
AIN
SHDN
REF
2
4
T/H
AIN
REF
MAX1240
MAX1241
DOUT
GND
2.5V REFERENCE
(MAX1240 ONLY)
MAX1240
MAX1241
5
GND
DIP/SO
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+2 .7 V, Lo w -P o w e r,
1 2 -Bit S e ria l ADCs in 8 -P in S O
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND .............................................................-0.3V to +6V
Operating Temperature Ranges
AIN to GND................................................-0.3V to (V + 0.3V)
MAX1240_C_A/MAX1241_C_A .........................0°C to +70°C
MAX1240_E_ A/MAX1241_E_ A.....................-40°C to +85°C
MAX1240_MJA/MAX1241_MJA ...................-55°C to +125°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10sec)............................+300°C
DD
REF to GND ...............................................-0.3V to (V + 0.3V)
DD
Digital Inputs to GND...............................................-0.3V to +6V
DOUT to GND............................................-0.3V to (V + 0.3V)
DD
DOUT Current..................................................................±25mA
Continuous Power Dissipation (T = +70°C)
A
Plastic DIP (derate 9.09mW/°C above +70°C) ...........727mW
SO (derate 5.88mW/°C above +70°C)........................471mW
CERDIP (derate 8.00mW/°C above +70°C)................640mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +2.7V to +3.6V (MAX1240); V = +2.7V to +5.25V (MAX1241); 73ksps, f
= 2.1MHz (50% duty cycle); MAX1240—4.7µF
CLK
DD
DD
S
capacitor at REF pin, MAX1241—external reference; V
= 2.500V applied to REF pin; T = T
to T ; unless otherwise noted.)
MAX
REF
A
MIN
0/MAX241
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
LSB
LSB
LSB
MAX124_A
±0.5
±1.0
±1
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
INL
MAX124_B/C
DNL
No missing codes over temperature
MAX124_A
±0.5
±0.5
±3.0
±4.0
±4.0
MAX124_B/C
Gain Error (Note 3)
±0.5
LSB
Gain Temperature Coefficient
±0.25
ppm/°C
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 73ksps, f
= 2.1MHz)
SCLK
MAX124_A/B
MAX124_C
70
80
Signal-to-Noise Plus
Distortion Ratio
SINAD
THD
dB
dB
dB
71.5
-88
MAX124_A/B
MAX124_C
-80
Total Harmonic Distortion
Up to the 5th harmonic
MAX124_A/B
MAX124_C
-3dB rolloff
Spurious-Free Dynamic Range
SFDR
88
2.25
1.0
Small-Signal Bandwidth
Full-Power Bandwidth
CONVERSION RATE
Conversion Time
MHz
MHz
t
5.5
7.5
1.5
73
µs
µs
CONV
Track/Hold Acquisition Time
Throughput Rate
t
ACQ
f
= 2.1MHz
ksps
ns
SCLK
Aperture Delay
t
Figure 8
30
APR
Aperture Jitter
<50
ps
ANALOG INPUT
Input Voltage Range
Input Capacitance
0
V
REF
V
16
pF
2
_______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r,
1 2 -Bit S e ria l ADCs in 8 -P in S O
0/MAX241
ELECTRICAL CHARACTERISTICS (continued)
(V = +2.7V to +3.6V (MAX1240); V = +2.7V to +5.25V (MAX1241); 73ksps, f
= 2.1MHz (50% duty cycle); MAX1240—4.7µF
CLK
DD
DD
S
capacitor at REF pin, MAX1241—external reference; V
= 2.500V applied to REF pin; T = T
to T ; unless otherwise noted.)
MAX
REF
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INTERNAL REFERENCE (MAX1240 only)
REF Output Voltage
T
A
= +25°C
2.480 2.500 2.520
30
V
REF Short-Circuit Current
mA
MAX1240AC/BC
MAX1240AE/BE
MAX1240AM/BM
MAX1240C
±30
±30
±30
±30
0.35
±50
±60
±80
REF Temperature Coefficient
ppm/°C
Load Regulation (Note 4)
Capacitive Bypass at REF
0mA to 0.2mA output load
4.7
µF
EXTERNAL REFERENCE (V
= 2.500V)
REF
V
50mV
+
DD
1.00
Input Voltage Range
V
Input Current
100
25
150
10
µA
kΩ
µA
µF
Input Resistance
18
REF Input Current in Shutdown
Capacitive Bypass at REF
±0.01
SHDN = 0V
0.1
DIGITAL INPUTS: SCLK, CS, SHDN
SCLK, CS Input High Voltage
SCLK, CS Input Low Voltage
V
≤ 3.6V
2.0
3.0
DD
V
V
IH
V
DD
> 3.6V (MAX1241)
V
IL
0.8
V
V
V
0.2
SCLK, CS Input Hysteresis
SCLK, CS Input Leakage
SCLK, CS Input Capacitance
SHDN Input High Voltage
SHDN Input Low Voltage
SHDN Input Current
HYST
I
IN
V
IN
= 0V or V
DD
±0.01
±1
15
µA
pF
V
C
(Note 5)
IN
V
V
- 0.4
SH
DD
V
0.4
V
SL
±4.0
µA
V
SHDN = 0V or V
DD
V
1.1
V
- 1.1
SHDN Input Mid Voltage
SHDN Voltage, Floating
SM
DD
V
V
DD
/2
V
SHDN = float
SHDN = float
FLT
SHDN Max Allowed Leakage,
Mid Input
±100
nA
V
DIGITAL OUTPUT: DOUT
I
= 5mA
0.4
0.8
SINK
Output Voltage Low
V
OL
I
= 16mA
SINK
Output Voltage High
V
OH
I
= 0.5mA
V - 0.5
DD
V
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
I
±0.01 ±10
15
µA
pF
CS = V
L
DD
C
CS = V (Note 5)
OUT
DD
_______________________________________________________________________________________
3
+2 .7 V, Lo w -P o w e r,
1 2 -Bit S e ria l ADCs in 8 -P in S O
ELECTRICAL CHARACTERISTICS (continued)
(V = +2.7V to +3.6V (MAX1240); V = +2.7V to +5.25V (MAX1241); 73ksps, f
= 2.1MHz (50% duty cycle); MAX1240—4.7µF
CLK
DD
DD
S
capacitor at REF pin, MAX1241—external reference; V
= 2.500V applied to REF pin; T = T
to T ; unless otherwise noted.)
MAX
REF
A
MIN
PARAMETERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
MAX1240
MAX1241
2.7
2.7
3.6
5.25
2.0
3.5
1.5
2.5
2.8
3.8
10
Supply Voltage
V
V
DD
MAX1240A/B
MAX1240C
= 3.6V
1.4
1.4
0.9
1.6
0.9
1.6
1.9
3.5
±0.3
V
DD
V
DD
= 3.6V
= 5.25V
= 3.6V
= 5.25V
= 3.6V
= 5.25V
Operating
mode
MAX1241A/B
MAX1241C
mA
V
DD
Supply Current
I
DD
V
DD
V
DD
V
DD
Power-down, digital inputs
at 0V or V
µA
DD
V
DD
15
0/MAX241
Supply Rejection
PSR
(Note 5)
mV
TIMING CHARACTERISTICS (Figure 8)
(V = +2.7V to +3.6V (MAX1240); V = +2.7V to +5.25V (MAX1241); T = T
to T , unless otherwise noted.)
MAX
DD
DD
A
MIN
PARAMETERS
SYMBOL
CONDITIONS
MIN
1.5
20
TYP
MAX
UNITS
Acquisition Time
t
µs
CS = V (Note 6)
ACQ
DD
MAX124_ _C/E
MAX124_ _M
200
240
240
240
2.1
Figure 1,
= 50pF
SCLK Fall to Output Data Valid
t
ns
DO
C
LOAD
20
t
Figure 1, C
Figure 2, C
= 50pF
= 50pF
ns
ns
CS Fall to Output Enable
CS Rise to Output Disable
SCLK Clock Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Low to CS Fall Setup Time
DOUT Rise to SCLK Rise (Note 5)
CS Pulse Width
DV
LOAD
LOAD
t
TR
f
0
MHz
ns
SCLK
t
200
200
50
CH
t
ns
CL
t
ns
CS0
t
0
ns
STR
t
CS
240
ns
Note 1: Tested at V = +2.7V.
DD
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3: MAX1240—internal reference, offset nulled; MAX1241—external reference (V
= +2.500V), offset nulled.
REF
Note 4: External load should not change during conversion for specified accuracy.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: Measured as [V (2.7V) - V (V
)].
FS
FS DD(MAX
Note 7: To guarantee acquisition time, t
is the maximum time the device takes to acquire the signal, and is also the minimum
ACQ
time needed for the signal to be acquired.
4
_______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r,
1 2 -Bit S e ria l ADCs in 8 -P in S O
0/MAX241
+2.7V
6k
DOUT
DOUT
6k
C
= 50pF
C
= 50pF
LOAD
LOAD
DGND
a) High-Z to V and V to V
DGND
b) High-Z to V and V to V
OL
OH
OL
OH
OL
OH
Figure 1. Load Circuits for DOUT Enable Time
+2.7V
6k
DOUT
DOUT
6k
C
= 50pF
C
= 50pF
LOAD
LOAD
DGND
DGND
a) V to High-Z
b) V to High-Z
OL
OH
Figure 2. Load Circuits for DOUT Disable Time
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = 3.0V, V
= 2.5V, f
= 2.1MHz, C = 20pF, T = +25°C, unless otherwise noted.)
DD
REF
SCLK
L
A
OPERATING SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OFFSET ERROR
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
2.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.3
1.2
1.1
1.0
R = ∞
CODE = 101010100000
L
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
MAX1240
MAX1240
MAX1241
MAX1241
= ∞
0.9
0.8
R
LOAD
CODE = 10101010000
-60 -20 20
TEMPERATURE (°C)
2
3
4
5
6
2.25 2.75 3.25 3.75 4.25 4.75 5.25
SUPPLY VOLTAGE (V)
60
100
140
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
5
+2 .7 V, Lo w -P o w e r,
1 2 -Bit S e ria l ADCs in 8 -P in S O
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = 3.0V, V
= 2.5V, f
= 2.1MHz, C = 20pF, T = +25°C, unless otherwise noted.)
DD
REF
SCLK
L
A
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
4.0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
DD
= 2.7V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-30
-55
-5 20 45 70 95 120 145
TEMPERATURE (°C)
2.25 2.75 3.25 3.75 4.25 4.75 5.25
-60
-20
20
60
100
140
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
0/MAX241
MAX1240
GAIN ERROR
vs. SUPPLY VOLTAGE
GAIN ERROR
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
2.5020
2.5015
2.5010
2.5005
2.5000
2.4995
2.4990
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
DD
= 2.7V
2.25 2.75 3.25 3.75 4.25 4.75 5.25
2.25 2.75 3.25 3.75 4.25 4.75 5.25
SUPPLY VOLTAGE (V)
-55 -30 -5 20 45 70 95 120 145
TEMPERATURE (°C)
V
(V)
DD
MAX1240
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
INTEGRAL NONLINEARITY
vs. TEMPERATURE
2.501
1.2
1.0
0.8
0.6
0.4
0.2
0
1.2
1.0
0.8
0.6
0.4
0.2
0
V
DD
= 2.7V
2.500
2.499
V
DD
= 3.6V
V
= 2.7V
DD
2.498
2.497
2.496
MAX1240
MAX1241
MAX1240
MAX1241
2.495
2.494
2.25 2.75 3.25 3.75 4.25 4.75 5.25
SUPPLY VOLTAGE (V)
-60
-20
20
60
100
140
-60 -40 -20
0
20 40 60 80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r,
1 2 -Bit S e ria l ADCs in 8 -P in S O
0/MAX241
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = 3.0V, REF = 2.5V, f
= 2.1MHz, C = 20pF, T = +25°C, unless otherwise noted.)
L A
DD
SCLK
INTEGRAL NONLINEARITY
vs. CODE
FFT PLOT
20
0
0.6
0.4
0.2
0
f
AIN
= 10kHz, 2.5Vp-p
f
= 73ksps
SAMPLE
-20
-40
-60
-80
-0.2
-100
-0.4
-0.6
-120
-140
0
18.75
37.50
0
1024
2048
3072
4096
CODE
FREQUENCY (kHz)
_______________________________________________________________________P in De s c rip t io n
PIN
1
NAME
FUNCTION
V
DD
Positive Supply Voltage: 2.7V to 3.6V, (MAX1240); 2.7 to 5.25V (MAX1241)
2
AIN
Sampling Analog Input, 0V to V
range
REF
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1240/MAX1241 down to 15µA (max)
supply current. Both the MAX1240 and MAX1241 are fully operational with either SHDN high or float-
ing. For the MAX1240, pulling SHDN high enables the internal reference, and letting SHDN float dis-
ables the internal reference and allows for the use of an external reference.
3
4
SHDN
Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output for MAX1240;
bypass with 4.7µF capacitor. External reference voltage input for MAX1241, or for MAX1240 with the
internal reference disabled. Bypass REF with a minimum of 0.1µF when using an external reference.
REF
5
6
GND
Analog and Digital Ground
Serial Data Output. Data changes state at SCLK’s falling edge. DOUT is high impedance when CS is
high.
DOUT
Active-Low Chip Select initiates conversions on the falling edge. When CS is high, DOUT is high
impedance.
7
8
CS
SCLK
Serial Clock Input. SCLK clocks data out at rates up to 2.1MHz.
_______________________________________________________________________________________
7
+2 .7 V, Lo w -P o w e r,
1 2 -Bit S e ria l ADCs in 8 -P in S O
+2.7V to +3.6V*
*V
DD,MAX
= +5.25V (MAX1241)
**4.7µF (MAX1240)
0.1µF (MAX1241)
12-BIT CAPACITIVE DAC
REF
4.7µF 0.1µF
COMPARATOR
1
2
8
C
HOLD
TRACK
V
SCLK
AIN
INPUT
ZERO
DD
-
+
7
SERIAL
INTERFACE
ANALOG INPUT
16pF
MAX1240
MAX1241
AIN
CS
HOLD
0V TO V
REF
9k
R
IN
C
3
4
6
5
SHUTDOWN
INPUT
SWITCH
SHDN
REF
DOUT
GND
HOLD
TRACK
AT THE SAMPLING INSTANT,
THE INPUT SWITCHES FROM
AIN TO GND.
REFERENCE
INPUT
(MAX1241 ONLY)
C**
GND
Figure 3. Operational Diagram
Figure 4. Equivalent Input Circuit
0/MAX241
switch opens and maintains a constant input to the
ADC’s SAR section.
_______________De t a ile d De s c rip t io n
Co n ve rt e r Op e ra t io n
The MAX1240/MAX1241 use an input track/hold (T/H)
and successive-approximation register (SAR) circuitry
to convert an analog input signal to a digital 12-bit out-
put. No external-hold capacitor is needed for the T/H.
Figure 3 shows the MAX1240/MAX1241 in its simplest
configuration. The MAX1240/MAX1241 convert input
signals in the 0V to VREF range in 9µs, including T/H
acquisition time. The MAX1240’s internal reference is
trimmed to 2.5V, while the MAX1241 requires an external
reference. Both devices accept voltages from 1.0V to
During acquisition, the analog input (AIN) charges
capacitor CHOLD. Bringing CS low ends the acquisition
interval. At this instant, the T/H switches the input side
of CHOLD to GND. The retained charge on CHOLD repre-
sents a sample of the input, unbalancing node ZERO at
the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0V within the limits of 12-
bit resolution. This action is equivalent to transferring a
charge from CHOLD to the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
s id e of CHOLD s witc he s b a c k to AIN, a nd CHOLD
charges to the input signal again.
V . The serial interface requires only three digital lines
DD
(SCLK, CS, and DOUT) and provides an easy interface
to microprocessors (µPs).
The MAX1240/MAX1241 have two modes: normal and
shutdown. Pulling SHDN low shuts the device down and
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
reduces supply current below 10µA (V ≤ 3.6V), while
DD
pulling SHDN high or leaving it open puts the device
into operational mode. Pulling CS low initiates a conver-
sion. The conversion result is available at DOUT in
unipolar serial format. The serial data stream consists
of a high bit, signaling the end of conversion (EOC), fol-
lowed by the data bits (MSB first).
(t
) is the maximum time the device takes to acquire
ACQ
the signal, and is also the minimum time needed for the
signal to be acquired. Acquisition time is calculated by:
An a lo g In p u t
Figure 4 illustrates the sampling architecture of the ana-
log-to-digital converter’s (ADC’s) comparator. The full-
scale input voltage is set by the voltage at REF.
tACQ = 9(RS + RIN) x 16pF
where RIN = 9kΩ, RS = the input signal’s source imped-
ance, and tACQ is never less than 1.5µs. Source imped-
ances below 1kΩ do not significantly affect the ADC’s
AC performance.
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
8
_______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r,
1 2 -Bit S e ria l ADCs in 8 -P in S O
0/MAX241
Higher source impedances can be used if a 0.01µF
down (see the section Using SHDN to Reduce Supply
Current). The internal reference is enabled by pulling the
SHDN pin high. Letting SHDN float disables the internal
reference, which allows the use of an external reference,
as described in the External Reference section.
capacitor is connected to the analog input. Note that
the input capacitor forms an RC filter with the input
sourc e imp e d a nc e , limiting the ADC’s inp ut signa l
bandwidth.
External Reference
The MAX1240/MAX1241 operate with an external refer-
ence at the REF pin. To use the MAX1240 with an
external reference, disable the internal reference by let-
ting SHDN float. Stay within the +1.0V to VDD voltage
range to achieve specified accuracy. The minimum
input impedance is 18kΩ for DC currents. During con-
version, the external reference must be able to deliver
up to 250µA of DC load current and have an output
impedance of 10Ω or less. The recommended mini-
mum value for the bypass capacitor is 0.1µF. If the ref-
e re nc e ha s hig he r outp ut imp e d a nc e or is nois y,
bypass it close to the REF pin with a 4.7µF capacitor.
Input Bandwidth
The ADCs’ input tracking circuitry has a 2.25MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to V
and GND, allow the input to swing from
DD
GND - 0.3V to VDD + 0.3V without damage. However,
for accurate conversions near full scale, the input must
not exceed VDD by more than 50mV, or be lower than
GND by 50mV.
____________________S e ria l In t e rfa c e
In it ia liza t io n a ft e r P o w e r-Up a n d
S t a rt in g a Co n ve rs io n
If the analog input exceeds 50mV beyond the sup-
plies, limit the input current to 2mA.
When power is first applied, and if SHDN is not pulled
low, it ta ke s the fully d is c ha rg e d 4.7µF re fe re nc e
bypass capacitor up to 20ms to provide adequate
charge for specified accuracy. With an external refer-
ence, the internal reset time is 10µs after the power
supplies have stabilized. No conversions should be
performed during these times.
Internal Reference (MAX1240)
The MAX1240 ha s a n on-c hip volta g e re fe re nc e
trimmed to 2.5V. The internal reference output is con-
nected to REF and also drives the internal capacitive
DAC. The output can be used as a reference voltage
source for other components and can source up to
400µA. Bypass REF with a 4.7µF capacitor. Larger
capacitors increase wake-up time when exiting shut-
To start a conversion, pull CS low. At CS’s falling edge,
the T/H enters its hold mode and a conversion is initiat-
COMPLETE CONVERSION SEQUENCE
CS
t
WAKE
SHDN
DOUT
CONVERSION 0
POWERED UP
CONVERSION 1
POWERED UP
POWERED DOWN
Figure 5. Shutdown Sequence
_______________________________________________________________________________________
9
+2 .7 V, Lo w -P o w e r,
1 2 -Bit S e ria l ADCs in 8 -P in S O
ed. After an internally timed conversion period, the end
of conversion is signaled by DOUT pulling high. Data
can then be shifted out serially with the external clock.
10
1
V
R
LOAD
= V = 3.0V
DD REF
= ∞, C
= 50pF
LOAD
CODE = 010101010000
Us in g SHDN t o Re d u c e S u p p ly Cu rre n t
Power consumption can be reduced significantly by
shutting down the MAX1240/MAX1241 between con-
versions. Figure 6 shows a plot of average supply cur-
rent versus conversion rate. Because the MAX1241
uses an external reference voltage (assumed to be pre-
sent continuously), it “wakes up” from shutdown more
quickly (in 4µs) and therefore provides lower average
0.1
0.01
MAX1240
MAX1241
1k
supply currents. The wake-up time (t
) is the time
WAKE
0.001
from when SHDN is deasserted to the time when a con-
version may be initiated (Figure 5). For the MAX1240,
this time depends on the time in shutdown (Figure 7)
because the external 4.7µF reference bypass capacitor
loses charge slowly during shutdown.
0.1
1
10
100
10k 100k
CONVERSION RATE (Hz)
Figure 6. Average Supply Current vs. Conversion Rate
0/MAX241
Ex t e rn a l Clo c k
The actual conversion does not require the external
clock. This allows the conversion result to be read back
at the µP’s convenience at any clock rate from up to
2.1MHz. The clock duty cycle is unrestricted if each
clock phase is at least 200ns. Do not run the clock
while a conversion is in progress.
1.0
0.8
0.6
0.4
0.2
0.0
Tim in g a n d Co n t ro l
Conversion-start and data-read operations are controlled
by the CS and SCLK digital inputs. The timing diagrams
of Figures 8 and 9 outline serial-interface operation.
A
CS falling edge initiates a conversion sequence: the
T/H stage holds the input voltage, the ADC begins to
convert, and DOUT changes from high impedance to
logic low. SCLK must be kept low during the conver-
sion. An internal register stores the data when the con-
version is in progress.
0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (sec)
Figure 7. Typical Reference Power-Up Delay vs. Time in
Shutdown
CS
1
4
8
12
16
SCLK
DOUT
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
EOC
EOC
CONVERSION
IN PROGRESS
TRAILING
ZEROS
CLOCK OUT SERIAL DATA
TRACK
INTERFACE IDLE
TRACK/HOLD
IDLE
HOLD
HOLD
TRACK
STATE
0.24µs
(t
12.5 × 0.476µs = 5.95µs
TOTAL = 13.7µs
0µs
7.5µs (t
)
0µs
CONV
)
CS
CYCLE TIME
Figure 8. Interface Timing Sequence
10 ______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r,
1 2 -Bit S e ria l ADCs in 8 -P in S O
0/MAX241
t
CS
CS
…
…
t
CS0
t
CH
SCLK
DOUT
t
DO
t
CL
t
TR
t
DV
t
CONV
…
…
B2
B1
B0
t
APR
t
STR
(TRACK/ACQUIRE)
(HOLD)
(TRACK/ACQUIRE)
INTERNAL
T/H
Figure 9. Detailed Serial-Interface Timing
End of conversion (EOC) is signaled by DOUT going
high. DOUT’s rising edge can be used as a framing
signal. SCLK shifts the data out of this register any time
after the conversion is complete. DOUT transitions on
SCLK’s falling edge. The next falling clock edge pro-
duces the MSB of the conversion at DOUT, followed by
the remaining bits. Since there are 12 data bits and one
leading high bit, at least 13 falling clock edges are
needed to shift out these bits. Extra clock pulses occur-
ring after the conversion result has been clocked out,
and prior to a rising edge of CS, produce trailing zeros
at DOUT and have no effect on converter operation.
ing the conversion’s LSB. After the specified minimum
time (t ), CS can be pulled low again to initiate the
CS
next conversion.
Ou t p u t Co d in g a n d Tra n s fe r Fu n c t io n
The data output from the MAX1240/MAX1241 is binary,
and Figure 10 depicts the nominal transfer function.
Code transitions occur halfway between successive-
integer LSB values. If VREF = +2.500V, then 1 LSB =
610µV or 2.500V/4096.
____________Ap p lic a t io n s In fo rm a t io n
Co n n e c t io n t o S t a n d a rd In t e rfa c e s
The MAX1240/MAX1241 serial interface is fully compat-
ible with SPI/QSPI and MICROWIRE standard serial
interfaces (Figure 11).
Minimum cycle time is accomplished by using DOUT’s
rising edge as the EOC signal. Clock out the data with
12.5 clock cycles at full speed. Pull CS high after read-
If a serial interface is available, set the CPU’s serial
interface in master mode so the CPU generates the ser-
ial clock. Choose a clock frequency up to 2.1MHz.
OUTPUT CODE
FULL-SCALE
TRANSITION
11…111
1) Use a general-purpose I/O line on the CPU to pull CS
11…110
11…101
low. Keep SCLK low.
2) Wait the for the maximum conversion time specified
before activating SCLK. Alternatively, look for a DOUT
rising edge to determine the end of conversion.
FS = V - 1LSB
REF
V
REF
1LSB =
3) Activate SCLK for a minimum of 13 clock cycles. The
first falling clock edge produces the MSB of the
DOUT conversion. DOUT output data transitions on
SCLK’s falling edge and is available in MSB-first for-
mat. Observe the SCLK to DOUT valid timing char-
a c te ris tic . Da ta c a n b e c loc ke d into the µP on
SCLK’s rising edge.
4096
00…011
00…010
00…001
00…000
0
1
2
3
FS
4) Pull CS high at or after the 13th falling clock edge. If
CS remains low, trailing zeros are clocked out after
the LSB.
INPUT VOLTAGE (LSBs)
FS - 3/2LSB
Figure 10. Unipolar Transfer Function, Full Scale (FS) = V
-
REF
1LSB, Zero Scale (ZS) = GND
______________________________________________________________________________________ 11
+2 .7 V, Lo w -P o w e r,
1 2 -Bit S e ria l ADCs in 8 -P in S O
5) With CS = high, wait the minimum specified time, tCS,
before initiating a new conversion by pulling CS low.
If a conversion is aborted by pulling CS high before
the conversion’s end, wait for the minimum acquisi-
I/O
SCK
CS
SCLK
DOUT
MISO
tion time, t
, before starting a new conversion.
ACQ
+3V
CS must be held low until all data bits are clocked out.
Data can be output in two bytes or continuously, as
shown in Figure 8. The bytes contain the result of the
conversion padded with one leading 1, and trailing 0s.
MAX1240
MAX1241
SS
a) SPI
SPI a nd MICROWIRE
When using SPI or MICROWIRE, set CPOL = 0 and
CPHA = 0. Conversion begins with a CS falling edge.
DOUT goes low, indicating a conversion in progress. Wait
until DOUT goes high or until the maximum specified
7.5µs conversion time elapses. Two consecutive 1-byte
reads are required to get the full 12 bits from the ADC.
DOUT output data transitions on SCLK’s falling edge and
is clocked into the µP on SCLK’s rising edge.
CS
SCK
CS
SCLK
DOUT
MISO
+3V
MAX1240
MAX1241
SS
0/MAX241
b) QSPI
The first byte contains a leading 1, and seven bits of con-
version result. The second byte contains the remaining
five bits and three trailing zeros. See Figure 11 for con-
nections and Figure 12 for timing.
I/O
SK
SI
CS
SCLK
DOUT
QSPI
Set CPOL = CPHA = 0. Unlike SPI, which requires two
1-byte reads to acquire the 12 bits of data from the ADC,
QSPI allows the minimum number of clock cycles neces-
s a ry to c loc k in the d a ta . The MAX1240/MAX1241
requires 13 clock cycles from the µP to clock out the 12
bits of data with no trailing zeros (Figure 13). The maxi-
mum clock frequency to ensure compatibility with QSPI is
2.097MHz.
MAX1240
MAX1241
c) MICROWIRE
Figure 11. Common Serial-Interface Connections to the
MAX1241
La yout, Grounding, a nd Bypa s s ing
For best performance, use printed circuit boards. Wire-
wrap boards are not recommended. Board layout should
ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital (especially
clock) lines parallel to one another, or digital lines under-
neath the ADC package.
the ADC’s high-speed comparator. Bypass this supply to
the single-point analog ground with 0.1µF and 4.7µF
bypass capacitors. Minimize capacitor lead lengths for
best supply-noise rejection. If the power supply is very
noisy, a 10Ω resistor can be connected as a lowpass filter
to attenuate supply noise (Figure 14).
Figure 14 shows the recommended system ground con-
nections. Establish a single-point analog ground (“star”
ground point) at GND, separate from the logic ground.
Connect all other analog grounds and DGND to this star
ground point for further noise reduction. No other digital
system ground should be connected to this single-point
analog ground. The ground return to the power supply for
this ground should be low impedance and as short as
possible for noise-free operation.
High-frequency noise in the VDD power supply may affect
12 ______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r,
1 2 -Bit S e ria l ADCs in 8 -P in S O
0/MAX241
1ST BYTE READ
2ND BYTE READ
SCLK
CS
t
CONV
HIGH-Z
D11 D10 D9
MSB
D8
D7
D6
D5
D4
D3
D2
D1
D0
DOUT*
LSB
EOC
*WHEN CS IS HIGH, DOUT = HIGH -Z
Figure 12. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0)
SCLK
CS
t
CONV
HIGH-Z
D11 D10 D9
MSB
D8
D7
D6
D5
D4
D3
D2
D1
D0
DOUT*
LSB
EOC
*WHEN CS IS HIGH, DOUT = HIGH -Z
Figure 13. QSPI Serial Interface Timing (CPOL = CPHA = 0)
SUPPLIES
+3V
+3V
GND
R* = 10Ω
4.7µF
0.1µF
V
GND
+3V DGND
DD
DIGITAL
CIRCUITRY
MAX1240
MAX1241
*OPTIONAL
Figure 14. Power-Supply Grounding Condition
______________________________________________________________________________________ 13
+2 .7 V, Lo w -P o w e r,
1 2 -Bit S e ria l ADCs in 8 -P in S O
__Ord e rin g In fo rm a t io n (c o n t in u e d )
PIN-
PACKAGE
INL
(LSB)
PART
TEMP. RANGE
MAX1240AEPA -40°C to +85°C
MAX1240BEPA -40°C to +85°C
MAX1240CEPA -40°C to +85°C
MAX1240AESA -40°C to +85°C
MAX1240BESA -40°C to +85°C
MAX1240CESA -40°C to +85°C
8 Plastic DIP
8 Plastic DIP
8 Plastic DIP
8 SO
±1/2
±1
±1
±1/2
8 SO
±1
8 SO
±1
MAX1240AMJA -55°C to +125°C 8 CERDIP**
MAX1240BMJA -55°C to +125°C 8 CERDIP**
MAX1240CMJA -55°C to +125°C 8 CERDIP**
±1/2
±1
±1
MAX1241ACPA
MAX1241BCPA
MAX1241CCPA
MAX1241ACSA
MAX1241BCSA
MAX1241CCSA
MAX1241BC/D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
8 Plastic DIP
8 Plastic DIP
8 Plastic DIP
8 SO
±1/2
±1
±1
±1/2
0/MAX241
8 SO
±1
8 SO
±1
Dice*
±1
MAX1241AEPA -40°C to +85°C
MAX1241BEPA -40°C to +85°C
MAX1241CEPA -40°C to +85°C
MAX1241AESA -40°C to +85°C
MAX1241BESA -40°C to +85°C
MAX1241CESA -40°C to +85°C
8 Plastic DIP
8 Plastic DIP
8 Plastic DIP
8 SO
±1/2
±1
±1
±1/2
8 SO
±1
8 SO
±1
MAX1241AMJA -55°C to +125°C 8 CERDIP**
MAX1241BMJA -55°C to +125°C 8 CERDIP**
MAX1241CMJA -55°C to +125°C 8 CERDIP**
±1/2
±1
±1
* Dice are specified at T = +25°C, DC parameters only.
A
** Contact factory for availability and processing to MIL-STD-883.
___________________Ch ip In fo rm a t io n
TRANSISTOR COUNT: 2558
SUBSTRATE CONNECTED TO GND
14 ______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r,
1 2 -Bit S e ria l ADCs in 8 -P in S O
0/MAX241
________________________________________________________P a c k a g e In fo rm a t io n
______________________________________________________________________________________ 15
+2 .7 V, Lo w -P o w e r,
1 2 -Bit S e ria l ADCs in 8 -P in S O
___________________________________________P a c k a g e In fo rm a t io n (c o n t in u e d )
0/MAX241
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1998 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX1240BCSA+T
ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial Access, CMOS, PDSO8, 0.150 INCH, LEAD FREE, SOIC-8
MAXIM
MAX1240BCSA-T
ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial Access, CMOS, PDSO8, 0.150 INCH, SOIC-8
MAXIM
MAX1240BESA+T
ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial Access, CMOS, PDSO8, 0.150 INCH, LEAD FREE, SOIC-8
MAXIM
©2020 ICPDF网 联系我们和版权申明