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MAX1236EUA-T [MAXIM]

ADC, Successive Approximation, 12-Bit, 1 Func, 4 Channel, Serial Access, BICMOS, PDSO8, MICRO MAX PACKAGE-8;
MAX1236EUA-T
型号： MAX1236EUA-T
厂家： MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述：

ADC, Successive Approximation, 12-Bit, 1 Func, 4 Channel, Serial Access, BICMOS, PDSO8, MICRO MAX PACKAGE-8
文件： 总22页 (文件大小：405K)
中文：  中文翻译
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19-2333; Rev 2; 2/03  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
General Description  
Features  
o High-Speed I C-Compatible Serial Interface  
400kHz Fast Mode  
2
The MAX1236–MAX1239 low-power, 12-bit, multichan-  
nel analog-to-digital converters (ADCs) feature internal  
track/hold (T/H), voltage reference, clock, and an  
1.7MHz High-Speed Mode  
2
I C-compatible 2-wire serial interface. These devices  
o Single-Supply  
operate from a single supply of 2.7V to 3.6V (MAX1237/  
MAX1239) or 4.5V to 5.5V (MAX1236/MAX1238) and  
require only 670µA at the maximum sampling rate of  
94.4ksps. Supply current falls below 230µA for sam-  
pling rates under 46ksps. AutoShutdown™ powers  
down the devices between conversions, reducing sup-  
ply current to less than 1µA at low throughput rates.  
The MAX1236/MAX1237 have four analog input chan-  
nels each, while the MAX1238/MAX1239 have 12 ana-  
log input channels each. The fully differential analog  
inputs are software configurable for unipolar or bipolar,  
and single-ended or differential operation.  
2.7V to 3.6V (MAX1237/MAX1239)  
4.5V to 5.5V (MAX1236/MAX1238)  
o Internal Reference  
2.048V (MAX1237/MAX1239)  
4.096V (MAX1236/MAX1238)  
o External Reference: 1V to V  
o Internal Clock  
DD  
o 4-Channel Single-Ended or 2-Channel Fully  
Differential (MAX1236/MAX1237)  
o 12-Channel Single-Ended or 6-Channel Fully  
The full-scale analog input range is determined by the  
internal reference or by an externally applied reference  
voltage ranging from 1V to V . The MAX1237/  
DD  
Differential (MAX1238/MAX1239)  
o Internal FIFO with Channel-Scan Mode  
MAX1239 feature a 2.048V internal reference and the  
MAX1236/MAX1238 feature a 4.096V internal reference.  
o Low Power  
670µA at 94.4ksps  
230µA at 40ksps  
60µA at 10ksps  
6µA at 1ksps  
0.5µA in Power-Down Mode  
The MAX1236/MAX1237 are available in an 8-pin µMAX  
package. The MAX1238/MAX1239 are available in a 16-  
pin QSOP package. The MAX1236–MAX1239 are guar-  
anteed over the extended temperature range  
(-40°C to +85°C). For pin-compatible 10-bit parts, refer to  
the MAX1136–MAX1139 data sheet. For pin-compatible  
8-bit parts, refer to the MAX1036–MAX1039 data sheet.  
o Software-Configurable Unipolar/Bipolar  
o Small Packages  
8-Pin µMAX (MAX1236/MAX1237)  
16-Pin QSOP (MAX1238/MAX1239)  
Applications  
Hand-Held Portable Applications  
Medical Instruments  
Ordering Information  
Battery-Powered Test Equipment  
Solar-Powered Remote Systems  
Received-Signal-Strength Indicators  
System Supervision  
TEMP  
RANGE  
PIN-  
PACKAGE ADDRESS (LSB)  
I2C SLAVE INL  
PART  
MAX1236EUA -40°C to +85°C 8 µMAX  
MAX1236KEUA* -40°C to +85°C 8 µMAX  
MAX1236LEUA* -40°C to +85°C 8 µMAX  
MAX1236MEUA* -40°C to +85°C 8 µMAX  
MAX1237EUA -40°C to +85°C 8 µMAX  
MAX1237KEUA* -40°C to +85°C 8 µMAX  
MAX1237LEUA* -40°C to +85°C 8 µMAX  
MAX1237MEUA* -40°C to +85°C 8 µMAX  
*Future product—contact factory for availability.  
0110100  
0110000  
0110010  
0110110  
0110100  
0110000  
0110010  
0110110  
1
1
1
1
1
1
1
1
Selector Guide  
INTERNAL  
REFERENCE  
(V)  
INPUT  
CHANNELS  
SUPPLY  
VOLTAGE (V)  
PART  
MAX1236EUA  
MAX1237EUA  
MAX1238EEE  
MAX1239EEE  
4
4
4.096  
2.048  
4.096  
2.048  
4.5 to 5.5  
2.7 to 3.6  
4.5 to 5.5  
2.7 to 3.6  
12  
12  
Ordering Information continued at end of data sheet.  
Pin Configurations appear at end of data sheet.  
Typical Operating Circuit appears at end of data sheet.  
AutoShutdown is a trademark of Maxim Integrated Products, Inc.  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
ABSOLUTE MAXIMUM RATINGS  
DD  
AIN0–AIN11,  
V
to GND..............................................................-0.3V to +6V  
Operating Temperature Range ...........................-40°C to +85°C  
Junction Temperature......................................................+150°C  
Storage Temperature Range.............................-60°C to +150°C  
Lead Temperature (soldering, 10s) .................................+300°C  
REF to GND............-0.3V to the lower of (V  
+ 0.3V) and 6V  
DD  
SDA, SCL to GND.....................................................-0.3V to +6V  
Maximum Current Into Any Pin......................................... 50mA  
Continuous Power Dissipation (T = +70°C)  
A
8-Pin µMAX (derate 4.5mW/°C above +70°C).............362mW  
16-Pin QSOP (derate 8.3mW/°C above +70°C)........666.7mW  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect device reliability.  
ELECTRICAL CHARACTERISTICS  
(V  
= 2.7V to 3.6V (MAX1237/MAX1239), V  
= 4.5V to 5.5V (MAX1236/MAX1238), V  
= 2.048V (MAX1237/MAX1239), V  
=
DD  
DD  
REF  
REF  
4.096V (MAX1236/MAX1238), C  
= 0.1µF, f  
= 1.7MHz, T = T  
to T  
, unless otherwise noted. Typical values are at  
REF  
SCL  
A
MIN  
MAX  
T
A
= +25°C, see Tables 1–5 for programming notation.)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
DC ACCURACY (Note 1)  
Resolution  
12  
Bits  
LSB  
LSB  
LSB  
Relative Accuracy  
Differential Nonlinearity  
Offset Error  
INL  
(Note 2)  
1
1
4
DNL  
No missing codes over temperature  
Offset-Error Temperature  
Coefficient  
Relative to FSR  
0.3  
ppm/°C  
Gain Error  
(Note 3)  
4
LSB  
Gain-Temperature Coefficient  
Relative to FSR  
0.3  
0.1  
ppm/°C  
Channel-to-Channel Offset  
Matching  
LSB  
LSB  
Channel-to-Channel Gain  
Matching  
0.1  
DYNAMIC PERFORMANCE (f  
Signal-to-Noise Plus Distortion  
Total Harmonic Distortion  
Spurious-Free Dynamic Range  
Full-Power Bandwidth  
= 10kHz, V  
= V  
, f  
= 94.4ksps)  
IN(SINE-WAVE)  
IN(P-P)  
REF SAMPLE  
SINAD  
70  
-78  
78  
3
dB  
dB  
THD  
Up to the 5th harmonic  
SFDR  
dB  
SINAD > 68dB  
-3dB point  
MHz  
MHz  
Full-Linear Bandwidth  
5
CONVERSION RATE  
Internal clock  
External clock  
7.5  
Conversion Time (Note 4)  
t
µs  
CONV  
10.6  
2
_______________________________________________________________________________________  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
ELECTRICAL CHARACTERISTICS (continued)  
(V  
= 2.7V to 3.6V (MAX1237/MAX1239), V  
= 4.5V to 5.5V (MAX1236/MAX1238), V  
= 2.048V (MAX1237/MAX1239), V  
=
DD  
DD  
REF  
REF  
4.096V (MAX1236/MAX1238), C  
= 0.1µF, f  
= 1.7MHz, T = T  
to T  
, unless otherwise noted. Typical values are at  
REF  
SCL  
A
MIN  
MAX  
T
A
= +25°C, see Tables 1–5 for programming notation.)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Internal clock, SCAN[1:0] = 01  
51  
Internal clock, SCAN[1:0] = 00  
CS[3:0] = 1011 (MAX1238/MAX1239)  
Throughput Rate  
f
ksps  
51  
SAMPLE  
External clock  
94.4  
Track/Hold Acquisition Time  
Internal Clock Frequency  
800  
ns  
2.8  
60  
30  
MHz  
External clock, fast mode  
Aperture Delay (Note 5)  
t
ns  
AD  
External clock, high-speed mode  
ANALOG INPUT (AIN0–AIN11)  
Unipolar  
Bipolar  
0
0
V
REF  
Input-Voltage Range, Single-  
Ended and Differential (Note 6)  
V
V
/2  
REF  
1
Input Multiplexer Leakage Current  
Input Capacitance  
ON/OFF leakage current, V _ = 0 or V  
AIN  
0.01  
22  
µA  
pF  
DD  
C
IN  
INTERNAL REFERENCE (Note 7)  
MAX1237/MAX1239  
1.968  
3.936  
2.048  
4.096  
2.128  
4.256  
Reference Voltage  
V
T
= +25°C  
A
V
REF  
MAX1236/MAX1238  
Reference-Voltage Temperature  
Coefficient  
TCV  
25  
ppm/°C  
REF  
REF Short-Circuit Current  
REF Source Impedance  
EXTERNAL REFERENCE  
REF Input-Voltage Range  
REF Input Current  
2
mA  
1.5  
kΩ  
V
(Note 8)  
1
V
V
REF  
DD  
I
f
= 94.4ksps  
SAMPLE  
40  
µA  
REF  
DIGITAL INPUTS/OUTPUTS (SCL, SDA)  
✕
Input-High Voltage  
Input-Low Voltage  
Input Hysteresis  
Input Current  
V
0.7  
V
V
V
V
IH  
DD  
DD  
✕
V
0.3  
V
DD  
IL  
✕
V
0.1  
V
HYST  
I
V
= 0 to V  
DD  
10  
µA  
pF  
V
IN  
IN  
Input Capacitance  
Output Low Voltage  
C
15  
IN  
V
I
= 3mA  
0.4  
OL  
SINK  
_______________________________________________________________________________________  
3
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
ELECTRICAL CHARACTERISTICS (continued)  
(V  
= 2.7V to 3.6V (MAX1237/MAX1239), V  
= 4.5V to 5.5V (MAX1236/MAX1238), V  
= 2.048V (MAX1237/MAX1239), V  
=
DD  
DD  
REF  
REF  
4.096V (MAX1236/MAX1238), C  
= 0.1µF, f  
= 1.7MHz, T = T  
to T  
, unless otherwise noted. Typical values are at  
REF  
SCL  
A
MIN  
MAX  
T
A
= +25°C, see Tables 1–5 for programming notation.)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
POWER REQUIREMENTS  
MAX1237/MAX1239  
MAX1236/MAX1238  
= 94.4ksps  
2.7  
4.5  
3.6  
5.5  
Supply Voltage  
V
V
DD  
Internal reference  
External reference  
Internal reference  
External reference  
Internal reference  
External reference  
Internal reference  
External reference  
900  
670  
530  
230  
380  
60  
1150  
900  
f
SAMPLE  
external clock  
f
= 40ksps  
SAMPLE  
internal clock  
Supply Current  
I
µA  
DD  
f
SAMPLE  
= 10ksps  
internal clock  
330  
6
f
=1ksps  
SAMPLE  
internal clock  
Shutdown (internal REF off)  
Full-scale input (Note 9)  
0.5  
0.5  
10  
Power-Supply Rejection Ratio  
PSRR  
0.2  
LSB/V  
TIMING CHARACTERISTICS (Figure 1)  
(V  
= 2.7V to 3.6V (MAX1237/MAX1239), V  
= 4.5V to 5.5V (MAX1236/MAX1238), V  
= 2.048V (MAX1237/MAX1239), V  
=
DD  
DD  
REF  
REF  
4.096V (MAX1236/MAX1238), C  
= 0.1µF, f  
= 1.7MHz, T = T  
to T  
, unless otherwise noted. Typical values are at  
REF  
SCL  
A
MIN  
MAX  
T
A
= +25°C, see Tables 1–5 for programming notation.)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
TIMING CHARACTERISTICS FOR FAST MODE  
Serial-Clock Frequency  
f
400  
kHz  
µs  
SCL  
Bus Free Time Between a STOP (P)  
and a START (S) Condition  
t
1.3  
BUF  
Hold Time for START (S) Condition  
Low Period of the SCL Clock  
High Period of the SCL Clock  
t
t
0.6  
1.3  
0.6  
µs  
µs  
µs  
HD, STA  
t
LOW  
t
HIGH  
Setup Time for a Repeated START  
Condition (Sr)  
0.6  
µs  
SU, STA  
Data Hold Time (Note 10)  
Data Setup Time  
t
0
900  
ns  
ns  
HD, DAT  
t
100  
SU, DAT  
Rise Time of Both SDA and SCL  
Signals, Receiving  
t
Measured from 0.3V  
Measured from 0.3V  
- 0.7V  
- 0.7V  
20 + 0.1C  
300  
300  
ns  
R
DD  
DD  
DD  
B
B
Fall Time of SDA Transmitting  
t
20 + 0.1C  
0.6  
ns  
µs  
pF  
ns  
F
DD  
Setup Time for STOP (P) Condition  
Capacitive Load for Each Bus Line  
Pulse Width of Spike Suppressed  
t
SU, STO  
C
400  
50  
B
t
SP  
4
_______________________________________________________________________________________  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
TIMING CHARACTERISTICS (Figure 1) (continued)  
(V  
= 2.7V to 3.6V (MAX1237/MAX1239), V  
= 4.5V to 5.5V (MAX1236/MAX1238), V  
= 2.048V (MAX1237/MAX1239), V  
=
DD  
DD  
REF  
REF  
4.096V (MAX1236/MAX1238), C  
= 0.1µF, f  
= 1.7MHz, T = T  
to T  
, unless otherwise noted. Typical values are at  
REF  
SCL  
A
MIN  
MAX  
T
A
= +25°C, see Tables 1–5 for programming notation.)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C = 400pF, Note 11)  
B
Serial Clock Frequency  
f
(Note 12)  
1.7  
MHz  
ns  
SCLH  
Hold Time, Repeated START  
Condition (Sr)  
t
160  
HD, STA  
Low Period of the SCL Clock  
High Period of the SCL Clock  
t
320  
120  
ns  
ns  
LOW  
t
HIGH  
Setup Time for a Repeated START  
Condition (Sr)  
t
,
160  
ns  
SU STA  
Data Hold Time  
Data Setup Time  
t
,
(Note 10)  
0
150  
ns  
ns  
HD DAT  
t
,
10  
SU DAT  
Rise Time of SCL Signal  
(Current Source Enabled)  
t
20  
20  
80  
ns  
ns  
RCL  
Rise Time of SCL Signal after  
Acknowledge Bit  
t
Measured from 0.3V  
- 0.7V  
160  
RCL1  
DD  
DD  
Fall Time of SCL Signal  
t
Measured from 0.3V  
Measured from 0.3V  
Measured from 0.3V  
- 0.7V  
- 0.7V  
- 0.7V  
20  
20  
80  
ns  
ns  
ns  
ns  
pF  
ns  
FCL  
DD  
DD  
DD  
DD  
DD  
DD  
Rise Time of SDA Signal  
t
160  
160  
RDA  
Fall Time of SDA Signal  
t
20  
FDA  
Setup Time for STOP (P) Condition  
Capacitive Load for Each Bus Line  
Pulse Width of Spike Suppressed  
t
,
160  
SU STO  
C
400  
10  
B
t
(Notes 10 and 12)  
0
SP  
Note 1: For DC accuracy, the MAX1136/MAX1138 are tested at V  
= 5V and the MAX1137/MAX1139 are tested at V  
= 3V. All  
DD  
DD  
devices are configured for unipolar, single-ended inputs.  
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and  
offsets have been calibrated.  
Note 3: Offset nulled.  
Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion  
time does not include acquisition time. SCL is the conversion clock in the external clock mode.  
Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.  
Note 6: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to V  
.
DD  
Note 7: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11) decouple AIN_/REF to GND with a  
0.01µF capacitor.  
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µV  
.
P-P  
Note 9: Measured as for the MAX1237/MAX1239  
2N − 1  
V
(3.6V)− V (2.7V) ×  
[
]
FS  
FS  
V
REF   
(3.6V − 2.7V)  
_______________________________________________________________________________________  
5
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
TIMING CHARACTERISTICS (Figure 1) (continued)  
(V  
= 2.7V to 3.6V (MAX1237/MAX1239), V  
= 4.5V to 5.5V (MAX1236/MAX1238), V  
= 2.048V (MAX1237/MAX1239), V  
=
DD  
DD  
REF  
REF  
4.096V (MAX1236/MAX1238), C  
= 0.1µF, f  
= 1.7MHz, T = T  
to T  
, unless otherwise noted. Typical values are at  
REF  
SCL  
A
MIN  
MAX  
T
A
= +25°C, see Tables 1–5 for programming notation.)  
and for the MAX1236/MAX1238 where N is the number of bits and V  
.
REF  
2N − 1  
V
(5.5V)− V (4.5V) ×  
[
]
FS  
FS  
V
REF   
(5.5V − 4.5V)  
Note 10: A master device must provide a data hold time for SDA (referred to V of SCL) in order to bridge the undefined region of  
IL  
SCL’s falling edge (see Figure 1).  
Note 11: C = total capacitance of one bus line in pF.  
B
Note 12: f  
must meet the minimum clock low time plus the rise/fall times.  
SCL  
Typical Operating Characteristics  
(V  
= 3.3V (MAX1237/MAX1239), V  
= 5V (MAX1236/MAX1238), f  
= 1.7MHz, (50% duty cycle), f  
= 94.4ksps, single-  
DD  
DD  
SCL  
SAMPLE  
ended, unipolar, T = +25°C, unless otherwise noted.)  
A
DIFFERENTIAL NONLINEARITY  
vs. DIGITAL CODE  
INTEGRAL NONLINEARITY  
vs. DIGITAL CODE  
FFT PLOT  
1.0  
-60  
0.5  
f
f
= 94.4ksps  
SAMPLE  
0.8  
0.6  
0.4  
0.3  
= 10kHz  
IN  
-80  
-100  
-120  
-140  
-160  
-180  
0.2  
0.1  
0.4  
0.2  
0
0
0.1  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.2  
-0.3  
-0.4  
-0.5  
0
500 1000 1500 2000 2500 3000 3500 4000  
DIGITAL OUTPUT CODE  
500 1000 1500  
3000 3500  
4000  
0
10k  
20k  
30k  
40k  
50k  
0
2000 2500  
FREQUENCY (Hz)  
DIGITAL OUTPUT CODE  
SHUTDOWN SUPPLY CURRENT  
vs. TEMPERATURE  
SUPPLY CURRENT vs. TEMPERATURE  
(MAX1238/MAX1239)  
SHUTDOWN SUPPLY CURRENT  
vs. SUPPLY VOLTAGE  
800  
750  
700  
650  
600  
550  
500  
450  
400  
350  
300  
0.50  
0.45  
0.40  
0.35  
0.30  
0.25  
0.20  
0.15  
0.10  
0.05  
0
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
SDA = SCL = V  
DD  
INTERNAL REFERENCE MAX1238/MAX1236  
MAX1238  
SETUP BYTE  
EXT REF: 10111011  
INT REF: 11011011  
INTERNAL REFERENCE MAX1239/MAX1237  
EXTERNAL REFERENCE MAX1238/MAX1236  
MAX1239  
EXTERNAL REFERENCE MAX1239/MAX1237  
-40 -25 -10  
5
20 35 50 65 80  
-40  
-10  
5
20 35 50 65 80  
2.7  
3.2  
3.7  
4.2  
4.7  
5.2  
-25  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
INPUT VOLTAGE (V)  
6
_______________________________________________________________________________________  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
Typical Operating Characteristics (continued)  
(V  
= 3.3V (MAX1237/MAX1239), V  
= 5V (MAX1236/MAX1238), f  
= 1.7MHz, (50% duty cycle), f  
= 94.4ksps, single-  
DD  
DD  
SCL  
SAMPLE  
ended, unipolar, T = +25°C, unless otherwise noted.)  
A
NORMALIZED REFERENCE VOLTAGE  
vs. SUPPLY VOLTAGE  
AVERAGE SUPPLY CURRENT vs.  
CONVERSION RATE (EXTERNAL CLOCK)  
INTERNAL REFERENCE VOLTAGE  
vs. TEMPERATURE  
1.00010  
1.00008  
1.00006  
1.00004  
1.00002  
1.00000  
0.99998  
0.99996  
0.99994  
0.99992  
0.99990  
1.0010  
1.0008  
1.0006  
1.0004  
1.0002  
1.0000  
0.9998  
0.9996  
0.9994  
0.9992  
0.9990  
800  
750  
700  
650  
600  
550  
500  
450  
400  
350  
300  
250  
200  
NORMALIZED TO VALUE AT +25°C  
A) INTERNAL REFERENCE ALWAYS ON  
B) EXTERNAL REFERENCE  
MAX1236/MAX1238  
NORMALIZED TO  
A
REFERENCE VALUE AT  
MAX1238  
V
= 5V  
DD  
B
MAX1239  
MAX1237/MAX1239  
NORMALIZED TO  
REFERENCE VALUE AT  
= 3.3V  
MAX1238  
V
DD  
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4  
(V)  
0
10 20 30 40 50 60 70 80 90 100  
CONVERSION RATE (ksps)  
-40 -25 -10  
5
20 35 50 65 80  
V
TEMPERATURE (°C)  
DD  
OFFSET ERROR vs. TEMPERATURE  
OFFSET ERROR vs. SUPPLY VOLTAGE  
0
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
-0.6  
-0.7  
-0.8  
-0.9  
-1.0  
2.0  
1.6  
1.2  
0.8  
0.4  
0
-0.4  
-0.8  
-1.2  
-1.6  
-2.0  
-40 -25 -10  
5
20 35 50 65 80  
2.7  
3.2  
3.7  
4.2  
(V)  
4.7  
5.2 5.5  
TEMPERATURE (°C)  
V
DD  
GAIN ERROR vs. SUPPLY VOLTAGE  
GAIN ERROR vs. TEMPERATURE  
2.0  
1.6  
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
1.2  
0.8  
0.4  
0
-0.4  
-0.8  
-1.2  
-1.6  
-2.0  
2.7  
3.2  
3.7  
4.2  
(V)  
4.7  
5.2 5.5  
-40 -25 -10  
5
20 35 50 65 80  
V
TEMPERATURE (°C)  
DD  
_______________________________________________________________________________________  
7
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
Pin Description  
PIN  
NAME  
DESCRIPTION  
MAX1236  
MAX1237  
MAX1238  
MAX1239  
1, 2, 3  
—
1, 2, 3  
4–8  
AIN0–AIN2  
AIN3–AIN7  
AIN8–AIN10  
Analog Inputs  
—
16, 15, 14  
Analog Input 3/Reference Input or Output. Selected in the setup  
register (see Tables 1 and 6).  
4
—
AIN3/REF  
Analog Input 11/Reference Input or Output. Selected in the setup  
register (see Tables 1 and 6).  
—
13  
AIN11/REF  
5
6
7
8
9
SCL  
SDA  
GND  
Clock Input  
10  
11  
12  
Data Input/Output  
Ground  
V
Positive Supply. Bypass to GND with a 0.1µF capacitor.  
DD  
A. F/S-MODE 2-WIRE SERIAL INTERFACE TIMING  
SDA  
t
t
t
R
F
t
t
HD.DAT  
SU.DAT  
t
t
BUF  
HD.STA  
t
LOW  
t
t
SU.STO  
SU.STA  
SCL  
t
HD.STA  
t
HIGH  
t
t
R
F
S
Sr  
A
P
S
B. HS-MODE 2-WIRE SERIAL INTERFACE TIMING  
SDA  
t
t
RDA  
FDA  
t
t
HD.DAT  
SU.DAT  
t
t
BUF  
HD.STA  
t
LOW  
t
SU.STO  
t
SU.STA  
SCL  
t
t
HD.STA  
HIGH  
t
t
FCL  
t
RCL  
RCL1  
S
Sr  
A
S
P
HS-MODE  
F/S-MODE  
Figure 1. 2-Wire Serial Interface Timing  
_______________________________________________________________________________________  
8
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
SDA  
SCL  
INPUT SHIFT REGISTER  
V
DD  
INTERNAL  
OSCILLATOR  
CONTROL  
LOGIC  
SETUP REGISTER  
GND  
CONFIGURATION REGISTER  
AIN0  
AIN1  
OUTPUT SHIFT  
REGISTER  
AND RAM  
12-BIT  
ADC  
AIN2  
T/H  
AIN3  
AIN4  
ANALOG  
INPUT  
MUX  
AIN5  
AIN6  
REF  
AIN7  
AIN8  
REFERENCE  
4.096V (MAX1238)  
2.048V (MAX1239)  
MAX1238  
MAX1239  
AIN9  
AIN10  
AIN11/REF  
Figure 2. MAX1238/MAX1239 Simplified Functional Diagram  
Figure 2 shows the simplified internal structure for the  
MAX1238/MAX1239.  
V
DD  
I
I
OL  
Power Supply  
The MAX1236–MAX1239 operates from a single supply  
and consumes 670µA (typ) at sampling rates up to  
94.4ksps. The MAX1237/MAX1239 feature a 2.048V  
internal reference and the MAX1236/MAX1238 feature  
a 4.096V internal reference. All devices can be config-  
V
SDA  
OUT  
400pF  
ured for use with an external reference from 1V to V  
.
DD  
OH  
Analog Input and Track/Hold  
The MAX1236–MAX1239 analog-input architecture con-  
tains an analog-input multiplexer (mux), a fully differen-  
tial track-and-hold (T/H) capacitor, T/H switches, a  
comparator, and a fully differential switched capacitive  
digital-to-analog converter (DAC) (Figure 4).  
Figure 3. Load Circuit  
Detailed Description  
The MAX1236–MAX1239 analog-to-digital converters  
(ADCs) use successive-approximation conversion tech-  
niques and fully differential input track/hold (T/H) cir-  
cuitry to capture and convert an analog signal to a  
serial 12-bit digital output. The MAX1236/MAX1237 are  
4-channel ADCs, and the MAX1238/MAX1239 are 12-  
channel ADCs. These devices feature a high-speed, 2-  
wire serial interface supporting data rates up to 1.7MHz.  
In single-ended mode, the analog input multiplexer con-  
nects C  
between the analog input selected by  
T/H  
CS[3:0] (see the Configuration Setup Bytes section) and  
GND (Table 3). In differential mode, the analog-input  
multiplexer connects C  
inputs selected by CS[3:0] (Table 4).  
to the “+” and “-” analog  
T/H  
During the acquisition interval, the T/H switches are in  
the track position and C  
charges to the analog input  
T/H  
_______________________________________________________________________________________  
9
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
signal. At the end of the acquisition interval, the T/H  
switches move to the hold position retaining the charge  
clock pulse during the shifting out of the first byte of the  
result. The conversion is performed during the next 12  
clock cycles.  
on C  
as a stable sample of the input signal.  
T/H  
During the conversion interval, the switched capacitive  
DAC adjusts to restore the comparator input voltage to  
0V within the limits of a 12-bit resolution. This action  
requires 12 conversion clock cycles and is equivalent  
The time required for the T/H circuitry to acquire an  
input signal is a function of the input sample capaci-  
tance. If the analog-input source impedance is high,  
the acquisition time constant lengthens and more time  
must be allowed between conversions. The acquisition  
to transferring a charge of 11pF ✕ (V  
- V ) from  
IN-  
IN+  
C
T/H  
to the binary weighted capacitive DAC, forming a  
time (t  
) is the minimum time needed for the signal  
ACQ  
digital representation of the analog input signal.  
to be acquired. It is calculated by:  
Sufficiently low source impedance is required to ensure  
an accurate sample. A source impedance of up to 1.5kΩ  
does not significantly degrade sampling accuracy. To  
minimize sampling errors with higher source impedances,  
connect a 100pF capacitor from the analog input to GND.  
This input capacitor forms an RC filter with the source  
impedance limiting the analog-input bandwidth. For larg-  
er source impedances, use a buffer amplifier to maintain  
analog-input signal integrity and bandwidth.  
t
≥ 9 ✕ (R  
SOURCE  
+ R ) ✕ C  
IN IN  
ACQ  
where R  
IN  
is the analog-input source impedance,  
SOURCE  
= 2.5kΩ, and C = 22pF. t  
clock mode and t  
R
is 1.5/f  
for internal  
IN  
ACQ  
ACQ  
SCL  
= 2 / f  
for external clock mode.  
SCL  
Analog Input Bandwidth  
The MAX1236–MAX1239 feature input-tracking circuitry  
with a 5MHz small-signal bandwidth. The 5MHz input  
bandwidth makes it possible to digitize high-speed tran-  
sient events and measure periodic signals with band-  
widths exceeding the ADC’s sampling rate by using  
under sampling techniques. To avoid high-frequency  
signals being aliased into the frequency band of interest,  
anti-alias filtering is recommended.  
When operating in internal clock mode, the T/H circuitry  
enters its tracking mode on the eighth rising clock edge  
of the address byte, see the Slave Address section. The  
T/H circuitry enters hold mode on the falling clock edge of  
the acknowledge bit of the address byte (the ninth clock  
pulse). A conversion, or series of conversions, are then  
internally clocked and the MAX1236–MAX1239 holds  
SCL low. With external clock mode, the T/H circuitry  
enters track mode after a valid address on the rising  
edge of the clock during the read (R/W = 1) bit. Hold  
mode is then entered on the rising edge of the second  
Analog Input Range and Protection  
Internal protection diodes clamp the analog input to  
V
DD  
and GND. These diodes allow the analog inputs to  
HOLD  
ANALOG INPUT MUX  
REF  
C
T/H  
AIN0  
TRACK  
CAPACITIVE  
DAC  
AIN1  
AIN2  
V
/2  
DD  
AIN3/REF  
CAPACITIVE  
DAC  
TRACK  
GND  
C
T/H  
MAX1236  
MAX1237  
REF  
HOLD  
Figure 4. Equivalent Input Circuit  
10 ______________________________________________________________________________________  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
swing from (GND - 0.3V) to (V  
+ 0.3V) without caus-  
START and STOP Conditions section). Both SDA and  
DD  
ing damage to the device. For accurate conversions,  
the inputs must not go more than 50mV below GND or  
SCL remain high when the bus is not busy.  
START and STOP Conditions  
The master initiates a transmission with a START condi-  
tion (S), a high-to-low transition on SDA while SCL is high.  
The master terminates a transmission with a STOP condi-  
tion (P), a low-to-high transition on SDA while SCL is high  
(Figure 5). A repeated START condition (Sr) can be used  
in place of a STOP condition to leave the bus active and  
the interface mode unchanged (see HS mode).  
above V  
.
DD  
Single-Ended/Differential Input  
The SGL/DIF of the configuration byte configures the  
MAX1236–MAX1239 analog-input circuitry for single-  
ended or differential inputs (Table 2). In single-ended  
mode (SGL/DIF = 1), the digital conversion results are the  
difference between the analog input selected by CS[3:0]  
and GND (Table 3). In differential mode (SGL/ DIF = 0),  
the digital conversion results are the difference between  
the “+” and the “-” analog inputs selected by CS[3:0]  
(Table 4).  
S
Sr  
P
Unipolar/Bipolar  
When operating in differential mode, the BIP/UNI bit of  
the set-up byte (Table 1) selects unipolar or bipolar  
operation. Unipolar mode sets the differential input  
SDA  
SCL  
range from 0 to V  
. A negative differential analog  
REF  
input in unipolar mode causes the digital output code  
to be zero. Selecting bipolar mode sets the differential  
Figure 5. START and STOP Conditions  
input range to  
V
/2. The digital output code is bina-  
REF  
Acknowledge Bits  
ry in unipolar mode and two’s complement in bipolar  
mode, see the Transfer Functions section.  
Data transfers are acknowledged with an acknowledge  
bit (A) or a not-acknowledge bit (A). Both the master  
and the MAX1236–MAX1239 (slave) generate acknowl-  
edge bits. To generate an acknowledge, the receiving  
device must pull SDA low before the rising edge of the  
acknowledge-related clock pulse (ninth pulse) and  
keep it low during the high period of the clock pulse  
(Figure 6). To generate a not-acknowledge, the receiv-  
er allows SDA to be pulled high before the rising edge  
of the acknowledge-related clock pulse and leaves  
SDA high during the high period of the clock pulse.  
Monitoring the acknowledge bits allows for detection of  
unsuccessful data transfers. An unsuccessful data  
transfer happens if a receiving device is busy or if a  
system fault has occurred. In the event of an unsuc-  
cessful data transfer, the bus master should reattempt  
communication at a later time.  
In single-ended mode, the MAX1236–MAX1239 al-  
ways operates in unipolar mode irrespective of  
BIP/UNI. The analog inputs are internally referenced to  
GND with a full-scale input range from 0 to V  
.
REF  
2-Wire Digital Interface  
The MAX1236–MAX1239 feature a 2-wire interface con-  
sisting of a serial data line (SDA) and serial clock line  
(SCL). SDA and SCL facilitate bidirectional communica-  
tion between the MAX1236–MAX1239 and the master at  
rates up to 1.7MHz. The MAX1236–MAX1239 are slaves  
that transfer and receive data. The master (typically a  
microcontroller) initiates data transfer on the bus and  
generates the SCL signal to permit that transfer.  
SDA and SCL must be pulled high. This is typically done  
with pullup resistors (750Ω or greater) (see the Typical  
Operating Circuit). Series resistors (R ) are optional. They  
S
protect the input architecture of the MAX1236–MAX1239  
from high voltage spikes on the bus lines and minimize  
crosstalk and undershoot of the bus signals.  
S
NOT ACKNOWLEDGE  
SDA  
SCL  
Bit Transfer  
One data bit is transferred during each SCL clock  
cycle. A minimum of 18 clock cycles are required to  
transfer the data in or out of the MAX1236–MAX1239.  
The data on SDA must remain stable during the high  
period of the SCL clock pulse. Changes in SDA while  
SCL is stable are considered control signals (see the  
ACKNOWLEDGE  
8 9  
1
2
Figure 6. Acknowledge Bits  
______________________________________________________________________________________ 11  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
Slave Address  
Bus Timing  
A bus master initiates communication with a slave device  
by issuing a START condition followed by a slave  
address. When idle, the MAX1236–MAX1239 continu-  
ously wait for a START condition followed by their slave  
address. When the MAX1236–MAX1239 recognize their  
slave address, they are ready to accept or send data.  
Please refer to the table in the ordering information sec-  
tion for the factory programmed slave address of the  
selected device. The least significant bit (LSB) of the  
address byte (R/W) determines whether the master is  
writing to or reading from the MAX1236–MAX1239  
(R/W = 0 selects a write condition, R/W = 1 selects a  
read condition). After receiving the address, the  
MAX1236–MAX1239 (slave) issues an acknowledge by  
pulling SDA low for one clock cycle.  
At power-up, the MAX1236–MAX1239 bus timing is set  
for fast-mode (F/S-mode), which allows conversion rates  
up to 22.2ksps. The MAX1236–MAX1239 must operate  
in high-speed mode (HS-mode) to achieve conversion  
rates up to 94.4ksps. Figure 1 shows the bus timing for  
the MAX1236–MAX1239’s 2-wire interface.  
HS-Mode  
At power-up, the MAX1236–MAX1239 bus timing is set  
for F/S-mode. The bus master selects HS-mode by  
addressing all devices on the bus with the HS-mode  
master code 0000 1XXX (X = don’t care). After success-  
fully receiving the HS-mode master code, the MAX1236–  
MAX1239 issue a not-acknowledge, allowing SDA to be  
pulled high for one clock cycle (Figure 8). After the not-  
acknowledge, the MAX1236–MAX1239 are in HS-mode.  
The bus master must then send a repeated START fol-  
lowed by a slave address to initiate HS-mode communi-  
cation. If the master generates a STOP condition, the  
MAX1236–MAX1239 return to F/S-mode.  
SLAVE ADDRESS  
MAX1236/MAX1237  
S
0
1
1
0
1
0
0
R/W  
A
SDA  
SCL  
1
2
3
4
5
6
7
8
9
SEE ORDERING INFORMATION FOR SLAVE ADDRESS OPTIONS AND DETAILS.  
Figure 7. MAX1236/MAX1237 Slave Address Byte  
HS-MODE MASTER CODE  
S
0
0
0
0
1
X
X
X
A
Sr  
SDA  
SCL  
F/S-MODE  
HS-MODE  
Figure 8. F/S-Mode to HS-Mode Transfer  
12 ______________________________________________________________________________________  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
Configuration/Setup Bytes (Write Cycle)  
A write cycle begins with the bus master issuing a  
START condition followed by seven address bits (Figure  
7) and a write bit (R/W = 0). If the address byte is suc-  
cessfully received, the MAX1236–MAX1239 (slave)  
issues an acknowledge. The master then writes to the  
slave. The slave recognizes the received byte as the  
set-up byte (Table 1) if the most significant bit (MSB) is  
1. If the MSB is 0, the slave recognizes that byte as the  
configuration byte (Table 3). The master can write either  
one or two bytes to the slave in any order (setup byte,  
then configuration byte; configuration byte, then setup  
byte; setup byte or configuration byte only; Figure 9). If  
the slave receives a byte successfully, it issues an  
acknowledge. The master ends the write cycle by issu-  
ing a STOP condition or a repeated START condition.  
When operating in HS-mode, a STOP condition returns  
the bus into F/S-mode (see the HS-Mode section).  
MASTER TO SLAVE  
SLAVE TO MASTER  
A. ONE-BYTE WRITE CYCLE  
1
7
1
1
8
1
1
NUMBER OF BITS  
SETUP OR  
CONFIGURATION BYTE  
S
SLAVE ADDRESS W A  
A
P or Sr  
MSB DETERMINES WHETHER  
SETUP OR CONFIGURATION BYTE  
B. TWO-BYTE WRITE CYCLE  
1
7
1
1
8
1
8
1
1
NUMBER OF BITS  
SETUP OR  
CONFIGURATION BYTE  
SETUP OR  
CONFIGURATION BYTE  
S
SLAVE ADDRESS W A  
A
A
P or Sr  
MSB DETERMINES WHETHER  
SETUP OR CONFIGURATION BYTE  
Figure 9. Write Cycle  
Table 1. Setup Byte Format  
BIT 7  
(MSB)  
BIT 0  
(LSB)  
BIT 6  
BIT 5  
SEL1  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
REG  
SEL2  
SEL0  
CLK  
BIP/UNI  
RST  
X
BIT  
7
NAME  
REG  
SEL2  
SEL1  
SEL0  
CLK  
DESCRIPTION  
Register bit. 1 = setup byte, 0 = configuration byte (see Table 2).  
6
Three bits select the reference voltage and the state of AIN_/REF (Table 6). Default to 000 at  
power-up.  
5
4
3
1 = external clock, 0 = internal clock. Default to 0 at power-up.  
1 = bipolar, 0 = unipolar. Default to 0 at power-up (see the Unipolar/Bipolar section).  
2
BIP/UNI  
RST  
1
1= no action, 0 = resets the configuration register to default. Setup register remains unchanged.  
Don’t care, can be set to 1 or 0.  
0
X
______________________________________________________________________________________ 13  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
Table 2. Configuration Byte Format  
BIT 7  
(MSB)  
BIT 0  
(LSB)  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
REG  
SCAN1  
SCAN0  
CS3  
CS2  
CS1  
CS0  
SGL/DIF  
BIT  
7
NAME  
REG  
DESCRIPTION  
Register bit 1 = setup byte (see Table 1), 0 = configuration byte.  
6
SCAN1  
SCAN0  
CS3  
Scan select bits. Two bits select the scanning configuration (Table 5). Default to 00 at power-up.  
5
4
Channel select bits. Four bits select which analog input channels are to be used for conversion  
(Tables 3 and 4). Default to 0000 at power-up. For MAX1236/MAX1237, CS3 and CS2 are  
internally set to 0.  
3
CS2  
2
CS1  
1
CS0  
1 = single-ended, 0 = differential (Tables 3 and 4). Default to 1 at power-up. See the Single-  
Ended/Differential Input section.  
0
SGL/DIF  
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)  
CS31 CS21 CS1  
CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN112 GND  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
+
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
RESERVED  
RESERVED  
RESERVED  
RESERVED  
1. For MAX1236/MAX1237, CS3 and CS2 are internally set to 0.  
2. When SEL1 = 1, a single-ended read of AIN3/REF (MAX1236/MAX1237) or AIN11/REF (MAX1238/MAX1239) is ignored; scan  
stops at AIN2 or AIN10.  
14 ______________________________________________________________________________________  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)  
CS31  
CS21  
CS1  
0
CS0  
0
AIN0  
AIN1 AIN2 AIN32 AIN4 AIN5  
AIN6 AIN7 AIN8 AIN9 AIN10 AIN112  
0
0
+
-
-
0
0
0
1
+
0
0
1
0
+
-
-
0
0
1
1
+
0
1
0
0
+
-
-
0
1
0
1
+
0
1
1
0
+
-
-
0
1
1
1
+
1
0
0
0
+
-
-
1
0
0
1
+
1
0
1
0
+
-
-
1
0
1
1
+
1
1
0
0
RESERVED  
RESERVED  
RESERVED  
RESERVED  
1
1
0
1
1
1
1
0
1
1
1
1
1. For MAX1236/MAX1237, CS3 and CS2 are internally set to 0.  
2. When SEL1 = 1, a differential read between AIN2 and AIN3/REF (MAX1236/MAX1237) or AIN10 and AIN11/REF  
(MAX1238/MAX1239) returns the difference between GND and AIN2 or AIN10, respectively. For example, a differential read of 1011  
returns the negative difference between AIN10 and GND. In differential scanning, the address increments by 2 until limit set by  
CS3:CS1 has been reached.  
Data Byte (Read Cycle)  
A read cycle must be initiated to obtain conversion  
results. Read cycles begin with the bus master issuing  
a START condition followed by seven address bits and  
a read bit (R/W = 1). If the address byte is successfully  
received, the MAX1236–MAX1239 (slave) issues an  
acknowledge. The master then reads from the slave.  
The result is transmitted in two bytes; first four bits of  
the first byte are high, then MSB through LSB are con-  
secutively clocked out. After the master has received  
the byte(s), it can issue an acknowledge if it wants to  
continue reading or a not-acknowledge if it no longer  
wishes to read. If the MAX1236–MAX1239 receive a not-  
acknowledge, they release SDA, allowing the master to  
generate a STOP or a repeated START condition. See  
the Clock Modes and Scan Mode sections for detailed  
information on how data is obtained and converted.  
Internal Clock  
When configured for internal clock mode (CLK = 0), the  
MAX1236–MAX1239 use their internal oscillator as the con-  
version clock. In internal clock mode, the MAX1236–  
MAX1239 begin tracking the analog input after a valid  
address on the eighth rising edge of the clock. On the  
falling edge of the ninth clock, the analog signal is  
acquired and the conversion begins. While converting the  
analog input signal, the MAX1236–MAX1239 holds SCL  
low (clock stretching). After the conversion completes, the  
results are stored in internal memory. If the scan mode is  
set for multiple conversions, they all happen in succession  
with each additional result stored in memory. The  
MAX1236/MAX1237 contain four 12-bit blocks of memory,  
and the MAX1238/ MAX1239 contain twelve 12-bit blocks  
of memory. Once all conversions are complete, the  
MAX1236–MAX1239 release SCL, allowing it to be pulled  
high. The master can now clock the results out of the mem-  
ory in the same order the scan conversion has been done  
at a clock rate of up to 1.7MHz. SCL is stretched for a max-  
imum of 0.3µs per channel (see Figure 10).  
Clock Modes  
The clock mode determines the conversion clock and  
the data acquisition and conversion time. The clock  
mode also affects the scan mode. The state of the set-  
up byte’s CLK bit determines the clock mode (Table 1).  
At power-up, the MAX1236–MAX1239 are defaulted to  
internal clock mode (CLK = 0).  
The device memory contains all of the conversion  
results when the MAX1236–MAX1239 release SCL. The  
converted results are read back in a first-in-first-out  
______________________________________________________________________________________ 15  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
MASTER TO SLAVE  
SLAVE TO MASTER  
A. SINGLE CONVERSION WITH INTERNAL CLOCK  
1
7
1
1
8
8
1
1
NUMBER OF BITS  
CLOCK STRETCH  
S
SLAVE ADDRESS  
R
A
RESULT 4 MSBs  
A
RESULT 8 LSBs  
A
P or Sr  
t
ACQ  
t
CONV  
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK  
1
7
1
1
8
1
8
1
8
1
8
1
1
NUMBER OF BITS  
CLOCK STRETCH  
CLOCK STRETCH  
S
SLAVE ADDRESS  
R
A
RESULT 1 ( 4MSBs)  
A
RESULT 1 (8 LSBs)  
A
RESULT N (4MSBs)  
A
RESULT N (8LSBs)  
A
P or Sr  
t
t
t
ACQ1  
ACQ2  
ACQN  
t
t
t
CONV1  
CONV2  
CONVN  
Figure 10. Internal Clock Mode Read Cycles  
(FIFO) sequence. If AIN_/REF is set to be a reference  
input or output (SEL1 = 1, Table 6), AIN_/REF is exclud-  
ed from a multichannel scan. The memory contents can  
be read continuously. If reading continues past the  
result stored in memory, the pointer wraps around and  
point to the first result. Note that only the current con-  
version results is read from memory. The device must  
be addressed with a read command to obtain new con-  
version results.  
The internal clock mode’s clock stretching quiets the  
SCL bus signal reducing the system noise during con-  
version. Using the internal clock also frees the bus  
master (typically a microcontroller) from the burden of  
running the conversion clock, allowing it to perform  
other tasks that do not need to use the bus.  
External Clock  
When configured for external clock mode (CLK = 1),  
the MAX1236–MAX1239 use the SCL as the conversion  
MASTER TO SLAVE  
SLAVE TO MASTER  
A. SINGLE CONVERSION WITH EXTERNAL CLOCK  
1
7
1
1
8
1
8
1
1
NUMBER OF BITS  
S
R
A
A
SLAVE ADDRESS  
RESULT (4 MSBs)  
RESULT (8 LSBs)  
A
P OR Sr  
t
ACQ  
t
CONV  
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK  
1
7
1
1
8
1
8
1
8
1
8
1
1
NUMBER OF BITS  
S
R
A
A
A
A
P OR Sr  
A
SLAVE ADDRESS  
RESULT 1 (4 MSBs)  
RESULT 2 (8 LSBs)  
RESULT N (4 MSBs)  
RESULT N (8 LSBs)  
t
t
t
ACQ1  
ACQ2  
ACQN  
t
t
CONV1  
CONVN  
Figure 11. External Clock Mode Read Cycle  
16 ______________________________________________________________________________________  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
Table 5. Scanning Configuration  
SCAN1  
SCAN0  
SCANNING CONFIGURATION  
Scans up from AIN0 to the input selected by CS3–CS0. When CS3–CS0 exceeds 11, the scanning stops  
at AIN11. When AIN_/REF is set to be a REF in/out, scanning stops at AIN10 or AIN3.  
0
0
0
1
*Converts the input selected by CS3–CS0 eight times (see Tables 3 and 4).  
Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for AIN0–AIN2,  
the scanning stops at AIN2 (MAX1236/MAX1237). When AIN/REF is set to be a REF IN/OUT, scanning  
stops at AIN3 or AIN10.  
Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0-AIN6, scanning  
stops at AIN6 (MAX1238/MAX1239). When AIN/REF is set to be a REF IN/OUT, scanning stops at AIN or  
AIN10.  
1
1
0
1
*Converts channel selected by CS3–CS0.  
*When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11 and converting occurs  
perpetually until not-acknowledge occurs.  
clock. In external clock mode, the MAX1236–MAX1239  
begin tracking the analog input on the ninth rising clock  
Applications Information  
Power-On Reset  
The configuration and setup registers (Tables 1 and 2)  
default to a single-ended, unipolar, single-channel con-  
edge of a valid slave address byte. Two SCL clock  
cycles later, the analog signal is acquired and the con-  
version begins. Unlike internal clock mode, converted  
data is available immediately after the first four empty  
high bits. The device continuously converts input chan-  
nels dictated by the scan mode until given a not  
acknowledge. There is no need to readdress the  
device with a read command to obtain new conversion  
results (see Figure 11).  
version on AIN0 using the internal clock with V  
as the  
DD  
reference and AIN_/REF configured as an analog input.  
The memory contents are unknown after power-up.  
Automatic Shutdown  
SEL[2:0] of the setup byte (Table 1 and Table 6) control  
the state of the reference and AIN_/REF. If automatic  
shutdown is selected (SEL[2:0] = 100), shutdown  
occurs between conversions when the MAX1236–  
MAX1239 are idle. When operating in external clock  
mode, a STOP, not-acknowledge, or repeated START  
condition must be issued to place the devices in idle  
mode and benefit from automatic shutdown. A STOP  
condition is not necessary in internal clock mode to  
benefit from automatic shutdown because power-down  
occurs once all contents are written to memory (Figure  
10). All analog circuitry is inactive in shutdown and  
supply current is less than 0.5µA. The digital conversion  
results are maintained in memory during shutdown and  
are available for access through the serial interface at  
any time prior to a STOP or a repeated START condition.  
The conversion must complete in 1ms, or droop on the  
track-and-hold capacitor degrades conversion results.  
Use internal clock mode if the SCL clock period  
exceeds 60µs.  
The MAX1236–MAX1239 must operate in external clock  
mode for conversion rates from 40ksps to 94.4ksps.  
Below 40ksps, internal clock mode is recommended  
due to much smaller power consumption.  
Scan Mode  
SCAN0 and SCAN1 of the configuration byte set the  
scan mode configuration. Table 5 shows the scanning  
configurations. If AIN_/REF is set to be a reference  
input or output (SEL1 = 1, Table 6), AIN_/REF is exclud-  
ed from a multichannel scan. The scanned results are  
written to memory in the same order as the conversion.  
Read the results from memory in the order they were  
converted. Each result needs a 2-byte transmission; the  
first byte begins with four empty bits, during which SDA  
is left high. Each byte has to be acknowledged by the  
master or the memory transmission is terminated. It is  
not possible to read the memory independently of con-  
version.  
When idle, the MAX1236–MAX1239 continuously wait  
for a START condition followed by their slave address  
(see the Slave Address section). Upon reading a valid  
address byte, the MAX1236–MAX1239 power up. The  
internal reference requires 10ms to wake up, so when  
using the internal reference it should be powered up  
10ms prior to conversion or powered continuously.  
Wake-up is invisible when using an external reference  
or V  
as the reference.  
DD  
______________________________________________________________________________________ 17  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
Table 6. Reference Voltage and AIN_/REF Format  
INTERNAL REFERENCE  
STATE  
SEL2  
SEL1  
SEL0  
REFERENCE VOLTAGE  
AIN_/REF  
0
0
1
1
1
1
0
1
0
0
1
1
X
X
0
1
0
1
V
Analog Input  
Reference Input  
Analog Input  
Always Off  
Always Off  
Always Off  
Always On  
Always Off  
Always On  
DD  
External Reference  
Internal Reference  
Internal Reference  
Internal Reference  
Internal Reference  
Analog Input  
Reference Output  
Reference Output  
Automatic shutdown results in dramatic power savings,  
particularly at slow conversion rates and with internal  
clock. For example, at a conversion rate of 10ksps, the  
average supply current for the MAX1237 is 60µA (typ) and  
drops to 6µA (typ) at 1ksps. At 0.1ksps the average sup-  
ply current is just 1µA, or a minuscule 3µW of power con-  
sumption, see Average Supply Current vs. Conversion  
Rate in the Typical Operating Characteristics section).  
of bits (12). Code transitions occur halfway between  
successive-integer LSB values. Figures 12 and 13  
show the input/output (I/O) transfer functions for unipo-  
lar and bipolar operations, respectively.  
Layout, Grounding, and Bypassing  
Only use PC boards. Wire-wrap configurations are not  
recommended since the layout should ensure proper  
separation of analog and digital traces. Do not run ana-  
log and digital lines parallel to each other, and do not  
layout digital signal paths underneath the ADC pack-  
age. Use separate analog and digital PC board ground  
sections with only one star point (Figure 14) connecting  
the two ground systems (analog and digital). For lowest  
noise operation, ensure the ground return to the star  
ground’s power supply is low impedance and as short  
as possible. Route digital signals far away from sensi-  
tive analog and reference inputs.  
Reference Voltage  
SEL[2:0] of the setup byte (Table 1) control the reference  
and the AIN_/REF configuration (Table 6). When  
AIN_/REF is configured to be a reference input or refer-  
ence output (SEL1 = 1), differential conversions on  
AIN_/REF appear as if AIN_/REF is connected to GND  
(see Note 2 and Table 4). Single-ended conversion in  
scan mode AIN_/REF is ignored by the internal limiter,  
which sets the highest available channel at AIN2 or  
AIN10.  
Internal Reference  
The internal reference is 4.096V for the MAX1236/  
MAX1238 and 2.048V for the MAX1237/MAX1239. SEL1 of  
the setup byte controls whether AIN_/REF is used for an  
analog input or a reference (Table 6). When AIN_/REF is  
configured to be an internal reference output (SEL[2:1] =  
11), decouple AIN_/REF to GND with a 0.1µF capacitor.  
Once powered up, the reference always remains on until  
reconfigured. The reference should not be used to supply  
current for external circuitry.  
OUTPUT CODE  
FULL-SCALE  
TRANSITION  
111...111  
111...110  
FS = REF + GND  
ZS = GND  
100...010  
100...001  
100...000  
V
4096  
REF  
1 LSB =  
011...111  
011...110  
011...101  
External Reference  
The external reference can range from 1V to V . For  
DD  
maximum conversion accuracy, the reference must be  
able to deliver up to 40µA and have an output imped-  
ance of 500kΩ or less. If the reference has a higher out-  
put impedance or is noisy, bypass it to GND as close to  
AIN_/REF as possible with a 0.1µF capacitor.  
000...001  
000...000  
2048  
INPUT VOLTAGE (LSB)  
0
1
1
GND  
Transfer Functions  
Output data coding for the MAX1236–MAX1239 is bina-  
ry in unipolar mode and two’s complement in bipolar  
FS - LSB  
2
Figure 12. Unipolar Transfer Function  
mode with 1 LSB = (V  
/ 2N) where “N” is the number  
REF  
18 ______________________________________________________________________________________  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
OUTPUT CODE  
V
REF  
2
FS =  
+ AIN-  
SUPPLIES  
011...111  
011...110  
ZS = AIN-  
GND  
3V OR 5V  
V
= 3V/5V  
LOGIC  
-V  
REF  
2
-FS =  
+ AIN-  
000...010  
000...001  
000...000  
V
REF  
1 LSB =  
4096  
4.7µF  
R* = 5Ω  
111...111  
111...110  
111...101  
0.1µF  
V
GND  
3V/5V DGND  
DD  
100...001  
100...000  
DIGITAL  
CIRCUITRY  
MAX1236–  
MAX1239  
AIN-  
-FS+1/2 LSB  
INPUT VOLTAGE (LSB)  
V
+FS - 1 LSB  
REF  
2
AIN- ≥  
*OPTIONAL  
Figure 13. Bipolar Transfer Function  
Figure 14. Power-Supply Grounding Connection  
High-frequency noise in the power supply (V ) could  
DD  
Aperture Delay  
influence the proper operation of the ADC’s fast com-  
Aperture delay (t ) is the time between the falling  
AD  
parator. Bypass V  
to the star ground with a network of  
edge of the sampling clock and the instant when an  
actual sample is taken.  
DD  
two parallel capacitors, 0.1µF and 4.7µF, located as  
close as possible to the MAX1236–MAX1239 power-sup-  
ply pin. Minimize capacitor lead length for best supply  
noise rejection, and add an attenuation resistor (5Ω) in  
series with the power supply if it is extremely noisy.  
Signal-to-Noise Ratio  
For a waveform perfectly reconstructed from digital sam-  
ples, the theoretical maximum SNR is the ratio of the full-  
scale analog input (RMS value) to the RMS quantization  
error (residual error). The ideal, theoretical minimum ana-  
log-to-digital noise is caused by quantization error only  
and results directly from the ADC’s resolution (N Bits):  
Definitions  
Integral Nonlinearity  
Integral nonlinearity (INL) is the deviation of the values on  
an actual transfer function from a straight line. This straight  
line can be either a best straight-line fit or a line drawn  
between the endpoints of the transfer function, once offset  
and gain errors have been nullified. The MAX1236–  
MAX1239’s INL is measured using the endpoint.  
SNR  
= 6.02 ✕ N + 1.76  
dB dB  
MAX[dB]  
In reality, there are other noise sources besides quanti-  
zation noise: thermal noise, reference noise, clock jitter,  
etc. SNR is computed by taking the ratio of the RMS  
signal to the RMS noise, which includes all spectral  
components minus the fundamental, the first five har-  
monics, and the DC offset.  
Differential Nonlinearity  
Differential nonlinearity (DNL) is the difference between  
an actual step width and the ideal value of 1 LSB. A  
DNL error specification of less than 1 LSB guarantees  
no missing codes and a monotonic transfer function.  
Signal-to-Noise Plus Distortion  
Signal-to-noise plus distortion (SINAD) is the ratio of the  
fundamental input frequency’s RMS amplitude to the  
RMS equivalent of all other ADC output signals.  
Aperture Jitter  
Aperture jitter (t ) is the sample-to-sample variation in  
AJ  
the time between the samples.  
SignalRMS  
NoiseRMS+ THDRMS  
SINAD(dB) = 20 × log  
______________________________________________________________________________________ 19  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
Effective Number of Bits  
Pin Configurations  
Effective number of bits (ENOB) indicates the global  
accuracy of an ADC at a specific input frequency and  
sampling rate. An ideal ADC’s error consists of quanti-  
zation noise only. With an input range equal to the  
ADC’s full-scale range, calculate the ENOB as follows:  
TOP VIEW  
AIN0  
AIN1  
1
2
3
4
8
7
6
5
V
DD  
GND  
SDA  
SCL  
ENOB = (SINAD - 1.76) / 6.02  
MAX1236  
MAX1237  
AIN2  
AIN3/REF  
Total Harmonic Distortion  
Total harmonic distortion (THD) is the ratio of the RMS  
sum of the input signal’s first five harmonics to the fun-  
damental itself. This is expressed as:  
µMAX  
AIN0  
AIN1  
AIN2  
AIN3  
AIN4  
AIN5  
AIN6  
AIN7  
1
16 AIN8  
2
2
2
2
V
+ V + V + V  
3 4 5  
2
3
4
5
6
7
8
15 AIN9  
2
THD = 20 × log  
V
14 AIN10  
13 AIN11/REF  
1
MAX1238  
MAX1239  
where V is the fundamental amplitude, and V through  
V are the amplitudes of the 2nd- through 5th-order  
12  
V
DD  
1
2
5
11 GND  
10 SDA  
harmonics.  
Spurious-Free Dynamic Range  
Spurious-free dynamic range (SFDR) is the ratio of the  
RMS amplitude of the fundamental (maximum signal  
component) to the RMS value of the next largest distor-  
tion component.  
9
SCL  
QSOP  
Typical Operating Circuit  
Ordering Information (continued)  
TEMP  
RANGE  
PIN-  
PACKAGE ADDRESS (LSB)  
I2C SLAVE INL  
3.3V or 5V  
PART  
0.1µF  
MAX1238EEE  
-40°C to +85°C 16 QSOP 0110101  
1
1
1
1
1
1
1
1
V
DD  
MAX1238KEEE* -40°C to +85°C 16 QSOP 0110001  
MAX1238LEEE* -40°C to +85°C 16 QSOP 0110011  
MAX1238MEEE* -40°C to +85°C 16 QSOP 0110111  
AIN0  
AIN1  
*R  
*R  
S
S
MAX1236  
MAX1237  
MAX1238  
MAX1239  
SDA  
SCL  
ANALOG  
INPUTS  
AIN3**/REF  
MAX1239EEE  
-40°C to +85°C 16 QSOP 0110101  
C
0.1µF  
GND  
REF  
MAX1239KEEE -40°C to +85°C 16 QSOP 0110001  
MAX1239LEEE -40°C to +85°C 16 QSOP 0110011  
MAX1239MEEE -40°C to +85°C 16 QSOP 0110111  
*Future product—contact factory for availability.  
5V  
R
P
P
5V  
R
SDA  
SCL  
µC  
Chip Information  
MAX1236/MAX1237 TRANSISTORS COUNT: 11,362  
MAX1238/MAX1239 TRANSISTORS COUNT: 12,956  
PROCESS: BiCMOS  
*OPTIONAL  
**AIN11/REF (MAX1238/MAX1239)  
20 ______________________________________________________________________________________  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
Package Information  
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,  
go to www.maxim-ic.com/packages.)  
4X S  
8
8
MILLIMETERS  
INCHES  
DIM MIN  
MAX  
MAX  
MIN  
-
-
0.043  
0.006  
0.037  
0.014  
0.007  
0.120  
1.10  
0.15  
0.95  
0.36  
0.18  
3.05  
A
0.002  
0.030  
0.010  
0.005  
0.116  
0.05  
0.75  
0.25  
0.13  
2.95  
A1  
A2  
b
E
H
ÿ 0.50 0.1  
c
D
e
0.0256 BSC  
0.65 BSC  
0.6 0.1  
E
H
0.116  
0.188  
0.016  
0∞  
0.120  
2.95  
4.78  
0.41  
0∞  
3.05  
5.03  
0.66  
6∞  
0.198  
0.026  
6∞  
L
1
1
α
S
0.6 0.1  
0.0207 BSC  
0.5250 BSC  
BOTTOM VIEW  
D
TOP VIEW  
A1  
A2  
A
c
α
e
L
b
SIDE VIEW  
FRONT VIEW  
PROPRIETARY INFORMATION  
TITLE:  
PACKAGE OUTLINE, 8L uMAX/uSOP  
APPROVAL  
DOCUMENT CONTROL NO.  
REV.  
1
21-0036  
J
1
______________________________________________________________________________________ 21  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,  
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs  
Package Information (continued)  
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,  
go to www.maxim-ic.com/packages.)  
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are  
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.  
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600  
© 2003 Maxim Integrated Products  
Printed USA  
is a registered trademark of Maxim Integrated Products.  

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