MAX1198E/D [MAXIM]
ADC, Flash Method, 8-Bit, 1 Func, 2 Channel, Parallel, 8 Bits Access, CMOS, DIE-48;
| 型号： | MAX1198E/D |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Flash Method, 8-Bit, 1 Func, 2 Channel, Parallel, 8 Bits Access, CMOS, DIE-48 转换器 |
| 文件： | 总22页 (文件大小：551K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2412; Rev 0; 4/02
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
General Description
Features
The MAX1198 is a 3.3V, dual, 8-bit analog-to-digital con-
verter (ADC) featuring fully differential wideband track-
and-hold (T/H) inputs, driving two ADCs. The MAX1198
is optimized for low power, small size, and high-dynamic
performance for applications in imaging, instrumenta-
tion, and digital communications. This ADC operates
from a single 2.7V to 3.6V supply, consuming only
264mW, while delivering a typical signal-to-noise and
distortion (SINAD) of 48.1dB at an input frequency of
50MHz and a sampling rate of 100Msps. The T/H-driven
input stages incorporate 400MHz (-3dB) input ampli-
fiers. The converters may also be operated with single-
ended inputs. In addition to low operating power, the
MAX1198 features a 3.2mA sleep mode, as well as a
0.15µA power-down mode to conserve power during
idle periods.
o Single 2.7V to 3.6V Operation
o Excellent Dynamic Performance
48.1dB/47.6dB SINAD at f = 50MHz/200MHz
IN
66dBc/61.5dBc SFDR at f = 50MHz/200MHz
IN
o -72dB Interchannel Crosstalk at f = 50MHz
IN
o Low Power
264mW (Normal Operation)
10.6mW (Sleep Mode)
0.5µW (Shutdown Mode)
o 0.05dB Gain and 0.1° Phase Matching
o Wide 1V
Differential Analog Input Voltage
P-P
Range
o 400MHz -3dB Input Bandwidth
o On-Chip 2.048V Precision Bandgap Reference
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
applied reference, if desired, for applications requiring
increased accuracy or a different input voltage range.
The MAX1198 features parallel, CMOS-compatible three-
state outputs. The digital output format can be set to two’s
complement or straight offset binary through a single con-
trol pin. The device provides for a separate output power
supply of 1.7V to 3.6V for flexible interfacing with various
logic families. The MAX1198 is available in a 7mm x 7mm,
48-pin TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
o User-Selectable Output Format—Two’s
Complement or Offset Binary
o Pin-Compatible 8-Bit and 10-Bit Upgrades
Available
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX1198ECM
-40°C to +85°C
48 TQFP-EP*
*EP = Exposed paddle
Functional Diagram and Pin Compatible Upgrades table
appear at end of data sheet.
Pin-compatible lower speed versions of the MAX1198
are also available. Refer to the MAX1195 data sheet for
40Msps and the MAX1197 data sheet for 60Msps. In
addition to these speed grades, this family includes a
multiplexed output version (MAX1196, 40Msps), for
which digital data is presented time interleaved and on
a single, parallel 8-bit output port.
For a 10-bit, pin-compatible upgrade, refer to the
MAX1180 data sheet. With the N.C. pins of the
MAX1198 internally pulled down to ground, this ADC
becomes a drop-in replacement for the MAX1180.
Pin Configuration
COM
1
2
36 N.C.
35 N.C.
34 OGND
V
DD
GND
INA+
INA-
3
4
33 OV
32 OV
DD
DD
5
V
DD
6
31 OGND
30 N.C.
29 N.C.
MAX1198
Applications
GND
INB-
INB+
GND
7
8
Baseband I/Q Sampling
WLAN, WWAN, WLL,
MMDS Modems
D0B
D1B
D2B
D3B
9
28
27
26
25
10
11
12
Multichannel IF Sampling
Ultrasound and Medical
Imaging
V
DD
Set-Top Boxes
VSAT Terminals
CLK
Battery-Powered
Instrumentation
TQFP-EP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ABSOLUTE MAXIMUM RATINGS
V
, OV
to GND ...............................................-0.3V to +3.6V
Continuous Power Dissipation (T = +70°C)
DD
DD
A
OGND to GND.......................................................-0.3V to +0.3V
48-Pin TQFP (derate 12.5mW/°C above +70°C).........1000mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
REFIN, REFOUT, REFP, REFN,
DD
COM, CLK to GND .................................-0.3V to (V
OE, PD, SLEEP, T/B, D7A–D0A,
+ 0.3V)
DD
D7B–D0B to OGND .............................-0.3V to (OV
+ 0.3V)
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 3.3V, OV
= 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
DD
DD
10kΩ resistor, V = 2V
(differential with respect to COM), C = 10pF at digital outputs, f
= 100MHz, T = T
to T
, unless
MAX
IN
P-P
L
CLK
A
MIN
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at
T
= +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
8
Bits
Integral Nonlinearity
INL
f
f
= 7.5MHz (Note 1)
0.3
0.2
1
1
LSB
IN
= 7.5MHz, no missing codes guaranteed
IN
Differential Nonlinearity
DNL
LSB
(Note 1)
Offset Error
4
4
%FS
%FS
Gain Error
Gain Temperature Coefficient
ANALOG INPUT
100
1.0
ppm/°C
Differential Input Voltage Range
V
Differential or single-ended inputs
Switched capacitor load
V
V
DIFF
Common-Mode Input Voltage
Range
V
/ 2
DD
V
CM
0.2
Input Resistance
R
57
5
kΩ
IN
IN
Input Capacitance
C
pF
CONVERSION RATE
Maximum Clock Frequency
f
100
MHz
CLK
Clock
Cycles
Data Latency
5
DYNAMIC CHARACTERISTICS (f
= 100MHz, 4096-point FFT)
CLK
f
f
f
f
= 7.5MHz at -1dB FS
= 20MHz at -1dB FS
= 50MHz at -1dB FS
= 115.1MHz at -1dB FS
48.5
48.3
48.3
48.1
INA or B
INA or B
INA or B
INA or B
47.0
Signal-to-Noise Ratio
SNR
dB
2
_______________________________________________________________________________________
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V, OV
= 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
DD
DD
10kΩ resistor, V = 2V
(differential with respect to COM), C = 10pF at digital outputs, f
= 100MHz, T = T
to T
, unless
MAX
IN
P-P
L
CLK
A
MIN
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at
T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
= 7.5MHz at -1dB FS
= 20MHz at -1dB FS
= 50MHz at -1dB FS
= 115.1MHz at -1dB FS
= 7.5MHz at -1dB FS
= 20MHz at -1dB FS
= 50MHz at -1dB FS
= 115.1MHz at -1dB FS
= 7.5MHz at -1dB FS
= 20MHz at -1dB FS
= 50MHz at -1dB FS
= 115.1MHz at -1dB FS
MIN
TYP
48.3
48.2
48.1
48
MAX
UNITS
f
f
f
f
f
f
f
f
f
f
f
f
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
46.5
Signal-to-Noise and Distortion
Spurious-Free Dynamic Range
Third-Harmonic Distortion
SINAD
dB
67
60
67
SFDR
HD3
dBc
dBc
66
65
-67
-67
-67
-66
f
f
= 1.989MHz at -7dB FS
= 2.038MHz at -7dB FS
IN1(A or B)
IN2(A or B)
Intermodulation Distortion
(First Five Odd-Order IMDs)
IMD
IM3
-69.5
-80
dBc
dBc
(Note 2)
f
f
= 1.989MHz at -7dB FS
= 2.038MHz at -7dB FS
IN1(A or B)
Third-Order Intermodulation
Distortion
IN2(A or B)
(Note 2)
f
f
f
f
= 7.5MHz at -1dB FS
= 20MHz at -1dB FS
= 50MHz at -1dB FS
= 115.1MHz at -1dB FS
-66
-67
-64
-58
500
400
INA or B
INA or B
INA or B
INA or B
-57
Total Harmonic Distortion
(First Four Harmonics)
THD
dBc
Small-Signal Bandwidth
Full-Power Bandwidth
Input at -20dB FS, differential inputs
Input at -1dB FS, differential inputs
MHz
MHz
FPBW
f
f
= 106MHz at -1dB FS
= 118MHz at -1dB FS
IN1(A or B)
Gain Flatness
(12MHz Spacing)
0.05
dB
ns
IN2(A or B)
(Note 3)
Aperture Delay
t
1
2
2
AD
Aperture Jitter
t
1dB SNR degradation at Nyquist
ps
RMS
AJ
Overdrive Recovery Time
For 1.5 × full-scale input
ns
INTERNAL REFERENCE (REFIN = REFOUT through 10kΩ resistor; REFP, REFN, and COM levels are generated internally.)
2.048
3%
Reference Output Voltage
V
(Note 4)
(Note 5)
(Note 5)
(Note 5)
V
V
V
V
REFOUT
Positive Reference Output
Voltage
V
2.162
REFP
REFN
Negative Reference Output
Voltage
V
1.138
V
DD
/ 2
Common-Mode Level
V
COM
0.1
_______________________________________________________________________________________
3
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V, OV
= 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
DD
DD
10kΩ resistor, V = 2V
(differential with respect to COM), C = 10pF at digital outputs, f
= 100MHz, T = T
to T
, unless
MAX
IN
P-P
L
CLK
A
MIN
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at
T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
- V
MIN
TYP
MAX
UNITS
Differential Reference Output
Voltage Range
1.024
3%
∆V
∆V
= V
V
REF
REF
REF
REFP
REFN
Reference Temperature
Coefficient
TC
100
ppm/°C
BUFFERED EXTERNAL REFERENCE (V
= 2.048V)
(Note 5)
REFIN
REFP
Positive Reference Output
V
2.162
1.138
V
V
V
Voltage
Negative Reference Output
Voltage
V
(Note 5)
(Note 5)
REFN
V
DD
/ 2
Common-Mode Level
V
COM
0.1
Differential Reference Output
Voltage Range
1.024
2%
∆V
∆V
= V
- V
REFN
V
REF
REF
REFP
REFIN Resistance
R
>50
MΩ
mA
REFIN
Maximum REFP, COM Source
Current
I
I
5
SOURCE
Maximum REFP, COM Sink
Current
I
-250
µA
SINK
Maximum REFN Source Current
Maximum REFN Sink Current
250
-5
µA
SOURCE
I
mA
SINK
UNBUFFERED EXTERNAL REFERENCE (V
= AGND, reference voltage applied to REFP, REFN, and COM)
REFIN
R
R
,
Measured between REFP, COM, REFN,
and COM
REFP
REFP, REFN Input Resistance
4
kΩ
pF
V
REFN
REFP, REFN, COM Input
Capacitance
C
15
IN
Differential Reference Input
Voltage Range
1.024
10%
∆V
∆V
= V
- V
REFP REFN
REF
REF
V
/ 2
5%
DD
COM Input Voltage Range
REFP Input Voltage
V
V
COM
REFP
REFN
V
COM
+
V
V
∆V
/ 2
REF
V
COM
-
REFN Input Voltage
V
V
∆V
/ 2
REF
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)
0.8 ×
CLK
V
DD
Input High Threshold
V
V
IH
0.8 ×
OV
PD, OE, SLEEP, T/B
DD
4
_______________________________________________________________________________________
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V, OV
= 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
DD
DD
10kΩ resistor, V = 2V
(differential with respect to COM), C = 10pF at digital outputs, f
= 100MHz, T = T
to T
, unless
MAX
IN
P-P
L
CLK
A
MIN
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at
T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.2 ×
CLK
V
DD
Input Low Threshold
V
V
IL
0.2 ×
OV
PD, OE, SLEEP, T/B
DD
Input Hysteresis
Input Leakage
V
0.15
5
V
HYST
I
IH
V
V
= V
= 0
= OV
DD
20
IH
IL
DD
µA
pF
I
IL
20
0.2
10
Input Capacitance
C
IN
DIGITAL OUTPUTS ( D7A–D0A, D7B–D0B)
Output Voltage Low
V
I
I
= -200µA
V
V
OL
SINK
OV
0.2
-
DD
Output Voltage High
V
= 200µA
SOURCE
OH
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
I
OE = OV
OE = OV
µA
pF
LEAK
DD
C
5
OUT
DD
V
2.7
1.7
3.3
2.5
3.6
3.6
V
V
DD
OV
C = 15pF
L
DD
Operating, f
applied to both channels
= 20MHz at -1dB FS
INA & B
80
95
mA
Analog Supply Current
Output Supply Current
Analog Power Dissipation
I
VDD
Sleep mode
3.2
Shutdown, clock idle, PD = OE = OV
0.15
20
µA
DD
Operating, f
= 20MHz at -1dB FS
INA & B
11.5
mA
applied to both channels (Note 6)
I
OVDD
Sleep mode
2
2
µA
Shutdown, clock idle, PD = OE = OV
10
DD
Operating, f
= 20MHz at -1dB FS
INA & B
264
314
applied to both channels
mW
PDISS
PSRR
Sleep mode
10.6
0.5
3
Shutdown, clock idle, PD = OE = OV
66
µW
DD
Offset, V
5%
5%
DD
Power-Supply Rejection
mV/V
Gain, V
3
DD
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Time
t
C = 20pF (Notes 1, 7)
L
6
8.25
ns
DO
OE Fall to Output Enable Time
OE Rise to Output Disable Time
CLK Pulse Width High
t
5
5
ns
ns
ns
ns
ENABLE
t
DISABLE
t
Clock period: 10ns (Note 7)
Clock period: 10ns (Note 7)
5
0.5
0.5
CH
CLK Pulse Width Low
t
5
CL
_______________________________________________________________________________________
5
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V, OV
= 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
DD
DD
10kΩ resistor, V = 2V
(differential with respect to COM), C = 10pF at digital outputs, f
= 100MHz, T = T
to T
, unless
MAX
IN
P-P
L
CLK
A
MIN
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at
T
A
= +25°C.)
PARAMETER
Wake-Up Time
SYMBOL
CONDITIONS
Wake up from sleep mode
MIN
TYP
1
MAX
UNITS
t
µs
WAKE
Wake up from shutdown mode (Note 11)
20
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
f
f
f
= 20MHz at -1dB FS (Note 8)
= 20MHz at -1dB FS (Note 9)
= 20MHz at -1dB FS (Note 10)
-72
0.05
0.1
dB
dB
INA or B
INA or B
INA or B
Gain Matching
Phase Matching
Degrees
Note 1: Guaranteed by design. Not subject to production testing.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the total input power.
Note 3: Analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted FFT between two
applied input signals with the same magnitude (peak-to-peak) at f and f
.
IN2
IN1
Note 4: REFIN and REFOUT should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor.
Note 5: REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor.
Note 6: Typical analog output current at f
= 20MHz. For digital output currents vs. analog input frequency,
INA & B
see Typical Operating Characteristics.
Note 7: See Figure 3 for detailed system timing diagrams. Clock to data valid timing is measured from 50% of the clock
level to 50% of the data output level.
Note 8: Crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at DC level.
Crosstalk is measured by calculating the power ratio of the fundamental of each channel’s FFT.
Note 9: Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-
mental of the calculated FFT.
Note 10: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental
of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
Note 11: SINAD settles to within 0.5dB of its typical value in unbuffered external reference mode.
6
_______________________________________________________________________________________
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Typical Operating Characteristics
(V
noted.)
= 3.3V, OV
= 2.5V, V
= 2.048V, differential input at -1dB FS, f
= 100MHz, C ≈ 10pF, T = +25°C, unless otherwise
DD
DD
REFIN
CLK
L
A
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
f
f
f
= 100.050607MHz
= 49.7443997MHz
= 19.8708908MHz
f
f
f
= 100.050607MHz
= 114.9629350MHz
= 99.5010126MHz
f
f
f
= 100.050607MHz
= 19.8708908MHz
= 7.5355498MHz
CLK
INA
INB
CLK
INA
INB
CLK
INA
INB
AIN = -1dB FS
AIN = -1dB FS
AIN = -1dB FS
f
INA
COHERENT SAMPLING
COHERENT SAMPLING
COHERENT SAMPLING
f
INA
f
INA
HD3
HD2
HD3
HD3
HD2
f
INB
f
f
INB
INB
HD2
0
5
10 15 20 25 30 35 40 45 50
ANALOG INPUT FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45 50
ANALOG INPUT FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45 50
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
8192-POINT DATA RECORD)
0
50
48
46
44
42
40
0
f
f
f
= 100.007936MHz
= 10.022768MHz
= 10.047184MHz
AIN = -7dB FS
COHERENT SAMPLING
CHB
CLK
IN1
IN2
f
f
f
= 100.007936MHz
= 1.989904MHz
= 2.038736MHz
CLK
IN1
IN2
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
AIN = -7dB FS
CHA
COHERENT SAMPLING
f
f
IN1
f
IN1
f
IN2
IN2
7
8
9
10
11
12
13
0
40
80
120
160
200
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE + DISTORTION
vs. ANALOG INPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
50
48
46
44
42
40
-40
-48
-56
-64
-72
-80
80
72
64
56
48
40
CHA
CHA
CHB
CHB
CHB
CHA
0
40
80
120
160
200
0
40
80
120
160
200
0
40
80
120
160
200
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
7
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Typical Operating Characteristics (continued)
(V
noted.)
= 3.3V, OV
= 2.5V, V
= 2.048V, differential input at -1dB FS, f
= 100MHz, C ≈ 10pF, T = +25°C, unless otherwise
DD
DD
REFIN
CLK
L
A
SMALL-SIGNAL INPUT BANDWIDTH vs.
ANALOG INPUT FREQUENCY, DIFFERENTIAL
FULL-POWER INPUT BANDWIDTH vs.
ANALOG INPUT FREQUENCY, DIFFERENTIAL
SNR/SINAD, THD/SFDR vs. TEMPERATURE
90
80
70
60
50
40
30
1
2
f
= 19.87089082MHz
SFDR
V
IN
= 100mV
P-P
IN
0
-1
-2
-3
-4
-5
1
0
-1
-2
-3
-4
THD
SNR
SINAD
-40
-15
10
35
60
85
1
10
100
1000
1
10
100
1000
TEMPERATURE (°C)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE RATIO vs.
INPUT POWER (f = 19.87089082MHz)
TOTAL HARMONIC DISTORTION vs.
INPUT POWER (f = 19.87089082MHz)
SIGNAL-TO-NOISE + DISTORTION vs.
INPUT POWER (f = 19.87089082MHz)
IN
IN
IN
55
50
45
40
35
30
25
55
50
45
40
35
30
25
-45
-50
-55
-60
-65
-70
-75
-20
-16
-12
-8
-4
0
-20
-16
-12
-8
-4
0
-20
-16
-12
-8
-4
0
INPUT POWER (dB FS)
INPUT POWER (dB FS)
INPUT POWER (dB FS)
SPURIOUS-FREE DYNAMIC RANGE vs.
INPUT POWER (f = 19.87089082MHz)
INTEGRAL NONLINEARITY
(262144-POINT DATA RECORD)
DIFFERENTIAL NONLINEARITY
(262144-POINT DATA RECORD)
IN
75
70
65
60
55
50
45
0.5
0.4
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-20
-16
-12
-8
-4
0
0
32 64 98 128 160 192 224 256
DIGITAL OUTPUT CODE
0
32 64 98 128 160 192 224 256
DIGITAL OUTPUT CODE
INPUT POWER (dB FS)
8
_______________________________________________________________________________________
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Typical Operating Characteristics (continued)
(V
noted.)
= 3.3V, OV
= 2.5V, V
= 2.048V, differential input at -1dB FS, f
= 100MHz, C ≈ 10pF, T = +25°C, unless otherwise
DD
DD
REFIN
CLK L A
OFFSET ERROR vs. TEMPERATURE,
SNR/SINAD, THD/SFDR
vs. SAMPLING SPEED
EXTERNAL REFERENCE V
= 2.048V
REFIN
0.5
0.3
0.8
0.3
80
72
64
56
48
40
SFDR
f
= 19.87089082MHz
IN
CHB
CHA
CHA
THD
SNR
0.1
-0.2
-0.7
-1.2
-0.1
-0.3
CHB
SINAD
80 100
-40
-15
10
35
60
85
-40
-15
10
35
60
85
0
20
40
60
120
TEMPERATURE (°C)
TEMPERATURE (°C)
SAMPLING SPEED (Msps)
DIGITAL SUPPLY CURRENT
vs. ANALOG INPUT FREQUENCY
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
SNR/SINAD, THD/SFDR
vs. CLOCK DUTY CYCLE
90
86
82
78
74
70
20
16
12
8
80
70
60
50
40
30
SFDR
THD
SNR
SINAD
4
f
IN
= 19.87089082MHz
0
-40
-15
10
35
60
85
0
10
20
30
40
50
40
44
48
52
56
60
TEMPERATURE (°C)
ANALOG INPUT FREQUENCY (MHz)
CLOCK DUTY CYCLE (%)
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.0430
2.0425
2.0420
2.0415
2.0410
2.0405
2.0400
2.0500
2.0460
2.0420
2.0380
2.0340
2.0300
2.70 2.85 3.00 3.15 3.30 3.45 3.60
-40
-15
10
35
60
85
V
DD
(V)
TEMPERATURE (°C)
_______________________________________________________________________________________
9
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Pin Description
PIN
NAME
FUNCTION
1
COM
Common-Mode Voltage I/O. Bypass to GND with a ≥0.1µF capacitor.
Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with
0.1µF.
2, 6, 11, 14, 15
V
DD
3, 7, 10, 13, 16
GND
INA+
INA-
INB-
INB+
CLK
Analog Ground
4
5
Channel A Positive Analog Input. For single-ended operation connect signal source to INA+.
Channel A Negative Analog Input. For single-ended operation connect INA- to COM.
Channel B Negative Analog Input. For single-ended operation connect INB- to COM.
Channel B Positive Analog Input. For single-ended operation connect signal source to INB+.
Converter Clock Input
8
9
12
T/B Selects the ADC Digital Output Format
High: Two’s complement
Low: Straight offset binary
17
18
19
20
T/B
SLEEP
PD
Sleep Mode Input
High: Disables both quantizers, but leaves the reference bias circuit active
Low: Normal operation
Active-High Power-Down Input
High: Power-down mode
Low: Normal operation
Active-Low Output Enable Input
High: Digital outputs disabled
Low: Digital outputs enabled
OE
21
D7B
D6B
D5B
D4B
D3B
D2B
D1B
D0B
N.C.
OGND
Three-State Digital Output, Bit 7 (MSB), Channel B
Three-State Digital Output, Bit 6, Channel B
Three-State Digital Output, Bit 5, Channel B
Three-State Digital Output, Bit 4, Channel B
Three-State Digital Output, Bit 3, Channel B
Three-State Digital Output, Bit 2, Channel B
Three-State Digital Output, Bit 1, Channel B
Three-State Digital Output, Bit 0, Channel B
No Connection
22
23
24
25
26
27
28
29, 30, 35, 36
31, 34
Output Driver Ground
Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in parallel
with 0.1µF.
32, 33
OV
DD
37
38
39
40
41
D0A
D1A
D2A
D3A
D4A
Three-State Digital Output, Bit 0, Channel A
Three-State Digital Output, Bit 1, Channel A
Three-State Digital Output, Bit 2, Channel A
Three-State Digital Output, Bit 3, Channel A
Three-State Digital Output, Bit 4, Channel A
10 ______________________________________________________________________________________
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Pin Description (continued)
PIN
42
NAME
D5A
FUNCTION
Three-State Digital Output, Bit 5, Channel A
Three-State Digital Output, Bit 6, Channel A
43
D6A
44
D7A
Three-State Digital Output, Bit 7 (MSB), Channel A
Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor-
divider.
45
46
47
48
REFOUT
REFIN
REFP
Reference Input. V
= 2 x (V
- V
REFN
).
REFIN
REFP
Bypass to GND with a >0.1µF capacitor.
Positive Reference I/O. Conversion range is (V
Bypass to GND with a >0.1µF capacitor.
- V
).
REFN
REFP
Negative Reference I/O. Conversion range is (V
Bypass to GND with a >0.1µF capacitor.
- V
).
REFN
REFP
REFN
2-BIT FLASH
ADC
2-BIT FLASH
ADC
STAGE 1
STAGE 2
STAGE 6
STAGE 7
STAGE 1
STAGE 2
STAGE 6
STAGE 7
DIGITAL ALIGNMENT LOGIC
8
DIGITAL ALIGNMENT LOGIC
8
T/H
T/H
D7A–D0A
D7B–D0B
V
INA
V
INB
V
INA
V
INB
= INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED)
= INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)
Figure 1. Pipelined Architecture—Stage Blocks
back into analog voltages, which are then subtracted
from the original held input signals. The resulting error
signals are then multiplied by two, and the residues are
passed along to the next pipeline stages where the
process is repeated until the signals have been processed
by all seven stages.
Detailed Description
The MAX1198 uses a seven-stage, fully differential
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is five clock cycles.
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the
input T/H circuits in both track and hold mode. In track
mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
Flash ADCs convert the held input voltages into a digi-
tal code. Internal MDACs convert the digitized results
______________________________________________________________________________________ 11
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
INTERNAL
COM
S5a
BIAS
S2a
C1a
S3a
S4a
S4b
INA+
INA-
OUT
OUT
C2a
C2b
S4c
S1
C1b
S3b
S5b
COM
S2b
INTERNAL
BIAS
CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
HOLD
HOLD
INTERNAL
BIAS
TRACK
TRACK
COM
S5a
S2a
C1a
S3a
S4a
S4b
INB+
INB-
OUT
OUT
C2a
C2b
S4c
S1
MAX1198
C1b
S3b
S5b
COM
S2b
INTERNAL
BIAS
Figure 2. MAX1198 T/H Amplifiers
are closed. The fully differential circuits sample the
input signals onto the two capacitors (C2a and C2b)
through switches S4a and S4b. S2a and S2b set the
common mode for the amplifier input, and open simul-
taneously with S1 sampling the input waveform.
Switches S4a, S4b, S5a, and S5b are then opened
before switches S3a and S3b connect capacitors C1a
and C1b to the output of the amplifier and switch S4c is
closed. The resulting differential voltages are held on
capacitors C2a and C2b. The amplifiers are used to
charge capacitors C1a and C1b to the same values
originally held on C2a and C2b. These values are then
presented to the first-stage quantizers and isolate the
pipelines from the fast-changing inputs. The wide input
bandwidth T/H amplifiers allow the MAX1198 to track
and sample/hold analog inputs of high frequencies
(>Nyquist). Both ADC inputs (INA+, INB+ and INA-,
INB-) can be driven either differentially or single ended.
12 ______________________________________________________________________________________
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
5-CLOCK-CYCLE LATENCY
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
ANALOG INPUT
CLOCK INPUT
t
AD
t
t
CH
t
CL
DO
DATA OUTPUT
N - 6
N - 5
N - 4
N - 4
N - 3
N - 3
N - 2
N - 1
N - 1
N
N
N + 1
D7A–D0A
DATA OUTPUT
N - 6
N - 5
N - 2
N + 1
D7B–D0B
Figure 3. System Timing Diagram
Match the impedance of INA+ and INA-, as well as
INB+ and INB-, and set the common-mode voltage to
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for REFP, COM, and REFN. With their buffers shut
down, these nodes become high-impedance inputs
and can be driven through separate, external reference
sources.
mid supply (V /2) for optimum performance.
DD
Analog Inputs and Reference
Configurations
The full-scale range of the MAX1198 is determined by
the internally generated voltage difference between
For detailed circuit suggestions and how to drive this
dual ADC in buffered/unbuffered external reference
mode, see the Applications Information section.
REFP (V /2 + V
/4) and REFN (V /2 - V
/4).
REFIN
DD
REFIN
DD
The full-scale range for both on-chip ADCs is
adjustable through the REFIN pin, which is provided for
this purpose.
Clock Input (CLK)
The MAX1198’s CLK input accepts a CMOS-compati-
ble clock signal. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). In particular,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR perfor-
mance of the on-chip ADCs as follows:
The MAX1198 provides three modes of reference operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, connect the internal refer-
ence output REFOUT to REFIN through a resistor (e.g.,
10kΩ) or resistor-divider, if an application requires a
reduced full-scale range. For stability and noise-filtering
purposes, bypass REFIN with a >10nF capacitor to
GND. In internal reference mode, REFOUT, COM,
REFP, and REFN become low-impedance outputs.
1
SNR = 20 × log
2 × π × f × t
IN
AJ
where f represents the analog input frequency and
IN
In buffered external reference mode, adjust the refer-
ence voltage levels externally by applying a stable and
accurate voltage at REFIN. In this mode, COM, REFP,
and REFN are outputs. REFOUT can be left open or
connected to REFIN through a >10kΩ resistor.
t
AJ
is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines.
______________________________________________________________________________________ 13
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Table 1. MAX1198 Output Codes For
OE
Differential Inputs
t
t
DISABLE
ENABLE
STRAIGHT
OFFSET
BINARY
T/B = 0
TWO’S
COMPLEMENT
DIFFERENTIAL
INPUT
VOLTAGE*
DIFFERENTIAL
INPUT
OUTPUT
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
VALID DATA
VALID DATA
D7A–D0A
T/B = 1
+Full Scale
- 1LSB
OUTPUT
D7B–D0B
V
x 255/256
1111 1111
1000 0001
0111 1111
REF
V
x 1/256
0
+1LSB
0000 0001
0000 0000
1111 1111
REF
Bipolar Zero 1000 0000
Figure 4. Output Timing Diagram
-V
REF
x 1/256
-1LSB
0111 1111
0000 0001
0000 0000
The MAX1198 clock input operates with a voltage thresh-
-Full Scale
+ 1LSB
-V
x 255/256
x 256/256
1000 0001
1000 0000
REF
REF
old set to V /2. Clock inputs with a duty cycle other
DD
than 50% must meet the specifications for high and low
-V
*V
-Full Scale
periods as stated in the Electrical Characteristics table.
= V
- V
REFN
REF
REFP
System Timing Requirements
Figure 3 depicts the relationship between the clock
input, analog input, and data output. The MAX1198
samples at the rising edge of the input clock. Output
data for channels A and B is valid on the next rising
edge of the input clock. The output data has an internal
latency of five clock cycles. Figure 3 also determines
the relationship between the input clock parameters
and the valid output data on channels A and B.
Power-Down and Sleep Modes
The MAX1198 offers two power-save modes—sleep
mode (SLEEP) and full power-down (PD) mode. In
sleep mode (SLEEP = 1), only the reference bias circuit
is active (both ADCs are disabled), and current con-
sumption is reduced to 3.2mA.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to power-down. Pulling OE high forces the
digital outputs into a high-impedance state.
Digital Output Data (D0A/B–D7A/B), Output
Data Format Selection (T/B), Output
Enable (OE)
Applications Information
All digital outputs, D0A–D7A (channel A) and D0B–D7B
(channel B), are TTL/CMOS-logic compatible. There is a
five-clock-cycle latency between any particular sample
and its corresponding output data. The output
coding can either be straight offset binary or two’s com-
plement (Table 1) controlled by a single pin (T/B). Pull
T/B low to select offset binary and high to activate two’s
complement output coding. The capacitive load on the
digital outputs D0A–D7A and D0B–D7B should be kept
as low as possible (<15pF), to avoid large digital cur-
rents that could feed back into the analog portion of the
MAX1198, thereby degrading its dynamic performance.
Using buffers on the digital outputs of the ADCs can fur-
ther isolate the digital outputs from heavy capacitive
loads. To further improve the dynamic performance of
the MAX1198, small-series resistors (e.g., 100Ω) may
be added to the digital output paths close to the
MAX1198.
Figure 5 depicts a typical application circuit containing
two single-ended-to-differential converters. The internal
reference provides a V /2 output voltage for level-
DD
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
amplifier suppresses some of the wideband noise
associated with high-speed op amps. The user can
select the R
and C values to optimize the filter per-
IN
ISO
formance, to suit a particular application. For the appli-
cation in Figure 5, a R of 50Ω is placed before the
ISO
capacitive load to prevent ringing and oscillation. The
22pF C capacitor acts as a small filter capacitor.
IN
Using Transformer Coupling
An RF transformer (Figure 6) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX1198 for
optimum performance. Connecting the center tap of the
transformer to COM provides a V /2 DC level shift to
DD
the input. Although a 1:1 transformer is shown, a step-
up transformer can be selected to reduce the drive
Figure 4 displays the timing relationship between out-
put enable and data output valid, as well as power-
down/wakeup and data output valid.
14 ______________________________________________________________________________________
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
+5V
0.1µF
LOWPASS FILTER
INA-
MAX4108
300Ω
R
IS0
50Ω
0.1µF
C
IN
22pF
0.1µF
-5V
600Ω
600Ω
300Ω
+5V
COM
INA+
0.1µF
+5V
0.1µF
0.1µF
600Ω
INPUT
0.1µF
0.1µF
LOWPASS FILTER
MAX4108
300Ω
300Ω
MAX4108
R
IS0
C
IN
22pF
50Ω
-5V
-5V
+5V
300Ω
300Ω
600Ω
MAX1198
0.1µF
0.1µF
LOWPASS FILTER
INB-
MAX4108
300Ω
R
IS0
50Ω
0.1µF
C
IN
22pF
-5V
600Ω
+5V
600Ω
600Ω
300Ω
0.1µF
0.1µF
0.1µF
+5V
INPUT
LOWPASS FILTER
0.1µF
MAX4108
300Ω
300Ω
INB+
MAX4108
R
IS0
50Ω
C
IN
22pF
-5V
0.1µF
-5V
300Ω
300Ω
600Ω
Figure 5. Typical Application for Single-Ended-to-Differential Conversion
______________________________________________________________________________________ 15
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
25Ω
REFP
INA+
22pF
1kΩ
R
ISO
50Ω
V
IN
0.1µF
0.1µF
INA+
COM
INA-
1
2
6
5
4
T1
V
IN
MAX4108
C
IN
22pF
100Ω
100Ω
1kΩ
N.C.
COM
2.2µF
0.1µF
3
REFN
0.1µF
R
ISO
50Ω
MINICIRCUITS
TT1–6-KK81
25Ω
25Ω
INA-
INB+
C
IN
22pF
22pF
22pF
REFP
MAX1198
MAX1198
R
1kΩ
ISO
50Ω
V
IN
0.1µF
INB+
0.1µF
MAX4108
1
2
3
6
5
4
T1
C
IN
22pF
V
IN
100Ω
100Ω
1kΩ
N.C.
REFN
2.2µF
0.1µF
0.1µF
R
ISO
50Ω
MINICIRCUITS
TT1-6-KK81
INB-
25Ω
C
IN
22pF
INB-
22pF
Figure 7. Using an Op Amp for Single-Ended, AC-Coupled
Input Drive
Figure 6. Transformer-Coupled Input Drive
requirements. A reduced signal swing from the input
driver, such as an op amp, can also improve the overall
distortion.
Buffered External Reference Drives
Multiple ADCs
Multiple-converter systems based on the MAX1198 are
well suited for use with a common reference voltage.
The REFIN pin of those converters can be connected
directly to an external reference source.
In general, the MAX1198 provides better SFDR and
THD with fully differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires half
the signal swing compared to single-ended mode.
A precision bandgap reference like the MAX6062 gen-
erates an external DC level of 2.048V (Figure 8), and
exhibits a noise-voltage density of 150nV/√Hz. Its out-
put passes through a 1-pole lowpass filter (with 10Hz
cutoff frequency) to the MAX4250, which buffers the
reference before its output is applied to a second 10Hz
lowpass filter. The MAX4250 provides a low offset volt-
age (for high gain accuracy) and a low noise level. The
passive 10Hz filter following the buffer attenuates noise
produced in the voltage reference and buffer stages.
This filtered noise density, which decreases for higher
frequencies, meets the noise levels specified for preci-
sion ADC operation.
Single-Ended AC-Coupled Input Signal
Figure 7 shows an AC-coupled, single-ended applica-
tion. Amplifiers like the MAX4108 provide high speed,
high bandwidth, low noise, and low distortion to main-
tain the integrity of the input signal.
16 ______________________________________________________________________________________
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
3.3V
3.3V
0.1µF
N.C.
29
31
32
1
REFOUT
REFIN
REFP
2.048V
0.1µF
1
MAX6062
3
0.1µF
16.2kΩ
REFN
N = 1
5
2
3
4
2
162Ω
COM
1
MAX1198
MAX4250
2
1µF
100µF
10Hz LOWPASS
FILTER
0.1µF 0.1µF 0.1µF
10Hz LOWPASS
FILTER
2.2µF
10V
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs.
0.1µF
29
31
32
1
N.C.
REFOUT
REFIN
REFP
N = 1000
0.1µF
REFN
MAX1198
2
COM
0.1µF 0.1µF 0.1µF
Figure 8. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference
Note that the common power supply for all active com-
ponents removes any concern regarding power-supply
sequencing when powering up or down. With the out-
puts of the MAX4252 matching better than 0.1%, the
buffers and subsequent lowpass filters can be replicat-
ed to support as many as 32 ADCs. For applications
that require more than 32 matched ADCs, a voltage
reference and divider string common to all converters
is highly recommended.
Unbuffered External Reference Drives
Multiple ADCs
Connecting each REFIN to analog ground disables the
internal reference of each device, allowing the internal
reference ladders to be driven directly by a set of
external reference sources. Followed by a 10Hz low-
pass filter and precision voltage-divider, the MAX6066
generates a DC level of 2.500V. The buffered outputs
of this divider are set to 2.0V, 1.5V, and 1.0V, with an
accuracy that depends on the tolerance of the divider
resistors.
Typical QAM Demodulation Application
A frequently used modulation technique in digital com-
munications applications is quadrature amplitude
modulation (QAM). Typically found in spread-spec-
trum-based systems, a QAM signal represents a carrier
frequency modulated in both amplitude and phase. At
the transmitter, modulating the baseband signal with
quadrature outputs, a local oscillator followed by sub-
sequent upconversion can generate the QAM signal.
The result is an in-phase (I) and a quadrature (Q) carri-
er component, where the Q component is 90° phase
These three voltages are buffered by the MAX4252,
which provides low noise and low DC offset. The indi-
vidual voltage followers are connected to 10Hz low-
pass filters, which filter both the reference voltage and
amplifier noise to a level of 3nV/√Hz. The 2.0V and 1.0V
reference voltages set the differential full-scale range
of the associated ADCs at 2V . The 2.0V and 1.0V
P-P
buffers drive the ADC’s internal ladder resistances
between them.
______________________________________________________________________________________ 17
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
3.3V
0.1µF
N.C.
29
31
32
1
REFOUT
REFIN
REFP
1
MAX6066
3
2.0V
3.3V
4
4
4
21.5kΩ
REFN
N = 1
2.0V AT 8mA
2
3
2
1/4 MAX4252
1
47Ω
MAX1198
2
COM
10µF
6V
330µF
6V
11
21.5kΩ
1.47kΩ
0.1µF 0.1µF 0.1µF
1.5V
3.3V
1.5V AT 0mA
5
6
1/4 MAX4252
7
47Ω
1µF
10µF
330µF
11
6V
6V
21.5kΩ
2.2µF
10V
1.47kΩ
0.1µF
3.3V
0.1µF
1.0V
3.3V
1.0V AT -8mA
10
9
1/4 MAX4252
8
47Ω
21.5kΩ
21.5kΩ
330µF
6V
29
31
32
1
N.C.
10µF
11
REFOUT
REFIN
REFP
MAX4254 POWER-SUPPLY
6V
BYPASSING. PLACE CAPACITOR
AS CLOSE AS POSSIBLE TO
THE OP AMP.
1.47kΩ
N = 32
REFN
MAX1198
2
COM
0.1µF 0.1µF 0.1µF
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 32 ADCs.
Figure 9. External Unbuffered Reference Drive with MAX4252 and MAX6066
shifted with respect to the in-phase component. At the
receiver, the QAM signal is divided down into its I and
Q components, essentially representing the modulation
Grounding, Bypassing,
and Board Layout
The MAX1198 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
process reversed. Figure 10 displays the demodulation
process performed in the analog domain, using the
dual matched 3.3V, 8-bit ADC MAX1198 and the
MAX2451 quadrature demodulator to recover and
digitize the I and Q baseband signals. Before being
digitized by the MAX1198, the mixed down-signal com-
ponents may be filtered by matched analog filters, such
as Nyquist or pulse-shaping filters, which remove
unwanted images from the mixing process, thereby
enhancing the overall signal-to-noise (SNR) perfor-
mance and minimizing intersymbol interference.
inductance. Bypass V , REFP, REFN, and COM with
DD
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OV ) to OGND. Multilayer
DD
boards with separated ground and power planes
produce the highest level of signal integrity. Consider
the use of a split ground plane arranged to match the
18 ______________________________________________________________________________________
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
MAX2451
INA+
INA-
0°
DSP
90°
POST-
MAX1198
PROCESSING
INB+
INB-
DOWNCONVERTER
÷
8
Figure 10. Typical QAM Application Using the MAX1198
Static Parameter Definitions
CLK
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1198 are mea-
sured using the best-straight-line-fit method.
ANALOG
INPUT
t
AD
t
AJ
SAMPLED
DATA (T/H)
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
HOLD
TRACK
TRACK
T/H
Figure 11. T/H Aperture Timing
physical location of the analog ground (GND) and the
digital output driver ground (OGND) on the ADC’s
package. The two ground planes should be joined at a
single point so the noisy digital ground currents do not
interfere with the analog ground plane. The ideal loca-
tion for this connection can be determined experimen-
tally at a point along the gap between the two ground
planes, which produces optimum results. Make this
connection with a low-value, surface-mount resistor (1Ω
to 5Ω), a ferrite bead, or a direct short.
Dynamic Parameter Definitions
Aperture Jitter
Figure 11 depicts the aperture jitter (t ), which is the
AJ
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 11).
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N-bits):
Alternatively, all ground pins could share the same
ground plane if the ground plane is sufficiently isolated
from any noisy, digital systems ground plane (e.g.,
downstream output buffer or DSP ground plane). Route
high-speed digital signal traces away from the sensitive
analog traces of either channel. Make sure to isolate
the analog input lines to each respective converter to
minimize channel-to-channel crosstalk. Keep all signal
lines short and free of 90° turns.
SNR
= 6.02 ✕ N + 1.76
dB dB
dB[max]
______________________________________________________________________________________ 19
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
In reality, there are other noise sources besides quanti-
2
2
2
2
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
V
+ V + V + V
3 4 5
2
THD = 20 × log
V
1
where V is the fundamental amplitude, and V through
1
2
V
are the amplitudes of the 2nd- through 5th-order
5
harmonics.
Signal-to-Noise Plus Distortion
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components minus the fundamental
and the DC offset.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio
expressed in decibels of the RMS amplitude of the fun-
damental (maximum signal component) to the RMS
value of the next largest spurious component, exclud-
ing DC offset.
Effective Number of Bits
Effective number of bits (ENOB) specifies the dynamic
performance of an ADC at a specific input frequency
and sampling rate. An ideal ADC’s error consists of
quantization noise only. ENOB for a full-scale sinusoidal
input waveform is computed from:
Intermodulation Distortion
The two-tone intermodulation distortion (IMD) is the
ratio expressed in decibels of either input tone to the
worst third-order (or higher) intermodulation products.
The individual input tone levels are at -7dB full scale
and their envelope is at -1dB full scale.
SINAD−1.76
ENOB =
6.02
Total Harmonic Distortion
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
Chip Information
TRANSISTOR COUNT: 11,601
PROCESS: CMOS
20 ______________________________________________________________________________________
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Functional Diagram
V
OGND
OV
DD
GND
DD
INA+
8
8
OUTPUT
DRIVERS
D7A–D0A
ADC
DEC
T/H
INA-
CLK
CONTROL
OE
INB+
INB-
8
8
OUTPUT
DRIVERS
DEC
T/H
ADC
D7B–D0B
T/B
PD
SLEEP
REFERENCE
MAX1198
REFOUT
REFN COM REFP
REFIN
Pin-Compatible Upgrades
(Sampling Speed and Resolution)
SAMPLING SPEED
8-BIT PART
10-BIT PART
(Msps)
MAX1195
MAX1197
MAX1198
MAX1196*
MAX1183
MAX1182
MAX1180
MAX1186
40
60
100
40, multiplexed
*Future product, please contact factory for availability.
______________________________________________________________________________________ 21
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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