MAX1178ACUP-T_技术文档

19-2755; Rev 1; 8/03

16-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

General Description

Features

The MAX1178/MAX1188 16-bit, low-power, successive-

approximation analog-to-digital converters (ADCs) fea-

ture automatic power-down, a factory-trimmed internal

clock, and a byte-wide parallel interface. The devices

operate from a single +4.75V to +5.25V analog supply

and feature a separate digital supply input for direct

interface with a +2.7V to +5.25V digital logic.

ꢀ Byte-Wide Parallel Interface

ꢀ Analog Input Voltage Range: ±±1Vꢀ ±ꢁV

ꢀ Single +4.7ꢁV to +ꢁ.2ꢁV Analog Supply Voltage

ꢀ Interface with +2.7V to +ꢁ.2ꢁV Digital Logic

ꢀ ±2 LSB IꢂL

ꢀ ±± LSB DꢂL

The MAX1188 accepts a bipolar analog input voltage

range of 1ꢀV, while the MAX1178 accepts a bipolar

analog input voltage range of 5V. All devices consume

no more than 26.5mW at a sampling rate of 135ksps

when using an external reference, and 31mW when using

the internal +4.ꢀ96V reference. AutoShutdown™ reduces

supply current to ꢀ.4mA at 1ꢀksps.

ꢀ Low Supply Current (max)

2.9mA (External Reference)

3.8mA (Internal Reference)

ꢁµA AutoShutdown Mode

ꢀ Small Footprint

ꢀ 21-Pin TSSOP Package

The MAX1178/MAX1188 are ideal for high-perfor-

mance, battery-powered, data-acquisition applications.

Excellent AC performance (THD = -1ꢀꢀdB) and DC

accuracy ( 2 ꢁSB ꢂIꢁ) make the MAX1178/MAX1188

ideal for industrial process control, instrumentation, and

medical applications.

Ordering Information

IꢂPUT

PIꢂ-

VOLTAGE

RAꢂGE (V)

PART

TEMP RAꢂGE

PACKAGE

The MAX1178/MAX1188 are available in a 2ꢀ-pin

TSSOP package and are fully specified over the -4ꢀ°C

to +85°C extended temperature range and the ꢀ°C to

+7ꢀ°C commercial temperature range.

MAX±±78ACUP

MAX1178BCUP

MAX1178CCUP

0°C to +70°C

20 TSSOP

5

MAX1178AEUP -40°C to +85°C

MAX1178BEUP -40°C to +85°C

MAX1178CEUP -40°C to +85°C

Ordering Information continued at end of data sheet.

Typical Operating Circuit

+5V ANALOG +5V DIGITAL

Applications

Temperature Sensing and Monitoring

ꢂndustrial Process Control

ꢂ/O Modules

0.1µF

Data-Acquisition Systems

Precision ꢂnstrumentation

AV

DD

DV

µP DATA

BUS

DD

D0–D7

OR

ANALOG INPUT

AIN

D8–D15

MAX1178

MAX1188

EOC

R/C

CS

REF

REFADJ

HBEN

HIGH

BYTE

0.1µF

10µF

AGND DGND

Pin Configuration and Functional Diagram appear at end of

data sheet.

LOW

BYTE

AutoShutdown is a trademark of Maxim Integrated Products, Inc.

________________________________________________________________ Maxim Integrated Products

±

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

16-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

Continuous Power Dissipation (T = +70°C)

TSSOP (derate 10.9mW/°C above +70°C) ..................879mW

A

AGND to DGND.....................................................-0.3V to +0.3V

AIN to AGND .....................................................-16.5V to +16.5V

Operating Temperature Ranges

MAX11_ _ _CUP..................................................0°C to +70°C

MAX11_ _ _EUP...............................................-40°C to +85°C

Storage Temperature Range.............................-65°C to +150°C

Junction Temperature......................................................+150°C

Lead Temperature (soldering, 10s) .................................+300°C

REF, REFADJ to AGND............................-0.3V to (AV

+ 0.3V)

DD

CS, R/C, HBEN to DGND .........................................-0.3V to +6V

D_, EOC to DGND ...................................-0.3V to (DV + 0.3V)

DD

Maximum Continuous Current into Any Pin ........................50mA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(AV

= DV

= +5V 5ꢀ, external reꢁerence = +4.096V, C

= 10µF, C

= 0.1µF, V

= AV , T = T

to T

,

DD

REF

REFADJ

DD

A

MIN

MAX

unless otherwise noted. Typical values are at T = +25°C.)

A

PARAMETER

DC ACCURACY

SYMBOL

RES

COꢂDITIOꢂS

MIꢂ

TYP

MAX

UꢂITS

Bits

Resolution

16

-1

MAX11_ _A

+1

+1.5

+2

No missing codes

over temperature

Diꢁꢁerential Nonlinearity

DNL

LSB

MAX11_ _B

MAX11_ _C

-1.0

-1

MAX11_ _A

MAX11_ _B

MAX11_ _C

-2

+2

Integral Nonlinearity

Transition Noise

INL

LSB

-2

+2

-4

+4

RMS noise, external reꢁerence

Internal reꢁerence

0.6

0.75

0

LSB

RMS

Oꢁꢁset Error

Gain Error

Oꢁꢁset Driꢁt

Gain Driꢁt

-10

+10

0.2

mV

0

ꢀFSR

µV/°C

16

1

ppm/°C

AC ACCURACY (ꢁ = 1kHz, V

= ꢁull range, 135ksps)

IN

AIN

Signal-to-Noise Plus Distortion

Signal-to-Noise Ratio

SINAD

SNR

86

87

90

91

dB

Total Harmonic Distortion

Spurious-Free Dynamic Range

AꢂALOG IꢂPUT

THD

-100

103

-92

SFDR

92

MAX1178

-5

+5

+10

9.2

Input Range

V

AIN

MAX1188

-10

5.3

3.0

7.8

6.0

Normal operation

6.9

10

MAX1178

Shutdown mode

Normal operation

Shutdown mode

Input Resistance

R

kΩ

AIN

13.0

MAX1188

2

_______________________________________________________________________________________

16-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

ELECTRICAL CHARACTERISTICS (continued)

(AV

= DV

= +5V 5ꢀ, external reꢁerence = +4.096V, C

= 10µF, C

= 0.1µF, V

= AV , T = T

to T

,

DD

REF

REFADJ

DD

A

MIN

MAX

unless otherwise noted. Typical values are at T = +25°C.)

A

PARAMETER

SYMBOL

COꢂDITIOꢂS

Normal operation

MIꢂ

-1.8

TYP

MAX

UꢂITS

+0.4

+1.8

+1.2

+1.8

MAX1178,

-5V ≤ V

≤ +5V

AIN

Shutdown mode

Normal operation

Shutdown mode

Input Current

I

mA

AIN

MAX1188,

-10V ≤ V

≤ +10V

AIN

MAX1178, V

operating mode

= +5V, shutdown mode to

AIN

1

1.4

0.7

Input Current Step at Power-Up

I

mA

pF

PU

MAX1188, V

= +10V, shutdown mode to

AIN

0.5

10

operating mode

Input Capacitance

C

IN

IꢂTERꢂAL REFEREꢂCE

REF Output Voltage

V

4.056

3.8

4.096

35

4.136

V

REF

REF Output Tempco

ppm/°C

mA

REF Short-Circuit Current

EXTERꢂAL REFEREꢂCE

I

10

REF-SC

REF and REFADJ Input-Voltage

Range

4.2

V

AV

-

AV

-

DD

REFADJ Buꢁꢁer-Disable Threshold

REF Input Current

0.4

0.1

Normal mode, ꢁ

= 135ksps

60

0.1

16

100

10

SAMPLE

I

µA

REF

Shutdown mode (Note 1)

REFADJ = AV

REFADJ Input Current

I

REFADJ

DD

DIGITAL IꢂPUTS/OUTPUTS

I

= 0.5mA, DV

= +5.25V

= +2.7V to +5.25V, DV

-

DD

SOURCE

DD

Output High Voltage

Output Low Voltage

Input High Voltage

Input Low Voltage

V

OH

AV

0.4

DD

I

= 1.6mA, DV

= +5.25V

= +2.7V to +5.25V,

DD

SINK

V

0.4

OL

AV

DD

0.7 ×

DV

V

IH

DD

0.3 ×

V

IL

DV

DD

Input Leakage Current

Input Hysteresis

Digital input = DV

or 0V

-1

+1

µA

V

DD

V

0.2

15

HYST

Input Capacitance

C

pF

µA

pF

IN

Tri-State Output Leakage

Tri-State Output Capacitance

I

10

OZ

C

15

OZ

_______________________________________________________________________________________

3

16-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

ELECTRICAL CHARACTERISTICS (continued)

(AV

= DV

= +5V 5ꢀ, external reꢁerence = +4.096V, C

= 10µF, C

= 0.1µF, V

= AV , T = T

to T

,

DD

REF

REFADJ

DD

A

MIN

MAX

unless otherwise noted. Typical values are at T = +25°C.)

A

PARAMETER

POWER SUPPLIES

SYMBOL

COꢂDITIOꢂS

MIꢂ

TYP

MAX

UꢂITS

Analog Supply Voltage

Digital Supply Voltage

AV

DV

4.75

2.70

5.25

5.3

V

DD

External reꢁerence, 135ksps

Internal reꢁerence, 135ksps

4

Analog Supply Current

I

mA

µA

AVDD

5.2

6.2

Shutdown mode (Note 1), digital input =

DV or 0V

0.5

3.7

5

Shutdown Supply Current

I

DD

SHDN

DVDD

Standby mode

mA

Digital Supply Current

Power-Supply Rejection

I

0.75

AV

= DV

= 4.75V to 5.25V

DD

3.5

LSB

DD

TIMIꢂG CHARACTERISTICS (Figures ± and 2)

(AV

= +4.75V to +5.25V, DV

= +2.7V to AV , external reꢁerence = +4.096V, C

= 10µF, C

= 0.1µF, V

= AV

,

DD

REF

REFADJ

DD

C

LOAD

= 20pF, T = T

to T

.)

A

MIN

MAX

PARAMETER

SYMBOL

COꢂDITIOꢂS

MIꢂ

TYP

MAX

UꢂITS

ksps

µs

Maximum Sampling Rate

Acquisition Time

ꢁ

135

SAMPLE-MAX

t

2

ACQ

Conversion Time

t

4.7

µs

CONV

CS Pulse-Width High

t

(Note 2)

40

60

0

ns

CSH

DV

= 4.75V to 5.25V

DD

CS Pulse-Width Low (Note 2)

R/C to CS Fall Setup Time

R/C to CS Fall Hold Time

t

ns

CSL

= 2.7V to 5.25V

t

DS

DV

= 4.75V to 5.25V

= 2.7V to 5.25V

= 4.75V to 5.25V

= 2.7V to 5.25V

40

60

DD

t

DH

40

80

CS to Output Data Valid

EOC Fall to CS Fall

t

ns

DO

t

0

DV

= 4.75V to 5.25V

= 2.7V to 5.25V

= 4.75V to 5.25V

= 2.7V to 5.25V

= 4.75V to 5.25V

= 2.7V to 5.25V

40

80

40

80

40

80

DD

CS Rise to EOC Rise

t

EOC

Bus Relinquish Time

t

ns

BR

HBEN Transition to Output Data

Valid

t

1

DO

ꢂote ±: Maximum speciꢁication is limited by automated test equipment.

ꢂote 2: To ensure best perꢁormance, ꢁinish reading the data and wait t beꢁore starting a new acquisition.

BR

4

_______________________________________________________________________________________

16-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

Typical Operating Characteristics

(Typical Operating Circuit, AV

= DV

= +5V, external reꢁerence = +4.096V, C

= 10µF, C

= 0.1µF, V

= AV

,

DD

REF

REFADJ

DD

C

LOAD

= 20pF. Typical values are at T = +25°C, unless otherwise noted.)

A

SUPPLY CURRENT (AV + DV

DD

)

DD

INL vs. CODE

DNL vs. CODE

vs. TEMPERATURE

MAX1178/88 toc01

MAX1178/88 toc02

2.5

2.0

2.5

2.0

4.80

4.75

4.70

4.65

4.60

4.55

4.50

4.45

4.40

5.25V

5.0V

1.5

1.0

0.5

0

-0.5

-1.0

-1.5

-2.0

-2.5

-0.5

-1.0

-1.5

-2.0

-2.5

4.75V

= 135ksps

f

SAMPLE

SHUTDOWN MODE

BETWEEN CONVERSIONS

0

10,000 20,000 30,000 40,000 50,000 60,000

CODE

0

10,000 20,000 30,000 40,000 50,000 60,000

CODE

80

-40

-20

0

20

40

60

TEMPERATURE (°C)

SUPPLY CURRENT (AV + DV

DD

)

DD

SHUTDOWN CURRENT (AV + DV )

DD DD

OFFSET ERROR vs. TEMPERATURE

vs. SAMPLE RATE

vs. TEMPERATURE

10

1

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

10

8

NO CONVERSIONS

6

STANDBY MODE

4

0.1

2

0

SHUTDOWN MODE

0.01

0.001

-2

-4

-6

-8

-10

MAX1188

MAX1178

V

AIN

= 0V

0.0001

0.01

0.1

1

10

100

1000

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

SAMPLE RATE (ksps)

TEMPERATURE (°C)

INTERNAL REFERENCE

vs. TEMPERATURE

GAIN ERROR vs. TEMPERATURE

FFT AT 1kHz

0.20

0.15

0.10

0.05

0

4.136

4.126

4.116

4.106

4.096

4.086

4.076

4.066

4.056

0

-20

f

= 131ksps

SAMPLE

-40

-60

-80

-100

-120

-140

-160

-180

-0.05

-0.10

-0.15

-0.20

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

0

10

20

30

40

50

60

TEMPERATURE (°C)

FREQUENCY (kHz)

_______________________________________________________________________________________

ꢁ

16-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

Typical Operating Characteristics (continued)

(Typical Operating Circuit, AV

= DV

= +5V, external reꢁerence = +4.096V, C

= 10µF, C

= 0.1µF, V

= AV

,

DD

REF

REFADJ

DD

C

LOAD

= 20pF. Typical values are at T = +25°C, unless otherwise noted.)

A

SFDR vs. FREQUENCY

SINAD vs. FREQUENCY

THD vs. FREQUENCY

120

100

80

60

40

20

0

100

90

80

70

60

50

40

30

20

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

f

= 131ksps

f = 131ksps

SAMPLE

f

= 131ksps

SAMPLE

1

10

FREQUENCY (kHz)

100

1

10

100

1

10

100

FREQUENCY (kHz)

Pin Description

PIꢂ

1

ꢂAME

D4/D12

D5/D13

D6/D14

D7/D15

FUꢂCTIOꢂ

Tri-State Digital-Data Output

2

3

4

Tri-State Digital-Data Output. D15 is the MSB.

Read/Convert Input. Power up and put the MAX1178/MAX1188 in acquisition mode by holding R/C

low during the ꢁirst ꢁalling edge oꢁ CS. During the second ꢁalling edge oꢁ CS, the level on R/C

determines whether the reꢁerence and reꢁerence buꢁꢁer power down or remain on aꢁter conversion.

Set R/C high during the second ꢁalling edge oꢁ CS to power down the reꢁerence and buꢁꢁer, or set R/C

low to leave the reꢁerence and buꢁꢁer powered up. Set R/C high during the third ꢁalling edge oꢁ CS to

put valid data on the bus.

5

R/C

6

7

EOC

End oꢁ Conversion. EOC drives low when conversion is complete.

Analog Supply Input. Bypass with a 0.1µF capacitor to AGND.

Analog Ground. Primary analog ground (star ground).

Analog Input

AV

DD

8

AGND

AIN

9

10

AGND

Analog Ground. Connect pin 10 to pin 8.

Reꢁerence Buꢁꢁer Output. Bypass REFADJ with a 0.1µF capacitor to AGND ꢁor internal reꢁerence

11

12

REFADJ

REF

mode. Connect REFADJ to AV

to select external reꢁerence mode.

DD

Reꢁerence Input/Output. Bypass REF with a 10µF capacitor to AGND ꢁor internal reꢁerence mode.

External reꢁerence input when in external reꢁerence mode.

6

_______________________________________________________________________________________

16-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

Pin Description (continued)

PIꢂ

ꢂAME

FUꢂCTIOꢂ

High-Byte Enable Input. Used to multiplex the 16-bit conversion result.

1: MSB available on the data bus.

13

HBEN

0: LSB available on the data bus.

Convert Start. The ꢁirst ꢁalling edge oꢁ CS powers up the device and enables acquire mode when R/C

is low. The second ꢁalling edge oꢁ CS starts conversion. The third ꢁalling edge oꢁ CS loads the result

onto the bus when R/C is high.

14

CS

15

16

17

18

19

20

DGND

Digital Ground

DV

Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND.

Tri-State Digital-Data Output. D0 is the LSB.

Tri-State Digital-Data Output

DD

D0/D8

D1/D9

D2/D10

D3/D11

Tri-State Digital-Data Output

Analog Input

DV

DD

Input Scaler

The MAX1178/MAX1188 have an input scaler, which

allows conversion oꢁ true bipolar input voltages and

input voltages greater than the power supply, while

operating ꢁrom a single +5V analog supply. The input

scaler attenuates and shiꢁts the analog input to match

the input range oꢁ the internal digital-to-analog converter

(DAC). The MAX1178 input voltage range is 5V, while

the MAX1188 input voltage range is 10V. Figure 4

shows the equivalent input circuit oꢁ the MAX1178/

MAX1188. This circuit limits the current going into or

out oꢁ AIN to less than 1.8mA.

1mA

DO–D15

C

= 20pF

C

= 20pF

1mA

LOAD

DGND

a) HIGH-Z TO V

,

OH

b) HIGH-Z TO V ,

OL

V

TO V , AND

OL

OH

V

OH

V

OL

TO V , AND

TO HIGH-Z

OL

TO HIGH-Z

Figure 1. Load Circuits

Track and Hold (T/H)

In track mode, the internal hold capacitor acquires the

analog signal (Figure 4). In hold mode, the T/H switch-

es open and the capacitive DAC samples the analog

input. During the acquisition, the analog input (AIN)

Detailed Description

Converter Operation

The MAX1178/MAX1188 use a successive-approxima-

tion (SAR) conversion technique with an inherent track-

and-hold (T/H) stage to convert an analog input into a

16-bit digital output. Parallel outputs provide a high-

speed interꢁace to microprocessors (µPs). The Func-

tional Diagram shows a simpliꢁied internal architecture oꢁ

the MAX1178/MAX1188. Figure 3 shows a typical oper-

ating circuit ꢁor the MAX1178/MAX1188.

charges capacitor C

. The acquisition ends on the

HOLD

second ꢁalling edge oꢁ CS. At this instant, the T/H

switches open. The retained charge on C repre-

HOLD

sents a sample oꢁ the input. In hold mode, the capaci-

tive DAC adjusts during the remainder oꢁ the conversion

time to restore node T/H OUT to zero within the limits oꢁ

16-bit resolution. Force CS low to put valid data on the

bus aꢁter conversion is complete.

_______________________________________________________________________________________

7

16-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

t

CSH

CSL

CS

R/C

t

ACQ

REF POWER-

DOWN CONTROL

t

DS

t

DV

EOC

DH

EOC

t

DO

CONV

HBEN

t

DO1

BR

DO

HIGH-Z

D7/D15–D0/D8

HIGH/LOW

BYTE VALID

HIGH/LOW

BYTE VALID

Figure 2. MAX1178/MAX1188 Timing Diagram

Power-Down Modes

Select standby mode or shutdown mode with the R/C

bit during the second ꢁalling edge oꢁ CS (see the

Selecting Standby or Shutdown Mode section). The

MAX1178/MAX1188 automatically enter either standby

mode (reꢁerence and buꢁꢁer on) or shutdown (reꢁerence

and buꢁꢁer oꢁꢁ) aꢁter each conversion, depending on the

status oꢁ R/C during the second ꢁalling edge oꢁ CS.

+5V ANALOG +5V DIGITAL

0.1µF

AV

DD

DV

DD

µP DATA

BUS

Internal Clock

The MAX1178/MAX1188 generate an internal conver-

sion clock to ꢁree the µP ꢁrom the burden oꢁ running the

D0–D7

ANALOG INPUT

AIN

OR

D8–D15

SAR conversion clock. Total conversion time (t

)

CONV

aꢁter entering hold mode (second ꢁalling edge oꢁ CS) to

MAX1178

MAX1188

end-oꢁ-conversion (EOC) ꢁalling is 4.7µs (max).

EOC

REF

Applications Information

R/C

CS

REFADJ

Starting a Conversion

CS and R/C control acquisition and conversion in the

MAX1178/MAX1188 (Figure 2). The ꢁirst ꢁalling edge oꢁ

CS powers up the device and puts it in acquire mode iꢁ

R/C is low. The convert start is ignored iꢁ R/C is high.

The MAX1178/MAX1188 need at least 12ms ꢁor the

internal reꢁerence to wake up and settle beꢁore starting

HBEN

0.1µF

10µF

HIGH

BYTE

AGND DGND

LOW

BYTE

the conversion (C

= 0.1µF, C

= 10µF), iꢁ

REF

REFADJ

powering up ꢁrom shutdown.

Figure 3. Typical Operating Circuit for the MAX1178/MAX1188

8

_______________________________________________________________________________________

16-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

Selecting Standby or Shutdown Mode

The MAX1178/MAX1188 have a selectable standby or

REF

low-power shutdown mode. In standby mode, the ADC’s

internal reꢁerence and reꢁerence buꢁꢁer do not power

MAX1178/MAX1188

down between conversions, eliminating the need to wait

R1

3.4kΩ

ꢁor the reꢁerence to power up beꢁore perꢁorming the next

C

HOLD

30pF

R2

161Ω

conversion. Shutdown mode powers down the reꢁerence

and reꢁerence buꢁꢁer aꢁter completing a conversion. The

reꢁerence and reꢁerence buꢁꢁer require a minimum oꢁ

TRACK

S1

AIN

T/H OUT

R3

HOLD

12ms to power up and settle ꢁrom shutdown (C

=

REFADJ

TRACK

HOLD

S2

S3

POWER-

DOWN

0.1µF, C

= 10µF).

REF

The state oꢁ R/C at the second ꢁalling edge oꢁ CS

selects which power-down mode the MAX1178/

MAX1188 enter upon conversion completion. Holding

R/C low causes the MAX1178/MAX1188 to enter stand-

by mode. The reꢁerence and buꢁꢁer are leꢁt on aꢁter the

conversion completes. R/C high causes the

MAX1178/MAX1188 to enter shutdown mode and

power-down the reꢁerence and buꢁꢁer aꢁter conversion

(Figures 5 and 6). Set the voltage at R/C high during

the second ꢁalling edge oꢁ CS to realize the lowest cur-

rent operation.

R2 = 7.85kΩ (MAX1188) OR 3.92kΩ (MAX1178)

S1, S2 = T/H SWITCH

S3 = POWER-DOWN

R3 = 5.45kΩ (MAX1188) OR 17.79kΩ (MAX1178)

Figure 4. Equivalent Input Circuit

DATA

OUT

ACQUISITION

CONVERSION

Standby Mode

While in standby mode, the supply current is less than

3.7mA (typ). The next ꢁalling edge oꢁ CS with R/C low

causes the MAX1178/MAX1188 to exit standby mode

and begin acquisition. The reꢁerence and reꢁerence

buꢁꢁer remain active to allow quick turn-on time.

CS

R/C

EOC

Shutdown Mode

In shutdown mode, the reꢁerence and reꢁerence buꢁꢁer

are shut down between conversions. Shutdown mode

reduces supply current to 0.5µA (typ) immediately aꢁter

the conversion. The next ꢁalling edge oꢁ CS with R/C low

causes the reꢁerence and buꢁꢁer to wake up and enter

acquisition mode. To achieve 16-bit accuracy, allow

REF AND

BUFFER

POWER

Figure 5. Selecting Standby Mode

12ms ꢁor the internal reꢁerence to wake up (C

=

REFADJ

DATA

OUT

0.1µF, C

= 10µF).

REF

ACQUISITION

CONVERSION

Internal and External Reference

Internal Reference

CS

The internal reꢁerence oꢁ the MAX1178/MAX1188 is

internally buꢁꢁered to provide +4.096V output at REF.

Bypass REF to AGND and REFADJ to AGND with 10µF

and 0.1µF, respectively. Sink or source current at

REFADJ to make ꢁine adjustments to the internal reꢁer-

ence. The input impedance oꢁ REFADJ is nominally

5kΩ. Use the circuit in Figure 7 to adjust the internal

reꢁerence to 1.5ꢀ.

R/C

EOC

REF AND

BUFFER

POWER

Figure 6. Selecting Shutdown Mode

_______________________________________________________________________________________

9

16-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

MAX1178

INPUT RANGE = -5V TO +5V

OUTPUT CODE

MAX1178

MAX1188

FULL-SCALE

TRANSITION

+5V

11 1111 1111 1111

11 1111 1111 1110

11 1111 1111 1101

68kΩ

100kΩ

REFADJ

10 0000 0000 0001

10 0000 0000 0000

01 1111 1111 1111

0.1µF

150kΩ

FULL-SCALE RANGE (FSR) = +1V

FSR x V

00 0000 0000 0011

00 0000 0000 0010

00 0000 0000 0001

00 0000 0000 0000

REF

1 LSB =

65,536 x 4.096

Figure 7. MAX1178/MAX1188 Reference-Adjust Circuit

-32,768 -32,766

0

+32,766+32,768

+32,767

-32,767 -32,765 -1

+1

INPUT VOLTAGE (LSB)

External Reference

An external reꢁerence can be placed at either the input

(REFADJ) or the output (REF) oꢁ the MAX1178/

MAX1188s’ internal buꢁꢁer ampliꢁier. Using the buꢁꢁered

REFADJ input makes buꢁꢁering the external reꢁerence

unnecessary. The input impedance oꢁ REFADJ is typi-

cally 5kΩ. The internal buꢁꢁer output must be bypassed

at REF with a 10µF capacitor.

Figure 8. MAX1178 Transfer Function

MAX1188

INPUT RANGE = -10V TO +10V

OUTPUT CODE

1111 1111 1111 1111

FULL-SCALE

TRANSITION

Connect REFADJ to AV

to disable the internal buꢁꢁer.

DD

1111 1111 1111 1110

1111 1111 1111 1101

Directly drive REF using an external 3.8V to 4.2V reꢁer-

ence. During conversion, the external reꢁerence must

be able to drive 100µA oꢁ DC load current and have an

output impedance oꢁ 10Ω or less.

1000 0000 0000 0001

1000 0000 0000 0000

0001 1111 1111 1111

For optimal perꢁormance, buꢁꢁer the reꢁerence through

an op amp and bypass REF with a 10µF capacitor.

Consider the MAX1178/MAX1188s’ equivalent input

noise (0.6 LSB) when choosing a reꢁerence.

FULL-SCALE RANGE (FSR) = +20V

FSR x V

0000 0000 0000 0011

0000 0000 0000 0010

0000 0000 0000 0001

0000 0000 0000 0000

REF

1 LSB =

65,536 x 4.096

Reading the Conversion Result

EOC is provided to ꢁlag the µP when a conversion is

complete. The ꢁalling edge oꢁ EOC signals that the data

is valid and ready to be output to the bus. D0–D15 are

the parallel outputs oꢁ the MAX1178/MAX1188. These

tri-state outputs allow ꢁor direct connection to a micro-

controller I/O bus. The outputs remain high impedance

during acquisition and conversion. Data is loaded onto

the output bus with the third ꢁalling edge oꢁ CS with R/C

-32,68 -32,766

0

+32,766+32,768

+32,767

-32,767 -32,765 -1

+1

INPUT VOLTAGE (LSB)

Figure 9. MAX1188 Transfer Function

Transfer Function

Figures 8 and 9 show the MAX1178/MAX1188 output

transꢁer ꢁunctions. The MAX1178 and MAX1188 outputs

are coded in oꢁꢁset binary.

high (aꢁter t ). Bringing CS high ꢁorces the output bus

DO

back to high impedance. The MAX1178/MAX1188 then

wait ꢁor the next ꢁalling edge oꢁ CS to start the next con-

version cycle (Figure 2).

Input Buffer

Most applications require an input buꢁꢁer ampliꢁier to

achieve 16-bit accuracy and prevent loading the

source. When the input signal is multiplexed, switch the

channels immediately aꢁter acquisition, rather than near

the end oꢁ, or aꢁter, a conversion. This allows more time

ꢁor the input buꢁꢁer ampliꢁier to respond to a large step

HBEN toggles the output between the high/low byte. The

low byte is loaded onto the output bus when HBEN is

low, and the high byte is on the bus when HBEN is high.

±1 ______________________________________________________________________________________

16-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

MAX1178

ANALOG INPUT CURRENT

vs. ANALOG INPUT VOLTAGE

REF

MAX1178

MAX1188

1.5

1.0

0.5

0

SHUTDOWN

MODE

AIN

ANALOG

INPUT

MAX427

-0.5

-1.0

-1.5

STANDBY

MODE

-5.0

-2.5

0

2.5

5.0

ANALOG INPUT VOLTAGE (V)

Figure 10. MAX1178/MAX1188 Fast-Settling Input Buffer

Figure 11. MAX1178 Analog Input Current

change in input signal. The input ampliꢁier must have a

high enough slew rate to complete the required output

voltage change beꢁore the beginning oꢁ the acquisition

time. Figure 10 shows an example oꢁ this circuit using

the MAX427.

MAX1188

ANALOG INPUT CURRENT

vs. ANALOG INPUT VOLTAGE

1.5

Figures 11 and 12 show how the MAX1178/MAX1188

analog input current varies depending on whether the

chip is operating or powered down. The part is ꢁully

powered down between conversions iꢁ the voltage at

R/C is set high during the second ꢁalling edge oꢁ CS.

The input current abruptly steps to the powered-up

value at the start oꢁ acquisition. This step in the input

current can disrupt the ADC input, depending on the

driving circuit’s output impedance at high ꢁrequencies. Iꢁ

the driving circuit cannot ꢁully settle by the end oꢁ acqui-

sition, the accuracy oꢁ the system can be compromised.

To avoid this situation, increase the acquisition time, use

1.0

0.5

0

SHUTDOWN

MODE

STANDBY

MODE

-0.5

-1.0

-1.5

-10

-5

0

5

10

a driving circuit that can settle within t

, or leave the

ANALOG INPUT VOLTAGE (V)

ACQ

MAX1178/MAX1188 powered up by setting the voltage

at R/C low during the second ꢁalling edge oꢁ CS.

Figure 12. MAX1188 Analog Input Current

do so at right angles to minimize coupling digital noise

onto the analog lines. Iꢁ the analog and digital sections

share the same supply, isolate the digital and analog

supply by connecting them with a low-value (10Ω)

resistor or ꢁerrite bead.

Layout, Grounding, and Bypassing

For best perꢁormance, use printed circuit boards. Do not

run analog and digital lines parallel to each other, and do

not lay out digital signal paths underneath the ADC pack-

age. Use separate analog and digital ground planes with

only one point connecting the two ground systems (ana-

log and digital) as close to the device as possible.

The ADC is sensitive to high-ꢁrequency noise on the

AV

supply. Bypass AV

to AGND with a 0.1µF

DD

capacitor in parallel with a 1µF to 10µF low-ESR capaci-

tor with the smallest capacitor closest to the device.

Keep capacitor leads short to minimize stray inductance.

Route digital signals ꢁar away ꢁrom sensitive analog and

reꢁerence inputs. Iꢁ digital lines must cross analog lines,

______________________________________________________________________________________ ±±

16-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

Signal-to-Noise Plus Distortion

Definitions

Signal-to-noise plus distortion (SINAD) is the ratio oꢁ the

ꢁundamental input ꢁrequency’s RMS amplitude to the

RMS equivalent oꢁ all the other ADC output signals:

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation oꢁ the values

on an actual transꢁer ꢁunction ꢁrom a straight line. This

straight line can be either a best-straight-line ꢁit or a line

drawn between the end points oꢁ the transꢁer ꢁunction,

once oꢁꢁset and gain errors have been nulliꢁied. The sta-

tic linearity parameters ꢁor the MAX1178/MAX1188 are

measured using the end-point method.













Signal

(Noise + Distortion)

RMS

SINAD(dB) = 20 × log

RMS

Effective Number of Bits

Eꢁꢁective number oꢁ bits (ENOB) indicates the global

accuracy oꢁ an ADC at a speciꢁic input ꢁrequency and

sampling rate. An ideal ADC error consists oꢁ quantiza-

tion noise only. With an input range equal to the ꢁull-

scale range oꢁ the ADC, calculate the ENOB as ꢁollows:

Differential Nonlinearity

Diꢁꢁerential nonlinearity (DNL) is the diꢁꢁerence between

an actual step width and the ideal value oꢁ 1 LSB. A

DNL error speciꢁication oꢁ 1 LSB guarantees no missing

codes and a monotonic transꢁer ꢁunction.

SINAD − 1.76

Signal-to-Noise Ratio

For a waveꢁorm perꢁectly reconstructed ꢁrom digital

samples, signal-to-noise ratio (SNR) is the ratio oꢁ the

ꢁull-scale analog input (RMS value) to the RMS quanti-

zation error (residual error). The ideal, theoretical mini-

mum analog-to-digital noise is caused by quantization

noise error only and results directly ꢁrom the ADC’s res-

olution (N bits):

ENOB =

6.02

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio oꢁ the RMS

sum oꢁ the ꢁirst ꢁive harmonics oꢁ the input signal to the

ꢁundamental itselꢁ. This is expressed as:









2

V

+ V + V + V

3 4 5

SNR = (6.02 × N + 1.76)dB

2

THD = 20 × log

V

1









where N = 16 bits.

In reality, there are other noise sources besides quanti-

zation noise: thermal noise, reꢁerence noise, clock jitter,

etc. The SNR is computed by taking the ratio oꢁ the

RMS signal to the RMS noise, which includes all spec-

tral components minus the ꢁundamental, the ꢁirst ꢁive

harmonics, and the DC oꢁꢁset.

where V is the ꢁundamental amplitude and V through

5

1

2

V are the 2nd- through 5th-order harmonics.

Spurious-Free Dynamic Range

Spurious-ꢁree dynamic range (SFDR) is the ratio oꢁ the

RMS amplitude oꢁ the ꢁundamental (maximum signal

component) to the RMS value oꢁ the next-largest ꢁre-

quency component.

±2 ______________________________________________________________________________________

16-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

Functional Diagram

REFADJ

HBEN

AV AGND DV DGND

DD

5kΩ

REFERENCE

8 BITS

OUTPUT

REGISTERS

D0–D7

OR

D8–D15

REF

INPUT

SCALER

CAPACITIVE

DAC

AIN

MAX1178

MAX1188

AGND

SUCCESSIVE-

CLOCK

APPROXIMATION

REGISTER AND

CONTROL LOGIC

EOC

CS

R/C

Pin Configuration

Ordering Information (continued)

IꢂPUT

VOLTAGE

RAꢂGE (V)

PIꢂ-

PACKAGE

TOP VIEW

PART

TEMP RAꢂGE

D4/D12

D5/D13

D6/D14

D7/D15

R/C

1

2

20 D3/D11

19

18

D2/D10

D1/D9

MAX±±88ACUP

MAX1188BCUP

MAX1188CCUP

0°C to +70°C

20 TSSOP

10

3

4

17 D0/D8

16

MAX1188AEUP -40°C to +85°C

MAX1188BEUP -40°C to +85°C

MAX1188CEUP -40°C to +85°C

5

DV

DD

MAX1178

MAX1188

EOC

6

15 DGND

7

14

13

12

11

AV

CS

DD

8

AGND

AIN

HBEN

REF

9

Chip Information

10

AGND

REFADJ

TRANSISTOR COUNT: 15,383

PROCESS: BiCMOS

TSSOP

______________________________________________________________________________________ ±3

16-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

Package Information

(The package drawing(s) in this data sheet may not reꢁlect the most current speciꢁications. For the latest package outline inꢁormation,

go to www.maxim-ic.com/packages.)

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

±4 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed USA

is a registered trademark oꢁ Maxim Integrated Products.


型号：	MAX1178ACUP-T
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Parallel, Word Access, BICMOS, PDSO20, 4.40 MM, MO-153, TSSOP-20
文件：	总14页 (文件大小：330K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX1178ACUP-T [MAXIM]

相关型号：

MAX1178AEUP

MAX1178AEUP+

MAX1178AEUP+T

MAX1178AEUP-T

MAX1178BCUP

MAX1178BCUP+

MAX1178BCUP+T

MAX1178BCUP-T

MAX1178BEUP

MAX1178BEUP+

MAX1178BEUP+T

MAX1178CCUP