MAX11663AUT+ [MAXIM]
500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs; 500KSPS ，低功耗，串行12位/ 10位/ 8位ADC
| 型号： | MAX11663AUT+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs |
| 文件： | 总28页 (文件大小：1601K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5530; Rev 1; 1/11
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
General Description
Features
S 500ksps Conversion Rate, No Pipeline Delay
S 12-/10-/8-Bit Resolution
The MAX11661−MAX11666 are 12-/10-/8-bit, compact,
low-power, successive approximation analog-to-digital
converters (ADCs). These high-performance ADCs include
a high-dynamic range sample-and-hold and a high-speed
serial interface. These ADCs accept a full-scale input from
0V to the power supply or to the reference voltage.
S 1-/2-Channel, Single-Ended Analog Inputs
S Low-Noise 73dB SNR
S Variable I/O: 1.5V to 3.6V (Dual-Channel Only)
Allows the Serial Interface to Connect Directly
to 1.5V, 1.8V, 2.5V, or 3V Digital Systems
The MAX11662/MAX11664/MAX11666 feature dual, sin-
gle-ended analog inputs connected to the ADC core
using a 2:1 MUX. The devices also include a separate
supply input for data interface and a dedicated input
for reference voltage. In contrast, the single-channel
devices generate the reference voltage internally from
the power supply.
S 2.2V to 3.6V Supply Voltage
S Low Power
2.98mW
Very Low Power Consumption at 2.5µA/ksps
S External Reference Input (Dual-Channel Devices Only)
S 1.3µA Power-Down Current
These ADCs operate from a 2.2V to 3.6V supply and
consume only 2.98mW. The devices include full power-
down mode and fast wake-up for optimal power man-
agement and a high-speed 3-wire serial interface. The
3-wire serial interface directly connects to SPIK, QSPIK,
and MICROWIREKdevices without external logic.
S SPI-/QSPI-/MICROWIRE-Compatible Serial
Interface
S 10-Pin, 3mm x 5mm µMAX Package
S 6-Pin, 2.8mm x 2.9mm SOT23 Package
S Wide -40NC to +125NC Operation
Excellent dynamic performance, low voltage, low power,
ease of use, and small package size make these con-
verters ideal for portable battery-powered data-acquisi-
tion applications, and for other applications that demand
low-power consumption and minimal space.
Applications
Data Acquisition
®
These ADCs are available in a 10-pin FMAX package,
Portable Data Logging
and a 6-pin SOT23 package. These devices operate
over the -40NC to +125NC temperature range.
Medical Instrumentation
Battery-Operated Systems
Communication Systems
Automotive Systems
Ordering Information
PART
MAX11661AUT+
MAX11662AUB+*
MAX11663AUT+
MAX11664AUB+*
MAX11665AUT+
MAX11666AUB+*
PIN-PACKAGE
6 SOT23
BITS
8
NO. OF CHANNELS
1
2
1
2
1
2
10 FMAX-EP**
6 SOT23
8
10
10
12
12
10 FMAX-EP**
6 SOT23
10 FMAX-EP**
Note: All devices are specified over the -40°C to +125°C operating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*Future product—contact factory for availability.
**EP = Exposed pad.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
DD
V
to GND.............................................................-0.3V to +4V
Continuous Power Dissipation (T = +70NC)
A
REF, OVDD, AIN1, AIN2, AIN to GND ........-0.3V to the lower of
(V + 0.3V) and +4V
6-Pin SOT23 (derate 8.7mW/NC above +70NC)...........696mW
10-Pin FMAX (derate 8.8mW/NC above +70NC)........707.3mW
Operating Temperature Range....................... .-40NC to +125NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
DD
CS, SCLK, CHSEL, DOUT TO GND............-0.3V to the lower of
(V + 0.3V) and +4V
OVDD
AGND to GND......................................................-0.3V to +0.3V
Input/Output Current (all pins) ...........................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS (MAX11666)
(V
DD
= 2.2V to 3.6V, V
= V , V
= V . f
= 8MHz, 50% duty cycle, 500ksps. C
= 10pF, T = -40NC to +125NC,
DOUT A
REF
DD OVDD
DD SCLK
unless otherwise noted. Typical values are at T = +25NC.)
A
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
12
Bits
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
OE
Q1
Q1
Q3
Q3
No missing codes
Excluding offset and reference errors
Q0.3
Q1
Gain Error
GE
Total Unadjusted Error
TUE
Q1.5
Channel-to-Channel Offset
Matching
Q0.4
LSB
LSB
Channel-to-Channel Gain
Matching
Q0.05
DYNAMIC PERFORMANCE (f
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
= 250kHz)
SINAD
SNR
AIN
70
72
72
dB
dB
70.5
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
THD
-85
85
-75
dB
SFDR
IMD
76
dB
f = 239.8kHz, f = 200.2kHz
-84
40
dB
1
2
-3dB point
MHz
MHz
MHz
dB
Full-Linear Bandwidth
SINAD > 68dB
2.5
45
Small-Signal Bandwidth
Crosstalk
-90
2
______________________________________________________________________________________
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11666) (continued)
(V
DD
= 2.2V to 3.6V, V
= V , V
= V . f
= 8MHz, 50% duty cycle, 500ksps. C
= 10pF, T = -40NC to +125NC,
DOUT A
REF
DD OVDD
DD SCLK
unless otherwise noted. Typical values are at T = +25NC.)
A
PARAMETER
CONVERSION RATE
Throughput
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5
500
ksps
Fs
Conversion Time
1.56
52
Acquisition Time
t
ns
ACQ
Aperture Delay
4
Fs
From CS falling edge
Aperture Jitter
15
ps
Serial-Clock Frequency
ANALOG INPUT (AIN1, AIN2)
Input Voltage Range
Input Leakage Current
f
0.08
0
8
MHz
CLK
V
V
V
AIN_
REF
I
0.002
20
Q1
FA
ILA
Track
Hold
Input Capacitance
C
pF
V
AIN_
4
EXTERNAL REFERENCE INPUT (REF)
V
+
DD
0.05
Reference Input Voltage Range
V
1
REF
ILR
Reference Input Leakage
Current
I
Conversion stopped
0.005
5
Q1
FA
Reference Input Capacitance
C
pF
REF
DIGITAL INPUTS (SCLK, CS, CHSEL)
0.75 x
Digital Input High Voltage
V
V
V
V
IH
V
OVDD
0.25 x
Digital Input Low Voltage
V
IL
V
OVDD
0.15 x
Digital Input Hysteresis
V
HYST
V
OVDD
0.001
2
Digital Input Leakage Current
Digital Input Capacitance
DIGITAL OUTPUT (DOUT)
I
Inputs at GND or V
Q1
FA
IL
DD
C
pF
IN
0.85 x
Output High Voltage
Output Low Voltage
V
I
= 200FA
SOURCE
V
V
OH
V
OVDD
0.15 x
V
I
= 200FA
SINK
OL
OL
V
OVDD
High-Impedance Leakage
Current
I
Q1.0
FA
pF
High-Impedance Output
Capacitance
C
4
OUT
_______________________________________________________________________________________
3
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11666) (continued)
(V
DD
= 2.2V to 3.6V, V
= V , V
= V . f
= 8MHz, 50% duty cycle, 500ksps. C
= 10pF, T = -40NC to +125NC,
DOUT A
REF
DD OVDD
DD SCLK
unless otherwise noted. Typical values are at T = +25NC.)
A
PARAMETER
POWER SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply Voltage
Digital I/O Supply Voltage
V
2.2
1.5
3.6
V
V
DD
V
V
DD
OVDD
I
V
V
= GND
= GND
1.6
Positive Supply Current
(Full-Power Mode)
VDD
AIN_
mA
mA
I
0.05
OVDD
AIN_
Positive Supply Current (Full-
Power Mode), No Clock
I
1.48
VDD
Power-Down Current
Line Rejection
I
Leakage only
= 2.2V to 3.6V, V
1.3
0.7
10
FA
PD
V
= 2.2V
LSB/V
DD
REF
TIMING CHARACTERISTICS (Note 1)
Quiet Time
t
4
10
5
ns
ns
ns
Q
t
CS Pulse Width
1
t
CS Fall to SCLK Setup
2
CS Falling Until DOUT High-
Impedance Disabled
t
(Note 2)
1
ns
ns
3
4
Figure 2, V
Figure 2, V
= 2.2V to 3.6V
= 1.5V to 2.2V
15
16.5
60
Data Access Time After SCLK
Falling Edge
OVDD
t
OVDD
SCLK Pulse Width Low
SCLK Pulse Width High
t
t
Percentage of clock period
Percentage of clock period
40
40
%
%
5
60
6
Data Hold Time From SCLK
Falling Edge
SCLK Falling Until DOUT High
Impedance
t
Figure 3
5
ns
7
8
t
Figure 4 (Note 2)
Conversion cycle
2.5
14
1
ns
Power-Up Time
Cycle
ELECTRICAL CHARACTERISTICS (MAX11665)
(V
DD
= 2.2V to 3.6V, f
= 8MHz, 50% duty cycle, 500ksps, C
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical
DOUT A
SCLK
values are at T = +25NC.)
A
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
12
Bits
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
Q1
Q1
Q4
Q3
DNL
OE
No missing codes
Excluding offset and reference errors
Q1.5
Q1
Gain Error
GE
Total Unadjusted Error
DYNAMIC PERFORMANCE (f
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
TUE
Q1.5
= 250kHz)
SINAD
SNR
AIN
70
72.5
73
dB
dB
70.5
4
______________________________________________________________________________________
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11665) (continued)
(V
DD
= 2.2V to 3.6V, f
= 8MHz, 50% duty cycle, 500ksps, C
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical
DOUT A
SCLK
values are at T = +25NC.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
-85
85
MAX
UNITS
dB
Total Harmonic Distortion
THD
-76
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
Small-Signal Bandwidth
CONVERSION RATE
Throughput
SFDR
IMD
77
dB
f = 239.8kHz, f = 200.2kHz
-84
40
dB
1
2
-3dB point
SINAD > 68dB
MHz
MHz
MHz
2.5
45
5
500
ksps
Fs
Conversion Time
1.56
52
Acquisition Time
t
ns
ACQ
Aperture Delay
4
ns
From CS falling edge
Aperture Jitter
15
ps
Serial Clock Frequency
ANALOG INPUT
f
0.08
0
8
MHz
CLK
Input Voltage Range
Input Leakage Current
V
V
V
AIN
DD
I
0.002
20
Q1
FA
ILA
Track
Hold
Input Capacitance
C
pF
AIN
4
DIGITAL INPUTS (SCLK, CS, CHSEL)
0.75 x
Digital Input High Voltage
V
V
V
V
IH
V
VDD
0.25 x
Digital Input Low Voltage
V
IL
V
VDD
0.15 x
Digital Input Hysteresis
V
HYST
V
VDD
Digital Input Leakage Current
Digital Input Capacitance
DIGITAL OUTPUT (DOUT)
I
Inputs at GND or V
0.001
2
Q1
FA
IL
DD
C
pF
IN
0.85 x
Output High Voltage
Output Low Voltage
V
I
= 200FA
SOURCE
V
V
OH
V
VDD
0.15 x
V
I
= 200FA
SINK
OL
OL
V
VDD
High-Impedance Leakage
Current
I
Q1.0
FA
pF
High-Impedance Output
Capacitance
C
4
OUT
POWER SUPPLY
Positive Supply Voltage
V
DD
2.2
3.6
V
Positive Supply Current
(Full-Power Mode)
I
V
AIN
= GND
1.76
mA
VDD
_______________________________________________________________________________________
5
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11665) (continued)
(V
DD
= 2.2V to 3.6V, f
= 8MHz, 50% duty cycle, 500ksps, C
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical
DOUT A
SCLK
values are at T = +25NC.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply Current (Full-
Power Mode), No Clock
I
1.48
mA
VDD
Power-Down Current
Line Rejection
I
Leakage only
= 2.2V to 3.6V
1.3
0.7
10
FA
PD
V
LSB/V
DD
TIMING CHARACTERISTICS (Note 1)
Quiet Time
t
4
10
5
ns
ns
ns
Q
t
CS Pulse Width
1
2
t
CS Fall to SCLK Setup
CS Falling Until DOUT High-
Impedance Disabled
t
(Note 2)
1
ns
ns
3
4
Data Access Time After SCLK
Falling Edge
t
Figure 2, V
= 2.2V to 3.6V
15
DD
SCLK Pulse Width Low
SCLK Pulse Width High
t
t
Percentage of clock period
Percentage of clock period
40
40
60
60
%
%
5
6
Data Hold Time From SCLK
Falling Edge
t
Figure 3
5
ns
7
8
SCLK Falling Until DOUT High
Impedance
t
Figure 4 (Note 2)
Conversion cycle
2.5
14
1
ns
Power-Up Time
Cycle
ELECTRICAL CHARACTERISTICS (MAX11664)
(V
DD
= 2.2V to 3.6V, V
= V , V
= V , f
= 8MHz, 50% duty cycle, 500ksps; C
= 10pF, T = -40NC to +125NC,
DOUT A
REF
DD OVDD
DD SCLK
unless otherwise noted. Typical values are at T = +25NC.)
A
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
10
Bits
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
OE
Q0.4
Q0.4
Q1
No missing codes
Excluding offset and reference errors
Q0.5
0
Gain Error
GE
Q1
Total Unadjusted Error
TUE
Q0.5
Channel-to-Channel Offset
Matching
Q0.05
LSB
LSB
Channel-to-Channel Gain
Matching
Q0.05
DYNAMIC PERFORMANCE (f
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
= 250kHz)
SINAD
SNR
AIN
61
61
61.8
61.8
-83
dB
dB
dB
dB
Total Harmonic Distortion
Spurious-Free Dynamic Range
THD
-74
SFDR
75
6
______________________________________________________________________________________
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11664) (continued)
(V
DD
= 2.2V to 3.6V, V
= V , V
= V , f
= 8MHz, 50% duty cycle, 500ksps; C
= 10pF, T = -40NC to +125NC,
DOUT A
REF
DD OVDD
DD SCLK
unless otherwise noted. Typical values are at T = +25NC.)
A
PARAMETER
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
Small-Signal Bandwidth
Crosstalk
SYMBOL
CONDITIONS
MIN
TYP
-82
40
MAX
UNITS
dB
IMD
f = 239.8kHz, f = 200.2kHz
1
2
-3dB point
SINAD > 60dB
MHz
MHz
MHz
dB
2.5
45
-90
CONVERSION RATE
Throughput
5
500
ksps
Fs
Conversion Time
1.56
52
Acquisition Time
t
ns
ACQ
Aperture Delay
4
ns
From CS falling edge
Aperture Jitter
15
ps
Serial-Clock Frequency
ANALOG INPUT (AIN1, AIN2)
Input Voltage Range
Input Leakage Current
f
0.08
0
8
MHz
CLK
V
V
V
AIN_
REF
I
0.002
20
Q1
FA
ILA
Track
Hold
Input Capacitance
C
pF
V
AIN-_
4
EXTERNAL REFERENCE INPUT (REF)
V
+
DD
0.05
Reference Input Voltage Range
V
1
REF
ILR
Reference Input Leakage
Current
I
Conversion stopped
0.005
5
Q1
FA
Reference Input Capacitance
C
pF
REF
DIGITAL INPUTS (SCLK, CS, CHSEL)
0.75 x
Digital Input High Voltage
V
V
V
V
IH
V
OVDD
0.25 x
Digital Input Low Voltage
V
IL
V
OVDD
0.15 x
Digital Input Hysteresis
V
HYST
V
OVDD
0.001
2
Digital Input Leakage Current
Digital Input Capacitance
DIGITAL OUTPUT (DOUT)
I
Inputs at GND or V
Q1
FA
IL
DD
C
pF
IN
0.85 x
Output High Voltage
Output Low Voltage
V
I
I
= 200µA
SOURCE
V
V
OH
V
OVDD
0.15 x
V
= 200µA
SINK
OL
V
OVDD
High-Impedance Leakage
Current
I
Q1.0
FA
pF
OL
High-Impedance Output
Capacitance
C
4
OUT
_______________________________________________________________________________________
7
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11664) (continued)
(V
DD
= 2.2V to 3.6V, V
= V , V
= V , f
= 8MHz, 50% duty cycle, 500ksps; C
= 10pF, T = -40NC to +125NC,
DOUT A
REF
DD OVDD
DD SCLK
unless otherwise noted. Typical values are at T = +25NC.)
A
PARAMETER
POWER SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply Voltage
Digital I/O Supply Voltage
V
2.2
1.5
3.6
V
V
DD
V
V
DD
OVDD
I
V
V
= GND
= GND
1.6
Positive Supply Current
(Full-Power Mode)
VDD
AIN_
AIN_
mA
mA
I
0.05
OVDD
Positive Supply Current
(Full-Power Mode), No Clock
I
1.48
VDD
Power-Down Current
Line Rejection
I
Leakage only
= 2.2V to 3.6V, V
1.3
10
FA
PD
V
= 2.2V
REF
0.17
LSB/V
DD
TIMING CHARACTERISTICS (Note 1)
Quiet Time
t
4
10
5
ns
ns
ns
Q
t
CS Pulse Width
1
2
t
CS Fall to SCLK Setup
CS Falling Until DOUT High-
Impedance Disabled
t
(Note 2)
1
ns
ns
3
4
V
V
= 2.2V to 3.6V
= 1.5V to 2.2V
15
16.5
60
Data Access Time After SCLK
Falling Edge (Figure 2)
OVDD
t
OVDD
SCLK Pulse Width Low
SCLK Pulse Width High
t
t
Percentage of clock period
Percentage of clock period
40
40
%
%
5
60
6
Data Hold Time From SCLK
Falling Edge
t
Figure 3
5
ns
7
8
SCLK Falling Until DOUT High
Impedance
t
Figure 4 (Note 2)
Conversion cycle
2.5
14
1
ns
Power-Up Time
Cycle
ELECTRICAL CHARACTERISTICS (MAX11663)
(V
DD
= 2.2V to 3.6V. f
= 8MHz, 50% duty cycle, 500ksps. C
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical
DOUT A
SCLK
values are at T = +25NC.)
A
PARAMETER
DC ACCURACY
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10
Bits
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
Q0.5
Q0.5
Q1.3
Q1.3
DNL
OE
No missing codes
Excluding offset and reference errors
Q0.3
Q0.15
Q1
Gain Error
GE
Total Unadjusted Error
TUE
8
______________________________________________________________________________________
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11663) (continued)
(V
DD
= 2.2V to 3.6V. f
= 8MHz, 50% duty cycle, 500ksps. C
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical
DOUT A
SCLK
values are at T = +25NC.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (f
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
Small-Signal Bandwidth
CONVERSION RATE
Throughput
= 250kHz)
SINAD
SNR
AIN
60.5
60.5
61.5
61.5
-85
dB
dB
THD
-73
dB
SFDR
IMD
75
dB
f =239.8kHz, f =200.2kHz
-82
40
dB
1
2
-3dB point
MHz
MHz
MHz
SINAD > 60dB
2.5
45
5
500
ksps
Fs
Conversion Time
1.56
52
Acquisition Time
t
ns
ACQ
Aperture Delay
4
ns
From CS falling edge
Aperture Jitter
15
ps
Serial Clock Frequency
ANALOG INPUT (AIN)
Input Voltage Range
Input Leakage Current
f
0.08
0
8
MHz
CLK
V
V
V
AIN
DD
I
0.002
20
Q1
FA
ILA
Track
Hold
Input Capacitance
C
pF
AIN
4
DIGITAL INPUTS (SCLK, CS, CHSEL)
0.75 x
Digital Input High Voltage
V
V
V
V
IH
V
VDD
0.25 x
Digital Input Low Voltage
V
IL
V
VDD
0.15 x
Digital Input Hysteresis
V
HYST
V
VDD
Digital Input Leakage Current
Digital Input Capacitance
I
Inputs at GND or V
0.001
2
Q1
FA
IL
DD
C
pF
IN
_______________________________________________________________________________________
9
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11663) (continued)
(V
DD
= 2.2V to 3.6V. f
= 8MHz, 50% duty cycle, 500ksps. C
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical
DOUT A
SCLK
values are at T = +25NC.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUT (DOUT)
0.85 x
Output High Voltage
Output Low Voltage
V
I
= 200µA
SOURCE
V
V
OH
V
VDD
0.15 x
V
I = 200µA
SINK
OL
OL
V
VDD
High-Impedance Leakage
Current
I
Q1.0
FA
pF
High-Impedance Output
Capacitance
C
4
OUT
POWER SUPPLY
Positive Supply Voltage
V
2.2
3.6
V
DD
Positive Supply Current
(Full-Power Mode)
I
V
AIN
= GND
1.76
mA
VDD
Positive Supply Current
(Full-Power Mode), No Clock
I
1.48
mA
VDD
Power-Down Current
Line Rejection
I
Leakage only
= 2.2V to 3.6V
1.3
10
FA
PD
V
0.17
LSB/V
DD
TIMING CHARACTERISTICS (Note 1)
Quiet Time
t
4
10
5
ns
ns
ns
Q
t
CS Pulse Width
1
2
t
CS Fall to SCLK Setup
CS Falling Until DOUT High-
Impedance Disabled
t
t
(Note 2)
1
ns
ns
3
4
Data Access Time After SCLK
Falling Edge
Figure 2, V
= 2.2V to 3.6V
15
DD
SCLK Pulse Width Low
SCLK Pulse Width High
t
t
Percentage of clock period
Percentage of clock period
40
40
60
60
%
%
5
6
Data Hold Time From SCLK
Falling Edge
t
t
Figure 3
5
ns
7
8
SCLK Falling Until DOUT High
Impedance
Figure 4 (Note 2)
Conversion cycle
2.5
14
1
ns
Power-Up Time
Cycle
10 _____________________________________________________________________________________
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11662)
(V
DD
= 2.2V to 3.6V, V
= V , V
= V , f
= 8MHz, 50% duty cycle, 500ksps, C
= 10pF, T = -40NC to +125NC,
A
REF
DD OVDD
DD SCLK
DOUT
MIN
8
unless otherwise noted. Typical values are at T = +25NC.)
A
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
TYP
MAX
UNITS
Resolution
Bits
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
OE
Q0.15
Q0.15
Q0.7
No missing codes
Excluding offset and reference errors
0.45
0
Gain Error
GE
Q0.2
Total Unadjusted Error
TUE
0.5
Channel-to-Channel Offset
Matching
0.01
0.01
LSB
LSB
Channel-to-Channel Gain
Matching
DYNAMIC PERFORMANCE (f
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
Small-Signal Bandwidth
Crosstalk
= 250kHz)
SINAD
SNR
AIN
49
49
49.8
49.8
-75
67
dB
dB
THD
-67
dB
SFDR
IMD
63
dB
f = 239.8kHz, f = 200.2kHz
-65
40
dB
1
2
-3dB point
SINAD > 49dB
MHz
MHz
MHz
dB
2.5
45
-90
CONVERSION RATE
Throughput
5
500
ksps
Fs
Conversion Time
1.56
52
Acquisition Time
t
ns
ACQ
Aperture Delay
4
ns
From CS falling edge
Aperture Jitter
15
ps
Serial-Clock Frequency
ANALOG INPUT (AIN1, AIN2)
Input Voltage Range
Input Leakage Current
f
0.08
0
8
MHz
CLK
V
V
V
AIN_
REF
I
0.002
20
Q1
FA
ILA
Track
Hold
Input Capacitance
C
pF
V
AIN_
4
EXTERNAL REFERENCE INPUT (REF)
V
+
DD
0.05
Reference Input Voltage Range
V
I
1
REF
Reference Input Leakage Current
Reference Input Capacitance
Conversion stopped
0.005
5
Q1
FA
ILR
C
pF
REF
______________________________________________________________________________________ 11
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11662) (continued)
(V
DD
= 2.2V to 3.6V, V
= V , V
= V , f
= 8MHz, 50% duty cycle, 500ksps, C
= 10pF, T = -40NC to +125NC,
A
REF
DD OVDD
DD SCLK
DOUT
unless otherwise noted. Typical values are at T = +25NC.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SCLK, CS)
0.75 x
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Hysteresis
V
V
V
V
IH
V
OVDD
0.25 x
V
IL
V
OVDD
0.15 x
V
HYST
V
OVDD
0.001
2
Digital Input Leakage Current
Digital Input Capacitance
DIGITAL OUTPUT (DOUT)
I
IL
Inputs at GND or V
Q1
FA
DD
C
pF
IN
0.85 x
Output High Voltage
Output Low Voltage
V
I
I
= 200µA (Note 2)
SOURCE
V
V
OH
V
OVDD
0.15 x
V
= 200µA (Note 2)
SINK
OL
V
OVDD
High-Impedance Leakage
Current
I
Q1.0
FA
OL
High-Impedance Output
Capacitance
C
OUT
4
pF
POWER SUPPLY
Positive Supply Voltage
Digital I/O Supply Voltage
V
2.2
1.5
3.6
V
V
DD
V
V
DD
OVDD
I
V
V
= GND
= GND
1.6
Positive Supply Current
(Full-Power Mode)
VDD
AIN_
mA
mA
I
0.05
OVDD
AIN_
Positive Supply Current
(Full-Power Mode), No Clock
I
1.48
VDD
Power-Down Current
Line Rejection
I
Leakage only
= 2.2V to 3.6V, V
1.3
10
FA
PD
V
= 2.2V
REF
0.17
LSB/V
DD
TIMING CHARACTERISTICS (Note 1)
Quiet Time
t
4
10
5
ns
ns
ns
Q
t
CS Pulse Width
1
2
t
CS Fall to SCLK Setup
CS Falling Until DOUT High-
Impedance Disabled
t
(Note 2)
1
ns
ns
3
4
V
V
= 2.2V to 3.6V
= 1.5V to 2.2V
15
16.5
60
Data Access Time After SCLK
Falling Edge (Figure 2)
OVDD
t
OVDD
SCLK Pulse Width Low
SCLK Pulse Width High
t
t
Percentage of clock period
Percentage of clock period
40
40
%
%
5
60
6
Data Hold Time From SCLK
Falling Edge
SCLK Falling Until DOUT High
Impedance
t
Figure 3
5
ns
7
8
t
Figure 4 (Note 2)
Conversion cycle
2.5
14
1
ns
Power-Up Time
Cycle
12 _____________________________________________________________________________________
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11661)
(V
DD
= 2.2V to 3.6V. f
= 8MHz, 50% duty cycle, 500ksps. C
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical
DOUT A
SCLK
values are at T = +25NC.)
A
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
8
Bits
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
Q0.25
Q0.25
Q0.8
DNL
OE
No missing codes
Excluding offset and reference errors
Q0.45
Q0.04
Q0.75
Gain Error
GE
Q0.5
Total Unadjusted Error
DYNAMIC PERFORMANCE (f
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
Small-Signal Bandwidth
CONVERSION RATE
Throughput
TUE
= 250kHz)
SINAD
SNR
AIN
49
49
49.5
49.5
-70
66
dB
dB
THD
-67
dB
SFDR
IMD
63
dB
f = 239.8kHz, f = 200.2kHz
-65
40
dB
1
2
-3dB point
MHz
MHz
MHz
SINAD > 49dB
2.5
45
5
500
ksps
Fs
Conversion Time
1.56
52
Acquisition Time
t
ns
ACQ
Aperture Delay
4
ns
From CS falling edge
Aperture Jitter
15
ps
Serial-Clock Frequency
ANALOG INPUT (AIN)
Input Voltage Range
Input Leakage Current
f
0.08
0
8
MHz
CLK
V
V
V
AIN
DD
I
0.002
20
Q1
FA
ILA
Track
Hold
Input Capacitance
C
pF
AIN
4
DIGITAL INPUTS (SCLK, CS)
0.75 x
Digital Input High Voltage
V
V
V
V
IH
V
VDD
0.25 x
Digital Input Low Voltage
Digital Input Hysteresis
V
IL
V
VDD
0.15
V
HYST
V
VDD
Digital Input Leakage Current
Digital Input Capacitance
I
Inputs at GND or V
0.001
2
Q1
FA
IL
DD
C
pF
IN
______________________________________________________________________________________ 13
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11661) (continued)
(V
DD
= 2.2V to 3.6V. f
= 8MHz, 50% duty cycle, 500ksps. C
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical
DOUT A
SCLK
values are at T = +25NC.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUT (DOUT)
0.85 x
Output High Voltage
Output Low Voltage
V
I
I
= 200µA
SOURCE
V
V
OH
V
VDD
0.15 x
V
= 200µA
SINK
OL
OL
V
VDD
High-Impedance Leakage
Current
I
Q1.0
FA
pF
High-Impedance Output
Capacitance
C
OUT
4
POWER SUPPLY
Positive Supply Voltage
V
DD
2.2
3.6
V
Positive Supply Current
(Full-Power Mode)
I
V
AIN
= GND
1.76
mA
VDD
Positive Supply Current
(Full-Power Mode), No Clock
I
1.48
mA
VDD
Power-Down Current
Line Rejection
I
Leakage only
= 2.2V to 3.6V
1.3
10
FA
PD
V
0.17
LSB/V
DD
TIMING CHARACTERISTICS (Note 1)
Quiet Time
t
4
10
5
ns
ns
ns
Q
t
CS Pulse Width
1
2
t
CS Fall to SCLK Setup
CS Falling Until DOUT High-
Impedance Disabled
t
(Note 2)
1
ns
ns
3
4
Data Access Time After SCLK
Falling Edge
t
Figure 2, V
= 2.2V to 3.6V
15
DD
SCLK Pulse Width Low
SCLK Pulse Width High
t
t
Percentage of clock period
Percentage of clock period
40
40
60
60
%
%
5
6
Data Hold Time From SCLK
Falling Edge
t
Figure 3
5
ns
7
8
SCLK Falling Until DOUT High
Impedance
t
Figure 4 (Note 2)
Conversion cycle
2.5
14
1
ns
Power-Up Time
Cycle
Note 1: All timing specifications given are with a 10pF capacitor.
Note 2: Guaranteed by design in characterization; not production tested.
14 _____________________________________________________________________________________
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
SAMPLE
SAMPLE
t
1
t
6
t
5
CS
t
2
SCLK
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
HIGH
IMPEDANCE
HIGH
IMPEDANCE
DOUT
(MSB)
t
3
t
4
t
7
t
t
8 QUIET
t
t
ACQ
CONVERT
1/f
SAMPLE
Figure 1. Interface Signals for Maximum Throughput, 12-Bit Devices
t
7
t
4
SCLK
DOUT
SCLK
V
V
IH
IL
V
IH
OLD DATA
NEW DATA
OLD DATA
NEW DATA
DOUT
V
IL
Figure 3. Hold Time After SCLK Falling Edge
Figure 2. Setup Time After SCLK Falling Edge
t
8
SCLK
HIGH IMPEDANCE
DOUT
Figure 4. SCLK Falling Edge DOUT Three-State
______________________________________________________________________________________ 15
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Typical Operating Characteristics
(MAX11665AUT+, T = +25°C, unless otherwise noted.)
A
SOT23 TYPICAL OPERATING CHARACTERISTICS
INTEGRAL NONLINEARITY (INL)
vs. OUTPUT CODE
DIFFERENTIAL NONLINEARITY (DNL)
vs. OUTPUT CODE
OFFSET ERROR vs. TEMPERATURE
1.0
0.5
0
1.0
0.5
0
3
2
1
0
-0.5
-1.0
-0.5
-1.0
0
1000
2000
3000
4000
0
1000
2000
3000
4000
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
DIGITAL OUTPUT CODE (DECIMAL)
DIGITAL OUTPUT CODE (DECIMAL)
SIGNAL-TO-NOISE RATIO (SNR)
vs. ANALOG INPUT FREQUENCY
GAIN ERROR vs. TEMPERATURE
2
1
76
74
72
70
0
-1
-2
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
0
50
100
150
(kHz)
200
250
f
IN
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
vs. ANALOG INPUT FREQUENCY
THD vs. ANALOG INPUT FREQUENCY
95
93
91
89
87
85
-70
-80
-90
-100
0
50
100
f
150
(kHz)
200
250
0
50
100
f
150
(kHz)
200
250
IN
IN
16 _____________________________________________________________________________________
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Typical Operating Characteristics (continued)
(MAX11665AUT+, T = +25°C, unless otherwise noted.)
A
SOT23 TYPICAL OPERATING CHARACTERISTICS
SIGNAL-TO-NOISE AND DISTORTION RATIO
(SINAD) vs. ANALOG INPUT FREQUENCY
100kHz SINE-WAVE INPUT
76
74
72
70
0
-20
f
f
V
= 99.4kHz
IN
S
= 500ksps
= 3V
DD
-40
-60
A
= - 88dB
HD2
-80
-100
-120
0
50
100
150
(kHz)
200
250
0
50
100
150
200
250
f
FREQUENCY (kHz)
IN
SIGNAL-TO-NOISE RATIO (SNR)
vs. SUPPLY VOLTAGE (V
SUPPLY CURRENT vs. TEMPERATURE
)
DD
1.6
1.5
1.4
1.3
1.2
75
74
73
72
71
V
V
= 3.6V
= 3V
DD
DD
V
= 2.2V
DD
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
(V)
V
DD
THD vs. INPUT RESISTANCE
HISTOGRAM FOR 30,000 CONVERSIONS
-75
-80
35,000
30,000
25,000
20,000
15,000
10,000
5000
f
f
= 500ksps
S
= 250kHz
IN
-85
-90
-95
-100
0
0
20
40
60
80
100
2046
2047
2048
2049
2050
R
(I)
DIGITAL CODE OUTPUT
IN
______________________________________________________________________________________ 17
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Pin Configurations
TOP VIEW
TOP VIEW
+
+
V
DD
1
6
5
4
CS
AIN1
AIN2
AGND
REF
1
2
3
4
5
10
9
SCLK
DOUT
OVDD
CHSEL
CS
MAX11661
MAX11663
MAX11665
MAX11662
MAX11664
MAX11666
8
GND
AIN
2
3
DOUT
SCLK
7
V
DD
6
EP*
µMAX
SOT23
*CONNECT EP TO GROUND PLANE. DEVICES DO NOT OPERATE WHEN EP IS NOT CONNECTED TO GROUND!
Pin Description
PIN
NAME
AIN1
FUNCTION
µMAX
SOT23
Analog Input Channel 1. Single-ended analog input with respect to AGND with range of 0V to
1
—
V
.
REF
Analog Input Channel 2. Single-ended analog input with respect to AGND with range of 0V to
2
—
AIN2
V
REF.
—
—
3
3
2
AIN
Analog Input Channel. Single-ended analog input with respect to GND with range of 0V to V
Ground. Connect GND to the GND ground plane.
.
DD
GND
—
AGND Analog Ground. Connect AGND directly the GND ground plane.
External Reference Input. REF defines the signal range of the input signal AIN1/AIN2: 0V to V
.
REF
4
—
1
REF
The range of V
is 1V to V
Bypass REF to AGND with 10FF || 0.1FF capacitor.
REF
DD.
Positive Supply Voltage. Bypass V
with a 10FF || 0.1FF capacitor to GND. V
range is 2.2V
DD
DD
5
V
to 3.6V. For the SOT23 package, V
also defines the signal range of the input signal AIN: 0V to
DD
DD
V
DD
.
Active-Low Chip-Select Input. The falling edge of CS samples the analog input signal, starts a
conversion, and frames the serial-data transfer.
6
7
6
—
—
5
CS
Channel Select. Set CHSEL high to select AIN2 for conversion. Set CHSEL low to select AIN1 for
conversion.
CHSEL
OVDD
DOUT
SCLK
GND
Digital Interface Supply for SCLK, CS, DOUT, and CHSEL. The OVDD range is 1.5V to V
Bypass OVDD with a 10FF || 0.1FF capacitor to GND.
.
DD
8
Three-State Serial-Data Output. ADC conversion results are clocked out on the falling edge of
SCLK, MSB first. See Figure 1.
9
Serial-Clock Input. SCLK drives the conversion process. DOUT is updated on the falling edge of
SCLK. See Figures 2 and 3.
10
EP
4
Exposed Pad. Connect EP directly to a solid ground plane. Devices do not operate when EP is
not connected to ground!
—
18 _____________________________________________________________________________________
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Functional Diagrams
V
OVDD
V
DD
DD
MAX11661
MAX11663
MAX11665
MAX11662
MAX11664
MAX11666
CS
CS
CONTROL
LOGIC
CONTROL
LOGIC
SCLK
SCLK
DOUT
OUTPUT
BUFFER
DOUT
OUTPUT
BUFFER
SAR
SAR
CHSEL
AIN
AIN1
AIN2
CDAC
= V
MUX
CDAC
V
REF
REF
DD
AGND
GND (EP)
GND
Typical Operating Circuit
V
DD
OVDD
V
OVDD
+3V
AIN1
AIN2
MAX11662
MAX11664
MAX11666
SCLK
DOUT
SCK
CPU
ANALOG
INPUTS
MISO
SS
AGND
REF
CS
+2.5V
CHSEL
GND (EP)
V
DD
SCLK
DOUT
SCK
+3V
MAX11661
MAX11663
MAX11665
MISO
SS
CPU
GND
AIN
CS
ANALOG
INPUT
______________________________________________________________________________________ 19
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Detailed Description
The MAX11661–MAX11666 are fast, 12-/10-/8-bit, low-
power, single-supply ADCs. The devices operate from
a 2.2V to 3.6V supply and consume only 2.98mW
throughput rates. The wake-up and power-down feature
is controlled by using the SPI interface as described in
the Operating Modes section.
Serial Interface
The devices feature a 3-wire serial interface that directly
connects to SPI, QSPI, and MICROWIRE devices without
external logic. Figures 1 and 5 show the interface sig-
nals for a single conversion frame to achieve maximum
throughput.
(V
= 2.2V) or 4.37mW (V
= 3V). These devices
DD
DD
are capable of sampling at full rate when driven by
an 8MHz clock. The dual-channel devices provide a
separate digital supply input (OVDD) to power the digi-
tal interface enabling communication with 1.5V, 1.8V,
2.5V, or 3V digital systems.
The falling edge of CS defines the sampling instant.
Once CS transitions low, the external clock signal
(SCLK) controls the conversion.
The conversion result appears at DOUT, MSB first, with a
leading zero followed by the 12-bit, 10-bit, or 8-bit result.
A 12-bit result is followed by two trailing zeros, a 10-bit
result is followed by four trailing zeros, and an 8-bit result
is followed by six trailing zeros. See Figures 1 and 5.
The SAR core successively extracts binary-weighted bits
in every clock cycle. The MSB appears on the data bus
during the 2nd clock cycle with a delay outlined in the
timing specifications. All extracted data bits appear suc-
cessively on the data bus with the LSB appearing during
the 13th/11th/9th clock cycle for 12-/10-/8-bit operation.
The serial data stream of conversion bits is preceded by
a leading “zero” and succeeded by trailing “zeros.” The
data output (DOUT) goes into a high-impedance state
during the 16th clock cycle.
The dual-channel devices feature a dedicated refer-
ence input (REF). The input signal range for AIN1/AIN2
is defined as 0V to V
with respect to AGND. The
REF
single-channel devices use V
as the reference. The
DD
input signal range of AIN is defined as 0V to V
respect to GND.
with
DD
These ADCs include a power-down feature allowing
minimized power consumption at 2.5FA/ksps for lower
SAMPLE
SAMPLE
CS
SCLK
DOUT
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
HIGH
IMPEDANCE
HIGH
IMPEDANCE
SAMPLE
SAMPLE
CS
SCLK
DOUT
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 5. 10-/8-Bit Timing Diagrams
20 _____________________________________________________________________________________
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
To sustain the maximum sample rate, all devices have to
be resampled immediately after the 16th clock cycle. For
lower sample rates, the CS falling edge can be delayed
leaving DOUT in a high-impedance condition. Pull CS
high after the 10th SCLK falling edge (see the Operating
Modes section).
The source impedance of the external driving stage in
conjunction with the sampling switch resistance affects
the settling performance. The THD vs. Input Resistance
graph in the Typical Operating Characteristics shows
THD sensitivity as a function of the signal source imped-
ance. Keep the source impedance at a minimum for
high-dynamic-performance applications. Use a high-
performance op amp such as the MAX4430 to drive the
analog input, thereby decoupling the signal source and
the ADC.
Analog Input
The devices produce a digital output that corresponds to
the analog input voltage within the specified operating
range of 0V to V
for the dual-channel devices and 0V
REF
While the ADC is in conversion mode, the sampling
to V
for the single-channel devices.
DD
switch is open presenting a pin capacitance, C (C
P
P
Figure 6 shows an equivalent circuit for the analog input
AIN (for single-channel devices) and AIN1/AIN2 (for
dual-channel devices). Internal protection diodes D1/D2
confine the analog input voltage within the power rails
= 5pF), to the driving stage. See the Applications
Information section for information on choosing an
appropriate buffer for the ADC.
(V , GND). The analog input voltage can swing from
ADC Transfer Function
The output format is straight binary. The code transi-
tions midway between successive integer LSB values
DD
GND - 0.3V to V
+ 0.3V without damaging the device.
DD
The electric load presented to the external stage driv-
ing the analog input varies depending on which mode
the ADC is in: track mode vs. conversion mode. In track
such as 0.5 LSB, 1.5 LSB, etc. The LSB size for single-
n
channel devices is V /2 and for dual-channel devices
DD
n
is V
/2 , where n is the resolution. The ideal transfer
REF
mode, the internal sampling capacitor C (16pF) has to
S
characteristic is shown in Figure 10.
be charged through the resistor R (R = 50I) to the input
voltage. For faithful sampling of the input, the capacitor
Operating Modes
voltage on C has to settle to the required accuracy dur-
S
The ICs offer two modes of operation: normal mode and
power-down mode. The logic state of the CS signal
during a conversion activates these modes. The power-
down mode can be used to optimize power dissipation
with respect to sample rate.
ing the track time.
SWITCH CLOSED IN TRACK MODE
SWITCH OPEN IN CONVERSION MODE
V
DD
Normal Mode
In normal mode, the devices are powered up at all times,
thereby achieving their maximum throughput rates.
Figure 7 shows the timing diagram of these devices in
normal mode. The falling edge of CS samples the analog
input signal, starts a conversion, and frames the serial-
data transfer.
D1
D2
C
S
R
AIN1/AIN2
AIN
C
P
Figure 6. Analog Input Circuit
KEEP CS LOW UNTIL AFTER THE 10TH SCLK FALLING EDGE
PULL CS HIGH AFTER THE 10TH SCLK FALLING EDGE
CS
SCLK
DOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VALID DATA
HIGH
HIGH
IMPEDANCE
IMPEDANCE
Figure 7. Normal Mode
______________________________________________________________________________________ 21
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
PULL CS HIGH AFTER THE 2ND AND BEFORE THE 10TH SCLK FALLING EDGE
CS
SCLK
DOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HIGH
IMPEDANCE
INVALID
DATA
INVALID DATA OR HIGH IMPEDANCE
HIGH IMPEDANCE
Figure 8. Entering Power-Down Mode
CS
SCLK
DOUT
HIGH
IMPEDANCE
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
N
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
INVALID DATA (DUMMY CONVERSION)
VALID DATA
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 9. Exiting Power-Down Mode
However, pulling CS high before the 10th SCLK falling
edge terminates the conversion, DOUT goes into high-
impedance mode, and the device enters power-down
mode. See Figure 8.
OUTPUT CODE
FS - 1.5 x LSB
111...111
111...110
111...101
Power-Down Mode
In power-down mode, all bias circuitry is shut down
drawing typically only 1.3FA of leakage current. To save
power, put the device in power-down mode between
conversions. Using the power-down mode between
conversions is ideal for saving power when sampling the
analog input infrequently.
000...010
000...001
000...000
Entering Power-Down Mode
To enter power-down mode, drive CS high between the
2nd and 10th falling edges of SCLK (see Figure 8). By
pulling CS high, the current conversion terminates and
DOUT enters high impedance.
ANALOG
INPUT (LSB)
n
n
n
0
1
2
3
2 -2 2 -1 2
FULL SCALE (FS):
AIN1/AIN2 = REF (TDFN, µMAX)
Exiting Power-Down Mode
To exit power-down mode, implement one dummy con-
version by driving CS low for at least 10 clock cycles
(see Figure 9). The data on DOUT is invalid during this
dummy conversion. The first conversion following the
dummy cycle contains a valid conversion result.
AIN = V (SOT23)
n = RESOLUTION
DD
Figure 10. ADC Transfer Function
To remain in normal mode, keep CS low until the falling
edge of the 10th SCLK cycle. Pulling CS high after the
10th SCLK falling edge keeps the part in normal mode.
The power-up time equals the duration of the dummy
cycle, and is dependent on the clock frequency. The
power-up time for 500ksps operation (8MHz SCLK) is 2Fs.
22 _____________________________________________________________________________________
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
is never powered down. The user can also power down
the ADC between conversions by using the power-down
mode. Figure 12 shows for the 500ksps device that as
the sample rate is reduced, the device remains in the
power-down state longer and the average supply cur-
Supply Current vs. Sampling Rate
For applications requiring lower throughput rates, the
user can reduce the clock frequency (f ) to lower
SCLK
the sample rate. Figure 11 shows the typical supply
current (I ) as a function of sample rate (f for the
VDD
S)
rent (I
) drops accordingly.
VDD
500ksps devices. The part operates in normal mode and
SUPPLY CURRENT vs. SAMPLING RATE
SUPPLY CURRENT vs. SAMPLING RATE
2.0
1.5
1.0
0.5
0
V
f
= 3V
V
f
= 3V
DD
DD
= 8MHz
= VARIABLE
SCLK
SCLK
16 CYCLES/CONVERSIONS
1.5
1.0
0.5
0
0
100
200
300
400
500
0
20 40 60 80 100 120 140 160
SAMPLING RATE (ksps)
SAMPLING RATE (ksps)
Figure 11. Supply Current vs. Sample Rate (Normal Operating
Mode)
Figure 12. Supply Current vs. Sample Rate (Device Powered
Down Between Conversions)
______________________________________________________________________________________ 23
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Dual-Channel Operation
Applications Information
The MAX11662/MAX11664/MAX11666 feature dual-input
channels. These devices use a channel-select (CHSEL)
input to select between analog input AIN1 (CHSEL = 0)
or AIN2 (CHSEL = 1). As shown in Figure 13, the CHSEL
signal is required to change between the 2nd and 12th
clock cycle within a regular conversion to guarantee
proper switching between channels.
Layout, Grounding, and Bypassing
For best performance, use PCBs with a solid ground
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
lines underneath the ADC package. Noise in the V
DD
power supply, OVDD, and REF affects the ADC’s perfor-
mance. Bypass the V , OVDD, and REF to ground with
0.1FF and 10FF bypass capacitors. Minimize capacitor
lead and trace lengths for best supply-noise rejection.
DD
14-Cycle Conversion Mode
The ICs can operate with 14 cycles per conversion.
Figure 14 shows the corresponding timing diagram.
Observe that DOUT does not go into high-impedance
Choosing an Input Amplifier
It is important to match the settling time of the input
amplifier to the acquisition time of the ADC. The conver-
sion results are accurate when the ADC samples the
input signal for an interval longer than the input signal’s
worst-case settling time. By definition, settling time is
the interval between the application of an input voltage
step and the point at which the output signal reaches
mode. Also, observe that t
needs to be sufficiently
ACQ
long to guarantee proper settling of the analog input
voltage. See the Electrical Characteristics table for t
ACQ
requirements and the Analog Input section for a descrip-
tion of the analog inputs.
CS
SCLK
CHSEL
DOUT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
DATA CHANNEL AIN2
DATA CHANNEL AIN1
Figure 13. Channel Select Timing Diagram
SAMPLE
SAMPLE
CS
SCLK
DOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
(MSB)
t
ACQ
1/f
SAMPLE
t
CONVERT
Figure 14. 14-Clock Cycle Operation
24 _____________________________________________________________________________________
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
and stays within a given error band centered on the
resulting steady-state amplifier output level. The ADC
input sampling capacitor charges during the sampling
cycle, referred to as the acquisition period. During this
acquisition period, the settling time is affected by the
input resistance and the input sampling capacitance.
This error can be estimated by looking at the settling of
an RC time constant using the input capacitance and
the source impedance over the acquisition time period.
Choosing a Reference
For devices using an external reference, the choice of
the reference determines the output accuracy of the
ADC. An ideal voltage reference provides a perfect initial
accuracy and maintains the reference voltage indepen-
dent of changes in load current, temperature, and time.
Considerations in selecting a reference include initial
voltage accuracy, temperature drift, current source,
sink capability, quiescent current, and noise. Figure 15
shows a typical application circuit using the MAX6126
to provide the reference voltage. The MAX6033 and
MAX6043 are also excellent choices.
Figure 15 shows a typical application circuit. The
MAX4430, offering a settling time of 37ns at 16 bits, is
an excellent choice for this application. See the THD
vs. Input Resistance graph in the Typical Operating
Characteristics.
+5V
0.1µF
10µF
3V
V
OVDD
100pF C0G
V
DD
OVDD
500I
10µF
0.1µF
SCK
10µF
0.1µF
AGND
AIN1
500I
5
AIN1
3
10I
1
MAX11662
MAX11664
MAX11666
MAX4430
470pF
C0G CAPACITOR
-5V
SCLK
DOUT
CS
V
DC
4
2
AIN2
REF
MISO
SS
470pF
C0G CAPACITOR
CPU
+3V
0.1µF
10µF
CHSEL
10µF
+5V
EP
0.1µF
10µF
7
8
2
1
OUTF
OUTS
IN
100pF C0G
0.1µF
1µF
500I
0.1µF
MAX6126
4
3
GNDS
NR
500I
5
AIN2
3
4
0.1µF
10I
GND
1
MAX4430
-5V
V
DC
2
0.1µF
10µF
Figure 15. Typical Application Circuit
______________________________________________________________________________________ 25
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Signal-to-Noise Ratio and Distortion
(SINAD)
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. For
these devices, the straight line is a line drawn between
the end points of the transfer function after offset and
gain errors are nulled.
SINAD is a dynamic figure of merit that indicates the
converter’s noise and distortion performance. SINAD
is computed by taking the ratio of the RMS signal to
the RMS noise plus distortion. RMS noise plus distor-
tion includes all spectral components to the Nyquist
frequency excluding the fundamental and the DC offset:
.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB or less guarantees no mis-
sing codes and a monotonic transfer function.
SIGNAL
RMS
SINAD(dB) = 20 × log
NOISE + DISTORTION
(
)
RMS
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
Offset Error
The deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, that is, AGND + 0.5 LSB.
Gain Error
The deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal after adjusting for the offset
2
2
2
2
5
V
+ V + V + V
3 4
2
THD = 20 × log
V
1
error, that is, V
- 1.5 LSB.
REF
Aperture Jitter
where V is the fundamental amplitude and V –V are
the amplitudes of the 2nd- through 5th-order harmonics.
1
2
5
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
Spurious-Free Dynamic Range (SFDR)
SFDR is a dynamic figure of merit that indicates the low-
est usable input signal amplitude. SFDR is the ratio of
the RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest spuri-
ous component, excluding DC offset. SFDR is specified
in decibels with respect to the carrier (dBc).
Aperture Delay
Aperture delay (t ) is the time between the falling edge
AD
of sampling clock and the instant when an actual sample
is taken.
Signal-to-Noise Ratio (SNR)
SNR is a dynamic figure of merit that indicates the con-
verter’s noise performance. For a waveform perfectly
reconstructed from digital samples, the theoretical maxi-
mum SNR is the ratio of the full-scale analog input (RMS
value) to the RMS quantization error (residual error).
The ideal, theoretical minimum analog-to-digital noise
is caused by quantization error only and results directly
from the ADC’s resolution (N bits):
Full-Power Bandwidth
Full-power bandwidth is the frequency at which the input
signal amplitude attenuates by 3dB for a full-scale input.
Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the
signal-to-noise ratio and distortion (SINAD) is equal to a
specified value.
SNR (dB) (MAX) = (6.02 x N + 1.76) (dB)
Intermodulation Distortion
Any device with nonlinearities creates distortion prod-
ucts when two sine waves at two different frequencies
In reality, there are other noise sources such as thermal
noise, reference noise, and clock jitter that also degrade
SNR. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spectral
components to the Nyquist frequency excluding the
fundamental, the first five harmonics, and the DC offset.
(f and f ) are applied into the device. Intermodulation
1
2
distortion (IMD) is the total power of the IM2 to IM5 inter-
modulation products to the Nyquist frequency relative to
the total input power of the two input tones, f and f . The
1
2
.
individual input tone levels are at -6dBFS
26 _____________________________________________________________________________________
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Chip Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PROCESS: CMOS
LAND
PATTERN
NO.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
10 µMAX
6 SOT23
U10E+3
U6+1
21-0109
21-0058
90-0148
90-0175
______________________________________________________________________________________ 27
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
11/10
1/11
0
1
Initial release
Released the MAX11663 and updated Figures 11 and 12.
—
1, 23
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
28
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
©
相关型号：
MAX11665AUT+T
A/D Converter, 12-Bit, 1 Func, 1 Channel, Serial Access, CMOS, PDSO6, 2.90 X 2.80 MM, ROHS COMPLIANT, SOT-23, 6 PIN
MAXIM
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