MAX1165BEUI [MAXIM]
Low-Power, 16-Bit Analog-to-Digital Converters with Parallel Interface; 低功耗， 16位模数转换，并行接口转换器
| 型号： | MAX1165BEUI |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Power, 16-Bit Analog-to-Digital Converters with Parallel Interface |
| 文件： | 总15页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2551; Rev 0; 6/02
Low-Power, 16-Bit Analog-to-Digital Converters
with Parallel Interface
General Description
Features
The MAX1165/MAX1166 16-bit, low-power, successive-
approximation analog-to-digital converters (ADCs) fea-
ture automatic power-down, factory-trimmed internal
clock, and a 16-bit wide (MAX1165) or byte wide
(MAX1166) parallel interface. The devices operate from
a single +4.75V to +5.25V analog supply and a +2.7V
to +5.25V digital supply.
o 16-Bit Wide (MAX1165) and Byte Wide (MAX1166)
Parallel Interface
o High Speed: 165ksps Sample Rate
o Accurate: ±±2SB Iꢀ2L 16 Bit ꢀN Missing ꢁNdes
o 4.096VL 35ppm/°ꢁ Internal Reference
o External Reference Range: +3.8V tN +5.±5V
o Single +4.75V tN +5.±5V AnalNg Supply VNltage
o +±.7V tN +5.±5V Digital Supply VNltage
The MAX1165/MAX1166 use an internal 4.096V refer-
ence or an external reference. The MAX1165/MAX1166
consume only 1.8mA at a sampling rate of 165ksps with
external reference and 2.7mA with internal reference.
AutoShutdown™ reduces supply current to 0.1mA at
10ksps.
o 2Nw Supply ꢁurrent
1.8mA (External Reference)
±.7mA (Internal Reference)
0.1µA (10kspsL External Reference)
The MAX1165/MAX1166 are ideal for high-perfor-
mance, battery-powered, data-acquisition applications.
Excellent dynamic performance and low power con-
sumption in a small package make the MAX1165/
MAX1166 ideal for circuits with demanding power con-
sumption and space requirements.
o Small FNNtprint
±8-Pin TSSOP Package (16-Bit Wide)
±0-Pin TSSOP Package (Byte Wide)
Ordering Information
The 16-bit wide MAX1165 is available in a 28-pin
TSSOP package and the byte wide MAX1166 is avail-
able in a 20-pin TSSOP package. Both devices are
available in either the 0°C to +70°C commercial, or the
-40°C to +85°C extended temperature range.
PART
TEMP RANGE PIN-PACKAGE
0°C to +70°C 28 TSSOP
0°C to +70°C 28 TSSOP
0°C to +70°C 28 TSSOP
-40°C to +85°C 28 TSSOP
-40°C to +85°C 28 TSSOP
-40°C to +85°C 28 TSSOP
INL
2
MAX1165ACUI*
MAX1165BCUI
MAX1165CCUI
MAX1165AEUI*
MAX1165BEUI*
MAX1165CEUI*
2
4
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
2
2
4
Applications
*Future product—contact factory for availability.
Temperature Sensor/Monitor
Industrial Process Control
I/O Boards
Ordering Information continued at end of data sheet.
Typical Operating Circuit
Data-Acquisition Systems
Cable/Harness Tester
Accelerometer Measurements
Digital Signal Processing
+5V ANALOG
+5V DIGITAL
0.1µF
0.1µF
µP DATA
BUS
DV
DD
D0–D15
AV
DD
ANALOG INPUT
AIN
Pin Configurations appear at end of data sheet.
Functional Diagram appears at end of data sheet.
MAX1165
EOC
R/C
CS
REF
REFADJ
RESET
AGND DGND
0.1µF
4.7µF
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
ABSOLUTE MAXIMUM RATINGS
AV
DV
to AGND .........................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
DD
DD
A
to DGND ........................................-0.3V to (AV
+ 0.3V)
20-Pin TSSOP (derate 10.9mW/°C above+70°C) ........879mW
28-Pin TSSOP (derate 12.8mW/°C above +70°C) .....1026mW
Operating Temperature Ranges
DD
AGND to DGND.....................................................-0.3V to +0.3V
AIN, REF, REFADJ to AGND....................-0.3V to (AV + 0.3V)
DD
MAX116_ _CU_...................................................0°C to +70°C
MAX116_ _EU_................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
CS, HBEN, R/C, RESET to DGND ............................-0.3V to +6V
Digital Output (D15–D0, EOC)
to DGND ..............................................-0.3V to (DV
+ 0.3V)
DD
Maximum Continuous Current Into Any Pin ........................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= DV
= +5V, external reference = +4.096V, C
= 4.7µF, C
= 0.1µF, T = T
to T
, unless otherwise noted.
MAX
DD
DD
REF
REFADJ
A
MIN
Typical values are at T = +25°C.)
A
PARAMETER
DC ACCURACY
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
N
16
-1
MAX116_A
MAX116_B
MAX116_C
2
2
Relative Accuracy
(Note 1)
INL
LSB
4
MAX116_A
MAX116_B
1
No missing codes
over temperature
Differential Nonlinearity
Transition Noise
DNL
LSB
1.5
2
MAX116_C
RMS noise, external reference, includes
quantization noise
0.65
LSB
LSB
RMS
Internal reference
0.7
0.05
0.002
0.6
RMS
Offset Error
Gain Error
Offset Drift
Gain Drift
1
mV
(Note 2)
0.02
%FSR
ppm/°C
ppm/°C
0.2
DYNAMIC PERFORMANCE (f
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Sample Rate
= 1kHz, V = 4.096V , 165ksps)
IN(SINE-WAVE)
SINAD
SNR
IN
P-P
86
87
90
90
dB
dB
THD
-102
105
4
-90
dB
SFDR
92
dB
-3dB point
MHz
kHz
SINAD > 81dB
33
f
165
ksps
ns
SAMPLE
Aperture Delay
27
Aperture Jitter
<100
ps
ANALOG INPUT
Input Range
V
0
V
V
AIN
AIN
REF
Input Capacitance
C
40
pF
2
_______________________________________________________________________________________
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +5V, external reference = +4.096V, C
= 4.7µF, C
= 0.1µF, T = T
to T
, unless otherwise noted.
MAX
DD
DD
REF
REFADJ
A
MIN
Typical values are at T = +25°C.)
A
PARAMETER
INTERNAL REFERENCE
REF Output Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
4.056
4.096
25
4.136
V
ppm/°C
mA
REF
REF Output Tempco
TC
REF
REFSC
REFADJ
REF Short-Circuit Current
Capacitive Bypass at REFADJ
Capacitive Bypass at REF
REFADJ Input Leakage Current
EXTERNAL REFERENCE
I
10
C
0.1
1
µF
C
µF
REF
REFADJ
I
20
µA
AV
0.4
-
AV
0.1
-
DD
DD
REFADJ Buffer Disable Threshold
REF Input Voltage Range
REF Input Current
To power down the internal reference
Internal reference disabled
V
V
3.8
AV
DD
V
= +4.096V, f
= 165ksps
SAMPLE
50
120
REF
I
µA
REF
Shutdown mode
0.1
DIGITAL INPUTS/OUTPUTS
Input High Voltage
0.7 ×
V
V
V
IH
DV
DD
0.3 ×
Input Low Voltage
V
IL
DV
DD
Input Leakage Current
Input Hysteresis
I
V
= 0 or DV
DD
0.1
0.1
15
1
µA
V
IN
IH
V
HYST
Input Capacitance
C
pF
IN
I
= 0.5mA, DV
= +5.25V
= +2.7V to +5.25V,
DV
0.4
-
DD
SOURCE
DD
Output High Voltage
Output Low Voltage
V
V
V
OH
AV
DD
I
= 1.6mA, DV
= +5.25V
= +2.7V to +5.25V,
DD
SINK
V
0.4
10
OL
AV
DD
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply
I
D0–D15
0.1
15
µA
pF
OZ
C
OZ
AV
DV
4.75
2.7
5.25
V
V
DD
AV
DD
DD
165ksps
2.7
2.0
1.0
1.0
1.8
1.1
0.1
0.01
3.2
100ksps
10ksps
1ksps
Internal reference
External reference
Analog Supply Current
I
mA
AVDD
165ksps
100ksps
10ksps
1ksps
2.3
_______________________________________________________________________________________
3
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +5V, external reference = +4.096V, C
= 4.7µF, C
= 0.1µF, T = T
A
to T
, unless otherwise noted.
MAX
DD
DD
REF
REFADJ
MIN
Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
0.5
MAX
UNITS
165ksps
100ksps
10ksps
1ksps
0.7
0.3
Digital Supply Current
I
I
D0–D15 = all zeros
mA
DVDD
SHDN
0.03
0.003
0.5
I
I
5
5
AVDD
DVDD
Full power-down
µA
mA
µA
dB
0.5
Shutdown Supply Current
I
1.0
1.2
AVDD
REF and REF buffer enabled
(standby mode)
I
DVDD
0.5
68
5
(Note 3)
Power-Supply Rejection Ratio
PSRR
AV
= +5V 5%, full-scale input (Note 4)
DD
TIMING CHARACTERISTICS (Figures 1 and 2)
(AV
= +4.75V to +5.25V, DV
= +2.7V to AV , external reference = +4.096V, C
= 4.7µF, C
= 0.1µF, C = 20pF,
LOAD
DD
DD
DD
REF
REFADJ
T
A
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
µs
Acquisition Time
Conversion Time
CS Pulse Width High
t
1.1
ACQ
t
4.7
CONV
t
(Note 5)
40
40
60
0
ns
CSH
V
V
= 4.75V to 5.25V
DVDD
DVDD
CS Pulse Width Low (Note 5)
R/C to CS Fall Setup Time
R/C to CS Fall Hold Time
t
ns
CSL
= 2.7V to 5.25V
t
ns
DS
V
V
V
V
V
V
= 4.75V to 5.25V
= 2.7V to 5.25V
= 4.75V to 5.25V
= 2.7V to 5.25V
= 4.75V to 5.25V
= 2.7V to 5.25V
40
60
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
t
ns
DH
40
80
40
80
CS to Output Data Valid
t
ns
DO
HBEN Transition to Output Data
Valid (MAX1166 Only)
t
ns
ns
ns
DO1
EOC Fall to CS Fall
t
0
DV
V
V
V
V
= 4.75V to 5.25V
= 2.7V to 5.25V
= 4.75V to 5.25V
= 2.7V to 5.25V
40
80
40
80
DVDD
DVDD
DVDD
DVDD
CS Rise to EOC Rise
t
EOC
Bus Relinquish Time (Note 5)
t
ns
BR
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 2: Offset nulled.
Note 3: Shutdown supply currents are typically 0.5µA, maximum specification is limited by automated test equipment.
Note 4: Defined as the change in positive full scale caused by a 5% variation in the nominal supply.
Note 5: To ensure best performance, finish reading the data and wait t before starting a new acquisition.
BR
4
_______________________________________________________________________________________
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
Typical Operating Characteristics
(AV
= DV
= +5V, external reference = +4.096V, C
= 4.7µF, C
= 0.1µF, T = +25°C, unless otherwise noted.)
DD
DD
REF
REFADJ A
IAV + IDV SUPPLY CURRENT
DD
DD
INL vs. OUTPUT CODE
DNL vs. OUTPUT CODE
vs. SAMPLE RATE
2.0
1.5
2.0
1.5
10
1
1.0
1.0
0.5
0.5
0.1
0
0
0.01
0.001
0.0001
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
0
16384
32768
49152
65536
0
16384
32768
49152
66536
0.01
0.1
1
10
100
1000
OUTPUT CODE
OUTPUT CODE
SAMPLE RATE (ksps)
IAV + IDV SHUTDOWN CURRENT
INTERNAL REFERENCE
vs. TEMPERATURE
IAV + IDV SUPPLY CURRENT
DD
DD
DD
DD
vs. TEMPERATURE
vs. TEMPERATURE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.136
4.126
4.116
4.106
4.096
4.086
4.076
4.066
4.056
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
SAMPLE RATE = 165ksps
20 40 60 80
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
-40
-20
0
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
OFFSET ERROR
vs. TEMPERATURE
GAIN ERROR
vs. TEMPERATURE
SINAD vs. FREQUENCY
1000
800
100
90
80
70
60
50
40
30
20
10
0
0.020
0.015
0.010
0.005
0
600
400
200
0
-200
-400
-600
-800
-1000
-0.005
-0.010
-0.015
-0.020
SAMPLE RATE = 165ksps
10 100
FREQUENCY (kHz)
-40
-20
0
20
40
60
80
0.1
1
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
Typical Operating Characteristics (continued)
(AV
= DV
= +5V, external reference = +4.096V, C
= 4.7µF, C
= 0.1µF, T = +25°C, unless otherwise noted.)
DD
DD
REF
REFADJ
A
THD vs. FREQUENCY
SFDR vs. FREQUENCY
0
120
110
100
90
SAMPLE RATE = 165ksps
-10
-20
-30
80
-40
70
-50
60
-60
50
-70
40
-80
30
-90
20
-100
-110
10
SAMPLE RATE = 165ksps
0
0.1
1
10
100
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
SNR vs. FREQUENCY
FFT AT 1kHz
120
110
100
90
0
-20
SAMPLE RATE = 165ksps
-40
80
70
-60
60
-80
50
40
-100
-120
-140
30
20
10
SAMPLE RATE = 165ksps
0
0.1
1
10
100
0
20
40
60
80
FREQUENCY (kHz)
FREQUENCY (kHz)
6
_______________________________________________________________________________________
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
Pin Description
PIN
NAME
FUNCTION
MAX1165 MAX1166 MAX1165 MAX1166
1
2
3
4
5
6
7
8
1
2
D8
D4/D12 Three-State Digital Data Output
D5/D13 Three-State Digital Data Output
D6/D14 Three-State Digital Data Output
D9
3
D10
D11
D12
D13
D14
D15
4
D7/D15 Three-State Digital Data Output. D15 is the MSB.
—
—
—
—
—
—
—
—
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output (MSB)
Read/Convert Input. Power up and put the MAX1165/MAX1166 in acquisition mode
by holding R/C low during the first falling edge of CS. During the second falling
edge of CS, the level on R/C determines whether the reference and reference
buffer power down or remain on after conversion. Set R/C high during the second
falling edge of CS to power down the reference and buffer, or set R/C low to leave
the reference and buffer powered up. Set R/C high during the third falling edge of
CS to put valid data on the bus.
9
5
R/C
10
11
12
13
6
7
8
9
EOC
End of Conversion. EOC drives low when conversion is complete.
Analog Supply Input. Bypass with a 0.1µF capacitor to AGND.
Analog Ground. Primary analog ground (star ground).
Analog Input
AV
DD
AGND
AIN
Analog Ground. Connect pin 14 to pin 12 (MAX1165). Connect pin 10 to pin 8
(MAX1166).
14
15
10
11
AGND
Reference Buffer Output. Bypass REFADJ with a 0.1µF capacitor to AGND for internal
reference mode. Connect REFADJ to AV to select external reference mode.
DD
REFADJ
Reference Input/Output. Bypass REF with a 4.7µF capacitor to AGND for internal
reference mode. External reference input when in external reference mode.
16
17
12
REF
—
RESET
Reset Input. Logic high resets the device.
High-Byte Enable Input. Used to multiplex the 14-bit conversion result:
1: Most significant byte available on the data bus.
0: Least significant byte available on the data bus.
—
13
14
HBEN
Convert Start. The first falling edge of CS powers up the device and enables
acquire mode when R/C is low. The second falling edge of CS starts conversion.
The third falling edge of CS loads the result onto the bus when R/C is high.
18
CS
19
20
21
22
23
24
25
26
27
28
15
16
17
18
19
20
—
—
—
—
DGND
Digital Ground
DV
Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND.
Three-State Digital Data Output
DD
D0
D1
D2
D3
D4
D5
D6
D7
D0/D8
D1/D9
Three-State Digital Data Output
D2/D10 Three-State Digital Data Output
D3/D11 Three-State Digital Data Output
—
—
—
—
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output
_______________________________________________________________________________________
7
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
Analog Input
DV
DD
The equivalent input circuit is shown in Figure 4. A
switched capacitor digital-to-analog converter (DAC)
provides an inherent T/H function. The single-ended
input is connected between AIN and AGND.
1mA
D0–D15
D0–D15
1mA
C
= 20pF
LOAD
Input Bandwidth
The ADC’s input-tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use anti-alias filtering.
C
= 20pF
LOAD
DGND
DGND
a) HIGH-Z TO V , V TO V
,
b) HIGH-Z TO V , V TO V ,
OL OH OL
OH OL
OH
AND V TO HIGH-Z
AND V TO HIGH-Z
OH
OL
Figure 1. Load Circuits
Analog Input Protection
Detailed Description
Internal protection diodes, which clamp the analog
input to AV
and/or AGND, allow the input to swing
DD
Converter Operation
from AGND - 0.3V to AV
the device.
+ 0.3V, without damaging
DD
The MAX1165/MAX1166 use a successive-approxima-
tion (SAR) conversion technique with an inherent track-
and-hold (T/H) stage to convert an analog input into a
16-bit digital output. Parallel outputs provide a high-
speed interface to most microprocessors (µPs). The
Functional Diagram shows a simplified internal archi-
tecture of the MAX1165/MAX1166. Figure 3 shows a
typical application circuit for the MAX1166.
If the analog input exceeds 300mV beyond the sup-
plies, limit the input current to 10mA.
t
CSH
t
CSL
CS
t
ACQ
REF POWER-
DOWN BIT
R/C
t
t
DS
t
t
t
DH
DV
EOC
EOC
D0–D15
HBEN*
t
CONV
BR
t
DO
HIGH-Z
HIGH-Z
DATA VALID
t
BR
t
DO1
D8/D15–
D0/D7*
HIGH-/LOW-
BYTE VALID
HIGH-/LOW-
BYTE VALID
*HBEN AND BYTE-WIDE DATA BUS
AVAILABLE ON MAX1166 ONLY.
Figure 2. MAX1165/MAX1166 Timing Diagram
8
_______________________________________________________________________________________
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
REF
+5V ANALOG
+5V DIGITAL
TRACK
CAPACITIVE DAC
AIN
0.1µF
0.1µF
ZERO
C
SWITCH
3pF
C
= 32pF
R
DAC
IN
800Ω
HOLD
µP DATA
BUS
AV
DD
DV
DD
AGND
D0–D7
TRACK
HOLD
ANALOG INPUT
AIN
OR
D8–D15
AUTOZERO
RAIL
MAX1166
EOC
R/C
CS
REF
Figure 4. Equivalent Input Circuit
REFADJ
HBEN
HIGH
BYTE
AGND DGND
0.1µF
4.7µF
Power-Down Modes
Select standby mode or shutdown mode with the R/C
bit during the second falling edge of CS (see the
Selecting Standby or Shutdown Mode section). The
MAX1165/MAX1166 automatically enter either standby
mode (reference and buffer on) or shutdown (reference
and buffer off) after each conversion depending on the
status of R/C during the second falling edge of CS.
LOW
BYTE
Figure 3. Typical Application Circuit for the MAX1166
Track and Hold (T/H)
In track mode, the analog signal is acquired on the inter-
nal hold capacitor. In hold mode, the T/H switches open
and the capacitive DAC samples the analog input.
Internal Clock
The MAX1165/MAX1166 generate an internal conver-
sion clock. This frees the microprocessor from the bur-
den of running the SAR conversion clock. Total
conversion time after entering hold mode (second
falling edge of CS) to end of conversion (EOC) falling is
4.7µs (max).
During the acquisition, the analog input (AIN) charges
capacitor C
. The acquisition ends on the second
DAC
falling edge of CS. At this instant, the T/H switches
open. The retained charge on C
ple of the input.
represents a sam-
DAC
In hold mode, the capacitive DAC adjusts during the
remainder of the conversion time to restore node ZERO
to zero within the limits of 16-bit resolution. Force CS low
to put valid data on the bus at the end of the conversion.
Applications Information
Starting a Conversion
CS and R/C control acquisition and conversion in the
MAX1165/MAX1166 (Figure 2). The first falling edge of
CS powers up the device and puts it in acquire mode if
R/C is low. The convert start is ignored if R/C is high.
The MAX1165/MAX1166 need at least 10ms
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(C
= 0.1µF, C
= 4.7µF) for the internal refer-
REFADJ
REF
(t
) is the maximum time the device takes to acquire
ACQ
ence to wake up and settle before starting the conver-
sion if powering up from shutdown. The ADC can wake
up, from shutdown, to an unknown state. Put the ADC
in a known state by completing one “dummy” conver-
sion. The MAX1165/MAX1166 are in a known state,
ready for actual data acquisition, after the completion
of the dummy conversion. A dummy conversion con-
sists of one full conversion cycle.
the signal. Use the following formula to calculate acqui-
sition time:
t
= 11 (R + R ) ✕ 35pF
S IN
ACQ
where R = 800Ω, R = the input signal’s source
IN
S
ACQ
impedance, and t
is never less than 1.1µs. A
source impedance less than 1kΩ does not significantly
affect the ADC’s performance.
The MAX1165 provides an alternative reset function to
reset the device (see the RESET section).
To improve the input signal bandwidth under AC condi-
tions, drive AIN with a wideband buffer (>4MHz) that
can drive the ADC’s input capacitance and settle
quickly.
_______________________________________________________________________________________
9
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
DATA
OUT
DATA
OUT
CONVERSION
ACQUISITION
CONVERSION
ACQUISITION
CS
R/C
CS
R/C
REF POWER-
DOWN BIT
REF POWER-
DOWN BIT
EOC
EOC
REF
AND
BUFFER
REF
AND
BUFFER
Figure 6. Selecting Shutdown Mode
Figure 5. Selecting Standby Mode
causes the reference and buffer to wake up and enter
acquisition mode. To achieve 16-bit accuracy, allow
Selecting Standby or Shutdown Mode
The MAX1165/MAX1166 have a selectable standby or
low-power shutdown mode. In standby mode, the
ADC’s internal reference and reference buffer do not
power down between conversions, eliminating the need
to wait for the reference to power up before performing
the next conversion. Shutdown mode powers down the
reference and reference buffer after completing a con-
version. The reference and reference buffer require a
10ms (C
= 0.1µF, C
= 4.7µF) for the internal
REFADJ
REF
reference to wake up.
Internal and External Reference
Internal Reference
The internal reference of the MAX1165/MAX1166 is
internally buffered to provide +4.096V output at REF.
Bypass REF to AGND and REFADJ to AGND with 4.7µF
and 0.1µF, respectively.
minimum of 10ms (C
= 0.1µF, C
= 4.7µF) to
REF
REFADJ
power up and settle from shutdown.
The state of R/C at the second falling edge of CS
selects which power-down mode the MAX1165/
MAX1166 enter upon conversion completion. Holding
R/C low causes the MAX1165/MAX1166 to enter stand-
by mode. The reference and buffer are left on after the
conversion completes. R/C high causes the MAX1165/
MAX1166 to enter shutdown mode and shut down the
reference and buffer after conversion (Figures 5 and 6).
When using an external reference, set the REF power-
down bit high for lowest current operation.
Fine adjustments can be made to the internal reference
voltage by sinking or sourcing current at REFADJ. The
input impedance of REFADJ is nominally 5kΩ. The
internal reference voltage is adjustable to 1.5% with
the circuit of Figure 7.
+5V
MAX1165
MAX1166
68kΩ
100kΩ
150kΩ
REFADJ
Standby Mode
While in standby mode, the supply current is reduced
to less than 1mA (typ). The next falling edge of CS with
R/C low causes the MAX1165/MAX1166 to exit standby
mode and begin acquisition. The reference and refer-
ence buffer remain active to allow quick turn-on time.
Standby mode allows significant power savings while
running at the maximum sample rate.
0.1µF
Figure 7. MAX1165/MAX1166 Reference Adjust Circuit
Shutdown Mode
In shutdown mode, the reference and reference buffer
are shut down between conversions. Shutdown mode
reduces supply current to 0.5µA (typ) immediately after
the conversion. The falling edge of CS with R/C low
External Reference
An external reference can be placed at either the input
(REFADJ) or the output (REF) of the MAX1165/
MAX1166s’ internal buffer amplifier. When connecting an
10 ______________________________________________________________________________________
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
external reference to REFADJ, the input impedance is
OUTPUT CODE
typically 5kΩ. Using the buffered REFADJ input makes
FULL-SCALE
TRANSITION
buffering the external reference unnecessary; however,
11...111
the internal buffer output must be bypassed at REF with
11...110
11...101
a 1µF capacitor.
Connect REFADJ to AV
to disable the internal buffer.
DD
Directly drive REF using an external reference. During
conversion the external reference must be able to drive
100µA of DC load current and have an output imped-
ance of 10Ω or less. REFADJ’s impedance is typically
5kΩ. The DC input impedance of REF is a minimum
40kΩ.
FS = V
REF
1LSB = V
REF
65536
00...011
00...010
00...001
00...000
0
1
2
3
FS
For optimal performance, buffer the reference through
an op amp and bypass REF with a 1µF capacitor.
Consider the MAX1165/MAX1166s’ equivalent input
INPUT VOLTAGE (LSB) FS - 3/2LSB
Figure 8. MAX1165/MAX1166 Transfer Function
noise (38µV ) when choosing a reference.
RMS
plexed, the input channel should be switched immedi-
ately after acquisition, rather than near the end of or
after a conversion. This allows more time for the input
buffer amplifier to respond to a large step change in
input signal. The input amplifier must have a high
enough slew rate to complete the required output volt-
age change before the beginning of the acquisition
time. At the beginning of acquisition, the internal sam-
pling capacitor array connects to AIN (the amplifier out-
put), causing some output disturbance. Ensure that the
sampled voltage has settled to within the required limits
before the end of the acquisition time. If the frequency
of interest is low, AIN can be bypassed with a large
enough capacitor to charge the internal sampling
capacitor with very little ripple. However, for AC use,
AIN must be driven by a wideband buffer (at least
10MHz), which must be stable with the ADC’s capaci-
tive load (in parallel with any AIN bypass capacitor
used) and also settle quickly. An example of this circuit
using the MAX4434 is given in Figure 9.
Reading a Conversion Result
EOC is provided to flag the microprocessor when a con-
version is complete. The falling edge of EOC signals
that the data is valid and ready to be output to the bus.
D0–D15 are the parallel outputs of the MAX1165/
MAX1166. These three-state outputs allow for direct
connection to a microcontroller I/O bus. The outputs
remain high-impedance during acquisition and conver-
sion. Data is loaded onto the bus with the third falling
edge of CS with R/C high after t . Bringing CS high
DO
forces the output bus back to high impedance. The
MAX1165/MAX1166 then wait for the next falling edge
of CS to start the next conversion cycle (Figure 2).
The MAX1165 loads the conversion result onto a 16-bit
wide data bus while the MAX1166 has a byte-wide out-
put format. HBEN toggles the output between the
most/least significant byte. The least significant byte is
loaded onto the output bus when HBEN is low and the
most significant byte is on the bus when HBEN is high
(Figure 2).
RESET
Toggle RESET with CS high. The next falling edge of CS
begins acquisition. This reset is an alternative to the
dummy conversion explained in the Starting a Conversion
section.
MAX1165
MAX1166
10Ω
AIN
40pF
ANALOG
INPUT
Transfer Function
Figure 8 shows the MAX1165/MAX1166 output transfer
function. The output is coded in standard binary.
MAX4434
Input Buffer
Most applications require an input buffer amplifier to
achieve 16-bit accuracy. If the input signal is multi-
Figure 9. MAX1165/MAX1166 Fast Settling Input Buffer
______________________________________________________________________________________ 11
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
noise error only and results directly from the ADC’s res-
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Do
not run analog and digital lines parallel to each other,
and do not lay out digital signal paths underneath the
ADC package. Use separate analog and digital ground
planes with only one point connecting the two ground
systems (analog and digital) as close to the device as
possible.
olution (N bits):
SNR = (6.02 ✕ N + 1.76)dB
where N = 16 bits.
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Route digital signals far away from sensitive analog and
reference inputs. If digital lines must cross analog lines,
do so at right angles to minimize coupling digital noise
onto the analog lines. If the analog and digital sections
share the same supply, then isolate the digital and ana-
log supply by connecting them with a low-value (10Ω)
resistor or ferrite bead.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals:
The ADC is sensitive to high-frequency noise on the
Signal
(Noise+Distortion)
AV
supply. Bypass AV
to AGND with a 0.1µF
DD
DD
RMS
SINAD (dB) = 20 × log
capacitor in parallel with a 1µF to 10µF low-ESR capaci-
tor with the smallest capacitor closest to the device.
Keep capacitor leads short to minimize stray inductance.
RMS
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1165/MAX1166
are measured using the end-point method.
SINAD − 1.76
ENOB =
6.02
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of 1 LSB guarantees no miss-
ing codes and a monotonic transfer function.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
2
2
2
2
Aperture Jitter and Delay
Aperture jitter is the sample-to-sample variation in the
time between samples. Aperture delay is the time
between the rising edge of the sampling clock and the
instant when the actual sample is taken.
V
+ V + V + V
3 4 5
2
THD = 20×log
V
1
where V is the fundamental amplitude and V through
5
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
1
2
V are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest fre-
quency component.
12 ______________________________________________________________________________________
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
Functional Diagram
AV AGND DV DGND
HBEN*
REFADJ
DD
DD
5kΩ
REFERENCE
16 OR 8*
16 OR 8*
D0–D15
OUTPUT
REGISTERS
OR
D0/D7–D8/D15*
REF
AIN
CAPACITIVE
DAC
MAX1165
MAX1166
AGND
RESET**
SUCCESSIVE-
APPROXIMATION
REGISTER AND
CONTROL LOGIC
CLOCK
EOC
CS
R/C
* BYTE WIDE (MAX1166 ONLY)
**16-BIT WIDE (MAX1165 ONLY)
Chip Information
Ordering Information (continued)
TRANSISTOR COUNT: 15,140
PART
TEMP RANGE PIN-PACKAGE
0°C to +70°C 20 TSSOP
0°C to +70°C 20 TSSOP
0°C to +70°C 20 TSSOP
INL
2
PROCESS: BiCMOS
MAX1166ACUP*
MAX1166BCUP
MAX1166CCUP
2
4
MAX1166AEUP* -40°C to +85°C 20 TSSOP
MAX1166BEUP* -40°C to +85°C 20 TSSOP
MAX1166CEUP* -40°C to +85°C 20 TSSOP
2
2
4
*Future product—contact factory for availability.
______________________________________________________________________________________ 13
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
Pin Configurations
TOP VIEW
D4/D12
D5/D13
D6/D14
D7/D15
R/C
1
2
3
4
5
6
7
8
9
20 D3/D11
19 D2/D10
18 D1/D9
17 D0/D8
D8
D9
1
2
3
4
5
6
7
8
9
28 D7
27 D6
26 D5
25 D4
24 D3
23 D2
22 D1
21 D0
20 DV
D10
D11
D12
D13
D14
D15
R/C
MAX1166
16 DV
DD
MAX1165
EOC
15 DGND
14
AV
DD
CS
AGND
AIN
13 HBEN
12 REF
DD
AGND 10
11 REFADJ
EOC 10
AV 11
19 DGND
18 CS
DD
TSSOP
AGND 12
AIN 13
17 RESET
16 REF
AGND 14
15 REFADJ
TSSOP
14 ______________________________________________________________________________________
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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