MAX11607_技术文档

19-4560; Rev 1; 7/09

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

0–MAX61

General Description

Features

o High-Speed I C-Compatible Serial Interface

400kHz Fast Mode

2

The MAX11606–MAX11611 low-power, 10-bit, multichan-

nel analog-to-digital converters (ADCs) feature internal

track/hold (T/H), voltage reference, clock, and an

1.7MHz High-Speed Mode

o Single-Supply

2

I C-compatible 2-wire serial interface. These devices

operate from a single supply of 2.7V to 3.6V (MAX11607/

MAX11609/MAX11611) or 4.5V to 5.5V (MAX11606/

MAX11608/MAX11610) and require only 670µA at the

maximum sampling rate of 94.4ksps. Supply current falls

below 230µA for sampling rates under 46ksps.

AutoShutdown™ powers down the devices between conver-

sions, reducing supply current to less than 1µA at low

throughput rates. The MAX11606/MAX11607 have 4 analog

input channels each, the MAX11608/MAX11609 have 8 ana-

log input channels each, while the MAX11610/MAX11611

have 12 analog input channels each. The fully differential

analog inputs are software configurable for unipolar or bipo-

lar, and single ended or differential operation.

2.7V to 3.6V (MAX11607/MAX11609/MAX11611)

4.5V to 5.5V (MAX11606/MAX11608/MAX11610)

o Internal Reference

2.048V (MAX11607/MAX11609/MAX11611)

4.096V (MAX11606/MAX11608/MAX11610)

o External Reference: 1V to V

o Internal Clock

DD

o 4-Channel Single-Ended or 2-Channel Fully

Differential (MAX11606/MAX11607)

o 8-Channel Single-Ended or 4-Channel Fully

Differential (MAX11608/MAX11609)

o 12-Channel Single-Ended or 6-Channel Fully

Differential (MAX11610/MAX11611)

o Internal FIFO with Channel-Scan Mode

o Low Power

The full-scale analog input range is determined by the

internal reference or by an externally applied reference

voltage ranging from 1V to V . The MAX11607/

DD

MAX11609/MAX11611 feature a 2.048V internal reference

and the MAX11606/MAX11608/MAX11610 feature a

4.096V internal reference.

The MAX11606/MAX11607 are available in an 8-pin

µMAX^®package. The MAX11608–MAX11611 are avail-

able in a 16-pin QSOP package. The MAX11606–

MAX11611 are guaranteed over the extended tempera-

ture range (-40°C to +85°C). For pin-compatible 12-bit

parts, refer to the MAX11612–MAX11617 data sheet. For

pin-compatible 8-bit parts, refer to the MAX11600–

MAX11605 data sheet.

670µA at 94.4ksps

230µA at 40ksps

60µA at 10ksps

6µA at 1ksps

0.5µA in Power-Down Mode

o Software-Configurable Unipolar/Bipolar

o Small Packages

8-Pin µMAX (MAX11606/MAX11607)

16-Pin QSOP (MAX11608–MAX11611)

Ordering Information

Applications

I²C SLAVE

Handheld Portable

Applications

Solar-Powered Remote

Systems

PIN-

PACKAGE ADDRESS

PART

TEMP RANGE

Medical Instruments

Received-Signal-Strength

Indicators

MAX11606EUA+

MAX11607EUA+

MAX11608EEE+

MAX11609EEE+

MAX11610EEE+

MAX11611EEE+

-40°C to +85°C 8 µMAX

-40°C to +85°C 16 QSOP

0110100

0110011

0110101

Battery-Powered Test

Equipment

System Supervision

+Denotes a lead(Pb)-free/RoHs-compliant package.

AutoShutdown is a trademark of Maxim Integrated Products, Inc.

µMAX is a registered trademark of Maxim Integrated Products, Inc.

Pin Configurations, Typical Operating Circuit, and Selector

Guide appear at end of data sheet.

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

ABSOLUTE MAXIMUM RATINGS

V

DD

to GND..............................................................-0.3V to +6V

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range.............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

AIN0–AIN11,

REF to GND............-0.3V to the lower of (V

+ 0.3V) and 6V

DD

SDA, SCL to GND.....................................................-0.3V to +6V

Maximum Current into Any Pin ......................................... 50mA

Continuous Power Dissipation (T = +70°C)

A

8-Pin µMAX (derate 4.5mW/°C above +70°C).............362mW

16-Pin QSOP (derate 8.3mW/°C above +70°C)........666.7mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V

= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V

= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V

= 2.048V

REF

DD

(MAX11607/MAX11609/MAX11611), V

= 4.096V (MAX11606/MAX11608/MAX11610), f

= 1.7MHz, T = T

to T , unless other-

MAX

REF

SCL

A

MIN

wise noted. Typical values are at T = +25°C. See Tables 1–5 for programming notation.)

A

PARAMETER

DC ACCURACY (Note 1)

Resolution

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

0–MAX61

10

Bits

LSB

Relative Accuracy

Differential Nonlinearity

Offset Error

INL

(Note 2)

1

DNL

No missing codes over temperature

Offset-Error Temperature

Coefficient

Relative to FSR

0.3

ppm/°C

Gain Error

(Note 3)

1

LSB

Gain-Temperature Coefficient

Relative to FSR

0.3

0.1

ppm/°C

Channel-to-Channel Offset

Matching

LSB

Channel-to-Channel Gain

Matching

0.1

DYNAMIC PERFORMANCE (f

Signal-to-Noise Plus Distortion

Total Harmonic Distortion

Spurious Free Dynamic Range

Full-Power Bandwidth

= 10kHz, V

= V

, f

= 94.4ksps)

IN(SINE-WAVE)

IN(P-P)

REF SAMPLE

SINAD

60

-70

70

dB

THD

Up to the 5th harmonic

SFDR

dB

SINAD > 57dB

-3dB point

3.0

5.0

MHz

Full-Linear Bandwidth

CONVERSION RATE

Internal clock

6.8

Conversion Time (Note 4)

t

µs

CONV

External clock

10.6

800

Internal clock, SCAN[1:0] = 01

53

Internal clock, SCAN[1:0] = 00

CS[3:0] = 1011 (MAX11610/MAX11611)

Throughput Rate

f

ksps

ns

SAMPLE

External clock

94.4

Track/Hold Acquisition Time

2

_______________________________________________________________________________________

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

0–MAX61

ELECTRICAL CHARACTERISTICS (continued)

(V

= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V

= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V

= 2.048V

REF

DD

(MAX11607/MAX11609/MAX11611), V

= 4.096V (MAX11606/MAX11608/MAX11610), f

= 1.7MHz, T = T

to T , unless other-

MAX

REF

SCL

A

MIN

wise noted. Typical values are at T = +25°C. See Tables 1–5 for programming notation.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

2.8

60

MAX

UNITS

Internal Clock Frequency

MHz

External clock, fast mode

Aperture Delay (Note 5)

t

ns

AD

External clock, high-speed mode

30

ANALOG INPUT (AIN0–AIN11)

Unipolar

Bipolar

0

V

REF

Input-Voltage Range, Single-

Ended and Differential (Note 6)

V

/2

REF

1

Input Multiplexer Leakage Current

Input Capacitance

On/off leakage current, VAIN_ = 0 or V

0.01

22

µA

pF

DD

C

IN

INTERNAL REFERENCE (Note 7)

MAX11607/MAX11609/MAX11611

MAX11606/MAX11608/MAX11610

1.968

3.939

2.048

4.096

2.128

4.256

Reference Voltage

V

T

A

= +25°C

V

REF

Reference-Voltage Temperature

Coefficient

TCVREF

25

ppm/°C

REF Short-Circuit Current

REF Source Impedance

EXTERNAL REFERENCE

2

mA

1.5

kΩ

REF Input-Voltage Range

REF Input Current

V

(Note 8)

1

V

REF

DD

I

f

= 94.4ksps

40

µA

REF

SAMPLE

DIGITAL INPUTS/OUTPUTS (SCL, SDA)

x

Input High Voltage

Input Low Voltage

Input Hysteresis

V

0.7

0.1

V

IH

DD

x

V

DD

V

0.3

IL

V

HYST

DD

Input Current

I

V

= 0 to V

DD

10

µA

pF

V

IN

Input Capacitance

Output Low Voltage

POWER REQUIREMENTS

C

15

IN

V

I

= 3mA

0.4

OL

SINK

MAX11607/MAX11609/MAX11611

MAX11606/MAX11608/MAX11610

2.7

4.5

3.6

5.5

Supply Voltage

Supply Current

V

DD

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

900

670

530

230

380

60

1150

900

f

= 94.4ksps

SAMPLE

external clock

f

= 40ksps

SAMPLE

internal clock

I

µA

DD

f

= 10ksps

SAMPLE

internal clock

330

6

f

=1ksps

SAMPLE

internal clock

Shutdown (internal reference off)

0.5

10

_______________________________________________________________________________________

3

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

ELECTRICAL CHARACTERISTICS (continued)

(V

= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V

= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V

= 2.048V

REF

DD

(MAX11607/MAX11609/MAX11611), V

= 4.096V (MAX11606/MAX11608/MAX11610), f

= 1.7MHz, T = T

to T , unless other-

MAX

REF

SCL

A

MIN

wise noted. Typical values are at T = +25°C. See Tables 1–5 for programming notation.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

POWER REQUIREMENTS

Power-Supply Rejection Ratio

PSRR

Full-scale input (Note 9)

0.01

0.5

LSB/V

TIMING CHARACTERISTICS (Figure 1)

(V

= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V

= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V = 2.048V

REF

DD

(MAX11607/MAX11609/MAX11611), V

= 4.096V (MAX11606/MAX11608/MAX11610), f

= 1.7MHz, T = T

to T , unless other-

MAX

REF

SCL

A

MIN

wise noted. Typical values are at T = +25°C. See Tables 1–5 for programming notation.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

kHz

TIMING CHARACTERISTICS FOR FAST MODE

Serial-Clock Frequency

f

400

SCL

Bus Free Time Between a

STOP (P) and a

0–MAX61

t

1.3

µs

BUF

START (S) Condition

Hold Time for START (S) Condition

Low Period of the SCL Clock

High Period of the SCL Clock

t

0.6

1.3

0.6

µs

HD,STA

t

LOW

t

HIGH

Setup Time for a Repeated START

Condition (Sr)

0.6

µs

SU,STA

Data Hold Time

Data Setup Time

t

(Note 10)

0

900

ns

HD,DAT

t

100

SU,DAT

Rise Time of Both SDA and SCL

Signals, Receiving

t

Measured from 0.3V

to 0.7V

20 + 0.1C

300

ns

R

DD

B

Fall Time of SDA Transmitting

t

to 0.7V (Note 11)

20 + 0.1C

0.6

ns

µs

pF

ns

F

DD

Setup Time for STOP (P) Condition

Capacitive Load for Each Bus Line

Pulse Width of Spike Suppressed

t

SU,STO

C

400

50

B

t

SP

TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C = 400pF, Note 12)

B

Serial-Clock Frequency

f

(Note 13)

1.7

MHz

ns

SCLH

Hold Time, Repeated START

Condition (Sr)

t

160

HD,STA

Low Period of the SCL Clock

High Period of the SCL Clock

t

320

120

ns

LOW

t

HIGH

Setup Time for a Repeated START

Condition (Sr)

t

,

160

ns

SU STA

Data Hold Time

Data Setup Time

t

,

(Note 10)

0

150

ns

HD DAT

t

,

10

SU DAT

4

_______________________________________________________________________________________

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

0–MAX61

TIMING CHARACTERISTICS (Figure 1) (continued)

(V

= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V

= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V

= 2.048V

REF

DD

(MAX11607/MAX11609/MAX11611), V

= 4.096V (MAX11606/MAX11608/MAX11610), f

= 1.7MHz, T = T

to T , unless other-

MAX

REF

SCL

A

MIN

wise noted. Typical values are at T = +25°C. See Tables 1–5 for programming notation.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

80

UNITS

Rise Time of SCL Signal

(Current Source Enabled)

t

Measured from 0.3V

to 0.7V

20

ns

RCL

DD

Rise Time of SCL Signal after

Acknowledge Bit

t

Measured from 0.3V

to 0.7V

20

160

ns

RCL1

Fall Time of SCL Signal

t

Measured from 0.3V

to 0.7V

20

80

ns

pF

ns

FCL

DD

Rise Time of SDA Signal

t

160

RDA

DD

Fall Time of SDA Signal

t

to 0.7V (Note 11)

20

FDA

DD

Setup Time for STOP (P) Condition

Capacitive Load for Each Bus Line

Pulse Width of Spike Suppressed

t

,

160

SU STO

C

400

10

B

t

(Notes 10 and 13)

0

SP

Note 1: For DC accuracy, the MAX11606/MAX11608/MAX11610 are tested at V

= 5V and the MAX11607/MAX11609/MAX11611

= 3V. All devices are configured for unipolar, single-ended inputs.

DD

are tested at V

DD

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and

offsets have been calibrated.

Note 3: Offset nulled.

Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion

time does not include acquisition time. SCL is the conversion clock in the external clock mode.

Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.

Note 6: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to V

.

DD

Note 7: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11), decouple AIN_/REF to GND with a

0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit).

Note 8: ADC performance is limited by the converter’s noise floor, typically 300µV

Note 9: Measured as follows for the MAX11607/MAX11609/MAX11611:

.

P-P

2^N−1

V_REF

⎡

⎤

⎥

⎦

V (3.6V)− V (2.7V) ×

[

]

⎢

FS

⎣

(3.6V − 2.7V)

and for the MAX11606/MAX11608/MAX11610, where N is the number of bits:

2^N−1

V_REF

⎡

⎤

⎥

⎦

V (5.5V)− V (4.5V) ×

[

]

⎢

FS

⎣

(5.5V − 4.5V)

Note 10: A master device must provide a data hold time for SDA (referred to V of SCL) to bridge the undefined region of SCL’s

IL

falling edge (see Figure 1).

Note 11: The minimum value is specified at T = +25°C.

A

Note 12: C = total capacitance of one bus line in pF.

B

Note 13: f

must meet the minimum clock low time plus the rise/fall times.

SCL

_______________________________________________________________________________________

5

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

Typical Operating Characteristics

(V

= 3.3V (MAX11607/MAX11609/MAX11611), V

= 5V (MAX11606/MAX11608/MAX11610), f = 1.7MHz, external clock,

SCL

DD

f

= 94.4ksps, single-ended, unipolar, T = +25°C, unless otherwise noted.)

SAMPLE

A

INTEGRAL NONLINEARITY

vs. DIGITAL CODE

DIFFERENTIAL NONLINEARITY

vs. DIGITAL CODE

FFT PLOT

0.5

0.4

0

-20

0.3

0.2

0.1

0

f

= 94.4ksps

SAMPLE

= 10kHz

IN

0.3

-40

0.2

-60

0.1

0

-80

-0.1

-0.2

-0.3

-0.4

-0.5

-100

-120

-140

-160

-0.1

-0.2

-0.3

0

10k

20k

30k

40k

50k

200

400

600

800

1000

0

200

400

600

800

1000

FREQUENCY (Hz)

DIGITAL OUTPUT CODE

SUPPLY CURRENT

vs. TEMPERATURE

SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE

SHUTDOWN SUPPLY CURRENT

vs. SUPPLY VOLTAGE

0–MAX61

800

750

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.6

0.5

0.4

0.3

0.2

0.1

0

MAX11610/MAX11608/

MAX11606

SDA = SCL = V

DD

INTERNAL REFERENCE

MAX11610/MAX11608/MAX11606

700

650

600

550

500

450

400

350

300

SETUP BYTE

EXT REF: 10111011

INT REF: 11011011

MAX11611/MAX11609/

MAX11607

INTERNAL REFERENCE

MAX11610/MAX11608/

MAX11606

EXTERNAL REFERENCE

MAX11611/MAX11609/MAX11607

MAX11611/MAX11609/

MAX11607

EXTERNAL REFERENCE

-40 -25 -10

5

20 35 50 65 80

-40 -10

-25

5

20 35 50 65 80

2.7

3.2

3.7

4.2

4.7

5.2

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

AVERAGE SUPPLY CURRENT

vs. CONVERSION RATE (EXTERNAL CLOCK)

AVERAGE SUPPLY CURRENT vs.

CONVERSION RATE (EXTERNAL CLOCK)

800

750

700

650

600

550

500

450

400

350

300

250

200

A) INTERNAL REFERENCE ALWAYS ON

B) EXTERNAL REFERENCE

A) INTERNAL REFERENCE ALWAYS ON

B) EXTERNAL REFERENCE

A

700

600

500

A

B

400

300

200

MAX11611/MAX11609/MAX11607

MAX11610/MAX11608/MAX11606

0

20

40

60

80

100

0

10 20 30 40 50 60 70 80 90 100

CONVERSION RATE (ksps)

CONVERSATION RATE (ksps)

6

_______________________________________________________________________________________

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

0–MAX61

Typical Operating Characteristics (continued)

(V

= 3.3V (MAX11607/MAX11609/MAX11611), V

= 5V (MAX11606/MAX11608/MAX11610), f

= 1.7MHz, external clock,

SCL

DD

f

= 94.4ksps, single-ended, unipolar, T = +25°C, unless otherwise noted.)

SAMPLE

A

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

NORMALIZED REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

1.0010

1.0008

1.0006

1.0004

1.0002

1.0000

0.9998

0.9996

0.9994

0.9992

0.9990

1.00010

1.00008

1.00006

1.00004

1.00002

1.00000

0.99998

0.99996

0.99994

0.99992

0.99990

NORMALIZED TO REFERENCE VALUE

= +25°C

MAX11610/11608/MAX11606,

NORMALIZED TO

REFERENCE VALUE AT

T

A

MAX11610/MAX11608/MAX11606

V

= 5V

DD

MAX11611/11609/MAX11607,

NORMALIZED TO

REFERENCE VALUE AT

MAX11611/MAX11609/MAX11607

V

= 3.3V

DD

-40 -25 -10

5

20 35 50 65 80

2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4

(V)

TEMPERATURE (°C)

V

DD

OFFSET ERROR vs. SUPPLY VOLTAGE

OFFSET ERROR vs. TEMPERATURE

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1.0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1.0

2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4

-40 -25 -10

5

20 35 50 65 80

V

(V)

TEMPERATURE (°C)

DD

GAIN ERROR vs. TEMPERATURE

GAIN ERROR vs. SUPPLY VOLTAGE

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

-40 -25 -10

5

20 35 50 65 80

2.7

3.2

3.7

4.2

(V)

4.7

5.2

TEMPERATURE (°C)

V

DD

_______________________________________________________________________________________

7

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

Pin Description

MAX11606

MAX11607

MAX11608

MAX11609

MAX11610

MAX11611

NAME

FUNCTION

1, 2, 3

—

5, 6, 7

8–12

—

5, 6, 7

8–12

AIN0, AIN1, AIN2

AIN3–AIN7

Analog Inputs

—

4, 3, 2

AIN8–AIN10

Analog Input 3/Reference Input or Output. Selected in the

setup register (see Tables 1 and 6).

4

—

1

—

1

AIN3/REF

REF

Reference Input or Output. Selected in the setup register

(see Tables 1 and 6).

—

Analog Input 11/Reference Input or Output. Selected in the

setup register (see Tables 1 and 6).

—

AIN11/REF

5

6

13

14

13

14

15

16

—

SCL

SDA

GND

Clock Input

Data Input/Output

7

15

Ground

8

16

V

Positive Supply. Bypass to GND with a 0.1µF capacitor.

No Connection. Not internally connected.

DD

0–MAX61

—

2, 3, 4

N.C.

A. F/S-MODE 2-WIRE SERIAL INTERFACE TIMING

SDA

t

R

t

F

t

HD.DAT

SU.DAT

t

BUF

HD.STA

t

LOW

t

SU.STO

SU.STA

SCL

t

HD.STA

t

HIGH

t

R

t

F

S

Sr

A

P

S

B. HS-MODE 2-WIRE SERIAL INTERFACE TIMING

SDA

t

RDA

FDA

t

HD.DAT

SU.DAT

t

BUF

HD.STA

t

LOW

t

SU.STO

t

SU.STA

SCL

t

HIGH

HD.STA

t

FCL

t

RCL

RCL1

S

Sr

A

S

F/S-MODE

P

HS-MODE

Figure 1. 2-Wire Serial-Interface Timing

_______________________________________________________________________________________

8

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

0–MAX61

SDA

SCL

INPUT SHIFT REGISTER

V

DD

INTERNAL

OSCILLATOR

CONTROL

LOGIC

SETUP REGISTER

GND

CONFIGURATION REGISTER

AIN0

AIN1

OUTPUT SHIFT

REGISTER

AND RAM

10-BIT

ADC

AIN2

T/H

AIN3

AIN4

ANALOG

INPUT

MUX

AIN5

REF

AIN6

AIN7

AIN8

REFERENCE

4.096V (MAX11610)

2.048V (MAX11611)

MAX11610

MAX11611

AIN9

AIN10

AIN11/REF

Figure 2. MAX11610/MAX11611 Functional Diagram

1.7MHz. Figure 2 shows the simplified internal structure

for the MAX11610/MAX11611.

V

DD

Power Supply

The MAX11606–MAX11611 operates from a single sup-

ply and consumes 670µA (typ) at sampling rates up to

94.4ksps. The MAX11607/MAX11609/MAX11611 feature

a 2.048V internal reference and the MAX11606/

MAX11608/MAX11610 feature a 4.096V internal refer-

ence. All devices can be configured for use with an

I

OL

V

SDA

OUT

400pF

external reference from 1V to V

.

I

DD

OH

Analog Input and Track/Hold

The MAX11606–MAX11611 analog-input architecture

contains an analog-input multiplexer (mux), a fully dif-

ferential track-and-hold (T/H) capacitor, T/H switches, a

comparator, and a fully differential switched capacitive

digital-to-analog converter (DAC) (Figure 4).

Figure 3. Load Circuit

Detailed Description

The MAX11606–MAX11611 analog-to-digital converters

(ADCs) use successive-approximation conversion tech-

niques and fully differential input track/hold (T/H) cir-

cuitry to capture and convert an analog signal to a

serial 12-bit digital output. The MAX11606/MAX11607

are 4-channel ADCs, the MAX11608/MAX11609 are

8-channel ADCs, and the MAX11610/MAX11611 are

12-channel ADCs. These devices feature a high-speed

2-wire serial interface supporting data rates up to

In single-ended mode, the analog-input multiplexer con-

nects C

between the analog input selected by

T/H

CS[3:0] (see the Configuration/Setup Bytes (Write

Cycle) section) and GND (Table 3). In differential mode,

the analog- input multiplexer connects C

to the + and

T/H

- analog inputs selected by CS[3:0] (Table 4).

During the acquisition interval, the T/H switches are in

the track position and C

charges to the analog input

T/H

_______________________________________________________________________________________

9

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

signal. At the end of the acquisition interval, the T/H

switches move to the hold position retaining the charge

clock pulse during the shifting out of the first byte of the

result. The conversion is performed during the next 10

clock cycles.

on C

as a stable sample of the input signal.

T/H

During the conversion interval, the switched capacitive

DAC adjusts to restore the comparator input voltage to

0V within the limits of 10-bit resolution. This action

requires 10 conversion clock cycles and is equivalent

The time required for the T/H circuitry to acquire an

input signal is a function of the input sample capaci-

tance. If the analog-input source impedance is high,

the acquisition time constant lengthens and more time

must be allowed between conversions. The acquisition

to transferring a charge of 11pF ^ꢀ(V

- V ) from

IN-

IN+

C

T/H

to the binary weighted capacitive DAC, forming a

time (t

) is the minimum time needed for the signal

ACQ

digital representation of the analog input signal.

to be acquired. It is calculated by:

Sufficiently low source impedance is required to ensure

an accurate sample. A source impedance of up to 1.5kΩ

does not significantly degrade sampling accuracy. To

minimize sampling errors with higher source impedances,

connect a 100pF capacitor from the analog input to GND.

This input capacitor forms an RC filter with the source

impedance limiting the analog-input bandwidth. For larg-

er source impedances, use a buffer amplifier to maintain

analog-input signal integrity and bandwidth.

t

≥ 9 ꢀ (R

+ R ) ꢀ C

SOURCE IN IN

ACQ

where R

IN

is the analog-input source impedance,

SOURCE

= 2.5kΩ, and C = 22pF. t

clock mode and t

R

is 1.5/f

for internal

IN

ACQ

SCL

= 2/f

for external clock mode.

SCL

Analog Input Bandwidth

The MAX11606–MAX11611 feature input-tracking cir-

cuitry with a 5MHz small-signal bandwidth. The 5MHz

input bandwidth makes it possible to digitize high-

speed transient events and measure periodic signals

with bandwidths exceeding the ADC’s sampling rate by

using under sampling techniques. To avoid high-fre-

quency signals being aliased into the frequency band

of interest, anti-alias filtering is recommended.

When operating in internal clock mode, the T/H circuitry

enters its tracking mode on the eighth rising clock edge

of the address byte (see the Slave Address section). The

T/H circuitry enters hold mode on the falling clock edge of

the acknowledge bit of the address byte (the ninth clock

pulse). A conversion or a series of conversions is then

internally clocked and the MAX11606–MAX11611 holds

SCL low. With external clock mode, the T/H circuitry

enters track mode after a valid address on the rising

edge of the clock during the read (R/W = 1) bit. Hold

mode is then entered on the rising edge of the second

0–MAX61

Analog Input Range and Protection

Internal protection diodes clamp the analog input to

V

DD

and GND. These diodes allow the analog inputs to

HOLD

ANALOG INPUT MUX

REF

C

T/H

AIN0

TRACK

CAPACITIVE

DAC

AIN1

AIN2

V

DD

/2

AIN3/REF

CAPACITIVE

DAC

TRACK

GND

C

T/H

MAX11606

MAX11607

REF

HOLD

Figure 4. Equivalent Input Circuit

10 ______________________________________________________________________________________

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

0–MAX61

swing from (GND - 0.3V) to (V

+ 0.3V) without caus-

SDA while SCL is stable are considered control signals

(see the START and STOP Conditions section). Both

SDA and SCL remain high when the bus is not busy.

DD

ing damage to the device. For accurate conversions

the inputs must not go more than 50mV below GND or

above V

.

DD

START and STOP Conditions

The master initiates a transmission with a START condi-

tion (S), a high-to-low transition on SDA while SCL is high.

The master terminates a transmission with a STOP condi-

tion (P), a low-to-high transition on SDA while SCL is high

(Figure 5). A repeated START condition (Sr) can be used

in place of a STOP condition to leave the bus active and

the mode unchanged (see the HS Mode section).

Single-Ended/Differential Input

The SGL/DIF of the configuration byte configures the

MAX11606–MAX11611 analog-input circuitry for single-

ended or differential inputs (Table 2). In single-ended

mode (SGL/DIF = 1), the digital conversion results are

the difference between the analog input selected by

CS[3:0] and GND (Table 3). In differential mode (SGL/

DIF = 0), the digital conversion results are the differ-

ence between the + and the - analog inputs selected

by CS[3:0] (Table 4).

S

Sr

P

Unipolar/Bipolar

When operating in differential mode, the BIP/UNI bit of

the setup byte (Table 1) selects unipolar or bipolar

operation. Unipolar mode sets the differential input

SDA

SCL

range from 0 to V

. A negative differential analog

REF

input in unipolar mode causes the digital output code

to be zero. Selecting bipolar mode sets the differential

Figure 5. START and STOP Conditions

input range to

V

/2. The digital output code is bina-

REF

Acknowledge Bits

ry in unipolar mode and two’s complement in bipolar

mode. See the Transfer Functions section.

Data transfers are acknowledged with an acknowledge

bit (A) or a not-acknowledge bit (A). Both the master

and the MAX11606–MAX11611 (slave) generate

acknowledge bits. To generate an acknowledge, the

receiving device must pull SDA low before the rising

edge of the acknowledge-related clock pulse (ninth

pulse) and keep it low during the high period of the

clock pulse (Figure 6). To generate a not-acknowledge,

the receiver allows SDA to be pulled high before the

rising edge of the acknowledge-related clock pulse

and leaves SDA high during the high period of the

clock pulse. Monitoring the acknowledge bits allows for

detection of unsuccessful data transfers. An unsuc-

cessful data transfer happens if a receiving device is

busy or if a system fault has occurred. In the event of

an unsuccessful data transfer, the bus master should

reattempt communication at a later time.

In single-ended mode, the MAX11606–MAX11611

always operate in unipolar mode irrespective of

BIP/UNI. The analog inputs are internally referenced to

GND with a full-scale input range from 0 to V

.

REF

2-Wire Digital Interface

The MAX11606–MAX11611 feature a 2-wire interface

consisting of a serial-data line (SDA) and serial-clock line

(SCL). SDA and SCL facilitate bidirectional communica-

tion between the MAX11606–MAX11611 and the master

at rates up to 1.7MHz. The MAX11606–MAX11611 are

slaves that transfer and receive data. The master (typi-

cally a microcontroller) initiates data transfer on the bus

and generates the SCL signal to permit that transfer.

SDA and SCL must be pulled high. This is typically done

with pullup resistors (750Ω or greater) (see the Typical

Operating Circuit). Series resistors (R ) are optional.

S

They protect the input architecture of the MAX11606–

MAX11611 from high voltage spikes on the bus lines,

minimize crosstalk, and undershoot of the bus signals.

NOT ACKNOWLEDGE

SDA

ACKNOWLEDGE

Bit Transfer

One data bit is transferred during each SCL clock

cycle. A minimum of 18 clock cycles are required to

transfer the data in or out of the MAX11606–

MAX11611. The data on SDA must remain stable dur-

ing the high period of the SCL clock pulse. Changes in

1

2

8

9

SCL

Figure 6. Acknowledge Bits

______________________________________________________________________________________ 11

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

DEVICE

SLAVE ADDRESS

0110100

MAX11606/MAX11607

MAX11608/MAX11609

MAX11610/MAX11611

0110011

0110101

SLAVE ADDRESS

MAX11606/MAX11607

S

0

1

0

1

0

R/W

A

SDA

SCL

1

2

3

4

5

6

7

8

9

Figure 7. MAX11606/MAX11607 Slave Address Byte

Slave Address

A bus master initiates communication with a slave device

by issuing a START condition followed by a slave

address. When idle, the MAX11606–MAX11611 continu-

ously wait for a START condition followed by their slave

address. When the MAX11606–MAX11611 recognize

their slave address, they are ready to accept or send

data. The slave address has been factory programmed

and is always 0110100 for the MAX11606/MAX11607,

0110011 for the MAX11608/MAX11609, and 0110101 for

MAX11610/MAX11611 (Figure 7). The least significant bit

(LSB) of the address byte (R/W) determines whether the

master is writing to or reading from the MAX11606–

MAX11611 (R/W = 0 selects a write condition, R/W = 1

selects a read condition). After receiving the address, the

MAX11606–MAX11611 (slave) issues an acknowledge by

pulling SDA low for one clock cycle.

up to 22.2ksps. The MAX11606–MAX11611 must oper-

ate in high-speed mode (HS mode) to achieve conver-

sion rates up to 94.4ksps. Figure 1 shows the bus timing

for the MAX11606–MAX11611’s 2-wire interface.

0–MAX61

HS Mode

At power-up, the MAX11606–MAX11611 bus timing is

set for F/S mode. The bus master selects HS mode by

addressing all devices on the bus with the HS-mode

master code 0000 1XXX (X = don’t care). After success-

fully receiving the HS-mode master code, the

MAX11606–MAX11611 issue a not-acknowledge, allow-

ing SDA to be pulled high for one clock cycle (Figure 8).

After the not-acknowledge, the MAX11606–MAX11611

are in HS mode. The bus master must then send a

repeated START followed by a slave address to initiate

HS-mode communication. If the master generates a

STOP condition the MAX11606–MAX11611 returns to

F/S mode.

Bus Timing

At power-up, the MAX11606–MAX11611 bus timing is

set for fast mode (F/S mode), allowing conversion rates

HS-MODE MASTER CODE

S

0

1

X

A

Sr

SDA

SCL

F/S MODE

HS MODE

Figure 8. F/S-Mode to HS-Mode Transfer

12 ______________________________________________________________________________________

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

0–MAX61

Configuration/Setup Bytes (Write Cycle)

A write cycle begins with the bus master issuing a

START condition followed by seven address bits (Figure

7) and a write bit (R/W = 0). If the address byte is suc-

cessfully received, the MAX11606–MAX11611 (slave)

issues an acknowledge. The master then writes to the

slave. The slave recognizes the received byte as the

setup byte (Table 1) if the most significant bit (MSB) is

1. If the MSB is 0, the slave recognizes that byte as the

configuration byte (Table 2). The master can write either

one or two bytes to the slave in any order (setup byte

then configuration byte; configuration byte then setup

byte; setup byte or configuration byte only; Figure 9). If

the slave receives a byte successfully, it issues an

acknowledge. The master ends the write cycle by issu-

ing a STOP condition or a repeated START condition.

When operating in HS mode, a STOP condition returns

the bus into F/S mode (see the HS Mode section).

MASTER TO SLAVE

SLAVE TO MASTER

A. ONE-BYTE WRITE CYCLE

1

7

1

8

1

NUMBER OF BITS

SETUP OR

CONFIGURATION BYTE

S

SLAVE ADDRESS W A

A

P or Sr

MSB DETERMINES WHETHER

SETUP OR CONFIGURATION BYTE

B. TWO-BYTE WRITE CYCLE

1

7

1

8

1

8

1

NUMBER OF BITS

SETUP OR

CONFIGURATION BYTE

SETUP OR

CONFIGURATION BYTE

S

SLAVE ADDRESS W A

A

P or Sr

MSB DETERMINES WHETHER

SETUP OR CONFIGURATION BYTE

Figure 9. Write Cycle

Table 1. Setup Byte Format

BIT 7

(MSB)

BIT 0

(LSB)

BIT 6

BIT 5

SEL1

BIT 4

BIT 3

BIT 2

BIT 1

REG

SEL2

SEL0

CLK

BIP/UNI

RST

X

BIT

7

NAME

REG

SEL2

SEL1

SEL0

CLK

DESCRIPTION

Register bit. 1 = setup byte, 0 = configuration byte (see Table 2).

6

Three bits select the reference voltage and the state of AIN_/REF

(MAX11606/MAX11607/MAX11610/MAX11611) or REF (MAX11608/MAX11609) (Table 6).

Defaulted to 000 at power-up.

5

4

3

1 = external clock, 0 = internal clock. Defaulted to 0 at power-up.

1 = bipolar, 0 = unipolar. Defaulted to 0 at power-up (see the Unipolar/Bipolar section).

2

BIP/UNI

RST

1

1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.

Don’t-care bit. This bit can be set to 1 or 0.

0

X

______________________________________________________________________________________ 13

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

Table 2. Configuration Byte Format

BIT 7

(MSB)

BIT 0

(LSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

REG

SCAN1

SCAN0

CS3

CS2

CS1

CS0

SGL/DIF

BIT

7

NAME

REG

DESCRIPTION

Register bit. 1= setup byte (see Table 1), 0 = configuration byte.

6

SCAN1

SCAN0

CS3

Scan select bits. Two bits select the scanning configuration (Table 5). Defaults to 00 at power-up.

5

4

Channel select bits. Four bits select which analog input channels are to be used for conversion

(Tables 3 and 4). Defaults to 0000 at power-up. For MAX11606/MAX11607, CS3 and CS2 are

internally set to 0. For the MAX11608/MAX11609, CS3 is internally set to 0.

3

CS2

2

CS1

1

CS0

1 = single-ended, 0 = differential (Tables 3 and 4). Defaults to 1 at power-up. See the Single-

Ended/Differential Input section.

0

SGL/DIF

Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)

0–MAX61

CS3¹CS2¹CS1

CS0 AIN0 AIN1 AIN2 AIN3²AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11²GND

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

+

-

+

RESERVED

1

2

For the MAX11606/MAX11607, CS3 and CS2 are internally set to 0. For the MAX11608/MAX11609, CS3 is internally set to 0.

When SEL1 = 1, a single-ended read of AIN3/REF (MAX11606/MAX11607) or AIN11/REF (MAX11610/MAX11611) is ignored; scan

stops at AIN2 or AIN10. This does not apply to the MAX11608/MAX11609 as each provides separate pins for AIN7 and REF.

14 ______________________________________________________________________________________

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

0–MAX61

Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)

CS3¹CS2¹

CS1

CS0

AIN0 AIN1

AIN2 AIN3²AIN4

AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11²

0

1

0

1

0

1

0

+

-

0

1

+

1

0

+

-

1

+

0

+

-

0

1

+

1

0

+

-

1

+

0

+

-

0

1

+

1

0

+

-

1

+

0

RESERVED

0

1

0

1

2

For the MAX11606/MAX11607, CS3 and CS2 are internally set to 0. For the MAX11608/MAX11609, CS3 is internally set to 0.

When SEL1 = 1, a differential read between AIN2 and AIN3/REF (MAX11606/MAX11607) or AIN10 and AIN11/REF

(MAX11610/MAX11611) returns the difference between GND and AIN2 or AIN10, respectively. For example, a differential read of 1011

returns the negative difference between AIN10 and GND. This does not apply to the MAX11608/MAX11609 as each provides separate

pins for AIN7 and REF. In differential scanning, the address increments by 2 until the limit set by CS3–CS1 has been reached.

Data Byte (Read Cycle)

Internal Clock

When configured for internal clock mode (CLK = 0), the

MAX11606–MAX11611 use their internal oscillator as the

conversion clock. In internal clock mode, the MAX11606–

MAX11611 begin tracking the analog input after a valid

address on the eighth rising edge of the clock. On the

falling edge of the ninth clock, the analog signal is

acquired and the conversion begins. While converting the

analog input signal, the MAX11606–MAX11611 holds SCL

low (clock stretching). After the conversion completes, the

results are stored in internal memory. If the scan mode is

set for multiple conversions, they all happen in succession

with each additional result stored in memory. The

MAX11606/MAX11607 contain four 10-bit blocks of memo-

ry, the MAX11608/MAX11609 contain eight 10-bit blocks of

memory, and the MAX11610/MAX11611 contain twelve 10-

bit blocks of memory. Once all conversions are complete,

the MAX11606–MAX11611 release SCL, allowing it to be

pulled high. The master may now clock the results out

of the memory in the same order the scan conversion

has been done at a clock rate of up to 1.7MHz. SCL is

stretched for a maximum of 7.6µs per channel (see

Figure 10).

A read cycle must be initiated to obtain conversion

results. Read cycles begin with the bus master issuing

a START condition followed by seven address bits and

a read bit (R/W = 1). If the address byte is successfully

received, the MAX11606–MAX11611 (slave) issues an

acknowledge. The master then reads from the slave.

The result is transmitted in two bytes; first six bits of the

first byte are high, then MSB through LSB are consecu-

tively clocked out. After the master has received the

byte(s), it can issue an acknowledge if it wants to con-

tinue reading or a not-acknowledge if it no longer wish-

es to read. If the MAX11606–MAX11611 receive a not-

acknowledge, they release SDA, allowing the master to

generate a STOP or a repeated START condition. See

the Clock Modes and Scan Mode sections for detailed

information on how data is obtained and converted.

Clock Modes

The clock mode determines the conversion clock and

the data acquisition and conversion time. The clock

mode also affects the scan mode. The state of the set-

up byte’s CLK bit determines the clock mode (Table 1).

At power-up, the MAX11606–MAX11611 are defaulted

to internal clock mode (CLK = 0).

______________________________________________________________________________________ 15

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

MASTER TO SLAVE

SLAVE TO MASTER

A. SINGLE CONVERSION WITH INTERNAL CLOCK

1

7

1

8

1

NUMBER OF BITS

CLOCK STRETCH

S

SLAVE ADDRESS

R

A

RESULT 2 MSBs

A

RESULT 8 LSBs

A

P or Sr

t

ACQ

t

CONV

B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK

1

7

1

8

1

8

1

8

1

8

1

NUMBER OF BITS

CLOCK STRETCH

S

SLAVE ADDRESS

R

A

RESULT 1 ( 2MSBs)

A

RESULT 1 (8 LSBs)

A

RESULT N (8MSBs)

A

RESULT N (8LSBs)

A

P or Sr

t

ACQ1

ACQ2

ACQN

t

CONVN

CONV1

CONV2

Figure 10. Internal Clock Mode Read Cycles

The device memory contains all of the conversion results

when the MAX11606–MAX11611 release SCL. The con-

verted results are read back in a first-in-first-out (FIFO)

sequence. If AIN_/REF is set to be a reference input or

output (SEL1 = 1, Table 6), AIN_/REF is excluded from a

multichannel scan. This does not apply to the

MAX11608/MAX11609 as each provides separate pins

for AIN7 and REF. The memory contents can be read

continuously. If reading continues past the result stored

in memory, the pointer wraps around and point to the

first result. Note that only the current conversion results

are read from memory. The device must be addressed

with a read command to obtain new conversion results.

0–MAX61

The internal clock mode’s clock stretching quiets the

SCL bus signal, reducing the system noise during con-

version. Using the internal clock also frees the bus

master (typically a microcontroller) from the burden of

running the conversion clock, allowing it to perform

other tasks that do not need to use the bus.

MASTER TO SLAVE

SLAVE TO MASTER

A. SINGLE CONVERSION WITH EXTERNAL CLOCK

1

7

1

8

1

8

1

NUMBER OF BITS

S

R

A

SLAVE ADDRESS

RESULT (2 MSBs)

RESULT (8 LSBs)

P OR Sr

t

ACQ

t

CONV

B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK

1

7

1

8

1

8

1

8

1

8

1

NUMBER OF BITS

S

R

A

P OR Sr

SLAVE ADDRESS

RESULT 1 (2 MSBs)

RESULT 2 (8 LSBs)

RESULT N (2 MSBs)

RESULT N (8 LSBs)

t

ACQ1

ACQ2

ACQN

t

CONV1

CONVN

Figure 11. External Clock Mode Read Cycle

16 ______________________________________________________________________________________

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

0–MAX61

Table 5. Scanning Configuration

SCAN1 SCAN0

SCANNING CONFIGURATION

Scans up from AIN0 to the input selected by CS3–CS0. When CS3–CS0 exceeds 1011, the scanning stops at

AIN11. When AIN_/REF is set to be a REF input/output, scanning stops at AIN2 or AIN10.

0

1

*Converts the input selected by CS3–CS0 eight times (see Tables 3 and 4).

MAX11606/MAX11607: Scans upper half of channels.

Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for AIN0, AIN1, and

AIN2, the only scan that takes place is AIN2 (MAX11606/MAX11607). When AIN/REF is set to be a REF

input/output, scanning stops at AIN2.

MAX11608/MAX11609: Scans upper quartile of channels.

Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the only scan

that takes place is AIN6 (MAX11608/MAX11609).

1

0

1

MAX11610/MAX11611: Scans upper half of channels.

Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the only scan

that takes place is AIN6 (MAX11610/MAX11611). When AIN/REF is set to be a REF input/output, scanning

stops at selected channel or AIN10.

*Converts channel selected by CS3–CS0.

*When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11, and converting occurs

perpetually until not acknowledge occurs.

External Clock

When configured for external clock mode (CLK = 1),

the MAX11606–MAX11611 use the SCL as the conver-

sion clock. In external clock mode, the MAX11606–

MAX11611 begin tracking the analog input on the ninth

rising clock edge of a valid slave address byte. Two

SCL clock cycles later the analog signal is acquired

and the conversion begins. Unlike internal clock mode,

converted data is available immediately after the first

four empty high bits. The device continuously converts

input channels dictated by the scan mode until given a

not acknowledge. There is no need to re-address the

device with a read command to obtain new conversion

results (see Figure 11).

from a multichannel scan. The scanned results are writ-

ten to memory in the same order as the conversion. Read

the results from memory in the order they were convert-

ed. Each result needs a 2-byte transmission, the first byte

begins with six empty bits during which SDA is left high.

Each byte has to be acknowledged by the master or the

memory transmission is terminated. It is not possible to

read the memory independently of conversion.

Applications Information

Power-On Reset

The configuration and setup registers (Tables 1 and 2)

default to a single-ended, unipolar, single-channel con-

version on AIN0 using the internal clock with V

as the

DD

The conversion must complete in 1ms or droop on the

track-and-hold capacitor degrades conversion results.

Use internal clock mode if the SCL clock period

exceeds 60µs.

reference and AIN_/REF configured as an analog input.

The memory contents are unknown after power-up.

Automatic Shutdown

Automatic shutdown occurs between conversions when

the MAX11606–MAX11611 are idle. All analog circuits

participate in automatic shutdown except the internal

reference due to its prohibitively long wake-up time.

When operating in external clock mode, a STOP, not-

acknowledge or repeated START, condition must be

issued to place the devices in idle mode and benefit

from automatic shutdown. A STOP condition is not nec-

essary in internal clock mode to benefit from automatic

shutdown because power-down occurs once all con-

version results are written to memory (Figure 10). When

The MAX11606–MAX11611 must operate in external

clock mode for conversion rates from 40ksps to

94.4ksps. Below 40ksps internal clock mode is recom-

mended due to much smaller power consumption.

Scan Mode

SCAN0 and SCAN1 of the configuration byte set the

scan mode configuration. Table 5 shows the scanning

configurations. If AIN_/REF is set to be a reference input

or output (SEL1 = 1, Table 6), AIN_/REF is excluded

______________________________________________________________________________________ 17

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

Table 6. Reference Voltage, AIN_/REF, and REF Format

AIN_/REF

(MAX11606/

MAX11607/

MAX11610/

MAX11611)

REF

(MAX11608/

MAX11609)

REFERENCE

VOLTAGE

INTERNAL

REFERENCE STATE

SEL2

SEL1

SEL0

0

1

0

1

0

1

X

0

1

0

1

V

Analog input

Reference input

Analog input

Not connected

Reference input

Not connected

Reference output

Always off

Always on

Always off

Always on

DD

External reference

Internal reference

1

Analog input

1

Reference output

1

X = Don’t care.

using an external reference or V

as a reference, all

Internal Reference

DD

analog circuitry is inactive in shutdown and supply cur-

rent is less than 0.5µA (typ). The digital conversion

results obtained in internal clock mode are maintained

in memory during shutdown and are available for

access through the serial interface at any time prior to a

STOP or a repeated START condition.

The internal reference is 4.096V for the MAX11606/

MAX11608/MAX11610 and 2.048V for the MAX11607/

MAX11609/MAX11611. SEL1 of the setup byte controls

whether AIN_/REF is used for an analog input or a refer-

ence (Table 6). When AIN_/REF is configured to be an

internal reference output (SEL[2:1] = 11), decouple

AIN_/REF to GND with a 0.1µF capacitor and a 2kΩ series

resistor (see the Typical Operating Circuit). Once powered

up, the reference always remains on until reconfigured.

The internal reference requires 10ms to wake up and is

accessed using SEL0 (Table 6). When in shutdown, the

internal reference output is in a high-impedance state. The

reference should not be used to supply current for exter-

nal circuitry. The internal reference does not require an

0–MAX61

When idle, the MAX11606–MAX11611 continuously wait

for a START condition followed by their slave address (see

Slave Address section). Upon reading a valid address

byte the MAX11606–MAX11611 power-up. The internal

reference requires 10ms to wake up, so when using the

internal reference it should be powered up 10ms prior to

conversion or powered continuously. Wake-up is invisible

when using an external reference or V as the reference.

DD

Automatic shutdown results in dramatic power savings,

particularly at slow conversion rates and with internal

clock. For example, at a conversion rate of 10ksps, the

average supply current for the MAX11607 is 60µA (typ)

and drops to 6µA (typ) at 1ksps. At 0.1ksps the average

supply current is just 1µA, or a minuscule 3µW of power

consumption, see Average Supply Current vs. Conversion

Rate in the Typical Operating Characteristics).

OUTPUT CODE

MAX11606–

MAX11611

FULL-SCALE

TRANSITION

11 . . . 111

11 . . . 110

11 . . . 101

FS = V

REF

Reference Voltage

SEL[2:0] of the setup byte (Table 1) control the reference

and the AIN_/REF configuration (Table 6). When

AIN_/REF is configured to be a reference input or refer-

ence output (SEL1 = 1), differential conversions on

AIN_/REF appear as if AIN_/REF is connected to GND

(see note 2 of Table 4). Single-ended conversion in scan

mode on AIN_/REF is ignored by internal limiter, which

sets the highest available channel at AIN2 or AIN10.

ZS = GND

V

REF

1 LSB =

1024

00 . . . 011

00 . . . 010

00 . . . 001

00 . . . 000

0

1

2

3

FS

FS - 3/2 LSB

INPUT VOLTAGE (LSB)

Figure 12. Unipolar Transfer Function

18 ______________________________________________________________________________________

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

0–MAX61

OUTPUT CODE

MAX11606–

MAX11611

V

REF

2

FS

=

SUPPLIES

011 . . . 111

011 . . . 110

ZS = 0

-FS =

GND

3V OR 5V

V

= 3V/5V

LOGIC

-V

REF

2

000 . . . 010

000 . . . 001

000 . . . 000

V

REF

1 LSB =

1024

4.7μF

R* = 5Ω

111 . . . 111

111 . . . 110

111 . . . 101

0.1μF

V

GND

3V/5V DGND

DD

100 . . . 001

100 . . . 000

DIGITAL

MAX11606–

MAX11611

CIRCUITRY

0

- FS

+FS - 1 LSB

INPUT VOLTAGE (LSB)

*V

COM

≥ V /2 *V = (AIN+) - (AIN-)

REF IN

*OPTIONAL

Figure 13. Bipolar Transfer Function

Figure 14. Power-Supply Grounding Connection

external bypass capacitor and works best when left

unconnected (SEL1 = 0).

as possible. Route digital signals far away from sensi-

tive analog and reference inputs.

High-frequency noise in the power supply (V ) could

DD

External Reference

influence the proper operation of the ADC’s fast com-

The external reference can range from 1V to V . For

DD

parator. Bypass V

to the star ground with a network of

DD

maximum conversion accuracy, the reference must be

able to deliver up to 40µA and have an output imped-

ance of 500Ω or less. If the reference has a higher out-

put impedance or is noisy, bypass it to GND as close

as possible to AIN_/REF with a 0.1µF capacitor.

two parallel capacitors, 0.1µF and 4.7µF, located as

close as possible to the MAX11606–MAX11611 power-

supply pin. Minimize capacitor lead length for best sup-

ply noise rejection, and add an attenuation resistor (5Ω)

in series with the power supply, if it is extremely noisy.

Transfer Functions

Output data coding for the MAX11606–MAX11611 is

binary in unipolar mode and two’s complement in bipo-

Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values on

an actual transfer function from a straight line. This straight

line can be either a best straight-line fit or a line drawn

between the endpoints of the transfer function, once offset

and gain errors have been nullified. The MAX11606–

MAX11611’s INL is measured using the endpoint.

lar mode with 1LSB = (V

/2N) where N is the number

REF

of bits (10). Code transitions occur halfway between

successive-integer LSB values. Figure 12 and Figure

13 show the input/output (I/O) transfer functions for

unipolar and bipolar operations, respectively.

Layout, Grounding, and Bypassing

Only use PC boards. Wire-wrap configurations are not

recommended since the layout should ensure proper

separation of analog and digital traces. Do not run ana-

log and digital lines parallel to each other, and do not

layout digital signal paths underneath the ADC pack-

age. Use separate analog and digital PCB ground sec-

tions with only one star point (Figure 14) connecting the

two ground systems (analog and digital). For lowest

noise operation, ensure the ground return to the star

ground’s power supply is low impedance and as short

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between

an actual step width and the ideal value of 1LSB. A

DNL error specification of less than 1LSB guarantees

no missing codes and a monotonic transfer function.

Aperture Jitter

Aperture jitter (t ) is the sample-to-sample variation in

AJ

the time between the samples.

______________________________________________________________________________________ 19

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

sampling rate. An ideal ADC’s error consists of quanti-

zation noise only. With an input range equal to the

ADC’s full-scale range, calculate the ENOB as follows:

Aperture Delay

Aperture delay (t ) is the time between the falling

AD

edge of the sampling clock and the instant when an

actual sample is taken.

⎡

⎢

⎣

⎤

⎥

⎦

SignalRMS

NoiseRMS+ THDRMS

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital sam-

ples, the theoretical maximum SNR is the ratio of the full-

scale analog input (RMS value) to the RMS quantization

error (residual error). The ideal, theoretical minimum ana-

log-to-digital noise is caused by quantization error only

and results directly from the ADC’s resolution (N Bits):

SINAD(dB) = 20 × log

ENOB = (SINAD - 1.76)/6.02

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS

sum of the input signal’s first five harmonics to the fun-

damental itself. This is expressed as:

SNR

= 6.02 ꢀ N + 1.76

dB dB

MAX[dB]

⎛

⎞

2

⎛

⎜

⎝

⎞

V

+ V + V + V

3 4 5

⎜

⎟

2

THD = 20 × log

⎟

⎠

⎜

⎟

V

1

In reality, there are other noise sources besides quanti-

zation noise: thermal noise, reference noise, clock jitter,

etc. SNR is computed by taking the ratio of the RMS

signal to the RMS noise, which includes all spectral

components minus the fundamental, the first five har-

monics, and the DC offset.

⎜

⎝

⎟

⎠

where V is the fundamental amplitude, and V through V

5

are the amplitudes of the 2nd through 5th order harmonics.

1

2

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of RMS

amplitude of the fundamental (maximum signal compo-

nent) to the RMS value of the next largest distortion

component.

0–MAX61

Signal-to-Noise Plus Distortion

Signal-to-noise plus distortion (SINAD) is the ratio of the

fundamental input frequency’s RMS amplitude to RMS

equivalent of all other ADC output signals.

SINAD (dB) = 20 ^ꢀlog (SignalRMS/NoiseRMS)

Chip Information

Effective Number of Bits

Effective number of bits (ENOB) indicates the global

accuracy of an ADC at a specific input frequency and

PROCESS: BiCMOS

20 ______________________________________________________________________________________

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

0–MAX61

Typical Operating Circuit

Pin Configurations

TOP VIEW

3.3V or 5V

+

AIN0

AIN1

1

2

3

4

8

7

6

5

V

DD

0.1μF

V

DD

GND

SDA

SCL

R *

S

MAX11606

MAX11607

AIN0

AIN1

AIN2

SDA

SCL

ANALOG

INPUTS

MAX11606–

MAX11611

AIN3/REF

R *

S

2kΩ

RC NETWORK*

AIN3**/REF

μMAX

GND

5V

C

0.1μF

REF

5V

R

P

+

(REF) AIN11/REF

(N.C.) AIN10

(N.C.) AIN9

(N.C.) AIN8

AIN0

1

16

V

DD

2

3

4

5

6

7

8

15 GND

14 SDA

13 SCL

12 AIN7

11 AIN6

10 AIN5

R

P

SDA

SCL

μC

MAX11608–

MAX11611

AIN1

*OPTIONAL

**AIN11/REF (MAX11610/MAX11611)

AIN2

AIN3

9

AIN4

QSOP

Package Information

( ) INDICATES PINS ON THE MAX11608/MAX11609.

For the latest package outline information and land patterns, go

to www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

Selector Guide

8 µMAX

U8CN+1

21-0036

21-0055

INTERNAL

REFERENCE VOLTAGE

SUPPLY

INPUT

CHANNELS

INL

(LSB)

16 QSOP

E16+1

PART

(V)

MAX11606

MAX11607

MAX11608

MAX11609

MAX11610

MAX11611

4

4.096

2.048

4.096

2.048

4.096

2.048

4.5 to 5.5

2.7 to 3.6

4.5 to 5.5

2.7 to 3.6

4.5 to 5.5

2.7 to 3.6

1

8

12

______________________________________________________________________________________ 21

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

Revision History

REVISION

NUMBER

REVISION

DATE

PAGES

CHANGED

DESCRIPTION

0

1

4/09

7/09

Introduction of the MAX11606/MAX11607

Introduction of the MAX11608–MAX116011

—

1

0–MAX61

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Maxim is a registered trademark of Maxim Integrated Products, Inc.


型号：	MAX11607
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs 2.7V至3.6V和4.5V至5.5V ，低功耗，4 / 8 / 12通道， 2线串行10位ADC
文件：	总22页 (文件大小：341K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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