MAX1143BCAP-T_技术文档

19-2037; Rev 0; 5/01

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

2/MAX143

General Description

Features

The MAX1142/MAX1143 are 200ksps, 14-bit ADCs.

These serially interfaced ADCs connect directly to

SPI™, QSPI™, and MICROWIRE™ devices without

external logic. They combine an input scaling network,

internal track/hold, a clock, +4.096V reference, and

three general-purpose digital output pins (for external

multiplexer or PGA control) in a 20-pin SSOP package.

The excellent dynamic performance (SINAD ≥ 81dB),

high-speed (200ksps), and low power (7.5mA) of these

ADCs, make them ideal for applications such as indus-

trial process control, instrumentation, and medical

applications. The MAX1142 accepts input signals of 0

to +12V (unipolar) or 12V (bipolar), while the

MAX1143 accepts input signals of 0 to +4.096V (unipo-

lar) or 4.096V (bipolar). Operating from a single

+4.75V to +5.25V analog supply and a +4.75V to

+5.25V digital supply, power-down modes reduce cur-

rent consumption to 1mA at 10ksps and further reduce

supply current to less than 20µA at slower data rates.

A serial strobe output (SSTRB) allows direct connection

to the TMS320-family of digital signal processors. The

MAX1142/MAX1143 user can select either the internal

clock, or an external serial-interface clock for the ADC

to perform analog-to-digital conversions.

♦ 200ksps (Bipolar) and 150ksps (Unipolar)

Sampling ADC

♦ 14-Bits, No Missing Codes

♦ 1LSB INL Guaranteed

♦ 81dB (min) SINAD

♦ +5V Single-Supply Operation

♦ Low Power Operation, 7.5mA (Unipolar Mode)

♦ 2.5µA Shutdown Mode

♦ Software-Configurable Unipolar & Bipolar Input

Ranges

0 to +12V and ±12V (MAX1142)

0 to +4.096V and ±4.096V (MAX1143)

Internal or External Reference

♦ Internal or External Clock

♦ SPI/QSPI/MICROWIRE-Compatible Wire Serial

Interface

♦ Three User-Programmable Logic Outputs

♦ Small 20-Pin SSOP Package

The MAX1142/MAX1143 feature internal calibration cir-

cuitry to correct linearity and offset errors. On-demand

calibration allows the user to optimize performance.

Three user-programmable logic outputs are provided

for the control of an 8-channel MUX or a PGA.

Ordering Information

PIN-

INL

PART

TEMP. RANGE

PACKAGE

(LSB)

MAX1142ACAP

0°C to +70°C

20 SSOP

±1

±2

MAX1142BCAP

Applications

Ordering Information continued at end of data sheet.

Industrial Process Control

Industrial I/O Modules

Pin Configuration

Data-Acquisition Systems

Medical Instruments

TOP VIEW

REF

REFADJ

AGND

1

2

20

AIN

Portable and Battery-Powered Equipment

19 AGND

CREF

CS

3

18

17

AV

DD

4

MAX1142

MAX1143

DGND

SHDN

P2

5

16 DIN

15 DV

6

DD

DGND

7

14

13 SCLK

12

Functional Diagram appears at end of data sheet.

Typical Application Circuit appears at end of data sheet.

P1

8

P0

9

RST

11 DOUT

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

SSTRB

10

SSOP

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

ABSOLUTE MAXIMUM RATINGS

AV

to AGND, DV

to DGND .............................-0.3V to +6V

Operating Temperature Ranges

DD

AGND to DGND.....................................................-0.3V to +0.3V

AIN to AGND..................................................................... 16.5V

REFADJ, CREF, REF to AGND.................-0.3V to (AV

Digital Inputs to DGND.............................................-0.3V to +6V

Digital Outputs to DGND .........................-0.3V to (DV + 0.3V)

MAX114_CAP ......................................................0°C to +70°C

MAX114_EAP....................................................-40°C to +85°C

Storage Temperature Range.............................-60°C to +150°C

Junction Temperature......................................................+150°C

Lead Temperature (soldering, 10s) .................................+300°C

+ 0.3V)

DD

Continuous Power Dissipation (T = +70°C)

A

20-SSOP (derate 8.00mW/°C above +70°C) ...............640mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(AV

= DV

= +4.096V, V

= +5V 5%, f

= 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external

DD

SCLK

V

REF

= AV , C

= 2.2µF, C

= 1µF, T = T

to T , unless otherwise noted. Typical values are at

MAX

REFADJ

DD

REF

CREF

A

MIN

T

= +25°C.)

A

2/MAX143

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DC ACCURACY (Note 1)

Resolution

14

Bits

Unipolar Mode

MAX114_A

MAX114_B

±1

±2

Relative Accuracy (Note 2)

INL

LSB

Differential Nonlinearity

Transition Noise

DNL

±1

LSB

0.34

LSB RMS

Unipolar

Bipolar

Unipolar

Bipolar

±4

±6

Offset Error

mV

±0.2

±0.3

Gain Error (Note 3)

%FSR

Offset Drift (Bipolar and Unipolar)

Gain Drift (Bipolar and Unipolar)

Excluding reference drift

±1

ppm/^oC

DYNAMIC SPECIFICATIONS (5kHz sine-wave input, 200ksps, 4.8MHz clock, bipolar input mode).

(MAX1142, 24Vp-p. MAX1143, 8.192Vp-p)

f

= 5kHz

81

82

IN

SINAD

SNR

dB

= 100kHz

= 5kHz

82

91

95

= 100kHz

= 5kHz

-88

THD

= 100kHz

= 5kHz

90

SFDR

= 100kHz

ANALOG INPUT

Unipolar

Bipolar

Unipolar

Bipolar

0

-12

0

12

MAX1142

MAX1143

Input Range

V

4.096

-4.096

2

_______________________________________________________________________________________

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

2/MAX143

ELECTRICAL CHARACTERISTICS (continued)

(AV

= DV

= +4.096V, V

= 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external

DD

SCLK

V

REF

= 2.2µF, C

= 1µF, T = T

to T , unless otherwise noted. Typical values are at

MAX

DD

REF

CREF

A

MIN

T

= +25°C.)

A

PARAMETER

SYMBOL

CONDITIONS

Unipolar

MIN

7.5

TYP

10.0

7.9

MAX

UNITS

kΩ

MAX1142

MAX1143

Bipolar

Unipolar

Bipolar

5.9

Input Impedance

100

3.4

1000

4.5

Input Capacitance

CONVERSION RATE

Internal Clock Frequency

Aperture Delay

32

pF

4

MHz

ns

t

10

50

AD

Aperture Jitter

t

ps

AJ

MODE 1 (24 External Clock Cycles per Conversion)

Unipolar

Bipolar

Unipolar

Bipolar

Unipolar

Bipolar

0.1

4.17

8

3

External Clock Frequency

Sample Rate

f

MHz

ksps

µs

SCLK

4.8

125

200

240

f

= f

/24

S

SCLK

t

=

CONV+ACQ

24 / f

Conversion Time (Note 4)

SCLK

5

MODE 2 (Internal Clock Mode)

External Clock Frequency

(Data Transfer Only)

8

6

MHz

µs

Conversion Time

SSTRB Low Pulse Width

Unipolar

4

1.82

1.14

Acquisition Time

µs

Bipolar

MODE 3 (32 External Clock Cycles per Conversion)

External Clock Frequency

Sample Rate

f

Unipolar or Bipolar

0.1

4.8

MHz

ksps

SCLK

f

= f

/32 Unipolar or Bipolar

3.125

150

S

SCLK

t

=

CONV+ACQ

Conversion Time (Note 4)

Unipolar or Bipolar

6.67

320

µs

32 / f

SCLK

INTERNAL REFERENCE

Output Voltage

V

4.056

4.096

24

4.136

V

mA

ppm/^oC

REF

REF Short Circuit Current

Output Tempco

±20

Capacitive Bypass at REF

0.47

10

µF

Maximum Capacitive Bypass at

REFADJ

10

µF

REFADJ Output Voltage

REFADJ Input Range

4.096

100

V

For small adjustments from 4.096V

mV

_______________________________________________________________________________________

3

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

ELECTRICAL CHARACTERISTICS (continued)

(AV

= DV

= +4.096V, V

= 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external

DD

SCLK

V

REF

= 2.2µF, C

= 1µF, T = T

to T , unless otherwise noted. Typical values are at

MAX

DD

REF

CREF

A

MIN

T

= +25°C.)

A

PARAMETER

SYMBOL

CONDITIONS

To power-down the internal reference

MIN

TYP

MAX

AV

UNITS

V

REFADJ Buffer Disable

Threshold

AV

-

DD

0.5V

0.1V

Buffer Voltage Gain

1

V/V

EXTERNAL REFERENCE (Reference buffer disabled. Reference applied to REF)

Input Range (Notes 5 and 6)

3.0

2.4

4.096

250

230

0.1

4.2

V

= 4.096V, f

= 4.8MHz

= 0

REF

SCLK

Input Current

µA

In power-down, f

= 0

SCLK

DIGITAL INPUTS

Input High Voltage

Input Low Voltage

Input Leakage

V

IH

2/MAX143

V

0.8

IL

I

V

= 0 or DV

DD

±1

µA

V

IN

Input Hysteresis

Input Capacitance

DIGITAL OUTPUTS

V

0.2

10

HYST

C

pF

IN

DV

0.5

-

DD

Output High Voltage

V

I

= 0.5mA

V

OH

SOURCE

I

= 5mA

0.4

0.8

SINK

Output Low Voltage

V

OL

= 16mA

Three-State Leakage Current

I

CS = DV

±10

µA

pF

L

DD

Three-State Output

Capacitance

CS = DV

10

DD

POWER SUPPLIES

Analog Supply (Note 7)

Digital Supply (Note 7)

AV

DV

4.75

5

5.25

8

V

DD

5

DD

Unipolar Mode

Bipolar Mode

5

mA

Analog Supply Current

I

ANALOG

8.5

0.3

2.5

2.2

11

SHDN= 0, or software power-down mode

10

µA

mA

µA

Unipolar or Bipolar Mode

3.5

10

Digital Supply Current

I

DIGITAL

PSRR

SHDN= 0, or software power-down mode

Power Supply Rejection Ratio

(Note 8)

AV

= DV

= 4.75V to 5.25V,

DD

72

dB

DD

4

_______________________________________________________________________________________

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

2/MAX143

TIMING CHARACTERISTICS (Figures 5 and 6)

(AV

= DV

= +5V 5%, T = T

to T , unless otherwise noted.)

MAX

DD

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

1.14

50

TYP

MAX

UNIT

µs

ns

Acquisition Time

t

ACQ

DIN to SCLK Setup

t

DS

DH

DO

DIN to SCLK Hold

t

0

SCLK to DOUT Valid

CS Fall to DOUT Enable

CS Rise to DOUT Disable

CS to SCLK Rise Setup

CS to SCLK Rise Hold

SCLK High Pulse Width

SCLK Low Pulse Width

SCLK Fall to SSTRB

t

70

80

t

C

= 50pF

DV

LOAD

t

TR

t

100

0

CSS

CSH

t

80

CH

t

CL

t

C

= 50pF

80

SSTRB

LOAD

CS Fall to SSTRB Enable

CS Rise to SSTRB Disable

SSTRB Rise to SCLK Rise

RST Pulse Width

t

= 50pF, External clock mode

SDV

t

STR

t

Internal clock mode

0

SCK

t

208

RS

Note 1: Tested at AV = DV = +5V, bipolar input mode.

DD

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset

error have been nulled.

Note 3: Offset nulled.

Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period, clock has 50% duty cycle.

Includes the acquisition time.

Note 5: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.

Note 6 When an external reference has a different voltage than the specified typical value, the full scale of the ADC will scale

proportionally.

Note 7: Electrical characteristics are guaranteed from AV

= DV

to AV

= DV . For operations beyond

DD(MAX)

DD(MIN)

DD(MAX)

this range, see the Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact

the factory.

Note 8: Defined as the change in positive full-scale caused by a 5% variation in the nominal supply voltage.

_______________________________________________________________________________________

5

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

Typical Operating Characteristics

(MAX1142/MAX1143, AV

= DV

= +5V , f

= 4.8MHz, external clock (50% duty cycle), 24-clocks/conversion (200ksps), bipo-

DD

SCLK

lar input, external REF = +4.096V, 0.22µF bypassing on REFADJ, 2.2µF on REF, 1µF on CREF, T = 25°C, unless otherwise noted.)

A

TOTAL SUPPLY CURRENT

vs. TEMPERATURE

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

1.0

0.8

11.5

11.3

11.1

10.9

10.7

10.5

10.3

10.1

9.9

1.0

0.5

0

A: AVDD, DVDD = +4.75V

B: AVDD, DVDD = +5.00V

C: AVDD, DVDD = +5.25V

0.6

0.4

0.2

C

0

B

-0.2

-0.4

-0.6

-0.8

-1.0

A

-0.5

-1.0

9.7

9.5

-40 -20

0

20

40

60

80

1

3263

6525

9787

13049

1631

1

3433

6865

10297

13729

15445

2/MAX143

1632

4894

8156 11418 14680

1717

5149

8581 12013

TEMPERATURE (°C)

DIGITAL OUTPUT CODE

OFFSET VOLTAGE

vs. TEMPERATURE

GAIN ERROR vs.

TEMPERATURE

TOTAL SUPPLY CURRENT vs.

CONVERSION RATE (USING SHUTDOWN)

0

0.04

0.03

0.02

100

10

A: AV , DV = +4.75V

DD DD

DD

B: AV , DV = +5.00V

DD

DD DD

C: AV , DV = +5.25V

DD

-1

-2

-3

-4

C

B

1

B

C

0.01

0

0.1

0.01

A

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

0

1

10

100

1000

TEMPERATURE (°C)

CONVERSION RATE (ksps)

6

_______________________________________________________________________________________

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

2/MAX143

Typical Operating Characteristics (continued)

(MAX1142/MAX1143, AV

= DV

= +5V , f

= 4.8MHz, external clock (50% duty cycle), 24-clocks/conversion (200ksps), bipo-

DD

SCLK

lar input, external REF = +4.096V, 0.22µF bypassing on REFADJ, 2.2µF on REF, 1µF on CREF, T = 25°C, unless otherwise noted.)

A

NORMALIZED REF VOLTAGE

SINAD PLOT

vs. TEMPERATURE

FFT PLOT

100

90

1.010

1.005

1

0

f

= 200kHz

SAMPLE

f

= 200kHz

SAMPLE

= 5kHz

IN

-20

80

70

60

-40

-60

50

40

-80

30

20

10

0

0.995

0.990

-110

-120

-40

-20

0

20

40

60

80

0

9

18 27 36 45 54 63 72 81 90 99

FREQUENCY (kHz)

0.1

1

10

100

TEMPERATURE (°C)

FREQUENCY (kHz)

SFDR PLOT

THD PLOT

120

110

100

0

f

= 200kHz

f

= 200kHz

SAMPLE

-10

-20

-30

90

80

-40

-50

70

60

-60

50

40

30

20

10

0

-70

-80

-90

-100

-110

0.1

1

10

100

0.1

1

10

100

FREQUENCY (kHz)

_______________________________________________________________________________________

7

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

Pin Description

NAME

FUNCTION

Reference Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In

internal reference mode, the reference buffer provides a +4.096V nominal output, externally adjustable at

REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to AV . Bypass to

DD

1

REF

AGND with a 2.2µF capacitor when using the internal reference.

Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to AGND with 0.22µF. When using an

2

REFADJ

AGND

external reference, connect REFADJ to AV

to disable the internal bandgap reference.

DD

3

4

5

6

7

8

9

Analog Ground. This is the primary analog ground (Star Ground).

AV

Analog Supply 5V ±5%. Bypass AV

to AGND (pin 3) with a 0.1µF capacitor.

DD

DGND

SHDN

P2

Digital Ground

Shutdown Control Input. Drive SHDN low to put the ADC in shutdown mode.

User-Programmable Output 2

2/MAX143

P1

User-Programmable Output 1

P0

User-Programmable Output 0

Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC begins a conversion and goes

high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period

before the MSB decision. It is high impedance when CS is high in external clock mode.

10

SSTRB

Serial Data Output. MSB first, straight binary format for unipolar input, two’s complement for bipolar input.

Each bit is clocked out of DOUT at the falling edge of SCLK.

11

12

13

DOUT

RST

Reset Input. Drive RST low to put the device in the power-on default mode. See the Power-On Reset section.

Serial Data Clock Input. Serial data on DIN is loaded on the rising edge of SCLK, and serial data is updated

on DOUT on the falling edge of SCLK. In external clock mode, SCLK sets the conversion speed.

SCLK

DGND

14

15

16

Digital Ground. Connect to pin 5.

DV

Digital Supply 5V ±5%. Bypass DV

to DGND (pin 14) with a 0.1µF capacitor.

DD

DIN

Serial Data Input. Serial data on DIN is latched on the rising edge of SCLK.

Chip Select Input. Drive CS low to enable the serial interface. When CS is high, DOUT is high-impedance.

In external clock mode SSTRB is high-impedance when CS is high.

17

CS

18

19

20

CREF

AGND

AIN

Reference Buffer Bypass. Bypass CREF to AGND (pin 3) with 1µF.

Analog Ground. Connect pin 19 to pin 3.

Analog Input

8

_______________________________________________________________________________________

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

2/MAX143

Detailed Description

BIPOLAR

VOLTAGE

The MAX1142/MAX1143 analog-to-digital converters

S1

REFERENCE

(ADCs) use a successive-approximation technique and

input track/hold (T/H) circuitry to convert an analog signal

to a 14-bit digital output. The MAX1142/MAX1143 easily

interfaces to microprocessors (µPs). The data bits can be

read either during the conversion in external clock mode

or after the conversion in internal clock mode.

UNIPOLAR

R1

2.5kΩ

C

HOLD

30pF

R2

TRACK

AIN

S2

HOLD

T/H OUT

HOLD

In addition to a 14-bit ADC, the MAX1142/MAX1143

include an input scaler, an internal digital microcontroller,

calibration circuitry, an internal clock generator, and an

internal bandgap reference. The input scaler for the

MAX1142 enables conversion of input signals ranging

from 0 to +12V (unipolar input) or 12V (bipolar input).

The MAX1143 accepts 0 to +4.096V (unipolar input) or

4.096V (bipolar input). Input range selection is software

controlled.

R3

TRACK

S3

S1 = BIPOLAR/UNIPOLAR

S2, S3 = T/H SWITCH

R2 = 7.6kΩ (MAX1142)

OR 2.5kΩ (MAX1143)

R3 = 3.9kΩ (MAX1142)

OR INFINITY (MAX1143)

Calibration

To minimize linearity, offset, and gain errors, the

MAX1142/MAX1143 have on-demand software calibra-

tion. Initiate calibration by writing a Control-Byte with bit

M1 = 0, and bit M0 = 1 (See Table 1). Select internal or

external clock for calibration by setting the INT/EXT bit in

the Control-Byte. Calibrate the MAX1142/MAX1143 with

the clock used for performing conversions.

Figure 1. Equivalent Input Circuit

Digital Interface

The digital interface pins consist of SHDN, RST, SSTRB,

DOUT, SCLK, DIN and CS. Bringing SHDN low, places

the MAX1142/MAX1143 in its 2.5µA shutdown mode. A

logic low on RST halts the MAX1142/MAX1143 opera-

tion and returns the part to its power-on reset state.

Offsets resulting from synchronous noise (such as the

conversion clock) are canceled by the MAX1142/

MAX1143’s calibration circuitry. However, because the

magnitude of the offset produced by a synchronous sig-

nal depends on the signal’s shape, recalibration may be

appropriate if the shape or relative timing of the clock or

other digital signals change, as might occur if more than

one clock signal or frequency is used.

In external clock mode, SSTRB is low and pulses high

for one clock cycle at the start of conversion. In internal

clock mode SSTRB goes low at the start of the conver-

sion, and goes high to indicate the conversion is fin-

ished.

The DIN input accepts Control-Byte data which is

clocked in on each rising edge of SCLK. After CS goes

low or after a conversion or calibration completes, the

first logic “1” clocked-into DIN is interpreted as the

START bit, the MSB of the 8-bit Control-Byte.

Input Scaler

The MAX1142/MAX1143 have an input scaler which

allows conversion of true bipolar input voltages while

operating from a single +5V supply. The input scaler

attenuates and shifts the input, as necessary, to map the

external input range to the input range of the internal

DAC. The MAX1142 analog input range is 0 to +12V

(unipolar) or 12V (bipolar). The MAX1143 analog input

range is 0 to +4.096V (unipolar) or 4.096V (bipolar).

Unipolar and bipolar mode selection is configured with bit

6 of the serial Control-Byte.

The SCLK input is the serial data transfer clock which

clocks data in and out of the MAX1142/MAX1143.

SCLK also drives the A/D conversion steps in external

clock mode (see Internal and External Clock Modes

section).

DOUT is the serial output of the conversion result.

DOUT is updated on the falling edge of SCLK. DOUT is

high-impedance when CS is high.

Figure 1 shows the equivalent input circuit of the

MAX1142/MAX1143. The resistor network on the analog

input provides 16.5V fault protection. This circuit limits

the current going into or out of the pin, to less than 2mA.

The overvoltage protection is active, even if the device is

CS must be low for the MAX1142/MAX1143 to accept a

Control-Byte. The serial interface is disabled when CS

is high.

in a power-down mode, or if AV = 0.

DD

_______________________________________________________________________________________

9

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

bit. If a new start bit occurs before the current conver-

User-Programmable Outputs

The MAX1142/MAX1143 have three user-programma-

ble outputs: P0, P1 and P2. The power-on default state

for the programmable outputs is zero. These are push-

pull CMOS outputs suitable for driving a multiplexer, a

PGA, or other signal preconditioning circuitry. The user-

programmable outputs are controlled by bits 0, 1 and 2

of the Control-Byte (Table 2).

sion is complete, the conversion is aborted and a new

acquisition is initiated. Table 1 shows the Control-Byte

format.

Internal and External Clock Modes

The MAX1142/MAX1143 may use either the external

serial clock or the internal clock to perform the succes-

sive-approximation conversion. In both clock modes,

the external clock shifts data in and out of the

MAX1142/MAX1143. Bit 5 (INT/EXT) of the Control-Byte

programs the clock mode.

The user-programmable outputs are set to zero during

power-on reset (POR) or when RST goes low. During

hardware or software shutdown P0, P1, and P2 are

unchanged and remain low-impedance.

External Clock

In external clock mode, the external clock not only

shifts data in and out, but it also drives the A/D conver-

sion steps. In short acquisition mode, SSTRB pulses

high for one clock period after the seventh falling edge

of SCLK, following the start bit. The MSB of the conver-

sion is available at DOUT on the eighth falling edge of

SCLK (Figure 2).

Starting a Conversion

Start a conversion by clocking a Control-Byte into the

device’s internal shift register. With CS low, each rising

edge on SCLK clocks a bit from DIN into the

MAX1142/MAX1143’s internal shift register. After CS

goes low or after a conversion or calibration completes,

the first arriving logic “1” is defined as the start bit of

the Control-Byte. Until this first start bit arrives, any

number of logic “0” bits can be clocked into DIN with

no effect. If at any time during acquisition or conversion,

CS is brought high and then low again, the part is

placed into a state where it can recognize a new start

2/MAX143

In long acquisition mode, when using the external

clock, SSTRB pulses high for one clock period after the

fifteenth falling edge of SCLK, following the start bit.

The MSB of the conversion is available at DOUT on the

sixteenth falling edge of SCLK (Figure 3).

Table 1. Control-Byte Format

BIT7

(MSB)

BIT0

(LSB)

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

START

BIT

UNI/BIP

NAME

START

INT/EXT

M1

M0

P2

P1

P0

DESCRIPTION

The first logic “1” bit, after CS goes low, defines the beginning of the Control-Byte

1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, analog

input signals from 0 to +12V (MAX1142) or 0 to V (MAX1143) can be converted. In bipolar

mode analog input signals from -12V to +12V (MAX1142) or -V

converted.

7 (MSB)

REF

6

UNI/BIP

to +V

(MAX1143) can be

REF

5

4

INT/EXT

Selects the internal or external conversion clock. 1 = Internal, 0 = External.

M1

M0

MODE

0

24 External clocks per conversion (short acquisition mode)

3

M0

0

1

0

1

Start Calibration. Starts internal calibration

Software power-down mode

32 External clocks per conversion (long acquisition mode)

2

1

P2

P1

P0

These three bits are stored in a port register and output to pins P2–P0 for use in addressing a

MUX or PGA. These three bits are updated in the port register simultaneously when a new

Control-Byte is written.

0(LSB)

10 ______________________________________________________________________________________

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

2/MAX143

Table 2. User-Programmable Outputs

PROGRAMMED

THROUGH

CONTROL-

BYTE

POWER-ON

OR

DEFAULT

OUTPUT

DESCRIPTION

P2

P1

P0

Bit 2

Bit 1

Bit 0

0

User programmable outputs follow the state of the Control-Byte’s three LSBs,

and are updated simultaneously when a new Control-Byte is written. Outputs

are push-pull. In hardware and software shutdown, these outputs are

unchanged and remain low-impedance.

In external clock mode, SSTRB is high-impedance

when CS is high. In external clock mode, CS is normally

held low during the entire conversion. If CS goes high

during the conversion, SCLK is ignored until CS goes

low. This allows external clock mode to be used with 8-

bit bytes.

The MSB of the conversion is available at DOUT when

SSTRB goes high. The subsequent 15 falling edges on

SCLK shift the remaining bits out of the internal storage

register (Figure 4). CS does not need to be held low

once a conversion is started.

When internal clock mode is selected, SSTRB does not

go into a high-impedance state when CS goes high.

Figure 5 shows the SSTRB timing in internal clock

mode. In internal clock mode, data can be shifted into

the MAX1142/MAX1143 at clock rates up to 4.8MHz,

provided that the minimum acquisition time,

Internal Clock

In internal clock mode, the MAX1142/MAX1143 gener-

ates its own conversion clock. This frees the micro-

processor from the burden of running the SAR conver-

sion clock, and allows the conversion results to be read

back at the processor’s convenience, at any clock rate

up to 8MHz.

t

, is kept above 1.14µs in bipolar mode and 1.82µs

ACQ

in unipolar-mode. Data can be clocked out at 8MHz.

SSTRB goes low at the start of the conversion and goes

high when the conversion is complete. SSTRB will be

low for a maximum of 6µs, during which time SCLK

should remain low for best noise performance. An inter-

nal register stores data when the conversion is in

progress. SCLK clocks the data out of the internal stor-

age register at any time after the conversion is com-

plete.

Output Data

The output data format is straight binary for unipolar

conversions and two’s complement in bipolar mode. In

both modes the MSB is shifted out of the MAX1142/

MAX1143 first.

CS

t

ACQ

1

4

8

12

15

21

24

SCLK

UNI/ INT/

BIP EXT

M1 M0

P2

P1

P0

START

DIN

SSTRB

FILLED WITH

ZEROS

B13

MSB

B0

LSB

B12 B11 B10 B9

B8

B7

B2 B1

X

DOUT

A/D

STATE

IDLE

ACQUISITION

CONVERSION

IDLE

Figure 2. Short Acquisition Mode (24-Clock Cycles) External Clock, Bipolar Mode

______________________________________________________________________________________ 11

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

CS

t

ACQ

1

4

8

15

19

21

32

SCLK

UNI/ INT/

BIP EXT

M1 M0

P2

P1

P0

START

DIN

SSTRB

FILLED WITH

ZEROS

B13

MSB

B0

LSB

B12 B11

B2

B1

X

DOUT

A/D

STATE

IDLE

ACQUISITION

CONVERSION

IDLE

Figure 3. Long Acquisition Mode (32-Clock Cycles) External Clock, Bipolar Mode

2/MAX143

CS

t

ACQ

1

4

8

9

10

21

24

SCLK

UNI/ INT/

BIP EXT

M1 M0

P2

P1

P0

START

DIN

SSTRB

t

CONV

FILLED WITH

ZEROS

B13

MSB

B0

LSB

DOUT

B12 B11

B2

B1

X

Figure 4. Internal Clock Mode Timing, Short Acquisition, Bipolar Mode

CS

t

CONV

CSS

t

SCK

CSH

SSTRB

t

SSTRB

SCLK

PO CLOCKED IN

NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

Figure 5. Internal Clock Mode SSTRB Detailed Timing

12 ______________________________________________________________________________________

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

2/MAX143

The MAX1142/MAX1143 should be calibrated after

power-up or the assertion of reset. Make sure the

power supplies and the reference voltage have fully

settled prior to initiating the calibration sequence.

Data Framing

The falling edge of CS does NOT start a conversion on

the MAX1142/MAX1143. The first logic high clocked

into DIN is interpreted as a start bit and defines the first

bit of the Control-Byte. A conversion starts on the falling

edge of SCLK, after the seventh bit of the Control-Byte

(the P1 bit) is clocked into DIN. The start bit is defined

as:

Initiate calibration by setting M1 = 0 and M0 = 1 in the

Control-Byte. In internal clock mode, SSTRB goes low

at the beginning of calibration and goes high to signal

the end of calibration, approximately 80,000 clock

cycles later. In external clock mode, SSTRB goes high

at the beginning of calibration and goes low to signal

the end of calibration. Calibration should be performed

in the same clock mode as will be used for conversions

(Figure 6).

The first high bit clocked into DIN with CS low, any-

time the converter is idle, e.g. after AV

is applied,

DD

or as the first high bit clocked into DIN after CS is

pulsed high, then low.

OR

If a falling edge on CS forces a start bit before the

conversion or calibration is complete, then the cur-

rent operation will be terminated and a new one

started.

Reference

The MAX1142/MAX1143 can be used with an internal or

external reference. An external reference can be con-

nected directly at the REF pin or at the REFADJ pin.

CREF is an internal reference node and must be

bypassed with a 1µF capacitor when using either the

internal or an external reference.

Applications Information

Power-On Reset

When power is first applied to the MAX1142/MAX1143

or if RST is pulsed low, the internal calibration registers

are set to their default values. The user-programmable

registers (P0, P1 and P2) are low, and the device is

configured for bipolar mode with internal clocking.

Internal Reference

When using the MAX1142/MAX1143’s internal refer-

ence, place a 0.22µF ceramic capacitor from REFADJ

to AGND and place a 2.2µF capacitor from REF to

AGND. Fine adjustments can be made to the internal

reference voltage by sinking or sourcing current at

REFADJ. The input impedance of REFADJ is nominally

9kΩ. The internal reference voltage is adjustable to

1.5% with the circuit of Figure 7.

Calibration

To compensate the MAX1142/MAX1143 for tempera-

ture drift and other variations, they should be periodi-

cally calibrated. After any change in ambient

temperature more than 10°C, the device should be

recalibrated. A 100mV change in supply voltage or any

change in the reference voltage should be followed by

a calibration. Calibration corrects for errors in gain, off-

set, integral nonlinearity and differential nonlinearity.

CS

t

STR

SDV

SSTRB

t

SSTRB

SCLK

P1 CLOCKED IN

Figure 6. External Clock Mode SSTRB Detailed Timing

______________________________________________________________________________________ 13

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

External reference

An external reference can be placed at either the input

+5V

(REFADJ) or the output (REF) of the MAX1142/

MAX1142

REFADJ

MAX1143’s internal buffer amplifier.

510kΩ

100kΩ

When connecting an external reference to REFADJ, the

input impedance is typically 9kΩ. Using the buffered

REFADJ input makes buffering of the external reference

unnecessary. The internal buffer output must be

bypassed at REF with a 2.2µF capacitor.

0.22µF

24kΩ

When connecting an external reference at REF,

REFADJ must be connected to AV . The input imped-

DD

Figure 7. MAX1142 Reference-Adjust Circuit

ance at REF is 16kΩ for DC currents. During conver-

sion, an external reference at REF must deliver 250µA

DC load current and have an output impedance of 10Ω

or less. If the reference has a higher output impedance

or is noisy, bypass it at the REF pin with a 4.7µF capac-

itor.

MAX1143. Unipolar and bipolar mode is programmed

with the UNI/BIP bit of the Control-Byte. When using a

reference other than the MAX1142/MAX1143’s internal

+4.096V reference, the full-scale input range will vary

accordingly. The full-scale input range depends on the

voltage at REF and the sampling mode selected (Tables

3 and 4).

2/MAX143

Analog Input

The MAX1142/MAX1143 use a capacitive DAC that

provides an inherent track/hold function. Drive AIN with

a source impedance less than 10Ω. Any signal condi-

tioning circuitry must settle with 16-bit accuracy in less

than 500ns. Limit the input bandwidth to less than half

the sampling frequency to eliminate aliasing. The

MAX1142/MAX1143 has a complex input impedance

which varies from unipolar to bipolar mode (Figure 1).

Input Acquisition and Settling

Clocking-in a Control-Byte starts input acquisition. In

bipolar mode, the main capacitor array starts acquiring

the input as soon as a start bit is recognized. If unipolar

mode is selected by the second DIN bit, the part will

immediately switch to unipolar sampling mode and

acquire a sample.

Input Range

The analog input range in unipolar mode is 0 to +12V

for the MAX1142, and 0 to +4.096V for the MAX1143. In

bipolar mode, the analog input can be -12V to +12V for

the MAX1142, and -4.096V to +4.096V for the

Acquisition can be extended by eight clock cycles by

setting M1 = 1, M0 = 1 (long acquisition mode). The

sampling instant in short acquisition completes on the

falling edge of the sixth clock cycle after the start bit

(Figure 2).

Table 3. Unipolar Full Scale and Zero Scale

PART

REFERENCE

Internal

ZERO SCALE

FULL SCALE

0

+12V

MAX1142

External

+12(V

/4.096)

REF

Internal

+4.096V

+V

MAX1143

External

REF

Table 4. Bipolar Full Scale, Zero Scale, and Negative Scale

NEGATIVE FULL

PART

REFERENCE

ZERO SCALE

FULL SCALE

SCALE

Internal

External

Internal

External

-12V

0

+12V

MAX1142

MAX1143

-12(V

/4.096)

+12(V

/4.096)

REF

-4.096V

+4.096V

+V

-V

REF

14 ______________________________________________________________________________________

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

2/MAX143

Acquisition is 5.5 clock cycles in short acquisition

510Ω

mode and 13.5 clock cycles in long acquisition mode.

Short acquisition mode is 24 clock cycles per conver-

sion. Using the external clock to run the conversion

process limits unipolar conversion speed to 125ksps

instead of 200ksps in bipolar mode. The input resis-

tance in unipolar mode is larger than that of bipolar

mode (Figure1). The RC time constant in unipolar mode

is larger than that of bipolar mode, reducing the maxi-

mum conversion rate in 24 external clock mode. Long

acquisition mode with external clock allows both unipo-

lar and bipolar sampling of 150ksps (4.8MHz/32 clock

cycles) by adding eight extra clock cycles to the con-

version.

+5V

0.1µF

2

3

7

22Ω

6

AIN

MAX410

IN

4

0.1µF

Most applications require an input buffer amplifier. If

the input signal is multiplexed, the input channel should

be switched immediately after acquision, rather than

near the end of or after a conversion. This allows more

time for the input buffer amplifier to respond to a large

step change in input signal. The input amplifier must

have a high enough slew-rate to complete the required

output voltage change before the beginning of the

acquisition time. At the beginning of acquisition, the

capacitive DAC is connected to the amplifier output,

causing some output disturbance. Ensure that the sam-

pled voltage has settled to within the required limits

before the end of the acquisition time. If the frequency

of interest is low, AIN can be bypassed with a large

enough capacitor to charge the capacitive DAC with

very little change in voltage. However, for AC use, AIN

must be driven by a wideband buffer (at least 10MHz),

which must be stable with the DAC’s capacitive load (in

parallel with any AIN bypass capacitor used) and also

settle quickly (Figures 8 or 9).

-5V

Figure 9. 5V Buffer for AC/DC Use has 3.5V Swing

Digital Noise

Digital noise can couple to AIN and REF. The conver-

sion clock (SCLK) and other digital signals that are

active during input acquisition, contribute noise to the

conversion result. If the noise signal is synchronous to

the sampling interval, an effective input offset is pro-

duced. Asynchronous signals produce random noise

on the input, whose high-frequency components may

be aliased into the frequency band of interest. Minimize

noise by presenting a low impedance (at the frequen-

cies contained in the noise signal) at the inputs. This

requires bypassing AIN to AGND, or buffering the input

with an amplifier that has a small-signal bandwidth of

several MHz, or preferably both. AIN has a bandwidth

of about 4MHz.

1kΩ

+15V

0.1µF

1000pF

2

3

7

4

6

AIN

MAX427

20Ω

IN

0.0033µF

0.1µF

-15V

Figure 8. AIN Buffer for AC/DC Use

______________________________________________________________________________________ 15

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

Offsets resulting from synchronous noise (such as the

conversion clock) are canceled by the MAX1142/

MAX1143’s calibration scheme. The magnitude of the

offset produced by a synchronous signal depends on

the signal’s shape. Recalibration may be appropriate if

the shape or relative timing of the clock or other digital

signals change, as might occur if more than one clock

signal or frequency is used.

which it will be used to do conversions. The part will

remain in calibration mode for approximately 80,000

clock cycles, unless the calibration is aborted.

Calibration is halted if RST or SHDN goes low, or if a

valid start condition occurs.

Software Shut-Down

A software power-down is initiated by setting M1 = 1,

M0 = 0. After the conversion completes, the part shuts

down. It reawakens upon receiving a new start bit.

Conversions initiated with M1 = 1 and M0 = 0 (shut-

down) use the acquisition mode selected for the previ-

ous conversion.

Distortion

Avoid degrading dynamic performance by choosing an

amplifier with distortion much less than the MAX1142/

MAX1143’s THD (-88dB) at frequencies of interest. If

the chosen amplifier has insufficient common-mode

rejection, which results in degraded THD performance,

use the inverting configuration to eliminate errors from

common-mode voltage. Low temperature-coefficient

resistors reduce linearity errors caused by resistance

changes due to self-heating. To reduce linearity errors

due to finite amplifier gain, use an amplifier circuit with

sufficient loop gain at the frequencies of interest.

Shutdown Mode

The MAX1142/MAX1143 may be shut down by pulling

SHDN low or by asserting software shutdown. In addi-

tion to lowering power dissipation to 13µW, consider-

able power can be saved by shutting down the

converter for short periods between conversions.

Duration will be affected by REF startup time with inter-

nal reference. There is no need to perform a calibration

after the converter has been shut down, unless the time

in shutdown is long enough that the supply voltage or

ambient temperature may have changed.

2/MAX143

DC Accuracy

If DC accuracy is important, choose a buffer with an

offset much less than the MAX1142/MAX1143’s maxi-

mum offset ( 6mV), or whose offset can be trimmed

while maintaining good stability over the required tem-

perature range.

Supplies, Layout, Grounding

and Bypassing

For best system performance, use separate analog and

digital ground planes. The two ground planes should

be tied together at the MAX1142/MAX1143. Use pins 3

and 14 as the primary AGND and DGND, respectively.

If the analog and digital supplies come from the same

source, isolate the digital supply from the analog with a

low value resistor (10Ω).

Operating Modes and Serial Interfaces

The MAX1142/MAX1143 are fully compatible with

MICROWIRE and SPI/QSPI devices. MICROWIRE and

SPI/QSPI both transmit a byte and receive a byte at the

same time. The simple software interface requires only

three 8-bit transfers to perform a conversion, one 8-bit

transfer to configure the ADC, and two more 8-bit trans-

fers to clock out the 14-bit conversion result.

The MAX1142/MAX1143 are not sensitive to the order

of AV

and DV

sequencing. Either supply can be

DD

present in the absence of the other. Do not apply an

external reference voltage until after both AV and

Mode 1 Short Acquisition Mode (24 SCLK)

Configure short acquisition by setting M1 = 0 and M0 =

0. In short acquisition mode, the acquisition time is 5.5

clock cycles. The total period is 24-clock cycles per

conversion.

DD

DV

are present.

DD

Be sure that digital return currents do not pass through

the analog ground. All return current paths must be

low-impedance. A 5mA current flowing through a PC

board ground trace impedance of only 0.05Ω, creates

an error voltage of about 250µV, or about 2LSBs error

with a 4V full-scale system. The board layout should

ensure that the digital and analog signal lines are kept

separate. Do not run analog and digital lines parallel to

one another. If you must cross one with the other, do so

at right angles.

Mode 2 Long Acquisition Mode (32 SCLK)

Configure long acquisition by setting M1 = 1 and M0 =

1. In long acquisition mode, the acquisition time is 13.5

clock cycles. The total period is 32 clock cycles per

conversion.

Calibration Mode

A calibration is initiated through the serial interface by

setting M1 = 0, M0 = 1. Calibration can be done in

either internal or external clock mode, though it is desir-

able that the part be calibrated in the same mode in

The ADC is sensitive to high-frequency noise on the

AV

power supply. Bypass this supply to the analog

DD

ground plane with 0.1µF. If the main supply is not ade-

16 ______________________________________________________________________________________

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

2/MAX143

quately bypassed, add an additional 1µF or 10µF low-

ESR capacitor in parallel with the primary bypass

capacitor.

Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values

on an actual transfer function from a straight line. This

straight-line can be either a best straight-line fit or a line

drawn between the end points of the transfer function,

once offset and gain errors have been nullified. INL for

the MAX1142/MAX1143 is measured using the end-

point method.

Transfer Function

Figures 10 and 11 show the MAX1142/MAX1143’s

transfer functions. In unipolar mode, the output data is

in binary format and in bipolar mode, it is two’s comple-

ment format.

OUTPUT CODE

FULL-SCALE

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between

an actual step width and the ideal value of 1LSB. A

DNL error specification of less than 1LSB guarantees

no missing codes and a monotonic transfer function.

TRANSITION

11 . . . 111

11 . . . 110

11 . . . 101

Aperture Jitter

Aperture jitter (t ) is the sample-to-sample variation in

AJ

FS = +4.096V

1LSB = FS

16384

the time between the samples.

Aperture Delay

Aperture delay (t ) is the time between the rising

AD

00 . . . 011

00 . . . 010

edge of the sampling clock and the instant when an

actual sample is taken.

00 . . . 001

00 . . . 000

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital

samples, signal-to-noise ratio (SNR) is the ratio of full-

scale analog input (RMS value) to the RMS quantization

error (residual error). The ideal, theoretical, minimum

analog-to-digital noise is caused by quantization error

only and results directly from the ADC’s resolution

(N-bits):

0

1

2

3

FS

FS - 3/2LSB

INPUT VOLTAGE (LSBs)

Figure 10. MAX1143 Unipolar Transfer Function, 4.096V = Full-

Scale

OUTPUT CODE

+FS = +4.096V

SNR = (6.02 ✕ N + 1.76)dB

In reality, there are other noise sources besides quanti-

zation noise, including thermal noise, reference noise,

clock jitter, etc. Therefore, SNR is calculated by taking

the ratio of the RMS signal to the RMS noise, which

includes all spectral components minus the fundamen-

tal, the first five harmonics and the DC offset.

011 . . . 111

-FS = -4.096V

011 . . . 110

1LSB = 8.192

000 . . . 010

16384

000 . . . 001

000 . . . 000

Signal-to-Noise Plus Distortion

Signal-to-noise plus distortion (SINAD) is the ratio of the

fundamental input frequency’s RMS amplitude to the

RMS equivalent of all other ADC output signals:

111 . . . 111

111 . . . 110

111 . . . 101

SINAD (dB) = 20 ✕ log (Signal

/Noise

)

RMS

100 . . . 001

100 . . . 000

0V

-FS

+FS - 1LSB

INPUT VOLTAGE (LSBs)

Figure 11. MAX1143 Bipolar Transfer Function, 4.096V = Full-

Scale

___________________________________________________ 17

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

Effective Number of Bits

Typical Application Circuit

Effective number of bits (ENOB) indicates the global

accuracy of an ADC at a specific input frequency and

sampling rate. An ideal ADC’s error consists of quanti-

zation noise only. With an input range equal to the full-

scale range of the ADC, calculate the effective number

of bits as follows:

+5V

0.1µF

AV

DD

ENOB = (SINAD - 1.76) / 6.02

SHDN

+5V

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS

sum of the first five harmonics of the input signal to the

fundamental itself. This is expressed as:

DV

DD

MAX1142

MAX1143

0.1µF

AIN

TO DGND

MC68HCXX

I/O

CS

SCLK

DIN

DOUT

RST

SCLK

MOSI

MISO

2

THD= 20 × log

V₂+ V₃+ V₄+ V₅/ V

1

CREF

REF

I/O

SSTRB

where V is the fundamental amplitude, and V through

1

2

REFADJ

1µF

2.2µF

0.22µF

2/MAX143

V

are the amplitudes of the 2nd- through 5th-order

harmonics.

5

DGND AGND

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of RMS

amplitude of the fundamental (maximum signal compo-

nent), to the RMS value of the next largest distortion

component.

Ordering Information (continued)

PIN-

INL

PART

TEMP. RANGE

PACKAGE

(LSB)

MAX1142AEAP

MAX1142BEAP

MAX1143ACAP*

MAX1143BCAP*

MAX1143AEAP*

MAX1143BEAP*

-40°C to +85°C

0°C to +70°C

20 SSOP

±1

±2

±1

±2

±1

±2

Chip Information

TRANSISTOR COUNT: 21,807

PROCESS : BiCMOS

0°C to +70°C

-40°C to +85°C

*Future product—contact factory for availability.

18 ______________________________________________________________________________________

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

2/MAX143

Functional Diagram

AV

DD

AGND

9kΩ

MAX1142

MAX1143

CREF

REFERENCE

REFADJ

REF

AIN

INPUT

DAC

COMPARATOR

SCALING

NETWORK

ANALOG TIMING CONTROL

DV

DD

SSTRB

DOUT

DGND

CS

SERIAL

OUTPUT

PORT

SERIAL

INPUT

PORT

P2

MEMORY

CALIBRATION

ENGINE

SCLK

P1

P0

DIN

RST

CLOCK

GENERATOR

CONTROL

SHDN

______________________________________________________________________________________ 19

14-Bit ADC, 200ksps, +5V Single-Supply

with Reference

Package Information

2/MAX143

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX1143BCAP-T
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	ADC, Successive Approximation, 14-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO20, 5.30 MM, 0.65 MM PITCH, SSOP-20 信息通信管理光电二极管转换器
文件：	总20页 (文件大小：1314K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX1143BCAP-T [MAXIM]

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MAX1144

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MAX1144ACAP

MAX1144ACAP+T

MAX1144ACAP-T

MAX1144AEAP

MAX1144AEAP+

MAX1144AEAP+T

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MAX1144BCAP+

MAX1144BCAP+T

MAX1144BCAP-T