MAX111ACAP-T [MAXIM]
ADC, Delta-Sigma, 14-Bit, 1 Func, 2 Channel, Serial Access, PDSO20, 5.30 MM, 0.65 MM PITCH, SSOP-20;
| 型号： | MAX111ACAP-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Delta-Sigma, 14-Bit, 1 Func, 2 Channel, Serial Access, PDSO20, 5.30 MM, 0.65 MM PITCH, SSOP-20 光电二极管 转换器 |
| 文件： | 总24页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0283; Rev 5; 11/98
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
0/MAX1
Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ Single +5V Supply (MAX111)
The MAX110/MAX111 a na log -to-d ig ita l c onve rte rs
(ADCs) use an internal auto-calibration technique to
achieve 14-bit resolution plus overrange, with no exter-
na l c omp one nts . Op e ra ting s up p ly c urre nt is only
550µA (MAX110) and reduces to 4µA in power-down
mode, making these ADCs ideal for high-resolution bat-
tery-powered or remote-sensing applications. A fast
serial interface simplifies signal routing and opto-isola-
tion, saves microcontroller pins, and offers compatibility
with SPI™, QSPI™, and MICROWIRE™. The MAX110
operates with ±5V supplies, and converts differential
analog signals in the -3V to +3V range. The MAX111
operates with a single +5V supply and converts differ-
ential analog signals in the ±1.5V range, or single-
ended signals in the 0V to +1.5V range.
♦ Two Differential Input Channels
♦ 14-Bit Resolution Plus Sign and Overrange
♦ 0.03% Linearity (MAX110)
0.05% Linearity (MAX111)
♦ Low Power Consumption:
550µA (MAX110)
640µA (MAX111)
4µA Shutdown Current
♦ Up to 50 Conversions/sec
♦ 50Hz/60Hz Rejection
♦ Auto-Calibration Mode
♦ No External Components Required
♦ 16-Pin DIP/SO, 20-Pin SSOP
Internal calibration allows for both offset and gain-error
correction under microprocessor (µP) control. Both
devices are available in space-saving 16-pin DIP and
SO packages, as well as an even smaller 20-pin SSOP
package.
Ord e rin g In fo rm a t io n
PART
TEMP. RANGE PIN-PACKAGE INL(%)
MAX110ACPE
MAX110BCPE
MAX110ACWE
MAX110BCWE
MAX110ACAP
MAX110BCAP
MAX110BC/D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
16 Plastic DIP
16 Plastic DIP
16 Wide SO
16 Wide SO
20 SSOP
±0.03
±0.05
±0.03
±0.05
±0.03
±0.05
±0.05
________________________Ap p lic a t io n s
Process Control
Weigh Scales
20 SSOP
Panel Meters
Dice*
Data-Acquisition Systems
Temperature Measurement
Ordering Information continued at end of data sheet.
* Contact factory for dice specifications.
P in Co n fig u ra t io n s
Typ ic a l Op e ra t in g Circ u it
+5V
TOP VIEW
IN1+
1
2
3
4
5
6
7
8
16 IN1-
15 IN2+
V
DD
IN1+
RCSEL
REF-
MAX110
MAX111
REF+
14 IN2-
13 (AGND)
IN1-
MAX110
MAX111
V
DD
V
SS
IN2+
IN2-
RCSEL
XCLK
SCLK
BUSY
12 GND
11 DIN
REF+
REF-
10 DOUT
CS
SCLK
9
CS
FROM µC
DIN
V
SS
DIP/SO
DOUT
(AGND)
( ) ARE FOR MAX111
( ) ARE FOR MAX111
-5V (0V)
Pin Configurations continued at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND ...........................................................................+6V
to GND (MAX110)..............................................+0.3V to -6V
16-Pin Wide SO (derate 9.52mW/°C above +70°C) ......762mW
20-Pin SSOP (derate 8.00mW/°C above +70°C) ...........640mW
16-Pin CERDIP (derate 10.00mW/°C above +70°C)......800mW
Operating Temperature Ranges
V
SS
AGND to DGND.....................................................-0.3V to +0.3V
, V ......................................(V + 0.3V) to (V - 0.3V)
V
IN1+ IN1-
DD
SS
V
, V
, V
......................................(V + 0.3V) to (V - 0.3V)
....................................(V + 0.3V) to (V - 0.3V)
MAX11_ _C_ _......................................................0°C to +70°C
MAX11_ _E_ _...................................................-40°C to +85°C
MAX11_BMJE .................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
IN2+ IN2-
DD
SS
V
REF+ REF- DD SS
Digital Inputs and Outputs .........................(V + 0.3V) to -0.3V
Continuous Power Dissipation
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C).....842mW
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX110
(V = 5V ±5%, V = -5V ±5%, f
= 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, V
= 1.5V, V = -1.5V,
REF-
DD
SS
XCLK
REF+
T
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX
A
0/MAX1
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY (Note 1)
14 + POL
+ OFL
Resolution
RES
(Note 2)
Bits
LSB
Bits
Differential Nonlinearity
DNL
(Notes 3, 4)
(Note 3)
±2
No-Missing-Codes
Resolution
13 + POL
+ OFL
-V
≤ V ≤ V
REF
±0.03 ±0.06
±0.015 ±0.03
±0.04
REF
IN
MAX110AC/E
MAX110BC/E
MAX110BM
-0.83 x V
≤ V ≤ 0.83 x V
IN REF
REF
-V
REF
≤ V ≤ V
IN REF
Relative Accuracy
(Notes 3, 5–7)
INL
%FSR
-0.83 x V
≤ V ≤ 0.83 x V
REF
±0.018
±0.1
REF
IN
-V
REF
≤ V ≤ V
IN REF
-0.83 x V
≤ V ≤ 0.83 x V
REF
±0.05
REF
IN
Offset Error
V
IN+
= V = 0V
±4
mV
IN-
After offset null
Uncalibrated
0.003
Offset Error
Temperature Drift
µV/°C
0.02
Common-Mode Rejection
Ratio
CMRR
-2.5V ≤ (V
= V ) ≤ 2.5V
6
ppm/V
%
IN+
IN-
After gain calibration (Note 5)
Uncalibrated
±0.1
0
Full-Scale Error
-8
Full-Scale Error
Temperature Drift
8
ppm/°C
ppm
V
= -5V, V = 4.75V to 5.25V
15
30
SS
DD
Power-Supply Rejection
V
DD
= 5V, V = -4.75V to -5.25V
SS
ANALOG INPUTS
Differential Input Voltage
Range
V
(Note 6)
(Note 3)
-V
+V
REF
V
V
IN
REF
V
SS
+
V
DD
-
Absolute Input Voltage
Range
V
,
IN+
V
IN-
2.25
2.25
500
10
Input Bias Current
Input Capacitance
I
, I
IN+ IN-
nA
pF
2
_______________________________________________________________________________________
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
0/MAX1
ELECTRICAL CHARACTERISTICS—MAX110 (continued)
(V = 5V ±5%, V = -5V ±5%, f
= 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, V
= 1.5V, V = -1.5V,
REF-
DD
SS
XCLK
REF+
T
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE INPUTS
Differential Reference
Input Voltage Range
V
0
3.0
V
V
REF
Absolute Reference Input
Voltage Range
V
,
V
+
V
-
REF+
SS
2.25
DD
V
REF-
2.25
I
I
,
REF+
Reference Input Current
V
= 2.5V, V
= 0V
500
nA
pF
REF+
REF-
REF-
Reference Input
Capacitance
(Note 3)
10
CONVERSION TIME
10,240 clock-cycles/conversion
102,400 clock-cycles/conversion
20.48
Synchronous Conversion
Time (Note 7)
t
ms
CONV
204.80
Oversampling Clock
Frequency
f
(Note 8)
0.25
2.4
1.25
MHz
OSC
DIGITAL INPUTS (CS, SCLK, DIN, and XCLK when RCSEL = 0V)
Input High Voltage
Input Low Voltage
Input Capacitance
Input Leakage Current
V
V
V
IH
V
IL
0.8
10
(Note 3)
pF
µA
I
Digital inputs at 0V or 5V
±1
LKG
DIGITAL OUTPUTS (DOUT, BUSY, and XCLK when RCSEL = V
)
DD
0.4
0.4
DOUT, BUSY, I
= 1.6mA
SINK
Output Low Voltage
V
V
V
OL
XCLK, I
= 200µA
SINK
V
- 0.5
DOUT, BUSY, V = 4.75V, I
= 1.0mA
DD
DD
SOURCE
Output High Voltage
V
OH
V - 0.5
DD
XCLK, V = 4.75V, I
= 200µA
DD
SOURCE
Leakage Current
I
V
= 5V or 0V
±10
10
µA
pF
LKG
OUT
Output Capacitance
(Note 3)
POWER REQUIREMENTS (all digital inputs at 0V or 5V)
Positive Supply Voltage
Negative Supply Voltage
V
Performance guaranteed by supply rejection test
Performance guaranteed by supply rejection test
4.75
5.25
V
V
DD
V
SS
-4.75
-5.25
f
= 500kHz,
XCLK
550
780
320
950
continuous-conversion mode
V
V
SS
= 5.25V,
= -5.25V
DD
Positive Supply Current
I
DD
µA
XCLK unloaded,
continuous-conversion mode, RC
oscillator operational (Note 9)
V
V
SS
= 5.25V,
= -5.25V
f
= 500kHz,
DD
XCLK
Negative Supply Current
Power-Down Current
I
650
µA
µA
SS
continuous-conversion mode
= 5.25V, V = -5.25V, V = 0V, PD = 1
SS XCLK
I
DD
4
10
2
V
DD
I
SS
0.05
_______________________________________________________________________________________
3
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
ELECTRICAL CHARACTERISTICS—MAX111
(V = 5V ±5%, f
= 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, V
= 1.5V, V
= 0V, T = T
to T
,
DD
XCLK
REF+
REF-
A
MIN
MAX
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY (Note 1)
14 + POL
+ OFL
Resolution
RES
(Note 2)
Bits
LSB
Bits
Differential Nonlinearity
DNL
(Notes 3, 4)
(Note 3)
±2
No-Missing-Codes
Resolution
13 + POL
+ OFL
-V
≤ V ≤ V
REF
±0.05 ±0.10
±0.03 ±0.05
±0.18
REF
IN
MAX111AC/E
MAX111BC/E
MAX111BM
MAX111AC/E
MAX111BC/E
MAX111BM
-0.667 x V
≤ V ≤ 0.667 x V
IN REF
REF
Relative Accuracy,
Differential Input
(Notes 3, 5–7)
-V
REF
≤ V ≤ V
IN REF
INL
%FSR
%FSR
-0.667 x V
≤ V ≤ 0.667 x V
REF
±0.10
REF
IN
0/MAX1
-V
REF
≤ V ≤ V
REF
±0.25
IN
-0.667 x V
≤ V ≤ 0.667 x V
REF
±0.20
REF
IN
0V ≤ V ≤ V
±0.1
IN
REF
V
IN
≤ 0.667 x V
±0.06
REF
REF
Relative Accuracy,
Single-Ended Input
(IN- = GND)
0V ≤ V ≤ V
±0.18
IN
INL
V
IN
≤ 0.667 x V
±0.10
REF
REF
0V ≤ V ≤ V
±0.25
IN
V
IN
≤ 0.667 x V
±0.15
REF
Offset Error
V
IN+
= V = 0V
±4
mV
IN-
Common-Mode Rejection
Ratio
CMRR
10mV ≤ (V
= V ) ≤ 2.0V
6
ppm/V
IN+
IN-
After gain calibration (Note 5)
Uncalibrated
±0.2
0
Full-Scale Error
%
-8
Full-Scale Error
Temperature Drift
8
ppm/°C
ppm
Power-Supply Rejection
V
DD
= 4.75V to 5.25V
15
ANALOG INPUTS
Differential Input Voltage
Range
V
(Note 6)
(Note 3)
-V
+V
REF
V
V
IN
REF
Absolute Input Voltage
Range
V
,
IN+
0
V
DD
- 3.2
V
IN-
Input Bias Current
Input Capacitance
I
, I
IN+ IN-
500
10
nA
pF
4
_______________________________________________________________________________________
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
0/MAX1
ELECTRICAL CHARACTERISTICS—MAX111 (continued)
(V = 5V ±5%, f
= 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, V
= 1.5V, V
= 0V, T = T
to T
,
DD
XCLK
REF+
REF-
A
MIN
MAX
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE INPUTS
Differential Reference
Input Voltage Range
V
0
0
1.5
V
V
REF
Absolute Reference Input
Voltage Range
V
,
REF+
V
- 3.2
DD
V
REF-
I
I
,
REF+
Reference Input Current
V
= 1.5V, V
= 0V
500
10
nA
pF
REF+
REF-
REF-
Reference Input
Capacitance
(Note 3)
CONVERSION TIME
10,240 clock-cycles/conversion
102,400 clock-cycles/conversion
20.48
204.80
Synchronous Conversion
Time (Note 7)
t
ms
CONV
Oversampling Clock
Frequency
f
(Note 8)
0.25
2.4
1.25
MHz
OSC
DIGITAL INPUTS (CS, SCLK, DIN, and XCLK when RCSEL = 0V)
Input High Voltage
Input Low Voltage
Input Capacitance
Input Leakage Current
V
V
V
IH
V
IL
0.8
10
(Note 3)
pF
µA
I
Digital inputs at 0V or 5V
±1
LKG
DIGITAL OUTPUTS (DOUT, BUSY, and XCLK when RCSEL = V
)
DD
0.4
0.4
DOUT, BUSY, I
= 1.6mA
SINK
Output Low Voltage
V
V
V
OL
XCLK, I
= 200µA
SINK
V
- 0.5
DOUT, BUSY, V = 4.75V, I
= 1.0mA
DD
DD
SOURCE
Output High Voltage
V
OH
V - 0.5
DD
XCLK, V = 4.75V, I
= 200µA
DD
SOURCE
Leakage Current
I
V
= 5V or 0V
±1
10
µA
pF
LKG
OUT
Output Capacitance
(Note 3)
POWER REQUIREMENTS (all digital inputs at 0V or 5V)
Positive Supply Voltage
V
DD
Performance guaranteed by supply rejection test
4.75
5.25
V
f
= 500kHz,
XCLK
640
1200
continuous-conversion mode
Supply Current
I
V
= 5.25V
µA
µA
DD
DD
XCLK unloaded,
continuous-conversion mode, RC
oscillator operational (Note 9)
960
4
Power-Down Current
I
DD
V
DD
= 5.25V, V = 0V, PD = 1
XCLK
10
_______________________________________________________________________________________
5
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
Note 1: These specifications apply after auto-null and gain calibration. Performance at power-supply tolerance limits is guaranteed
by power-supply rejection tests. Tests are performed at V = 5V and V = -5V (MAX110).
DD
SS
Note 2: 32,768 LSBs cover an input voltage range of ±V
(15 bits). An additional bit (OFL) is set for V > V
.
REF
IN
REF
Note 3: Guaranteed by design. Not subject to production testing.
Note 4: DNL is less than ±2 counts (LSBs) out of 215 counts (±14 bits). The major source of DNL is noise, and this can be further
improved by averaging.
Note 5: See 3-Step Calibration section in text.
Note 6:
V
REF
= (V
- V
), V = (V
- V
) or (V
- V
). The voltage is interpreted as negative when the voltage at
REF+
REF-
IN
IN1+
IN1-
IN2+
IN2-
the negative input terminal exceeds the voltage at the positive input terminal.
Note 7: Conversion time is set by control bits CONV1–CONV4.
Note 8: Tested at clock frequency of 1MHz with the divide-by-2 mode (i.e. oversampling clock of 500kHz). See Typical Operating
Characteristics section for the effect of other clock frequencies. Also read the Clock Frequency section.
Note 9: This current depends strongly on C
(see Applications Information section).
XCLK
TIMING CHARACTERISTICS (see Figure 6)
(V = 5V, V = -5V (MAX110), T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD
SS
A
MIN
0/MAX1
PARAMETER
SYMBOL
CONDITIONS
MIN
60
TYP
MAX
UNITS
T
= +25°C
A
CS to SCLK Setup Time
(Note 10)
t
MAX11_ _C/E
MAX11_ BM
80
ns
CSS
100
CS to SCLK Hold Time
(Note 10)
t
0
ns
ns
ns
ns
CSH
T
= +25°C
60
80
A
DIN to SCLK Setup Time
(Note 10)
t
DS
MAX11_ _C/E
MAX11_ BM
100
DIN to SCLK Hold Time
(Note 10)
t
0
DH
T
A
= +25°C
100
120
160
0
SCLK, XCLK Pulse Width
(Note 10)
t
MAX11_ _C/E
MAX11_ BM
CK
DA
DO
T
= +25°C
35
60
80
A
Data Access Time
(Note 10)
t
C
C
= 50pF
= 50pF
MAX11_ _C/E
MAX11_ BM
0
100
120
100
120
140
80
ns
LOAD
LOAD
0
T
A
= +25°C
0
SCLK to DOUT Valid
Delay (Note 10)
t
MAX11_ _C/E
MAX11_ BM
0
ns
ns
0
T
A
= +25°C
35
Bus Relinquish Time
(Note 10)
t
DH
MAX11_ _C/E/M
= +25°C
120
T
2.0
A
RC Oscillator Frequency
MHz
MAX11_ _C/E
MAX11_ BM
1.3
1.1
2.8
3.0
Note 10: Timing specifications are guaranteed by design. All input control signals are specified with t = t = 5ns
r
f
(10% to 90% of +5V) and timed from a +1.6V voltage level.
6
_______________________________________________________________________________________
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
0/MAX1
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(MAX110, V = 5V, V = -5V, V
= 1.5V, V
= -1.5V, differential input (V
= -V ), f
= 1MHz, ÷ 2 mode (DV2 = 1),
DD
SS
REF+
REF-
IN+
IN- XCLK
81,920 clocks/conv, T = +25°C, unless otherwise noted.)
A
MAX110 RELATIVE ACCURACY
MAX110 RELATIVE ACCURACY
(-V < V < V
(-0.83 V < V < 0.83 V
)
)
REF
REF
IN
REF
REF
IN
0.10
0.10
0.05
0
-40°C ≤ T ≤ +85°C
-40°C ≤ T ≤ +85°C
RANGE OF INL VALUES
(200 PIECE SAMPLE SIZE)
A
A
RANGE OF INL VALUES
(200 PIECE SAMPLE SIZE)
0.05
0
-0.05
-0.10
-0.05
-0.10
-4
-2
0
2
4
-4
-2
0
2
4
V
IN
(V)
V
IN
(V)
MAX110 RELATIVE ACCURACY vs.
OVERSAMPLING FREQUENCY (f
MAX110 RELATIVE ACCURACY
vs. TEMPERATURE
)
OSC
0.07
0.06
0.10
0.08
0.06
0.04
V
DD
= 4.75V
V
SS
= -4.75V
T = +85°C
A
0.05
0.04
0.03
0.02
0.01
0
÷1 MODE
÷2 MODE
0.02
0
÷ 4 MODE
0
0.25
0.50
0.75
(MHz)
1.00
1.25
-25
-50
0
25
50
75
100
f
TEMPERATURE (°C)
OSC
MAX110 POWER DISSIPATION vs.
OVERSAMPLING FREQUENCY (f
)
OSC
8
7
V
= 5.25V
= 0V
DD
V
IN
T = -40°C
A
6
5
4
÷ 4 MODE
÷ 2 MODE
÷ 1 MODE
3
2
0
0.25
0.50
0.75
(MHz)
1.00
1.25
f
OSC
_______________________________________________________________________________________
7
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(MAX111, V = 5V, V
= 1.5V, V
= 0V, differential input (V
= -V ), f = 1MHz, ÷ 2 mode (DV2 = 1),
IN- XCLK
DD
REF+
REF-
IN+
81,920 clocks/conv, T = +25°C, unless otherwise noted.)
A
MAX111 RELATIVE ACCURACY
MAX111 RELATIVE ACCURACY
(-V < V < V
)
(-0.667V < V < 0.667V )
REF
REF
IN
REF
REF
IN
0.10
0.05
0.10
0.05
0
0
-0.05
-0.05
0/MAX1
-0.10
-0.10
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
V
IN
(V)
V
IN
(V)
MAX111 RELATIVE ACCURACY
vs. TEMPERATURE
MAX111 RELATIVE ACCURACY vs.
OVERSAMPLING FREQUENCY (f
)
OSC
0.14
0.10
V
= 4.75V
= +85°C
DD
T
0.12
A
0.08
0.06
0.04
0.1
0.08
0.06
0.04
0.02
0
÷ 1 MODE
÷2 MODE
÷4 MODE
0.02
0
-25
0
0.25
0.50
1.00
-50
0
25
50
75
100
0.75
f
(MHz)
TEMPERATURE (°C)
OSC
MAX111 POWER DISSIPATION vs.
OVERSAMPLING FREQUENCY (f
)
OSC
7
6
V
= 5.25V
= 0V
DD
V
IN
T
A
= -40°C
5
4
3
2
1
0
÷ 4 MODE
÷ 2 MODE
÷ 1 MODE
0
0.25
0.50
0.75
1.00
1.25
f
(MHz)
OSC
8
_______________________________________________________________________________________
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
0/MAX1
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
DIP/SO
SSOP
1
2
3
4
1
2
3
6
IN1+
REF-
REF+
Channel 1 Positive Analog Input
Negative Reference Input
Positive Reference Input
V
DD
Positive Power-Supply Input—connect to +5V
RC Select Input. Connect to GND to select external clock mode. Connect to V to
DD
5
6
7
8
RCSEL
XCLK
select RC OSC mode. XCLK must be connected to V or GND through a resistor
(1MΩ or less) when RC OSC mode is selected.
DD
Clock Input / RC Oscillator Output. TTL/CMOS-compatible oversampling clock input
when RCSEL = GND. Connects to the internal RC oscillator when RCSEL = V . XCLK
DD
must be connected to V or GND through a resistor (1MΩ or less) when RC OSC
DD
mode is selected.
7
8
9
SCLK
Serial Clock Input. TTL/CMOS-compatible clock input for serial-interface data I/O.
Busy Output. Goes low at conversion start, and returns high at end of conversion.
10
BUSY
Chip-Select Input. Pull this input low to perform a control-word-write/data-read opera-
tion. A conversion begins when CS returns high, provided NO-OP is a 1. See the sec-
tion Using the MAX110/MAX111 with SPI, QSPI, and MICROWIRE Serial Interfaces.
9
11
CS
10
11
12
12
13
16
DOUT
DIN
Serial Data Output. High-impedance when CS is high.
Serial Data Input. See Control Register section.
GND
Digital Ground
V
MAX110 Negative Power-Supply Input—connect to -5V
MAX111 Analog Ground
SS
13
17
AGND
IN2-
14
15
16
—
18
19
Channel 2 Negative Analog Input
IN2+
IN1-
Channel 2 Positive Analog Input
20
Channel 1 Negative Analog Input
4, 5, 14, 15
N.C.
No Connect—there is no internal connection to this pin
to the ADC. The up/down counter clocks data in from
_______________De t a ile d De s c rip t io n
the comparator at the oversampling clock rate and
averages the pulse-width-modulated (PWM) square
wave to produce the conversion result. A 16-bit static
shift register stores the result at the end of the conver-
sion. Figure 2 shows the ADC waveforms for a differen-
The MAX110/MAX111 ADC c onve rts low-fre q ue nc y
analog signals to a 16-bit serial digital output (14 data
bits, a sign bit, and an overrange bit) using a first-order
sigma-delta loop (Figure 1). The differential input volt-
age is internally connected to a precision voltage-to-
current converter. The resulting current is integrated
and applied to a comparator. The comparator output
then drives an up/down counter and a 1-bit DAC. When
the DAC output is fed back to the integrator input, the
sigma-delta loop is completed.
tia l a na log inp ut e q ua l to 1/2 (V
- V
). The
REF+
REF-
resulting comparator and 1-bit DAC outputs are high
for seven cycles and low for three cycles of the over-
sampling clock.
Since the analog input signal is integrated over many
clock cycles, much of the signal and quantization noise
is attenuated. The more clock cycles allowed during
each conversion, the greater the noise attenuation (see
Programming Conversion Time).
During a conversion, the comparator output is a VREF-
to VREF+ square wave; its duty cycle is proportional to
the magnitude of the differential input voltage applied
_______________________________________________________________________________________
9
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
DIN SCLK CS
DITHER
GENERATOR
IN1+
IN1-
IN+
IN-
INTEGRATOR
IN2+
IN2-
INPUT
MUX
Gm
Gm
Σ
∫
SERIAL
SHIFT
REGISTER
UP/DOWN
COUNTER
DOUT
-
REF+
REF-
16 16
CONTROL
REGISTER
16 16
BUSY
TIMER + CONTROL
LOGIC + CLOCK GENERATOR
RCSEL
OSC
A
DIVIDER
NETWORK,
DIVIDE BY
1, 2, OR 4
XCLK
MAX110
MAX111
RC
OSCILLATOR
Figure 1. Functional Diagram
Ove rs a m p lin g Clo c k
XCLK internally connects to a clock-frequency divider
network, whose output is the ADC oversampling clock,
V
V
REF+
DC LEVEL AT 1/2 V
REF
DIFFERENTIAL
ANALOG
f
. This allows the selected clock source (internal RC
OSC
os c illa tor or e xte rna l c loc k a p p lie d to XCLK) to b e
divided by one, two, or four (see Clock Divider-Ratio
Control Bits).
INPUT
REF-
Figure 3 shows the two methods for providing the over-
sampling clock to the MAX110/MAX111. In external-
clock mode (Figure 3a), the internal RC oscillator is
disabled and XCLK accepts a TTL/CMOS-level clock to
provide the oversampling clock to the ADC.
V
REF+
OUTPUT FROM
1-BIT DAC
V
REF-
Select external-clock mode (Figure 3a) by connecting
RCSEL to GND and a TTL/CMOS-compatible clock to
XCLK (s e e Se le c ting the Ove rs a mp ling Cloc k
Frequency).
OVERSAMPLING
CLOCK
In RC-oscillator mode (Figure 3b), the internal RC oscil-
lator is active and its output is connected to XCLK
(Figure 1). Select RC-oscillator mode by connecting
MAX110
MAX111
RCSEL to V . This enables the internal oscillator and
DD
Figure 2. ADC Waveforms During a Conversion
connects it to XCLK for use by the ADC and external
system components. Minimize the capacitive loading on
XCLK when using the internal RC oscillator.
10 ______________________________________________________________________________________
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
0/MAX1
+5V
+5V
V
DD
V
DD
RCSEL
RCSEL
MAX110
MAX111
MAX110
MAX111
+5V
GND
GND
TTL/CMOS
1MΩ
XCLK
XCLK
V
(AGND)
SS
V
(AGND)
SS
-5V (0V)
( ) ARE FOR MAX111.
-5V (0V)
( ) ARE FOR MAX111.
Figure 3b. Connection for Internal RC-Oscillator Mode—XCLK
connects to the internal RC oscillator. Note, the pull-up resistor
is not necessary if the internal oscillator is never shut down.
Figure 3a. Connection for External-Clock Mode
properly if the reference voltage remains within the rec-
ommended voltage range (see Reference Inputs). If the
reference voltage exceeds the recommended input
range, the overrange bit may not operate properly.
ADC Op e ra t io n
The output data from the MAX110/MAX111 is arranged
in twos-complement format (Figures 4, 5). The sign bit
(POL) is shifted out first, followed by the overrange bit
(OR), and the 14 data bits (MSB first) (see Figure 6).
The MAX110 operates from ±5V power supplies and
c onve rts low-fre q ue nc y a na log s ig na ls in the ± 3V
range when using the maximum reference voltage of
). Within the ±3V input
range, greater accuracy is obtained within ±2.5V (see
Electrical Characteristics for details). Note that a nega-
Dig it a l In t e rfa c e —S t a rt in g a Co n ve rs io n
Data is transferred into and out of the serial I/O shift
register by pulling CS low and applying a serial clock
at SCLK. This fully static shift register allows SCLK to
range from DC to 2MHz. Output data from the ADC is
clocked out on SCLK’s falling edge and should be read
on SCLK’s rising edge. Input data to the ADC at DIN is
clocked in on SCLK’s rising edge. A new conversion
begins when CS returns high, provided the MSB in the
inp ut c ontrol word (NO-OP) is a 1 (s e e Us ing the
MAX110/MAX111 with MICROWIRE, SPI, and QSPI
Serial Interfaces). Figure 6 shows the detailed serial-
interface timing diagram.
V
= 3V (V
= V
- V
REF
REF
REF+
REF-
tive input voltage is defined as V
> V . For the
IN-
IN+
MAX110, the absolute voltage at any analog input pin
must remain within the (V + 2.25V) to (V - 2.25V)
SS
DD
range.
The MAX111 operates from a single +5V supply and
converts low-frequency differential analog signals in the
±1.5V range when using the maximum reference volt-
= 1.5V. As ind ic a te d in the Ele c tric a l
Characteristics, greater accuracy is achieved within the
±1.2V range. The absolute voltage at any analog input
CS must remain high during the conversion (while
BUSY remains low). Bringing CS low during the conver-
s ion c a us e s the ADC to s top c onve rting , a nd ma y
result in erroneous output data.
a g e of V
REF
pin for the MAX111 must remain within 0V to V - 3.2V.
DD
When V > V
the input is interpreted as negative.
IN-
IN+
Using the MAX110/MAX111 with SPI, QSPI, and
MICROWIRE Serial Interfaces
Figure 7 shows the most common serial-interface con-
nections. The MAX110/MAX111 are compatible with
SPI, QSPI (CPHA = 0, CPOL = 0), and MICROWIRE
serial-interface standards.
The overrange bit (OFL) is provided to sense when the
input voltage level has exceeded the reference voltage
level. The converter does not “saturate” until the input
voltage is typically 20% larger. The linearity is not guar-
anteed in this range. Note that the overrange bit works
______________________________________________________________________________________ 11
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
OUTPUT
CODE
+OVERFLOW
TRANSITION
POL OFL D13...D0
0
0
0
0
0
1
0
0
0
0
00 . . .000
+OVERFLOW
11 . . .111
11 . . .110
11 . . .101
11 . . .100
0
0
0
1
1
0
0
0
1
1
00 . . .001
00 . . .001
00 . . .000
11 . . .111
11 . . .110
-OVERFLOW
TRANSITION
0/MAX1
1
1
1
1
1
1
1
1
1
0
00 . . .011
00 . . .010
00 . . .001
00 . . .000
11 . . .111
-OVERFLOW
- V
REF
V
REF
-1LSB
INPUT VOLTAGE (LSBs)
Figure 4. Differential Transfer Function
OUTPUT
CODE
POL OFL D13...D0
OVERFLOW
TRANSITION
0
0
0
0
0
1
0
0
0
0
00 . . .000
11 . . .111
11 . . .110
11 . . .101
11 . . .100
+OVERFLOW
0
0
0
0
1
0
0
0
0
1
00 . . .011
00 . . .010
00 . . .001
00 . . .000
11 . . .111
0
1
2
3
V
REF
-1LSB
INPUT VOLTAGE (LSBs)
Figure 5. Unipolar Transfer Function
12 ______________________________________________________________________________________
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
0/MAX1
CS
t
t
CK
CSH
t
CSS
SCLK
DIN
t
CK
t
DH
t
DS
MSB
LSB
t
DO
t
DH
t
DA
DOUT
BUSY
POL
OFL
MSB
DO
END OF
CONVERSION
START OF
CONVERSION
Figure 6. Detailed Serial-Interface Timing
The ADC serial interface operates with just SCLK, DIN,
and DOUT (allow sufficient time for the conversion to
complete between read/write operations). Achieve con-
tinuous operation by connecting BUSY to an uncommit-
ted µP I/O or interrupt, to signal the processor when the
conversion results are ready. Figures 8a and 8b show
the timing for SPI/MICROWIRE and QSPI operation.
+5V
I/O
SCK
MISO
MOSI
CS
SCLK
DOUT
DIN
MAX110
MAX111
µP
SS
MASKABLE
INTERRUPT
BUSY
The fully static 16-bit I/O register allows infinite time
between the two 8-bit read/write operations necessary
to ob ta in the full 16 b its of d a ta with SPI a nd
MICROWIRE. CS must remain low during the entire
two-byte transfer (Figure 8a). QSPI allows a full 16-bit
data transfer (Figure 8b).
a. SPI/QSPI
I/O
SK
SI
SO
CS
SCLK
DOUT
DIN
MAX110
MAX111
µP
Interfacing to the 80C32 Microcontroller Family
Figure 7c shows the general 80C32 connection to the
MAX110/MAX111 using Port 1. For a more detailed dis-
cussion, see the MAX110 evaluation kit manual.
MASKABLE
INTERRUPT or I/O
BUSY
b. MICROWIRE
I/O S h ift Re g is t e r
Serial data transfer is accomplished with a 16-bit fully
static shift register. The 16-bit control word shifted into
this register during a data-transfer operation controls
the ADC’s va rious func tions . The MSB (NO-OP)
enables/disables transfer of the control word within the
ADC. A logic 1 causes the remaining 15 bits in the con-
trol word to be transferred from the I/O register into the
c ontrol re g is te r whe n CS g oe s hig h, up d a ting the
ADC’s configuration and starting a new conversion. If
P1.0
CS
SCLK
DIN
DOUT
BUSY
P1.1
µP
MAX110
MAX111
P1.2
P1.3
P1.4
c. 80C51/80C32
Figure 7. Common Serial-Interface Connections
______________________________________________________________________________________ 13
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
ST
ND
MAX110
MAX111
1
BYTE READ/WRITE
2
BYTE READ/WRITE
BUSY
CS
SCLK
DOUT
0/MAX1
POL
OFL D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DIN
NO OP NU NU CONV4 CONV3 CONV2 CONV1 DV4
DV2
NU NU CHS CAL NUL PDX PD
Figure 8a. SPI/MICROWIRE-Interface Timing
MAX110
MAX111
BUSY
CS
SCLK
DOUT
POL
OFL D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DIN
NO OP NU NU CONV4 CONV3 CONV2 CONV1 DV4 DV2 NU NU CHS CAL NUL PDX PD
Figure 8b. QSPI Serial-Interface Timing
14 ______________________________________________________________________________________
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
0/MAX1
Table 1. Input Control-Word Bit Map
15
NO-OP
↑
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NU
NU CONV4 CONV3 CONV2 CONV1 DV4
DV2
NU
NU
CHS
CAL
NUL
PDX
PD
First bit clocked in.
BIT
NAME
NO-OP
NU
DESCRIPTION
If this bit is a logic high, the remaining 15 LSBs are transferred to the control register and a
new conversion begins when CS returns high. If this bit is set low, the control word is not
passed to the control register, the ADC configuration remains unchanged, and no new con-
version begins when CS returns high.
15
5, 6, 13, 14
Used for test purposes only. Set these bits low.
Conversion Time Control Bits. See Table 4.
9–12
7, 8
CONV1–CONV4
DV2, DV4
XCLK to Oversampling Cock Ratio Control Bits. See Table 5.
Input Channel Select. A logic high selects channel 2 (IN2+ and IN2-), while a logic low
selects channel 1 (IN1+ and IN1-). See Tables 2 and 3.
4
CHS
3
2
1
0
CAL
NUL
PDX
PD
Gain-Calibration Bit. A logic high selects gain-calibration mode. See Table 3.
Internal Offset-Null Bit. A logic high selects offset-null mode. See Table 3.
Oscillator Power-Down. Set this bit high to power down the RC oscillator.
Analog Power-Down. Set this bit high to power down the analog section.
When PDX is set high, the internal RC oscillator stops
shortly after CS returns high. If the next control word
written to the device has NO-OP = 1 instructing the
ADC to convert, BUSY will go low, but because the RC
oscillator is stopped, BUSY will remain low and will not
allow a new conversion to begin. To avoid this situation,
write a “dummy” control word with NO-OP = 0 and any
combination of bits 14-0 in the control word following
the control word with PDX = 0. With NO-OP = 0, bits 14-
0 are ignored and the internal state machine resets.
Next, perform a normal 3-step calibration (see Table 3).
NO-OP is a zero, the control word is not transferred to
the control register, the ADC’s configuration remains
unchanged, and no new conversion is initiated. This
allows specific ADCs in a “daisy chain” arrangement to
b e re c onfig ure d while le a ving the re ma ining ADCs
unchanged. Table 1 lists the various ADC control word
functions.
Output data is shifted out of DOUT at the same time the
input control word for the next conversion is shifted in
(Figure 8).
On p owe r-up , a ll inte rna l re g is te rs re s e t to ze ro.
Therefore, when writing the first control word to the
ADC, the data simultaneously shifted out will be zeros.
The first conversion begins when CS goes high (NO-OP
= 1). The results are placed in the 16-bit I/O register for
access on the next data-transfer operation.
Note that XCLK must be connected to V
or GND
DD
through a resistor (suggested value is 1MΩ) when the
RC oscillator mode is selected (RCSEL = V ). This
DD
resistor is not necessary if the external oscillator mode
is used, or if the internal oscillator is not shut down.
S e le c t in g t h e An a lo g In p u t s
Bit 4 (CHS) controls which of the two differential inputs
connect to the internal ADC inputs (see the Functional
Diagram). A logic high selects IN2+ and IN2- while a
logic low selects IN1+ and IN1-. Table 2 shows the
allowable input multiplexer configurations.
P o w e r-Do w n Mo d e
Bits 0 and 1 control the ADC’s power-down mode. If bit
0 (PD) is a logic high, power is removed from all analog
circuitry except the RC oscillator. A logic high at bit 1
(PDX) removes power from the RC oscillator. If both bits
PD a nd PDX a re a log ic hig h, or if PD is hig h a nd
RCSEL is low, the supply currents reduce to 4µA. If an
external XCLK clock continues to run in power-down
mode, the supply current will depend on the clock rate.
______________________________________________________________________________________ 15
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
Table 2. Allowable Input Multiplexer Configurations
CAL NUL CHS NO-OP ADC IN+ ADC IN-
DESCRIPTION
0
0
0
0
1
0
0
1
1
1
0
1
1
1
1
1
1
IN1+
IN2+
IN1-
IN2-
REF-
IN1-
IN2-
IN1-
IN2-
REF-
Channel 1 connected to ADC inputs. Conversion begins when CS returns high.
Channel 2 connected to ADC inputs. Conversion begins when CS returns high.
IN1- connected to the ADC inputs; offset-null mode selected. Autonull conversion
begins when CS returns high, and the results are stored in the null register.
0
IN2- connected to the ADC inputs; offset-null mode selected. Autonull conversion
begins when CS returns high, and the results are stored in the null register.
1
REF- connected to the ADC inputs; offset-null mode selected. Autonull conversion
begins when CS returns high, and the results are stored in the null register.
X
0/MAX1
REF+ and REF- connected to the ADC inputs; gain-calibration mode
selected. Autocal conversion begins when CS returns high, and the results are
stored in the 16-bit I/O register.
1
0
X
X
1
0
REF+
REF-
Input control word is not transferred to the control register. ADC
configuration remains unchanged and no new conversion starts when CS
returns high.
No
No
X
X
Change Change
X = Don't Care
Table 3. Procedure to Calibrate the ADC
CONTROL WORD
Not CONV1- DV2 & Not
STEP
DESCRIPTION
NO-OP
CHS CAL NUL PDX PD
Used CONV4 DV4 Used
Sets the new conversion speed (if required)
and performs an offset correction conversion
with the internal ADC inputs shorted to REF-.
The result is stored in the null register.
(This step also selects the speed/resolution
for the ADC.)
New
Data
1
1
00
XX
00
X
X
1
1
0
0
Performs a gain-calibration conversion with
the null register contents as the starting value.
The result is stored in the calibration register.
No
Change
2
3
1
1
00
00
XX
XX
00
00
1
0
0
1
0
0
0
0
Performs an offset-null conversion with the
internal ADC inputs shorted to the selected
input channel's negative input (IN1- or IN2-).
The next operation performs the first signal
conversion with the new setup.
0
or
1
No
Change
X = Don't Care
16 ______________________________________________________________________________________
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
0/MAX1
Automatic gain calibration is not allowed in the
102,400 cycles per conversion mode (s e e
Programming Conversion Time). In this mode, calibra-
tion can be achieved by connecting the reference volt-
age to one input channel and performing a normal
conversion. Subsequent conversion results can be cor-
rected by software. Do not issue a NO-OP command
directly following the gain calibration, as the cali-
bration data will be lost.
3 -S t e p Ca lib ra t io n
The data sheet electrical specifications apply to the
device after optional calibration of gain error and offset.
Uncalibrated, the gain error is typically 2%.
Table 3 describes the three steps required to calibrate
the ADC completely.
Once the ADC is calibrated to the selected channel, set
CAL = 0 and NUL = 0 and leave CHS unchanged in the
next control word to perform a signal conversion on the
selected analog input channel.
P ro g ra m m in g Co n ve rs io n Tim e
The MAX110/MAX111 are specified for 12 bits of accu-
racy and up to ±14 bits of resolution. The ADC’s resolu-
tion depends on the number of clock cycles allowed
d uring e a c h c onve rs ion. Control-re g is te r b its 9–12
(CONV1–CONV4) determine the conversion time by
controlling the nominal number of oversampling clock
cycles required for each conversion (OSCC/CONV).
Table 4 lists the available conversion times and result-
ing resolutions.
Calibrate the ADC after the following operations:
— when power is first applied
— if the reference common-mode voltage changes
— if the common-mode voltage of the selected input
channel varies significantly. The CMRR of the analog
inputs is 0.25LSB/V.
— after changing channels (if the common-mode volt-
ages of the two channels are different)
To program a new conversion time, perform a 3-step
calibration with the appropriate CONV1–CONV4 data
used in Table 3. The ADC is now calibrated at the new
conversion speed/resolution.
— after changing conversion speed/resolution.
— after significant changes in temperature. The offset
drift with temperature is typically 0.003µV/°C.
Table 4. Available Conversion Times
CLOCK CYCLES
PER
CONVERSION
NOMINAL CONVERSION TIME
RCSEL = GND, DV2 = DV4 = 0, XCLK = 500kHz
(ms)
CONVERSION
RESOLUTION
(Bits)
CONV4 CONV3 CONV2 CONV1
1
0
0
0
0
0
1
0
0
1
1
0
1
1
0
0
10,240
20,480
20.48
40.96
12 + POL
13 + POL
14 + POL
14 + POL
81,920
163.84
204.80
102,400*
* Gain-calibration mode is not available with 102,400 clock cycles/conversion selected.
Table 5. Clock Divider-Ratio Control
DV2
DV4
DESCRIPTION
XCLK or internal RC oscillator connects directly to the ADC; f
0
0
1
1
0
1
0
1
= f
.
OSC
XCLK
XCLK or internal RC oscillator is divided by 4 and connects to the ADC; f
XCLK or internal RC oscillator is divided by 2 and connects to the ADC; f
Not allowed
= fXCLK ÷ 4.
= fXCLK ÷ 2.
OSC
OSC
Clock duty cycles of 50% ±10% are recommended.
______________________________________________________________________________________ 17
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
0
-10
-20
-30
-40
-50
-60
CONVERSION TIME
LINE CYCLE PERIOD
0.1
1
1
2
3
4
5
6
7 8 9 10
SIGNAL FREQUENCY IN Hz
FOR 100ms CONVERSION
TIME (see Table 6)
10
20
30 40 50 60 708090100
0/MAX1
Figure 9. MAX110/MAX111 Noise Rejection Follows SIN(X) / X Function
clock frequency can be used for best performance.
Over the extended and military temperature ranges, the
ratio of 2 or 4 gives the best performance. See the
Typical Operating Characteristics to observe the effect
of the clock divider on the converter’s linearity.
S e le c t in g t h e Ove rs a m p lin g
Clo c k Fre q u e n c y
Choose the oversampling frequency, f
, carefully to
OSC
achieve the best relative-accuracy performance from the
MAX110/MAX111 (see Typical Operating Characteristics).
5 0 Hz/6 0 Hz Lin e Fre q u e n c y Re je c t io n
High rejection of 50Hz or 60Hz is obtained by using an
oversampling clock frequency and a clock-cycles/con-
version setting so the conversion time equals an inte-
gral number of line cycles, as in the following equation:
Clock Divider-Ratio Control Bits
Bits 7 a nd 8 (DV2 a nd DV4) p rog ra m the c loc k-
frequency divider network. The divider network sets the
frequency ratio between f
(the frequency of the
XCLK
external TTL/CMOS clock or internal RC oscillator) and
(the oversampling frequency used by the ADC).
f
OSC
f
= f
x m / n
OSC
LINE
An oversampling clock frequency between 450kHz and
700kHz is optimum for the converter. Best perfor-
mance over the extended temperature range is
obtained by choosing 1MHz or 1.024MHz with the
divide-by-2 option (DV2 = 1) (see the section Effect
of Dither on INL). To determine the converter’s accura-
c y a t othe r c loc k fre q ue nc ie s , s e e the Typ ic a l
Operating Characteristics and Table 5.
where f
is the oversampling clock frequency, f
LINE
OSC
= 50Hz or 60Hz, m is the number of clock cycles per
conversion (see Table 4), and n is the number of line
cycles averaged every conversion.
This nois e re je c tion is inhe re nt in inte g ra ting a nd
sigma-delta ADCs, and follows a SIN(X) / X function
(Figure 9). Notches in this function represent extremely
high rejection, and correspond to frequencies with an
integral number of cycles in the MAX110/MAX111’s
selected conversion time.
Effect of Dither on Relative Accuracy
First-order sigma-delta converters require dither for
randomizing any systematic tone being generated in
the modulator. The frequency of the dither source plays
an important role in linearizing the modulator. The ratio
of the dither generator’s frequency to that of the modu-
lator’s oversampling clock can be changed by setting
the DV2/DV4 bits. The XCLK clock is directly used by
the dither generator while the DV2/DV4 bits reduce the
oversampling clock by a ratio of 2 or 4. Over the com-
mercial temperature range, any ratio (i.e., 1, 2, or 4)
between the dither frequency and the oversampling
The shortest conversion time resulting in maximum
simultaneous rejection of both 60Hz and 50Hz line fre-
quencies is 100ms. When using the MAX111, use a
200ms conversion time for maximum 60Hz and 50Hz
rejection and optimum performance. For either device,
select the appropriate oversampling clock frequency
and either an 81,240 or 102,400 clock cycles per con-
version (CCPC) ratio. Table 6 suggests the possible
configurations.
18 ______________________________________________________________________________________
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
0/MAX1
POWER
SUPPLIES
POWER
SUPPLIES
+5V
+5V
-5V
GND
GND
4.7µF
0.1µF
4.7µF
0.1µF
4.7µF
0.1µF
*R = 10Ω
*R = 10Ω
V
GND
AGND
+5V DGND
V
GND
V
+5V DGND
DD
DD
SS
DIGITAL
CIRCUITRY
DIGITAL
CIRCUITRY
MAX111
MAX110
*OPTIONAL
*OPTIONAL
Figure 10a. MAX110 Power-Supply Grounding Connections
A 100ms conversion time cannot be achieved with either
Figure 10b. MAX111 Power-Supply Grounding Connections
If you wish to use a configuration other than those sug-
gested in Table 6, you can accomplish similar 50Hz
and 60Hz line-frequency rejection off-chip by averag-
ing several conversions.
10,240 CCPC or 20,480 CCPC modes because f
would be below the minimum 250kHz requirement.
OSC
When the gain calibration is performed, the conversion
times change approximately 1% to compensate for the
modulator’s gain error. This slightly degrades the line-
frequency rejection, because the corrected conversion
time is no longer an exact multiple of the line frequency.
Typically, the rejection of 50Hz/60Hz from the converter
is 55dB; i.e., if there is 100mV injection at the reference
or the analog input pin, it will cause an uncertainty of
±0.006%. If the system has large 50Hz/60Hz noise, the
use of internal auto gain calibration is not recommend-
ed. Instead, gain calibration should be done off-chip,
using numerical computation methods.
__________Ap p lic a t io n s In fo rm a t io n
La yo u t , Gro u n d in g , Byp a s s in g
For minimal noise, bypass each supply to GND with a
0.1µF capacitor. A ground plane should also be placed
under the analog circuitry. To minimize the coupling
effects of stray capacitance, keep digital lines as far
from analog components and lines as possible. Figure
10 shows the suggested power-supply and ground-
plane connections.
Table 6. Suggested XCLK Frequencies to Achieve Maximum Rejection of Both 50Hz/60Hz Line
Frequencies
MAX111 (t
= 200ms)
MAX110 (t
= 100ms)
CONVERT
CONVERT
81,240 CCPC
102,400 CCPC
81,240 CCPC
102,400 CCPC
DIVIDER
RATIO
DIVIDER
RATIO
RELATIVE
ACCURACY
(%)
RELATIVE
ACCURACY
(%)
RELATIVE
ACCURACY
(%)
RELATIVE
ACCURACY
(%)
f
f
XCLK
(MHz)
f
f
XCLK
(MHz)
XCLK
XCLK
(MHz)
(MHz)
1:1
2:1
4:1
0.4062
0.8124
1.6248
0.030
0.025
0.022
0.512
1.024
2.048
0.030
0.025
0.023
1:1
2:1
4:1
0.8124
1.6248
3.2496
0.025
0.018
0.016
1.024
2.048
4.096
0.065
0.045
0.030
CCPC = Clock Cycles per Conversion
______________________________________________________________________________________ 19
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
+5V
0.1µF
+5V
V
DD
22k
10k
1k
REF+
REF-
1/2 MAX492
+5V
30mV
FULL-SCALE
1k
MAX111
1µF
1µF
+5V
121k
121k
49.9k
49.9k
IN1+
IN1-
CS
0/MAX1
2k
DIN
1k
DOUT
+5V
SCLK
GND
AGND
1/2 MAX492
Figure 11. Weigh Scale Application
Capacitive Loading Effects of XCLK in
Internal RC-Oscillator Mode
When using the internal RC oscillator, capacitive load-
We ig h S c a le Ap p lic a t io n
The fully differential analog signal and reference inputs
make the MAX111 easy to interface to transducers with
differential outputs, such as the load cell in Figure 11.
Because the ADC input is differential, the load cell only
requires differential gain, eliminating the need for the
difference amplifier (differential to single-ended con-
verter) of the standard three op-amp instrumentation-
amplifier realization.
ing effects on the XCLK pin must be minimized. Stray
capacitance causes the V
power consumption to
DD
increase by an amount p = 1⁄2CV2f, where C = stray
capacitance, V is the supply voltage, and f is the fre-
quency of the internal RC oscillator.
Ex t e rn a l Re fe re n c e
The reference inputs to the ADC are high impedance,
allowing both an external voltage reference and ratio-
metric applications without loading effects. The fully dif-
fe re ntia l a na log s ig na l a nd re fe re nc e inp uts a re
advantageous for performing ratiometric conversions
(Figures 11 and 12). For example, when measuring
load cells, the bridge excitation and the ADC reference
input both share the same voltage source. As the exci-
tation changes with temperature or voltage, the output
of the load cell will change. But since the differential
reference voltage also changes, the conversion results
remain constant, all else remaining equal.
The 30mV full-scale bridge output is amplified to 2V
full-s c a le a nd a p p lie d to the MAX111 c ha nne l-one
input. The reference voltage to the ADC is created by a
voltage divider connected to the +5V rail. The same 5V
provides excitation for the bridge; therefore, as the
excitation voltage varies, the reference voltage to the
ADC also varies, providing an ADC output that does
not depend on the supply voltage.
The two 121kΩ resistors connected to the +5V supplies
shift the common-mode voltage from 2.5V (5V/2) to
1.5V to ensure linearity. Match these two resistors to
avoid introducing differential offset, or trim the resistor
mismatch with a potentiometer. In practice, the scale is
“zeroed” or “tared” by storing the average of several
conversions in a memory location while the scale is
20 ______________________________________________________________________________________
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
0/MAX1
+5V
1/4 MAX479
V
DD
IN2+
IN2-
10k
10k
MAX110
1/4 MAX479
1k
+5V
1µF
V
IN
243k
243k
TEMP
IN1+
IN1-
CS
MAX874
OUT
K-TYPE
1k
DIN
DOUT
SCLK
10k
REF+
REF-
1k
V
SS
1µF
1/4 MAX479
-5V
1M
Figure 12. Thermocouple Circuit with Software Compensation
unloaded, and subtracting this value from actual weight
me a s ure me nts . The lowp a s s filte ring a c tion of the
MAX111’s sigma-delta converter helps minimize noise.
The re s olution of the we ig h s c a le c a n b e furthe r
increased by averaging several conversions.
where α is the Seebeck constant for the type of thermo-
couple, T1 is the temperature being measured, and
T
REF
is the temperature of the junction block. Although
one method to obtain T
is to force the junction block
REF
to a known te mp e ra ture (0°C), a more p op ula r
approach is to measure T
or PN junction voltage.
directly using a thermistor
REF
Th e rm o c o u p le Circ u it w it h S o ft w a re
Co m p e n s a t io n
The circuit in Figure 12 shows a k-type thermocouple
going through a 54dB gain stage to channel 1 of the
MAX110. A MAX874 voltage reference provides both
the 3V reference voltage and reference junction tem-
perature information to the MAX110. Armed with the
temperature information provided by the MAX874, the
thermocouple voltage created at the junction block can
be subtracted out in software. The TEMP output of the
MAX874 is nominally 690mV at room temperature, and
increases with temperature at about 2.3mV/°C. Place
the MAX874 as close as possible to the terminal block,
and ensure good thermal contact between them. This
circuit employs a common k-type thermocouple and,
with the component values shown, can indicate tem-
peratures in the range of -150°C to +125°C.
A thermocouple is created by the junction of dissimilar
metals, and generates a voltage proportional to temper-
ature (Seebeck voltage), making it useful for tempera-
ture-measurement instruments. When a thermocouple
probe is connected to a measurement instrument, other
thermoelectric potentials are created between the alloys
of the probe and the copper connectors of the instru-
ment. These potentials introduce a temperature-depen-
dent error that must be subtracted from the temperature
measurement to obtain an accurate result. According to
the law of intermediate metals, the junction of the ther-
mocouple-probe alloys with the copper of the instrument
junction block can be treated as another thermocouple
of the same type. The voltage measured by the instru-
ment can be expressed as:
V = α(T1 - T
)
REF
______________________________________________________________________________________ 21
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
_Ord e rin g In fo rm a t io n (c o n t in u e d )
__________________Ch ip To p o g ra p h y
PART
TEMP. RANGE PIN-PACKAGE INL(%)
REF+REF- IN1+
IN1- IN2+
IN2-
MAX110AEPE
MAX110BEPE
-40°C to +85°C
-40°C to +85°C
16 Plastic DIP
16 Plastic DIP
16 Wide SO
16 Wide SO
20 SSOP
±0.03
±0.05
±0.03
±0.05
±0.03
±0.05
±0.05
±0.03
±0.05
±0.03
±0.05
±0.03
±0.05
±0.05
±0.03
±0.05
±0.03
±0.05
±0.03
±0.05
±0.05
MAX110AEWE -40°C to +85°C
MAX110BEWE -40°C to +85°C
MAX110AEAP
MAX110BEAP
MAX110BMJE
MAX111ACPE
MAX111BCPE
MAX111ACWE
MAX111BCWE
MAX111ACAP
MAX111BCAP
MAX111BC/D
MAX111AEPE
MAX111BEPE
-40°C to +85°C
-40°C to +85°C
20 SSOP
V
SS
-55°C to +125°C 16 CERDIP**
(AGND)
V
SS
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
16 Plastic DIP
16 Plastic DIP
16 Wide SO
16 Wide SO
20 SSOP
(AGND)
GND
V
DD
GND
V
DD
0/MAX1
RCSEL
20 SSOP
0. 168"
(4. 27mm)
Dice*
16 Plastic DIP
16 Plastic DIP
16 Wide SO
16 Wide SO
20 SSOP
MAX111AEWE -40°C to +85°C
MAX111BEWE -40°C to +85°C
MAX111AEAP
MAX111BEAP
MAX111BMJE
-40°C to +85°C
-40°C to +85°C
20 SSOP
-55°C to +125°C 16 CERDIP**
XCLK
SCLK BUSY CS
DOUT
DIN
* Contact factory for dice specifications.
** Contact factory for availability.
0. 121"
(3. 07mm)
____P in Co n fig u ra t io n s (c o n t in u e d )
( ) ARE FOR MAX111
TRANSISTOR COUNT: 5849
SUBSTRATE CONNECTED TO VDD
TOP VIEW
IN1+
REF-
REF+
N.C.
1
2
3
4
5
6
7
8
9
20 IN1-
19 IN2+
18 IN2-
MAX110
MAX111
17
V (AGND)
SS
N.C.
16 GND
15 N.C.
14 N.C.
13 DIN
12 DOUT
11 CS
V
DD
RCSEL
XCLK
SCLK
BUSY 10
SSOP
( ) ARE FOR MAX111
22 ______________________________________________________________________________________
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
0/MAX1
_______________________________________________________P a c k a g e In fo rm a t io n
______________________________________________________________________________________ 23
Lo w -Co s t , 2 -Ch a n n e l, ±1 4 -Bit S e ria l ADCs
___________________________________________P a c k a g e In fo rm a t io n (c o n t in u e d )
0/MAX1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1998 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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