MAX11120_V01 [MAXIM]
1Msps, Low-Power, Serial 12-/10-/8-Bit, 4-/8-/16-Channel ADCs;
| 型号： | MAX11120_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 1Msps, Low-Power, Serial 12-/10-/8-Bit, 4-/8-/16-Channel ADCs |
| 文件： | 总40页 (文件大小：1886K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
General Description
Benefits and Features
● Scan Modes, Internal Averaging, and Internal Clock
● 16-Entry First-In/First-Out (FIFO)
● SampleSet: User-Defined Channel Sequence with
Maximum Length of 256
● Analog Multiplexer with True Differential Track/Hold
• 16-/8-/4-Channel Single-Ended
• 8-/4-/2-Channel Fully-Differential Pairs
• 15-/8-/4-Channel Pseudo-Differential Relative to a
Common Input
● Two Software-Selectable Bipolar Input Ranges
The MAX11120–MAX11128 are 12-/10-/8-bit with external
reference and industry-leading 1.5MHz, full linear band-
width, high speed, low-power, serial output successive-
approximation register (SAR) analog-to-digital converters
(ADCs). The MAX11120–MAX11128 include both internal
and external clock modes. These devices feature scan
mode in both internal and external clock modes. The inter-
nal clock mode features internal averaging to increase
SNR. The external clock mode features the SampleSet™
technology, a user-programmable analog input channel
sequencer. The SampleSet approach provides greater
sequencing flexibility for multichannel applications while
alleviating significant microcontroller or DSP (controlling
unit) communication overhead.
• ±V
/2, ±V
REF+
REF+
● Flexible Input Configuration Across All Channels
● High Accuracy
The internal clock mode features an integrated FIFO
allowing data to be sampled at high speeds and then held
for readout at any time or at a lower clock rate. Internal
averaging is also supported in this mode improving SNR
for noisy input signals. The devices feature analog input
channels that can be configured to be single-ended
inputs, fully differential pairs, or pseudo-differential inputs
with respect to one common input. The MAX11120–
MAX11128 operate from a 2.35V to 3.6V supply and
consume only 5.4mW at 1Msps.
• ±1 LSB INL, ±1 LSB DNL, No Missing Codes
Over Temperature Range
● 70dB SINAD Guaranteed at 250kHz Input Frequency
● 1.5V to 3.6V Wide Range I/O Supply
• Allows the Serial Interface to Connect Directly to
1.8V, 2.5V, or 3.3V Digital Systems
● 2.35V to 3.6V Supply Voltage
● Longer Battery Life for Portable Applications
• Low Power
• 5.4mW at 1Msps with 3V Supplies
• 2μA Full-Shutdown Current
The MAX11120–MAX11128 include AutoShutdown™, fast
wake-up, and a high-speed 3-wire serial interface. The
devices feature full power-down mode for optimal power
management.
● External Differential Reference (1V to V
)
DD
● 16MHz, 3-Wire SPI-/QSPI-/MICROWIRE-/DSP-
Compatible Serial Interface
● Wide -40°C to +125°C Operation
The 16MHz, 3-wire serial interface directly connects to
SPI, QSPI™, and MICROWIRE devices without external
®
● Space-Saving, 28-Pin, 5mm x 5mm TQFN Packages
● 1Msps Conversion Rate, No Pipeline Delay
● 12-/10-/8-Bit Resolution
logic.
Excellent dynamic performance, low voltage, low power,
ease of use, and small package size make these convert-
ers ideal for portable battery-powered data-acquisition
applications, and for other applications that demand low
power consumption and small space.
● AECQ-100 Qualified Variant Available (MAX11128ATI/V+)
Applications
● High-Speed Data Acquisition Systems
● High-Speed Closed-Loop Systems
● Industrial Control Systems
● Medical Instrumentation
The MAX11120–MAX11128 are available in 28-pin, 5mm
x 5mm, TQFN packages and operate over the -40°C to
+125°C temperature range.
● Battery-Powered Instruments
● Portable Systems
SampleSet and AutoShutdown are trademarks of Maxim
Integrated Products, Inc.
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corporation.
Ordering Information appears at end of data sheet.
19-6148; Rev 4; 2/19
MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Absolute Maximum Ratings
V
to GND............................................................-0.3V to +4V
Continuous Power Dissipation (T = +70°C)
A
DD
OVDD, AIN0–AIN13, CNVST/AIN14, REF+, REF-/AIN15
to GND...............-0.3V to the lower of (V + 0.3V) and +4V
TQFN (derate 34.4mW/°C above +70°C)..................2758mW
Operating Temperature Range......................... -40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
DD
CS, SCLK, DIN, DOUT, EOC TO GND......-0.3V to the Lower of
(V + 0.3V) and +4V
OVDD
DGND to GND......................................................-0.3V to +0.3V
Input/Output Current (all pins)............................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 1)
Package Thermal Characteristics
TQFN
Junction-to-Ambient Thermal Resistance (θ )..........29°C/W
JA
Junction-to-Case Thermal Resistance (θ ) ................2°C/W
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics (MAX11122/MAX11125/MAX11128)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
DC ACCURACY (Notes 3 and 4)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RES
INL
12 bit
12
Bits
±1.0
±1.2
±1.0
±2.5
±4.0
Integral Nonlinearity
LSB
MAX11128ATI/V+
No missing codes
Differential Nonlinearity
Offset Error
DNL
LSB
LSB
LSB
0.7
Gain Error
(Note 5)
-0.5
Offset Error Temperature
Coefficient
OE
GE
±2
ppm/°C
ppm/°C
LSB
TC
Gain Temperature Coefficient
±0.8
±0.5
±0.4
TC
Channel-to-Channel Offset
Matching
Line Rejection
PSR
(Note 6)
±1.5
-78
LSB/V
DYNAMIC PERFORMANCE (250kHz, input sine wave) (Notes 3 and 7)
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
SINAD
SNR
70
70
72.5
72.6
dB
dB
Total Harmonic Distortion
(Up to the 5th Harmonic)
THD
-87
dB
Spurious-Free Dynamic Range
Intermodulation Distortion
SFDR
IMD
79
88
dB
dB
f = 249.878kHz, f = 219.97kHz
-85
1
2
Maxim Integrated
│ 2
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Electrical Characteristics (MAX11122/MAX11125/MAX11128) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
Full-Power Bandwidth
Full-Linear Bandwidth
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
-3dB
50
7.5
1.5
-0.1dB
SINAD > 70dB
MHz
-0.5dB below full scale of 249.878kHz
sine wave input to the channel
being sampled, apply full-scale
219.97kHz sine wave signal to all 15
nonselected input channels
Crosstalk
-88
dB
CONVERSION RATE
Power-Up Time
t
Conversion cycle, external clock
Internally clocked (Note 8)
2
Cycles
ns
PU
Acquisition Time
t
156
5.9
ACQ
µs
Conversion Time
t
CONV
Externally clocked, f
16 cycles (Note 8)
= 16MHz,
SCLK
1000
0.16
ns
External Clock Frequency
Aperture Delay
f
16
MHz
ns
SCLK
8
Aperture Jitter
RMS
30
ps
ANALOG INPUT
Unipolar (single-ended and pseudo
differential)
0
V
REF+
Input Voltage Range
V
V
INA
RANGE bit set to 0
Bipolar
-V
/2
V
/2
REF+
REF+
(Note 9)
RANGE bit set to 1
-V
V
REF+
REF+
Absolute Input Voltage Range
Static Input Leakage Current
AIN+, AIN- relative to GND
-0.1
V
+ 0.1
V
REF+
I
V
= V , GND
-0.1
15
±1.5
µA
ILA
AIN_
DD
During acquisition time,
RANGE bit = 0 (Note 10)
Input Capacitance
C
pF
AIN
During acquisition time,
RANGE bit = 1 (Note 10)
7.5
EXTERNAL REFERENCE INPUT
REF- Input Voltage Range
V
-0.3
1
+1
V
V
REF-
V
+
DD
50mV
REF+ Input Voltage Range
REF+ Input Current
V
REF+
V
V
= 2.5V, f
= 2.5V, f
= 1Msps
= 0
36.7
0.1
REF+
SAMPLE
I
µA
REF+
REF+
SAMPLE
Maxim Integrated
│ 3
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Electrical Characteristics (MAX11122/MAX11125/MAX11128) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SCLK, DIN, CS, CNVST)
V
OVDD
0.25
×
Input Voltage Low
Input Voltage High
Input Hysteresis
V
V
V
IL
V
OVDD
0.75
×
V
IH
V
OVDD
0.15
×
V
mV
HYST
Input Leakage Current
I
V
= 0V or V
= 200µA
±0.09
3
±1.0
µA
pF
IN
AIN_
DD
Input Capacitance
C
IN
DIGITAL OUTPUTS (DOUT, EOC)
V
×
OVDD
0.15
Output Voltage Low
V
I
I
V
V
OL
SINK
V
×
OVDD
0.85
Output Voltage High
V
= 200µA
OH
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
I
CS = V
CS = V
-0.3
4
±1.5
µA
pF
L
DD
C
OUT
DD
V
2.35
1.5
3.0
3.0
1.8
1
3.6
3.6
2.5
V
V
DD
Digital I/O Supply Voltage
V
OVDD
f
f
= 1Msps
SAMPLE
Positive Supply Current
I
= 0 (1Msps devices)
mA
DD
SAMPLE
Full shutdown
0.0015
0.006
V
= 3V,
DD
5.4
Normal mode
(external
reference)
f
= 1Msps
SAMPLE
V
= 2.35V,
DD
3.8
2.6
1.6
f
= 1Msps
SAMPLE
mW
µW
V
= 3V,
DD
Power Dissipation
f
= 1Msps
SAMPLE
AutoStandby
V
= 2.35V,
DD
f
= 1Msps
SAMPLE
V
V
= 3V
4.5
2.1
Full/
AutoShutdown
DD
= 2.35V
DD
Maxim Integrated
│ 4
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Electrical Characteristics (MAX11122/MAX11125/MAX11128) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Figure 1) (Note 11)
SCLK Clock Period
SCLK Duty Cycle
t
Externally clocked conversion
62.4
40
4
ns
%
CP
t
60
16.5
15
CH
V
V
= 1.5V to 2.35V
= 2.35V to 3.6V
C
10pF
=
OVDD
LOAD
SCLK Fall to DOUT Transition
t
ns
DOT
4
OVDD
16th SCLK Fall to DOUT Disable
14th SCLK Fall to DOUT Disable
SCLK Fall to DOUT Enable
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
t
C
C
C
= 10pF, channel ID on
= 10pF, channel ID off
= 10pF
15
ns
ns
ns
ns
ns
ns
ns
ns
DOD
LOAD
LOAD
LOAD
16
t
14
DOE
t
4
1
4
1
5
DS
t
DH
CS Fall to SCLK Fall Setup
SCLK Fall to CS Fall Hold
CNVST Pulse Width
t
t
CSS
CSH
t
See Figure 6
CSW
CS or CNVST Rise to EOC Low
(Note 7)
t
See Figure 7, f
= 1Msps
SAMPLE
5.3
6.2
µs
ns
CNV_INT
CS Pulse Width
t
5
CSBW
Electrical Characteristics (MAX11121/MAX11124/MAX11127)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
DC ACCURACY (Notes 3 and 4)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RES
INL
10 bit
10
Bits
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
±0.4
±0.4
±1.0
±1.1
DNL
No missing codes
(Note 5)
0.5
Gain Error
-0.2
Offset Error Temperature
Coefficient
OE
GE
±2
ppm/°C
ppm/°C
LSB
TC
Gain Temperature Coefficient
±0.8
±0.5
±0.1
TC
Channel-to-Channel Offset
Matching
Line Rejection
PSR
(Note 6)
±0.3
LSB/V
Maxim Integrated
│ 5
www.maximintegrated.com
MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Electrical Characteristics (MAX11121/MAX11124/MAX11127) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+
DD
A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (250kHz, input sine wave) (Notes 3 and 7)
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
SINAD
SNR
61
61
61.7
61.7
dB
dB
Total Harmonic Distortion
(Up to the 5th Harmonic)
THD
-86
-76
dB
Spurious-Free Dynamic Range
Intermodulation Distortion
SFDR
IMD
77
85
-84
50
dB
f = 249.878kHz, f = 219.97kHz
dB
1
2
-3dB
MHz
MHz
MHz
Full-Power Bandwidth
Full-Linear Bandwidth
-0.1dB
7.5
1.5
SINAD > 61dB
-0.5dB below full-scale of
249.878kHz sine-wave input to the
channel being sampled; apply full-
scale 219.97kHz sine wave signal to
all 15 nonselected input channels
Crosstalk
-88
dB
CONVERSION RATE
Power-Up Time
t
Conversion cycle, external clock
2
Cycles
ns
PU
Acquisition Time
t
156
5.9
ACQ
f
= 1Msps
SAMPLE
Internally clocked
µs
ns
(Note 8)
Conversion Time
t
CONV
Externally clocked, f
16 cycles (Note 8)
= 16MHz,
SCLK
1000
0.16
External Clock Frequency
Aperture Delay
f
16
MHz
ns
SCLK
8
Aperture Jitter
RMS
30
ps
ANALOG INPUT
Unipolar (single-ended and pseudo
differential)
0
V
REF+
Input Voltage Range
V
V
INA
RANGE bit set to 0 -V
/2
+V
/2
REF+
REF+
Bipolar (Note 9)
RANGE bit set to 1 -V
+V
REF+
REF+
Absolute Input Voltage Range
Static Input Leakage Current
AIN+, AIN- relative to GND
-0.1
V
+ 0.1
V
REF+
I
V
= V , GND
-0.1
15
µA
ILA
AIN_
DD
During acquisition time,
RANGE bit = 0 (Note 10)
Input Capacitance
C
pF
AIN
During acquisition time,
RANGE bit = 1 (Note 10)
7.5
Maxim Integrated
│ 6
www.maximintegrated.com
MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Electrical Characteristics (MAX11121/MAX11124/MAX11127) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EXTERNAL REFERENCE INPUT
REF- Input Voltage Range
V
-0.3
1
+1
V
V
REF-
V
+
DD
50mV
REF+ Input Voltage Range
REF+ Input Current
V
REF+
V
V
= 2.5V, f
= 2.5V, f
= 1Msps
= 0
36.7
0.1
µA
µA
REF+
SAMPLE
I
REF+
REF+
SAMPLE
DIGITAL INPUTS (SCLK, DIN, CS, CNVST)
V
OVDD
0.25
×
Input Voltage Low
Input Voltage High
Input Hysteresis
V
V
V
IL
V
OVDD
0.75
×
V
IH
V
OVDD
0.15
×
V
mV
HYST
Input Leakage Current
I
V
= 0V or V
DD
±0.09
3
µA
pF
IN
AIN_
Input Capacitance
C
IN
DIGITAL OUTPUTS (DOUT, EOC)
V
×
OVDD
0.15
Output Voltage Low
V
I
I
= 200µA
V
V
OL
SINK
V
OVDD
0.85
×
Output Voltage High
V
OH
= 200µA
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
I
CS = V
CS = V
-0.3
4
µA
pF
L
DD
C
OUT
DD
V
2.35
1.5
3.0
3.0
1.8
1
3.6
3.6
2.5
V
V
DD
Digital I/O Supply Voltage
V
OVDD
f
f
= 1Msps
SAMPLE
Positive Supply Current
I
= 0 (1Msps devices)
mA
DD
SAMPLE
Full shutdown
0.0015
0.006
V
= 3V,
DD
5.4
Normal mode
(external
reference)
f
= 1Msps
SAMPLE
V
DD
= 2.35V,
3.8
2.6
1.6
f
= 1Msps
SAMPLE
mW
µW
V
DD
= 3V,
Power Dissipation
f
= 1Msps
SAMPLE
AutoStandby
V
DD
= 2.35V,
f
= 1Msps
SAMPLE
V
= 3V
4.5
2.1
Full/
AutoShutdown
DD
DD
V
= 2.35V
Maxim Integrated
│ 7
www.maximintegrated.com
MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Electrical Characteristics (MAX11121/MAX11124/MAX11127) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Figure 1) (Note 11)
SCLK Clock Period
SCLK Duty Cycle
t
Externally clocked conversion
62.4
40
ns
%
CP
t
60
CH
V
V
= 1.5V to 2.35V
= 2.35V to 3.6V
4
4
16.5
15
C
10pF
=
OVDD
LOAD
SCLK Fall to DOUT Transition
t
ns
DOT
OVDD
16th SCLK Fall to DOUT Disable
14th SCLK Fall to DOUT Disable
SCLK Fall to DOUT Enable
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
t
C
C
C
= 10pF, channel ID on
= 10pF, channel ID off
= 10pF
15
16
14
ns
ns
ns
ns
ns
ns
ns
ns
DOD
LOAD
LOAD
LOAD
t
DOE
t
4
1
4
1
5
DS
DH
t
CS Fall to SCLK Fall Setup
SCLK Fall to CS Fall Hold
CNVST Pulse Width
t
t
CSS
CSH
t
See Figure 6
CSW
CS or CNVST Rise to EOC Low
(Note 8)
t
See Figure 7, f
= 1Msps
SAMPLE
5.3
6.2
µs
ns
CNV_INT
CS Pulse Width
t
5
CSBW
Electrical Characteristics (MAX11120/MAX11123/MAX11126)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
DC ACCURACY (Notes 3 and 4)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RES
INL
8 bit
8
Bits
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
±0.02
±0.02
0.5
±0.15
±0.15
±0.7
DNL
No missing codes
(Note 5)
Gain Error
-0.03
±0.3
Offset Error Temperature
Coefficient
OE
GE
±2
ppm/°C
ppm/°C
LSB
TC
Gain Temperature Coefficient
±0.8
±0.5
+0.03
TC
Channel-to-Channel Offset
Matching
Line Rejection
PSR
(Note 6)
±0.1
LSB/V
Maxim Integrated
│ 8
www.maximintegrated.com
MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Electrical Characteristics (MAX11120/MAX11123/MAX11126) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+
DD
A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (250kHz, input sine wave) (Notes 3 and 7)
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
SINAD
SNR
49
49
49.6
49.6
dB
dB
Total Harmonic Distortion
(Up to the 5th Harmonic)
THD
-77
-66
dB
Spurious-Free Dynamic Range
Intermodulation Distortion
SFDR
IMD
63
69
-75
50
dB
f = 249.878kHz, f = 219.97kHz
dB
1
2
-3dB
MHz
MHz
MHz
Full-Power Bandwidth
Full-Linear Bandwidth
-0.1dB
7.5
1.5
SINAD > 49dB
-0.5dB below full-scale of
249.878kHz sine-wave input to the
channel being sampled; apply full-
scale 219.97kHz sine wave signal to
all 15 nonselected input channels
Crosstalk
-88
dB
CONVERSION RATE
Power-Up Time
t
Conversion cycle, external clock
2
Cycles
ns
PU
Acquisition Time
t
156
5.9
ACQ
Internally
clocked
f
= 1Msps
SAMPLE
(Note 8)
µs
ns
Conversion Time
t
CONV
Externally clocked, f
16 cycles (Note 8)
= 16MHz,
SCLK
1000
0.16
External Clock Frequency
Aperture Delay
f
16
MHz
ns
SCLK
8
Aperture Jitter
RMS
30
ps
ANALOG INPUT
Unipolar (single-ended and pseudo
differential)
0
V
REF+
REF+
Input Voltage Range
V
V
INA
RANGE bit set to 0
Bipolar (Note 9)
-V
/2
+V
/2
REF+
RANGE bit set to 1
-V
+V
REF+
REF+
Absolute Input Voltage Range
Static Input Leakage Current
AIN+, AIN- relative to GND
-0.1
V
+ 0.1
V
REF+
I
V
= V , GND
-0.1
15
µA
ILA
AIN_
DD
During acquisition time,
RANGE bit = 0 (Note 10)
Input Capacitance
C
pF
AIN
During acquisition time,
RANGE bit = 1 (Note 10)
7.5
Maxim Integrated
│ 9
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Electrical Characteristics (MAX11120/MAX11123/MAX11126) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EXTERNAL REFERENCE INPUT
REF- Input Voltage Range
V
-0.3
1
+1
V
V
REF-
V
+
DD
50mV
REF+ Input Voltage Range
REF+ Input Current
V
REF+
V
V
= 2.5V, f
= 2.5V, f
= 1Msps
= 0
36.7
0.1
µA
µA
REF+
SAMPLE
I
REF+
REF+
SAMPLE
DIGITAL INPUTS (SCLK, DIN, CS, CNVST)
V
OVDD
0.25
×
Input Voltage Low
Input Voltage High
Input Hysteresis
V
V
V
IL
V
OVDD
0.75
×
V
IH
V
OVDD
0.15
×
V
mV
HYST
Input Leakage Current
I
V
= 0V or V
DD
±0.09
3
µA
pF
IN
AIN_
Input Capacitance
C
IN
DIGITAL OUTPUTS (DOUT, EOC)
V
OVDD
0.15
×
Output Voltage Low
V
I
I
= 200µA
V
V
OL
SINK
V
×
OVDD
0.85
Output Voltage High
V
OH
= 200µA
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
I
CS = V
CS = V
-0.3
4
µA
pF
L
DD
C
OUT
DD
V
2.35
1.5
3.0
3.0
3.6
3.6
2.5
V
V
DD
Digital I/O Supply Voltage
V
OVDD
f
f
= 1Msps
1.8
SAMPLE
SAMPLE
Positive Supply Current
I
= 0
1.0
mA
DD
Full shutdown
0.0015
0.006
V
= 3V,
DD
5.4
3.8
2.6
1.6
Normal mode
(external
reference)
f
= 1Msps
SAMPLE
V
DD
= 2.35V,
f
= 1Msps
SAMPLE
mW
µW
V
DD
= 3V,
Power Dissipation
f
= 1Msps
SAMPLE
AutoStandby
V
DD
= 2.35V,
f
= 1Msps
SAMPLE
V
= 3V
4.5
2.1
Full/
AutoShutdown
DD
DD
V
= 2.35V
Maxim Integrated
│ 10
www.maximintegrated.com
MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Electrical Characteristics (MAX11120/MAX11123/MAX11126) (continued)
(V
DD
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Figure 1) (Note 11)
SCLK Clock Period
SCLK Duty Cycle
t
Externally clocked conversion
62.4
ns
%
CP
t
40
4
60
16.5
15
CH
V
V
= 1.5V to 2.35V
= 2.35V to 3.6V
C
10pF
=
OVDD
LOAD
SCLK Fall to DOUT Transition
t
ns
DOT
DOD
4
OVDD
16th SCLK Fall to DOUT Disable
14th SCLK Fall to DOUT Disable
SCLK Fall to DOUT Enable
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
t
C
C
C
= 10pF, channel ID on
= 10pF, channel ID off
= 10pF
15
ns
ns
ns
ns
ns
ns
ns
ns
LOAD
LOAD
LOAD
16
14
t
DOE
t
4
1
4
1
5
DS
t
DH
CS Fall to SCLK Fall Setup
SCLK Fall to CS Fall Hold
CNVST Pulse Width
t
t
CSS
CSH
t
See Figure 6
CSW
CS or CNVST Rise to EOC Low
(Note 8)
t
See Figure 7, f
= 1Msps
SAMPLE
5.3
6.2
µs
ns
CNV_INT
CS Pulse Width
t
5
CSBW
Note 2: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design.
A
Note 3: Channel ID disabled.
Note 4: Tested in single-ended mode.
Note 5: Offset nulled.
Note 6: Line rejection Δ(D
) with V
= 2.35V to 3.6V and V = 2.35V.
REF+
OUT
DD
Note 7: Tested and guaranteed with fully differential input.
Note 8: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle.
Maximum conversion time: 4.73µs + N x 16 x T
.
OSC_MAX
T
= 88.2ns, T
= 75ns.
OSC_MAX
OSC_TYP
Note 9: The operational input voltage range for each individual input of a differentially configured pair is from V
to GND. The
DD
operational input voltage difference is from -V
Note 10: See Figure 3 (Equivalent Input Circuit).
Note 11: Guaranteed by characterization.
/2 to +V
REF+
/2 or -V
REF+
to +V .
REF+
REF+
Maxim Integrated
│ 11
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
t
CSBW
CS
t
t
CSH
t
CP
CSS
t
CH
1ST
CLOCK
SCLK
16TH
CLOCK
t
DH
t
DS
t
DOT
DIN
t
DOD
t
DOE
DOUT
Figure 1. Detailed Serial-Interface Timing Diagram
Typical Operating Characteristics
(MAX11122ATI+/MAX11125ATI+/MAX11128ATI+, T = +25°C, unless otherwise noted.)
A
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
OFFSET ERROR vs. TEMPERATURE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.5
0
3
2
f
= 1.0Msps
f
= 1.0Msps
SAMPLE
SAMPLE
1
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-0.5
-1.0
0
1024
2048
3072
4096
0
1024
2048
3072
4096
-40 -25 -10
5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
DIGITAL OUTPUT CODE (DECIMAL)
DIGITAL OUTPUT CODE (DECIMAL)
Maxim Integrated
│ 12
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Typical Operating Characteristics (continued)
(MAX11122ATI+/MAX11125ATI+/MAX11128ATI+, T = +25°C, unless otherwise noted.)
A
SNR AND SINAD
GAIN ERROR vs. TEMPERATURE
HISTOGRAM FOR 30,000 CONVERSIONS
vs. ANALOG INPUT FREQUENCY
3
2
35,000
30,000
25,000
20,000
15,000
10,000
5000
74.0
73.5
73.0
72.5
72.0
71.5
71.0
f
= 1Msps
f
= 1Msps
SAMPLE
SAMPLE
29992 CODE HITS
SNR
1
0
SINAD
-1
-2
-3
4 CODE HITS
4 CODE HITS
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
2045
2058
2059
2060
2065
0
100
200
300
(kHz)
400
500
TEMPERATURE (°C)
OUTPUT CODE (DECIMAL)
f
IN
SFDR vs. ANALOG INPUT FREQUENCY
THD vs. ANALOG INPUT FREQUENCY
THD vs. INPUT RESISTANCE
100
95
90
85
80
-80
-85
-80
-85
f
= 1.0Msps
f
= 1.0Msps
f
= 1.0Msps
SAMPLE
= 250kHz
SAMPLE
SAMPLE
f
IN
-90
-90
-95
-95
-100
-100
0
100
200
300
(kHz)
400
500
0
100
200
f
300
(kHz)
400
500
0
100
200
(Ω)
300
400
f
IN
R
IN
IN
Maxim Integrated
│ 13
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Typical Operating Characteristics (continued)
(MAX11122ATI+/MAX11125ATI+/MAX11128ATI+, T = +25°C, unless otherwise noted.)
A
250kHz SINE-WAVE INPUT
(8192-POINT FFT PLOT)
REFERENCE CURRENT
vs. SAMPLING RATE
50
40
30
20
10
0
0
-20
f
f
= 1Msps
SAMPLE
= 250kHz
IN
A
= -92.369dB
HD3
f = 254.4kHz
-40
A = -104.1dB
HD2
f = 500kHz
-60
-80
-100
-120
0
200
400
600
800
1000
0
100
200
300
400
500
f
(ksps)
FREQUENCY (kHz)
SAMPLE
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
SNR vs. REFERENCE VOLTAGE
3.0
2.5
2.0
1.5
1.0
74
73
72
71
70
69
f
V
= 1.0Msps
f = 1.0Msps
SAMPLE
f = 250kHz
IN
SAMPLE
= 3.0V
DD
-40 -25 -10
5
20 35 50 65 80 95 110 125
1.0 1.4
1.8
2.2
2.6
(V)
3.0
3.4
TEMPERATURE (°C)
V
REFP
Maxim Integrated
│ 14
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Pin Configuration
TOP VIEW
21 20 19 18 17 16 15
21 20 19 18 17 16 15
14
13
DGND 22
OVDD 23
GND
REF-
14
13
DGND 22
OVDD 23
GND
REF-
12 CNVST
24
12 CNVST
24
DOUT
DOUT
MAX11120
MAX11121
MAX11122
MAX11123
MAX11124
MAX11125
GND
GND
GND
GND
11
10
9
GND
11
25
25
EOC
EOC
26
26
10
AIN0
AIN0
GND
27
28
GND
GND
AIN1
AIN2
27
28
9
8
AIN1
AIN2
+
+
8
1
2
3
4
5
6
7
1
2
3
4
5
6
7
TQFN
4 CHANNEL
TQFN
8 CHANNEL
21 20 19 18 17 16 15
14
13
DGND 22
OVDD 23
GND
REF-/AIN15
12 CNVST/AIN14
24
25
26
27
28
DOUT
EOC
AIN0
AIN1
AIN2
MAX11126
MAX11127
MAX11128
AIN13
AIN12
AIN11
AIN10
11
10
9
+
8
1
2
3
4
5
6
7
TQFN
16 CHANNEL
Maxim Integrated
│ 15
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Pin Description
MAX11120
MAX11121
MAX11122
MAX11123
MAX11124
MAX11125
MAX11126
MAX11127
MAX11128
NAME
FUNCTION
(4 CHANNEL)
(8 CHANNEL)
(16 CHANNEL)
26, 27, 28,
1–11
AIN0–
AIN13
—
—
Analog Inputs
—
26, 27, 28, 1–5
—
AIN0–AIN7
Analog Inputs
Analog Inputs
Ground
26, 27, 28, 1
2–11
—
—
—
AIN0–AIN3
GND
6–11
CNVST/
AIN14
—
12
—
—
12
—
12
—
13
Active-Low Conversion Start Input/Analog Input 14
CNVST
Active-Low Conversion Start Input
REF-/
AIN15
External Differential Reference Negative Input /Analog
Input 15
13
13
—
REF-
GND
External Differential Reference Negative Input
14, 16
14, 16
14, 16
Ground
External Positive Reference Input. Apply a reference
voltage at REF+. Bypass to GND with a 0.47µF
capacitor.
15
15
15
REF+
Power-Supply Input. Bypass to GND with a 10µF in
parallel with a 0.1µF capacitors.
17, 18
19
17, 18
19
17, 18
19
V
DD
Serial Clock Input. Clocks data in and out of the serial
interface
SCLK
Active-Low Chip Select Input. When CS is low, the serial
interface is enabled. When CS is high, DOUT is high
impedance or three-state.
20
20
20
CS
Serial Data Input. DIN data is latched into the serial
interface on the rising edge of SCLK.
21
22
23
21
22
23
21
22
23
DIN
DGND
OVDD
Digital I/O Ground
Interface Digital Power-Supply Input. Bypass to GND
with a 10µF in parallel with a 0.1µF capacitors.
Serial Data Output. Data is clocked out on the falling
edge of SCLK. When CS is high, DOUT is high
impedance or three-state.
24
24
24
DOUT
End of Conversion Output. Data is valid after EOC pulls
low (Internal clock mode only).
25
—
25
—
25
—
EOC
Exposed Pad. Connect EP directly to GND plane for
guaranteed performance.
EP
Maxim Integrated
│ 16
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Functional Diagram
V
DD
OVDD
REF+ REF-
AIN0
AIN1
REF+ REF-
DOUT
SCLK
ADC
CS
I/P
MUX
OSCILLATOR
AIN15
CS
SCLK
DIN
CONTROL LOGIC
AND
SEQUENCER
DOUT
CNVST
EOC
MAX11120–MAX11128
ing data to be sampled at high speed and then held for
readout at any time or at a lower clock rate. Internal aver-
aging is also supported in this mode improving SNR for
noisy input signals. All input channels are configurable for
single-ended, fully differential or pseudo-differential inputs
in unipolar or bipolar mode. The MAX11120–MAX11128
operate from a 2.35V to 3.6V supply and consume only
5.4mW at 1Msps.
Detailed Description
The MAX11120–MAX11128 are 12-/10-/8-bit with external
reference and industry-leading 1.5MHz, full linear band-
width, high-speed, low-power, serial output successive-
approximation register (SAR) analog-to-digital converters
(ADC). These devices feature scan mode, internal aver-
aging to increase SNR, and AutoShutdown.
The external clock mode features the SampleSet technol-
ogy, a user-programmable analog input channel sequenc-
er. The user may define and load a unique sequencing
pattern into the ADC allowing both high- and low-fre-
quency inputs to be converted without interface activity.
This feature frees the controlling unit for other tasks while
lowering overall system noise and power consumption.
The MAX11120–MAX11128 include AutoShutdown, fast
wake-up, and a high-speed 3-wire serial interface. The
devices feature full power-down mode for optimal power
management.
Data is converted from analog voltage sources in a
variety of channel and data-acquisition configurations.
Microprocessor (µP) control is made easy through a 3-wire
SPI-/QSPI-/MICROWIRE-compatible serial interface.
The MAX11120–MAX11128 includes internal clock. The
internal clock mode features an integrated FIFO, allow-
Maxim Integrated
│ 17
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Set CS low to latch input data at DIN on the rising edge
of SCLK. Output data at DOUT is updated on the falling
edge of SCLK. A high-to-low transition on CS samples
the analog inputs and initiates a new frame. A frame is
defined as the time between two falling edges of CS.
There is a minimum of 16 bits per frame. The serial data
input, DIN, carries data into the control registers clocked
in by the rising edge of SCLK. The serial data output,
DOUT, delivers the conversion results and is clocked out
by the falling edge of SCLK. DOUT is a 16-bit data word
containing a 4-bit channel address, followed by a 12-bit
conversion result led by the MSB when CHAN_ID is set
to 1 in the ADC Mode Control register (Figure 2a). In
this mode, keep the clock high for at least one full SCLK
period before the CS falling edge to ensure best perfor-
mance (Figure 2b). When CHAN_ID is set to 0 (external
clock mode only), the 16-bit data word includes a leading
zero and the 12-bit conversion result is followed by 3 trail-
ing zeros (Figure 2c). In the 10-bit ADC, the last 2 LSBs
are set to 0. In the 8-bit ADC, the last 4 LSBs are set to 0.
Input Bandwidth
The ADC’s input-tracking circuitry features a 1.5MHz,
small-signal, full-linear bandwidth to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. Anti-alias filtering of the input
signals is necessary to avoid high-frequency signals alias-
ing into the frequency band of interest.
3-Wire Serial Interface
The MAX11120–MAX11128 feature a serial interface
compatible with SPI/QSPI and MICROWIRE devices. For
SPI/QSPI, ensure the CPU serial interface runs in master
mode to generate the serial clock signal. Select the SCLK
frequency of 16MHz or less, and set clock polarity (CPOL)
and phase (CPHA) in the µP control registers to the same
value. The MAX11120–MAX11128 operate with SCLK
idling high, and thus operate with CPOL = CPHA = 1.
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
DIN
DI[15] DI[14]
DI[1] DI[0]
DOUT
Ch[3] Ch[2] Ch[1] Ch[0] MSB MSB-1
LSB+1 LSB
Figure 2a. External Clock Mode Timing Diagram with CHAN_ID=1
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
DIN
t
> t
QUIET SCLK
DI[15]
DI[1]
DI[0]
DOUT
Ch[3] Ch[2] Ch[1] Ch[0] MSB MSB-1
LSB+1 LSB
Figure 2b. External Clock Mode Timing Diagram with CHAN_ID=1 for Best Performance
Maxim Integrated
│ 18
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
DIN
DI[15] DI[14]
DI[1]
DI[0]
0
MSB] MSB-1 MSB-2
LSB
0
DOUT
Figure 2c. External Clock Timing Diagram with CHAN_ID=0
Single-Ended, Differential,
and Pseudo-Differential Input
DAC
The MAX11120–MAX11128 include up to 16 analog
input channels that can be configured to 16 single-ended
inputs, 8 fully differential pairs, or 15 pseudo-differential
inputs with respect to one common input (REF-/AIN15 is
the common input).
COMPARATOR
AINn
HOLD
AINn+1
(GND)
The analog input range is 0V to V
and pseudo-differential mode (unipolar) and ±V
in single-ended
REF+
/2 or
REF+
DAC
±V
in fully differential mode (bipolar) depending on
REF+
the RANGE register settings. See Table 7 for the RANGE
register setting.
Figure 3. Equivalent Input Circuit
Unipolar mode sets the differential input range from 0
to V
. If the positive analog input swings below the
REF+
Fully Differential Reference (REF+, REF-)
negative analog input in unipolar mode, the digital output
When the reference is used in fully differential mode
(REFSEL = 1), the full-scale range is set by the difference
between REF+ and REF-. The output clips if the input
signal surpasses this reference range.
code is zero. Selecting bipolar mode sets the differential
input range to ±V
/2 or ±V
depending on the
REF+
REF+
RANGE register settings (Table 7).
In single-ended mode, the ADC always operates in uni-
polar mode. The analog inputs are internally referenced
ADC Transfer Function
to GND with a full-scale input range from 0 to V
.
REF+
The output format of the MAX11120–MAX11128 is straight
binary in unipolar mode and two’s complement in bipolar
mode. The code transitions midway between successive
integer LSB values, such as 0.5 LSB, 1.5 LSB. Figure 4
and Figure 5 show the unipolar and bipolar transfer func-
tion, respectively. Output coding is binary, with 1 LSB =
Single-ended conversions are internally referenced to
GND (Figure 3).
The MAX11120–MAX11128 feature 15 pseudo differential
inputs by setting the PDIFF_COM bits in the Unipolar
register to 1 (Table 10). The 15 analog input signals inputs
are referenced to a DC signal applied to the REF-/AIN15.
V
/4096.
REF+
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
OUTPUT CODE (hex)
OUTPUT CODE (hex)
V
REF+
+FS =
FFF
FFE
FFD
FFC
FFB
FS = V
ZS = 0
1 LSB =
7FF
7FE
REF+
2
ZS = 0
-FS =
-V
REF+
V
REF+
2
V
4096
REF+
1 LSB =
001
000
FFF
FFE
4096
004
003
002
001
000
801
800
0
1
2
3
4
FS
-FS
0
+FS
FS -1.5 LSB
INPUT VOLTAGE (LSB)
-FS +0.5 LSB
+FS -1.5 LSB
INPUT VOLTAGE (LSB)
Figure 4. Unipolar Transfer Function for 12-Bit Resolution
Figure 5. Bipolar Transfer Function for 12-Bit Resolution
Control register (Table 2). The wake-up, acquisition, con-
version, and shutdown sequences are initiated through
CNVST and are performed automatically using the inter-
nal oscillator. Results are added to the internal FIFO.
Internal FIFO
The MAX11120–MAX11128 contain a FIFO buffer that can
hold up to 16 ADC results. This allows the ADC to handle
multiple internally clocked conversions without tying up
the serial bus. If the FIFO is filled and further conversions
are requested without reading from the FIFO, the oldest
ADC results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading channel address bits. After each falling edge of
CS, the oldest available byte of data is available at DOUT.
When the FIFO is empty, DOUT is zero.
With CS high, initiate a scan by setting CNVST low for
at least 5ns before pulling it high (Figure 6). Then, the
MAX11120–MAX11128 wake up, scan all requested chan-
nels, store the results in the FIFO, and shut down. After
the scan is complete, EOC is pulled low and the results
are available in the FIFO. Wait until EOC goes low before
pulling CS low to communicate with the serial interface.
EOC stays low until CS or CNVST is pulled low again.
Do not initiate a second CNVST before EOC goes low;
otherwise, the FIFO may become corrupted.
External Clock
In external clock mode, the analog inputs are sampled at
the falling edge of CS. Serial clock (SCLK) is used to per-
form the conversion. The sequencer reads in the channel
to be converted from the serial data input (DIN) at each
frame. The conversion results are sent to the serial output
(DOUT) at the next frame.
Alternatively, set SWCNV to 1 in the ADC Mode Control
register to initiate conversions with CS rising edge instead
of cycling CNVST (Table 2). For proper operation, CS
must be held low for 17 clock cycles to guarantee that the
device interprets the SWCNV setting. A delay is initiated
at the rising edge of CS and the conversion is started
when the delay times out. Upon completing the conver-
sion, this bit is reset to 0 (Figure 7). Apply a soft reset
when changing from internal to external clock mode:
RESET[1:0] = 10.
Internal Clock
The MAX11120–MAX11128 operate from an internal
oscillator, which is accurate within ±15% of the 13.33MHz
nominal clock rate. Request internally timed conversions
by writing the appropriate sequence to the ADC Mode
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
UP TO N INTERNALLY
CLOCKED ACQUISITIONS
AND CONVERSIONS
CNVST
CS
t
CSW
EOC
t
CNV_INT
1
16
1
16
SCLK
DIN
DOUT
INTERNAL
OSCILLATOR ON
READ DATA FROM FIFO
READ DATA FROM FIFO
SCAN OPERATION AND
RESULTS STORED IN FIFO
Figure 6. Internal Conversions with CNVST
UP TO N INTERNALLY
CLOCKED ACQUISITIONS
AND CONVERSIONS
t
CNV_INT
(N = 1)
CS
EOC
1
16
1
16
SCLK
SWCNV = 1
DIN
DOUT
MODE CONTROL
INTERNAL OSCILLATOR ON
READ DATA FROM FIFO
SCAN OPERATION AND
RESULTS STORED IN FIFO
Figure 7. Internal Conversions with SWCNV
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Custom Scan0 or Custom Scan1 registers. A new I/P
MUX is selected every frame on the thirteenth falling
edge of SCLK. Custom_Int works with the internal clock.
Custom_Ext works with the external clock.
Analog Input
The MAX11120–MAX11128 produce a digital output that
corresponds to the analog input voltage as long as the
analog inputs are within the specified operating range.
Internal protection diodes confine the analog input voltage
within the region of the analog power input rails (V
GND) and allow the analog input voltage to swing from
GND - 0.3V to V + 0.3V without damaging the device.
Input voltages beyond GND - 0.3V and V
ward bias the internal protection diodes. Limit the forward
diode current to less than 50mA to avoid damage to the
MAX11120–MAX11128.
Standard_Int and Standard_Ext
,
DD
In Standard_Int and Standard_Ext modes, the device
scans channels 0 through N in ascending order where
N is the last channel specified in the ADC Mode Control
register. A new I/P MUX is selected every frame on the
thirteenth falling edge of SCLK. Standard_Int works with
the internal clock. Standard_Ext works with the external
clock.
DD
+ 0.3V for-
DD
ECHO
Upper_Int and Upper_Ext
When writing to the ADC Configuration register, set
ECHO to 1 in ADC Configuration register to echo back
the configuration data onto DOUT at time n+1 (Figure 8,
Table 6).
In Upper_Int and Upper_Ext modes, the device scans
channels N through 15/11/7/3 in ascending order where
N is the first channel specified in the ADC Mode Control
register. A new I/P MUX is selected every frame on the
thirteenth falling edge of SCLK. Upper_Int works with the
internal clock. Upper_Ext works with the external clock.
Scan Modes
The MAX11120–MAX11128 feature nine scan modes
(Table 3).
SampleSet
The SampleSet mode of operation allows the definition of
a unique channel sequence combination with maximum
length of 256. SampleSet is supported only in the external
clock mode. SampleSet is ideally suited for multichannel
measurement applications where some analog inputs
must be converted more often than others.
Manual Mode
The next channel to be selected is identified in each SPI
frame. The conversion results are sent out in the next
frame. The manual mode works with the external clock
only. The FIFO is unused.
Repeat Mode
The SampleSet approach provides greater sequencing
flexibility for multichannel applications while alleviating
significant microcontroller or DSP (controlling unit) com-
munication overhead. SampleSet technology allows the
user to exploit available ADC input bandwidth without
need for constant communication between the ADC and
controlling unit. The user may define and load a unique
sequencing pattern into the ADC allowing both high- and
low-frequency inputs to be converted appropriately with-
out interface activity. With the unique sequence loaded
Repeat scanning channel N for number of times and store
all the conversion results in the FIFO. The number of
scans is programmed in the ADC Configuration register.
The repeat mode works with the internal clock only.
Custom_Int and Custom_Ext
In Custom_Int and Custom_Ext modes, the device scans
preprogrammed channels in ascending order. The chan-
nels to be scanned in sequence are programmed in the
t = n-1
t = n
t = n+1
t = n+2
CS
CONFIGURATION
DATA
CONFIGURATION
DATA
CONFIGURATION
DATA
DIN
TURN ON ECHO
CONFIGURATION
DATA
CONFIGURATION
DATA
DOUT
Figure 8. Echo Back the Configuration Data
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
into ADC memory, the pattern may be repeated indefi-
nitely or changed at any time.
the ADC can resolve (Nyquist Theorem) is 31.25kHz. If
all 16 channels must be measured, with some channels
having greater than 31.25kHz input frequency, the user
must revert back to manual mode requiring constant com-
munication on the serial interface. SampleSet technology
solves this problem. Figure 9 provides a SampleSet use-
model example.
For example, the maximum throughput of MAX11120–
MAX11128 is 1Msps. Traditional ADC scan modes allow
up to 16-channel conversions in ascending order. In this
case, the effective throughput per channel is 1Msps/16
channel or 62.5ksps. The maximum input frequency that
SampleSet REPEATS: LENGTH = 256
SAMPLE SET
(DEPTH = 256)
ST
ND
RD
3
TH
TH
5
TH
6
TH
7
TH
8
TH
9 CYCLE
1
CYCLE
2
CYCLE
CYCLE
4
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
POTENTIAL SampleSet PATTERN
AIN2/
AIN2/
AIN3
AIN2/
AIN3
AIN2/
AIN3
CHANNEL:
AIN0
2
AIN1
3
AIN0
4
AIN1
5
AIN0
AIN1
AIN3
AIN4
123
AIN5
124
AIN6
125
AIN7
126
AIN8
127
AIN9
128
AIN10 AIN11 AIN12 AIN13 AIN14 AIN15
129 130 131 132 133 134
AIN0
136
AIN1
137
AIN0
254
AIN1
255
1
120
121
122
135
256
ENTRY NO.:
120 CONVERSIONS:
AIN0 AND AIN1
120 CONVERSIONS:
AIN0 AND AIN1
ANALOG
INPUTS
AIN0
AIN1
100kHz
100 CYCLES
135
AIN2
FULLY
DIFFERENTIAL
10kHz
10 CYCLES
1
AIN3
122
123
124
125
256
1kHz
1 CYCLES
AIN4
AIN5
AIN6
t
= 1/f = 1/1Msps = 100ns
S
S
AIN7
CS
10
AIN8
8
AIN0
12
6
14
4
AIN9
16
32
10µs
2
18
30
T
S
5µs
AIN10
AIN11
AIN12
AIN13
20
28
22
f
= 100kHz
in
26
24
9
11
AIN1
7
13
5
15
3
17
31
19
5µs
10µs
T
S
29
21
27
23
25
Figure 9. SampleSet Use-Model Example
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Averaging Mode
Register Descriptions
In averaging mode, the device performs the specified
number of conversions and returns the average for each
requested result in the FIFO. The averaging mode works
with internal clock only.
The MAX11120–MAX11128 communicate between the
internal registers and the external circuitry through the
SPI-/QSPI-compatible serial interface. Table 1 details
the register access and control. Table 2 through Table 14
detail the various functions and configurations.
Scan Modes and Unipolar/Bipolar Setting
For ADC mode control, set bit 15 of the register code
identification to zero. The ADC Mode Control register
determines when and under what scan condition the ADC
operates.
When the Unipolar or Bipolar registers are configured
as pseudo-differential or fully differential, the analog
input pairs are repeated in this automated mode. For
example, if N is set to 15 to scan all 16 channels and
all analog input pairs are configured for fully-differential
conversion, the ADC converts the channels twice. In this
case, the user may avoid dual conversions on input pairs
by implementing Manual mode or using Custom_Int or
Custom_Ext scan modes.
To set the ADC data configuration, set the bit 15 of the
register code identification to one.
Table 1. Register Access and Control
REGISTER IDENTIFICATION CODE
DIN ≡ DATA INPUTS
REGISTER NAME
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT [10:0]
DIN
ADC Mode Control
ADC Configuration
Unipolar
0
1
1
1
1
1
1
1
1
DIN
0
DIN
0
DIN
0
DIN
0
DIN
0
0
0
1
DIN
Bipolar
0
0
1
0
DIN
RANGE
0
0
1
1
DIN
Custom Scan0
Custom Scan1
SampleSet
0
1
0
0
DIN
0
1
0
1
DIN
0
1
1
0
DIN
Reserved. Do not use.
1
1
1
1
DIN
Table 2. ADC Mode Control Register
DEFAULT
STATE
BIT NAME
BIT
FUNCTION
REG_CNTL
SCAN[3:0]
15
0
Set to 0 to select the ADC Mode Control register
ADC Scan Control register (Table 3)
14:11
0001
Analog Input Channel Select register (Table 4).
CHSEL[3:0]
10:7
6:5
0000
See Table 3 to determine which modes use CHSEL[3:0] for the channel scan
instruction.
RESET1
RESET0
FUNCTION
0
0
1
1
0
1
0
1
No reset
RESET[1:0]
00
Reset the FIFO only (resets to zero)
Reset all registers to default settings (includes FIFO)
Unused
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Table 2. ADC Mode Control Register (continued)
DEFAULT
STATE
BIT NAME
BIT
FUNCTION
Power Management Modes (Table 5). In external clock mode, PM[1:0] selects
between normal mode and various power-down modes of operation.
PM[1:0]
4:3
00
External Clock Mode. Channel address is always present in internal clock mode.
Set to 1, DOUT is a 16-bit data word containing a 4-bit channel address, followed by a
12-bit conversion result led by the MSB.
CHAN_ID
2
0
Set to 1 to initiate conversions with the rising edge of CS instead of cycling CNVST
(internal clock mode only).
This bit is used for the internal clock mode only and must be reasserted in the ADC
mode control, if another conversion is desired.
SWCNV
—
1
0
0
0
Unused
Table 3. ADC Scan Control
SCAN3 SCAN2 SCAN1 SCAN0
MODE NAME
FUNCTION
Continue to operate in the previously selected mode. Ignore data on
bits [10:0]. This feature is provided so that DIN can be held low when
no changes are required in the ADC Mode Control register. Bits [6:3, 1]
can be still written without changing the scan mode properties.
0
0
0
0
N/A
The next channel to be selected is identified in each SPI frame. The
conversion results are sent out in the next frame.
Clock mode: External clock only
0
0
0
1
Manual
Channel scan/sequence: Single channel per frame
Channel selection: See Table 4, CHSEL[3:0]
Averaging: No
Scans channel N repeatedly. The FIFO stores 4, 8, 12, or 16
conversion results for channel N.
Clock mode: Internal clock only
0
0
0
0
1
1
0
1
Repeat
Channel scan/sequence: Single channel per frame
Channel selection: See Table 4, CHSEL[3:0]
Averaging: Yes
Scans channels 0 through N. The FIFO stores N conversion results.
Clock mode: Internal clock
Standard_Int
Channel scan/sequence: N channels in ascending order
Channel selection: See Table 4, CHSEL[3:0] determines channel N
Averaging: Yes
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Table 3. ADC Scan Control (continued)
SCAN3 SCAN2 SCAN1 SCAN0
MODE NAME
FUNCTION
Scans channels 0 through N
Clock mode: External clock
0
1
0
0
Standard_Ext
Channel scan/sequence: N channels in ascending order
Channel selection: See Table 4, CHSEL[3:0] determines channel N
Averaging: No
Scans channel N through the highest numbered channel. The FIFO
stores X conversion results where:
X = Channel 16–N
X = Channel 8–N
16-channel devices
8-channel devices
4-channel devices
X = Channel 4–N
0
1
0
1
Upper_Int
Clock mode: Internal clock
Channel scan/sequence: Channel N through the highest numbered
channel in ascending order
Channel selection: See Table 4, CHSEL[3:0] determines channel N
Averaging: Yes
Scans channel N through the highest numbered channel
Clock mode: External clock
Channel scan/sequence: Channel N through the highest numbered
channel in ascending order
0
1
1
0
Upper_Ext
Channel selection: See Table 4, CHSEL[3:0] determines channel N
Averaging: No
Scans preprogrammed channels in ascending order. The FIFO stores
conversion results for this unique channel sequence.
Clock mode: Internal clock
Channel scan/sequence: Unique ascending channel sequence
Maximum depth: 16 conversions
0
1
1
1
Custom_Int
Channel selection: See Table 12, Custom Scan0 register and Table
13, Custom Scan1 register
Averaging: Yes
Scans preprogrammed channels in ascending order
Clock mode: External clock
Channel scan/sequence: Unique ascending channel sequence
Maximum depth: 16 conversions
1
0
0
0
Custom_Ext
Channel selection: See Table 12, Custom Scan0 register and Table
13, Custom Scan1 register
Averaging: No
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Table 3. ADC Scan Control (continued)
SCAN3 SCAN2 SCAN1 SCAN0
MODE NAME
FUNCTION
Scans preprogrammed channel sequence with maximum length of
256. There is no restriction on the channel pattern.
Clock mode: External clock only
Channel scan/sequence: Unique channel sequence
Maximum depth: 256 conversions
Channel Selection: See Table 4
Averaging: No
1
0
0
1
SampleSet
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
—
—
—
—
—
—
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
Table 4. Analog Input Channel Select
CHSEL3
CHSEL2
CHSEL1
CHSEL0
SELECTED CHANNEL (N)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
AutoShutdown with External Clock Mode
Power-Down Mode
When the PM_ bits in the ADC Mode Control register
are asserted (Table 5), the device shuts down at the ris-
ing edge of CS in the next frame. The device powers up
again at the following falling edge of CS. There are two
available options:
The MAX11120–MAX11128 feature three power-down
modes.
Static Shutdown
The devices shut down when the SPM bits in the ADC
Configuration register are asserted (Table 6). There are
two shutdown options:
● AutoShutdown where all circuitry is shutdown.
● AutoStandby where all circuitry are powered down
● Full shutdown where all circuitry is shutdown.
except for the internal bias generator.
● Partial shutdown where all circuitry is powered down
AutoShutdown with Internal Clock Mode
except for the internal bias generator.
The device shuts down after all conversions are complet-
ed. The device powers up again at the next falling edge
of CNVST or at the rising edge of CS after the SWCNV
bit is asserted.
Table 5. Power Management Modes
PM1
PM0
MODE
FUNCTION
0
0
Normal
All circuitry is fully powered up at all times.
The device enters full shutdown mode at the end of each conversion. All circuitry is
powered down. The device powers up following the falling edge of CS. It takes 2 cycles
before valid conversions take place. The information in the registers is retained.
0
1
AutoShutdown
The device powers down all circuitry except for the internal bias generator. The part
powers up following the falling edge of CS. It takes 2 cycles before valid conversions
take place. The information in the registers is retained.
1
1
0
1
AutoStandby
—
Unused.
Table 6. ADC Configuration Register
DEFAULT
STATE
BIT NAME
BIT
FUNCTION
CONFIG_SETUP
15:11
N/A
Set to 10000 to select the ADC Configuration register.
REFSEL
VOLTAGE REFERENCE
REF- CONFIGURATION
REFSEL
AVGON
10
9
0
0
0
1
External single-ended
AIN15 ( for the 16-channel devices)
REF-
External differential
Set to 1 to turn averaging on. Valid for internal clock mode only.
Set to 0 to turn averaging off.
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Table 6. ADC Configuration Register (continued)
DEFAULT
STATE
BIT NAME
BIT
FUNCTION
Valid for internal clock mode only.
AVGON NAVG1
NAVG0
FUNCTION
Performs 1 conversion for each requested
result.
0
1
1
1
1
X
0
0
1
1
X
Performs 4 conversions and returns the
average for each requested result.
0
1
0
1
NAVG[1:0]
8:7
00
Performs 8 conversions and returns the
average for each requested result.
Performs 16 conversions and returns the
average for each requested result.
Performs 32 conversions and returns the
average for each requested result.
Scans channel N and returns 4, 8, 12, or 16 results. Valid for repeat mode only.
NSCAN1
NSCAN0
FUNCTION
0
0
1
1
0
1
0
1
Scans channel N and returns 4 results.
Scans channel N and returns 8 results.
Scans channel N and returns 12 results.
Scans channel N and returns 16 results.
NSCAN[1:0]
6:5
00
Static power-down modes
SPM1
SPM0
MODE
Normal
Full
FUNCTION
0
0
All circuitry is fully powered up at all times.
All circuitry is powered down. The information
0
1
Shutdown in the registers is retained.
SPM[1:0]
4:3
00
All circuitry is powered down except for
the reference and reference buffer. The
information in the registers is retained.
Partial
Shutdown
1
1
0
1
—
Unused
Set to 0 to disable the instruction echo on DOUT.
ECHO
—
2
0
0
Set to 1 to echo back the DIN instruction given at time = n onto the DOUT line at
time = n + 1. It takes 1 full cycle for the echoing to begin (Figure 8).
1:0
Unused
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Table 7. RANGE Register (RANGE Settings Only Applies to Bipolar Fully Differential
Analog Input Configurations)
DEFAULT
STATE
BIT NAME
RANGE_SETUP
RANGE0/1
BIT
15:11
10
FUNCTION
N/A
Set to 10011 to select the RANGE register
Set to 0 for AIN0/1: ±V
Set to 1 for AIN0/1: ±V
/2
/2
/2
/2
/2
REF+
REF+
0
0
0
0
0
0
0
Set to 0 for AIN2/3: ±V
Set to 1 for AIN2/3: ±V
REF+
REF+
RANGE2/3
RANGE4/5
RANGE6/7
RANGE8/9
RANGE10/11
RANGE12/13
9
8
7
6
5
4
Set to 0 for AIN4/5: ±V
Set to 1 for AIN4/5: ±V
REF+
REF+
Set to 0 for AIN6/7: ±V
Set to 1 for AIN6/7: ±V
REF+
REF+
Set to 0 for AIN8/9: ±V
Set to 1 for AIN8/9: ±V
REF+
REF+
Set to 0 for AIN10/11: ±V
Set to 1 for AIN10/11: ±V
/2
REF+
REF+
Set to 0 for AIN12/13: ±V
Set to 1 for AIN12/13: ±V
/2
/2
REF+
REF+
Set to 0 for AIN14/15: ±V
Set to 1 for AIN14/15: ±V
REF+
REF+
RANGE14/15
—
3
0
2:0
000
Unused
ADC OUTPUT as a Function
of Unipolar and Bipolar Modes
The ADC Scan Control register (Table 3) determines the
ADC mode of operation. The Unipolar and Bipolar reg-
isters in Table 10 and Table 11 determine output coding
and whether input configuration is single-ended or fully
differential.
SampleSet Mode of Operation
The SampleSet register stores the unique channel
sequence length. The sequence pattern is comprised of
up to 256 unique single-ended and/or differential conver-
sions with any order or pattern.
Patterns are assembled in 4-bit channel identifier nib-
bles as described in Table 14. Figure 10 presents the
SampleSet timing diagram. Note that two CS frames are
required to configure the SampleSet functionality. The first
frame indicates the sequence length. The second frame is
used to encode the channel sequence pattern.
Table 9 details the conversion output for analog inputs,
AIN0 and AIN1. The truth table is consistent for any
other valid input pairs (AINn/AINn+1). Table 8 shows the
applicable input signal format with respect to analog input
configurations.
After the SampleSet register has been coded (Table 14),
by the next falling edge of CS, the new SampleSet pattern
is activated (Figure 10). If the pattern length is less than
SEQ_LENGTH, the remaining channels default to AIN0.
If the select pattern length is greater than SEQ_LENGTH,
the additional data is ignored as the ADC waits for the ris-
ing edge of CS. If CS is asserted in the middle of a nibble,
the full nibble defaults to AIN0.
CHSEL[3:0] is used for MANUAL, REPEAT, STANDARD_
EXT, STANDARD_INT, UPPER_EXT, UPPER_INT modes
of operation. CHSCAN[15:0] is used for CUSTOM_EXT
and CUSTOM_INT modes of operation.
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Table 8. Analog Input Configuration and Unipolar/Bipolar Waveforms
SUPPORTED WAVEFORMS
REFSEL = 0 REFSEL = 1
ANALOG INPUT
CONFIGURATION
UNIPOLAR/BIPOLAR
REGISTER SETTING
REF+
RANGE: 1V - V
REF+
RANGE: 1V - V
Table 10. Unipolar Register:
Set desired channel(s) to 0
or PDIFF_COM to 1.
V
IN+
V
IN+
DD
DD
Unipolar
(Binary
Coding)
Single-
Ended
REF+
REF+
Counterpart Register
1V
Table 11. Bipolar Register:
Set desired channel(s) to 0.
REF-
GND, AIN15
PDIFF_COM = 1
0V
-0.3V
REF+
REF+
RANGE: 1V - V
RANGE: 1V - V
DD
V
IN+
DD
Table 10. Unipolar Register:
Set desired channel(s) to 1.
V
IN+
Unipolar
(Binary
Coding)
Fully
Differential
REF+
REF+
V
V
IN-
V
IN-
Counterpart Register
Table 11. Bipolar Register:
Set desired channel(s) to 0.
V
IN-
IN-
(DC OFFSET
OR
1V
(DC OFFSET
OR
SINUSOID)
REF-
SINUSOID)
GND
0V
-0.3V
REF+
RANGE: 1V - V
REF+
RANGE: 1V - V
See Table 11. Bipolar
Register:
V
IN+
DD
DD
V
IN+
Set desired channel(s) to 1.
REF+
2
Fully
Differential
Bipolar
(2’s Comp)
REF+
REF+
V
IN-
V
IN-
Counterpart Register
1V
Table 10. Unipolar Register:
Set desired channel(s) to 0.
REF-
GND
0V
-0.3V
Table 9. ADC Output as a Function of Unipolar/Bipolar Register Settings
CHANNEL SELECTION
UNIPOLAR REGISTER
BIPOLAR REGISTER
FUNCTION
BIT NAME
UCH0/1 PDIFF_COM
BCH0/1
0
0
1
0
0
0
0
1
0
AIN0 (binary, unipolar)
AIN0/1 pair (two’s complement, bipolar)
AIN0/1 pair (binary, unipolar)
AIN0 Selection:
CHSEL[3:0] = 0000
CHSCAN0 = 1
AIN0/1 pair (binary, unipolar); Unipolar register
takes precedence
1
0
1
X
0
0
1
1
0
0
0
X
0
1
0
AIN0 referred to REF-/AIN15 (binary, unipolar)
AIN1 (binary, unipolar)
AIN0/1 pair (two’s complement, bipolar)
AIN0/1 pair (binary, unipolar)
AIN1 Selection:
CHSEL[3:0] = 0001
CHSCAN1 = 1
AIN0/1 pair (binary, unipolar), Unipolar register
takes precedence
1
0
1
1
X
X
AIN1 referred to REF-/AIN15 (binary, unipolar)
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Table 10. Unipolar Register
DEFAULT
STATE
BIT NAME
UNI_SETUP
UCH0/1
BIT
15:11
10
FUNCTION
—
Set to 10001 to select the Unipolar register.
Set to 1 to configure AIN0 and AIN1 for pseudo-differential conversion.
Set to 0 to configure AIN0 and AIN1 for single-ended conversion.
0
Set to 1 to configure AIN2 and AIN3 for pseudo-differential conversion.
Set to 0 to configure AIN2 and AIN3 for single-ended conversion.
Set to 1 to configure AIN4 and AIN5 for pseudo-differential conversion.
Set to 0 to configure AIN4 and AIN5 for single-ended conversion.
UCH2/3
UCH4/5
9
8
7
6
5
4
3
0
0
0
0
0
0
0
Set to 1 to configure AIN6 and AIN7 for pseudo-differential conversion.
Set to 0 to configure AIN6 and AIN7 for single-ended conversion.
UCH6/7
Set to 1 to configure AIN8 and AIN9 for pseudo-differential conversion.
Set to 0 to configure AIN8 and AIN9 for single-ended conversion.
Set to 1 to configure AIN10 and AIN11 for pseudo-differential conversion.
Set to 0 to configure AIN10 and AIN11 for single-ended conversion.
Set to 1 to configure AIN12 and AIN13 for pseudo-differential conversion.
Set to 0 to configure AIN12 and AIN13 for single-ended conversion.
Set to 1 to configure AIN14 and AIN15 for pseudo-differential conversion.
Set to 0 to configure AIN14 and AIN15 for single-ended conversion.
UCH8/9
UCH10/11
UCH12/13
UCH14/15
Set to 1 to configure AIN0–AIN14 to be referenced to one common DC voltage on
the REF-/AIN15. Set to 0 to disable the 15:1 pseudo differential mode.
PDIFF_COM
—
2
0
1:0
000
Unused.
Table 11. Bipolar Register
DEFAULT
STATE
BIT NAME
BIP_SETUP
BCH0/1
BIT
15:11
10
FUNCTION
—
Set to 10010 to select the Bipolar register.
Set to 1 to configure AIN0 and AIN1 for bipolar fully differential conversion.
Set to 0 to configure AIN0 and AIN1 for unipolar conversion mode.
0
Set to 1 to configure AIN2 and AIN3 for bipolar fully differential conversion.
Set to 0 to configure AIN2 and AIN3 for unipolar conversion mode.
BCH2/3
BCH4/5
9
8
7
6
5
4
0
0
0
0
0
0
Set to 1 to configure AIN4 and AIN5 for bipolar fully differential conversion.
Set to 0 to configure AIN4 and AIN5 for unipolar conversion mode.
Set to 1 to configure AIN6 and AIN7 for bipolar fully differential conversion.
Set to 0 to configure AIN6 and AIN7 for unipolar conversion mode.
BCH6/7
Set to 1 to configure AIN8 and AIN9 for bipolar fully differential conversion.
Set to 0 to configure AIN8 and AIN9 for unipolar conversion mode.
BCH8/9
Set to 1 to configure AIN10 and AIN11 for bipolar fully differential conversion.
Set to 0 to configure AIN10 and AIN11 for unipolar conversion mode.
BCH10/11
BCH12/13
Set to 1 to configure AIN12 and AIN13 for bipolar fully differential conversion.
Set to 0 to configure AIN12 and AIN13 for unipolar conversion mode.
Set to 1 to configure AIN14 and AIN15 for bipolar fully differential conversion.
Set to 0 to configure AIN14 and AIN15 for unipolar conversion mode.
BCH14/15
—
3
0
2:0
000
Unused.
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Table 12. Custom Scan0 Register
DEFAULT
STATE
BIT NAME
BIT
FUNCTION
CUST_SCAN0
CHSCAN15
CHSCAN14
CHSCAN13
CHSCAN12
CHSCAN11
CHSCAN10
CHSCAN9
CHSCAN8
—
15:11
—
0
Set to 10100 to select the Custom Scan0 register.
Set to 1 to scan AIN15. Set to 0 to omit AIN15.
Set to 1 to scan AIN14. Set to 0 to omit AIN14.
Set to 1 to scan AIN13. Set to 0 to omit AIN13.
Set to 1 to scan AIN12. Set to 0 to omit AIN12.
Set to 1 to scan AIN11. Set to 0 to omit AIN11.
Set to 1 to scan AIN10. Set to 0 to omit AIN10.
Set to 1 to scan AIN9. Set to 0 to omit AIN9.
Set to 1 to scan AIN8. Set to 0 to omit AIN8.
Unused.
10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2:0
000
Table 13. Custom Scan1 Register
DEFAULT
STATE
BIT NAME
BIT
FUNCTION
CUST_SCAN1
CHSCAN7
CHSCAN6
CHSCAN5
CHSCAN4
CHSCAN3
CHSCAN2
CHSCAN1
CHSCAN0
—
15:11
—
0
Set to 10101 to select the Custom Scan1 register.
Set to 1 to scan AIN7. Set to 0 to omit AIN7.
Set to 1 to scan AIN6. Set to 0 to omit AIN6.
Set to 1 to scan AIN5. Set to 0 to omit AIN5.
Set to 1 to scan AIN4. Set to 0 to omit AIN4.
Set to 1 to scan AIN3. Set to 0 to omit AIN3.
Set to 1 to scan AIN2. Set to 0 to omit AIN2.
Set to 1 to scan AIN1. Set to 0 to omit AIN1.
Set to 1 to scan AIN0. Set to 0 to omit AIN0.
Unused.
10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2:0
000
Table 14. SampleSet Register
DEFAULT
STATE
BIT NAME
BIT
FUNCTION
SMPL_SET
15:11
—
00000000
—
Set to 10110 to select the SampleSet register.
8-bit binary word indicating desired sequence length. The equation is:
Sequence length = SEQ_LENGTH + 1
00000000 = Sequence length = 1
11111111 = Sequence length = 256
Coding: Straight binary
SEQ_LENGTH
—
10:3
2:0
Maximum length: 256 ADC conversions
Unused.
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
CS
SCLK
DIN
1
16
1
1
ENTRY 1
ENTRY 2
ENTRY N = (SEQ_LENGTH)
DOUT
WRITE SampleSet REGISTER
DEFINE SEQ_LENGTH
LOAD SampleSet PATTERN
TIME BETWEEN CS FALLING AND
RISING EDGE DEPENDS IN SEQ_LENGTH
WRITE ADC MODE CONTROL
OR CONTINUE WITH ADDITIONAL
CONFIGURATION SETTINGS
Figure 10. SampleSet Timing Diagram
Upon receiving the SampleSet pattern, the user can
set the ADC Mode Control register to begin the conver-
sion process where data readout begins with the first
SampleSet entry. While the last conversion result is
read, the ADC can be instructed to enter AutoShutdown,
if desired. If the user wishes to change the SampleSet
length, a new pattern must be loaded into the ADC as
described in Figure 10.
Layout, Grounding, and Bypassing
For best performance, use PCBs with a solid ground
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
lines underneath the ADC package. Noise in the V
OVDD, and REF affects the ADC’s performance. Bypass
,
DD
the V , OVDD, and REF to ground with 0.1µF and 10µF
DD
bypass capacitors. Minimize capacitor lead and trace
lengths for best supply-noise rejection.
Applications Information
How to Program Modes
1) Configure the ADC (set the MSB on DIN to 1).
Choosing an Input Amplifier
It is important to match the settling time of the input ampli-
fier to the acquisition time of the ADC. The conversion
results are accurate when the ADC samples the input
signal for an interval longer than the input signal’s worst-
case settling time. By definition, settling time is the interval
between the application of an input voltage step and the
point at which the output signal reaches and stays within
a given error band centered on the resulting steady-state
amplifier output level. The ADC input sampling capaci-
tor charges during the sampling cycle, referred to as
the acquisition period. During this acquisition period, the
settling time is affected by the input resistance and the
input sampling capacitance. This error can be estimated
by looking at the settling of an RC time constant using
the input capacitance and the source impedance over
the acquisition time period. Figure 13 shows a typical
application circuit. The MAX4430, offering a settling time
of 37ns at 16-bit resolution, is an excellent choice for this
application. See the THD vs. Input Resistance graph in
the Typical Operating Characteristics.
2) Program ADC mode control (set the MSB on DIN to
0) to begin the conversion process or to control power
management features.
● If ADC mode control is written during a conversion
sequence, the ADC finishes the present conver-
sion and at the next falling edge of CS initiates its
new instruction.
● If configuration data (MSB on DIN is a 1) is written
during a conversion sequence, the ADC finishes
the present conversion in the existing scan mode.
However, data on DOUT is not valid in following
frames until a new ADC mode control instruction is
coded.
Programming Sequence Flow Chart
See Figure 11 for programming sequence.
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
SELECT REFERENCE
EXTERNAL SINGLE-ENDED
EXTERNAL DIFFERENTIAL
SINGLE-ENDED
OR DIFFERENTIAL
SELECT ADC
CONFIGURATION REGISTER
SET REFSEL BIT TO 1
SELECT ADC
CONFIGURATION REGISTER
SET REFSEL BIT TO 0
FIGURE OUT NUMBER
OF CHANNELS TO USE (N)
FOR EACH ADC CHANNEL
SINGLE-ENDED
PSEUDO-
DIFFERENTIAL
FULLY-
DIFFERENTIAL
SINGLE-ENDED
PSEUDO-
DIFFERENTIAL
UNIPOLAR OR
BIPOLAR
SE, PsD/FD
PSEUDO-DIFFERENTIAL
SINGLE-ENDED
BIPOLAR
UNIPOLAR
SELECT UNIPOLAR AND
BIPOLAR REGISTER SET PER
CHANNEL UCH{X}/{X+1}
AND BCH{X}/{X+1} TO 0 FOR
SINGLE-ENDED SELECTION
SELECT BIPOLAR REGISTER
SET PER CHANNEL
BCH{X}/{X+1} TO 1
SELECT UNIPOLAR AND
REGISTER SET BIT PDIFF_COM
TO 1 FOR PSEUDO-
SELECT UNIPOLAR
REGISTER SET PER
CHANNEL UCH{X}/{X+1}
TO 1 FOR UNIPOLAR
FOR BIPOLAR FULLY
DIFFERENTIAL
DIFFERENTIAL SELECTION
1
SELECT RANGE REGISTER SET PER CHANNEL
PAIR RANGE{X}/{X+1} TO 1 ±V
RANGE SELECT
0
REF+
SELECT RANGE REGISTER SET PER CHANNEL
PAIR RANGE{X}/{X+1} TO 0 ±V /2
FOR EACH ADC CHANNEL
REF+
NEXT CHANNEL
SEE FIGURE 12
Figure 11. ADC Programming Sequence
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
INTERNAL
EXTERNAL
INTERNAL/EXTERNAL
CLOCK
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0001
SET CHSEL[3:0] TO CHANNEL NUMBER
SELECT THE PM[1:0] BITS
YES
NO
REPEAT
NO
AVERAGE
YES
MANUAL
NO
YES
YES
YES
YES
YES
ADC CONFIGURATION REGISTER
SET AVG ON BIT TO 1
SET NAVG[1:0] TO N
ADC CONFIGURATION REGISTER
SET NSCAN[1:0] FOR SCAN COUNT
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0100
SET CHSEL[3:0] TO CHANNEL NUMBER
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0010
SET CHSEL[3:0] TO CHANNEL NUMBER
SELECT THE RIGHT SWCNV BIT
STANDARD-EXT
NO
YES
NO
STANDARD-INT
NO
AVERAGE
YES
ADC CONFIGURATION REGISTER
SET AVG ON BIT TO 1
SET NAVG[1:0] TO N
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0110
SET CHSEL[3:0] TO CHANNEL NUMBER
UPPER-EXT
NO
ADC MODE CONTROL REGISTER
SET SCA[3:0] TO 0011
SET CHSEL[3:0] TO CHANNEL NUMBER
SELECT THE RIGHT SWCNV BIT
YES
NO
UPPER-INT
NO
AVERAGE
YES
ADC CONFIGURATION REGISTER
SET AVG ON BIT TO 1
SET NAVG[1:0] TO N
SET CUSTOM Scan0 REGISTER
SET CUSTOM Scan1 REGISTER
CUSTOM-EXT
NO
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0101
SET CHSEL[3:0] TO CHANNEL NUMBER
SELECT THE RIGHT SWCNV BIT
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 1000
SET CHSEL[3:0] TO CHANNEL NUMBER
YES
NO
CUSTOM-INT
NO
AVERAGE
YES
ADC CONFIGURATION REGISTER
SET AVGON BIT TO 1
SET NAVG[1:0] TO N
SampleSet REGISTER
SET SEQ_DEPTH[7:0] TO SET
CHANNEL CAPTURE DEPTH
SampleSet
SET CUSTOM Scan0 REGISTER
SET CUSTOM Scan1 REGISTER
FOLLOW SampleSet REGISTER WITH
CHANNEL PATTERN OF THE SAME SIZE
AS SEQUENCE DEPTH
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0111
SET CHSEL[3:0] TO CHANNEL NUMBER
SELECT THE RIGHT SWCNV BIT
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 1001
SET CHSEL[3:0] TO CHANNEL NUMBER
Figure 12. ADC Mode Select Programming Sequence
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
● Initial voltage accuracy
● Temperature drift
Choosing a Reference
For devices using an external reference, the choice of the
reference determines the output accuracy of the ADC.
An ideal voltage reference provides a perfect initial accu-
racy and maintains the reference voltage independent
of changes in load current, temperature, and time. The
following parameters need to be considered in selecting
a reference:
● Current source capability
● Current sink capability
● Quiescent current
● Noise. The MAX6033 and MAX6043 are also excellent
reference choices (Figure 13).
+5V
0.1µF
10µF
V
DD
V
OVDD
100pF
V
DD
OVDD
0.1µF
10µF
0.1µF
10µF
500Ω
AGND
500Ω
4
3
5
INPUT 1
MAX11120–MAX11128
10Ω
1
AIN0
MAX4430
470pF
470pF
COG
CAPACITOR
V
DC
SCLK
SCLK
2
-5V
10µF
DOUT
AIN1
MISO
CPU
0.1µF
COG
CAPACITOR
INPUT 2
CS
SS
AIN15
MOSI
REF
DIN
+5V
GND
10µF
0.1µF
10µF
+5V
100pF
7
6
2
1
OUTF
OUTS
IN
1µF
0.1µF
500Ω
MAX6126
0.1µF
500Ω
4
3
4
3
5
GNDS
GND
NR
INPUT 2
10Ω
0.1µF
1
MAX4430
V
DC
2
-5V
10µF
0.1µF
Figure 13. Typical Application Circuit
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Total Harmonic Distortion
Total harmonic distortion (THD) is expressed as:
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nulled. The static
linearity parameters for the MAX11120–MAX11128 are
measured using the end-points method.
2
2
2
2
V
+ V + V + V
3 4 5
2
THD = 20 × log
V
1
where V is the fundamental amplitude, and V through V
5
are the amplitudes of the 2nd- through 5th-order harmonics.
1
2
Spurious-Free Dynamic Range
Differential Nonlinearity
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distor-
tion component.
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB or less guarantees no missing
codes and a monotonic transfer function.
Full-Power Bandwidth
Full-power bandwidth is the frequency at which the input
signal amplitude attenuates by 3dB for a full-scale input.
Signal-to-Noise Ratio
Signal-to-noise ratio is the ratio of the amplitude of the
desired signal to the amplitude of noise signals at a given
point in time. The larger the number, the better. The
theoretical minimum analog-to-digital noise is caused
by quantization error and results directly from the ADC’s
resolution (N bits):
Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the signal-
to-noise plus distortion (SINAD) is more than 68dB.
Intermodulation Distortion
SNR = (6.02 x N + 1.76) dB
Any device with nonlinearities creates distortion products
when two sine waves at two different frequencies (f1 and
f2) are input into the device. Intermodulation distortion
(IMD) is the total power of the IM2 to IM5 intermodula-
tion products to the Nyquist frequency relative to the total
input power of the two input tones, f1 and f2. The indi-
vidual input tone levels are at -6dBFS.
In reality, there are other noise sources besides quantiza-
tion noise, including thermal noise, reference noise, clock
jitter, etc. Therefore, SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first five
harmonics, and the DC offset.
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Ordering Information
PART
PIN-PACKAGE
BITS
8
SPEED (Msps)
NO. OF CHANNELS
MAX11120ATI+
MAX11121ATI+
MAX11122ATI+
MAX11123ATI+
MAX11124ATI+
MAX11125ATI+
MAX11126ATI+
MAX11127ATI+
MAX11128ATI+
MAX11128ATI/V+
28 TQFN-EP*
28 TQFN-EP*
28 TQFN-EP*
28 TQFN-EP*
28 TQFN-EP*
28 TQFN-EP*
28 TQFN-EP*
28 TQFN-EP*
28 TQFN-EP*
28 TQFN-EP*
1
1
1
1
1
1
1
1
1
1
4
4
10
12
8
4
8
10
12
8
8
8
16
16
16
16
10
12
12
Note: All devices are specified over the -40°C to +125°C temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE OUTLINE
LAND
PATTERN NO.
CODE
NO.
28 TQFN-EP
T2855+3
21-0140
90-0023
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
2
3
4
12/11
4/12
6/12
8/12
2/19
Initial release
—
39
Released the MAX11125
Released the MAX11120–MAX11124
Revised the Electrical Characteristics
Updated Electrical Characteristics and Ordering Information
39
5
1, 2, 39
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2019 Maxim Integrated Products, Inc.
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