MAX1092AEEG [MAXIM]
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface; 400ksps ， + 5V ，8 / 4通道， 10位ADC，带有+ 2.5V电压基准及并行接口
| 型号： | MAX1092AEEG |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface |
| 文件： | 总20页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1640; Rev 0; 1/00
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
General Description
Features
The MAX1090/MAX1092 low-power, 10-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2µs), on-chip clock, +2.5V internal reference, and
high-speed, byte-wide parallel interface. The devices
operate with a single +5V analog supply and feature a
ꢀ 10-Bit Resolution, 0ꢀ.5LB 5ineꢁaitꢂ
ꢀ +.V Lingle-Lupplꢂ Opeaꢁtion
ꢀ Usea-Adjustꢁble 5ogic 5evel (+2ꢀ7V to +.ꢀ.V)
ꢀ Inteanꢁl +2ꢀ.V Refeaence
V
pin that allows them to interface directly with a
LOGIC
ꢀ Loftwꢁae-Configuaꢁble Anꢁlog Input Multiplexea
8-Chꢁnnel Lingle-Ended/
+2.7V to +5.5V digital supply.
Power consumption is only 10mW (V
= V
) at a
DD
LOGIC
4-Chꢁnnel Pseudo-Diffeaentiꢁl (MAX1090)
400ksps max sampling rate. Two software-selectable
power-down modes enable the MAX1090/MAX1092 to
be shut down between conversions; accessing the par-
allel interface returns them to normal operation.
Powering down between conversions can cut supply
current to under 10µA at reduced sampling rates.
4-Chꢁnnel Lingle-Ended/
2-Chꢁnnel Pseudo-Diffeaentiꢁl (MAX1092)
ꢀ Loftwꢁae-Configuaꢁble Unipolꢁa/Bipolꢁa Anꢁlog
Inputs
ꢀ 5ow Cuaaent: 2ꢀ2mA (400ksps)
1ꢀ0mA (100ksps)
400µA (10ksps)
2µA (shutdown)
ꢀ Inteanꢁl 6MHz Full-Powea Bꢁndwidth Taꢁck/Hold
Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differen-
tial operation. In single-ended mode, the MAX1090 has
eight input channels and the MAX1092 has four input
channels (four and two input channels, respectively,
when in pseudo-differential mode).
ꢀ Bꢂte-Wide Pꢁaꢁllel (8+2) Inteafꢁce
Excellent dynamic performance and low power com-
bined with ease of use and small package size make
these converters ideal for battery-powered and data-
acquisition applications or for other circuits with
demanding power consumption and space require-
ments.
ꢀ Lmꢁll Footpaint: 28-Pin QLOP (MAX1090)
24-Pin QLOP (MAX1092)
Pin Configurations
The MAX1090 is available in a 28-pin QSOP package,
while the MAX1092 comes in a 24-pin QSOP. For pin-
compatible +3V, 10-bit versions, refer to the MAX1091/
MAX1093 data sheet.
TOP VIEW
HBEN
D7
1
2
3
4
5
6
7
8
9
24
23
V
V
LOGIC
DD
Applications
D6
22 REF
21 REFADJ
20 GND
19 COM
18 CH0
17 CH1
16 CH2
15 CH3
14 CS
D5
Industrial Control Systems
Energy Management
Data Logging
D4
Patient Monitoring
Touchscreens
MAX1092
D3
Data-Acquisition Systems
D2
D1/D9
D0/D8
Ordering Information
INT 10
RD 11
WR 12
IN5
TEMPꢀ RANGE PIN-PACKAGE
(5LB)
PART
13 CLK
MAX1090ACEI
0°C to +70°C 28 QSOP
0°C to +70°C 28 QSOP
0.5
1
MAX1090BCEI
QLOP
MAX1090AEEI -40°C to +85°C 28 QSOP
MAX1090BEEI -40°C to +85°C 28 QSOP
Ordering Information continued at end of data sheet.
0.5
1
Pin Configurations continued at end of data sheet.
Typical Operating Circuits appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
ABLO5UTE MAXIMUM RATINGL
V
DD
V
to GꢁD..............................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
to GꢁD.........................................................-0.3V to +6V
24-Pin QSOP (derate 9.5mW/°C above +70°C).........762mW
28-Pin QSOP (derate 8.00mW/°C above +70°C).......667mW
Operating Temperature ꢂanges
LOGIC
CH0–CH7, COM to GꢁD............................-0.3V to (V
ꢂEF, ꢂEFADꢃ to GꢁD.................................-0.3V to (V
+ 0.3V)
+ 0.3V)
DD
DD
Digital Inputs to GꢁD ...............................................-0.3V to +6V
MAX1090_C_ _/MAX1092_C_ _....................... 0°C to +70°C
MAX1090_E_ _/MAX1092_E_ _ .....................-40°C to +85°C
Storage Temperature ꢂange.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Digital Outputs (D0–D9, INT)
to GꢁD ........................................... -0.3V to (V
+ 0.3V)
LOGIC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
E5ECTRICA5 CHARACTERILTICL
(V
= V
= +5V 10ꢀ, COM = GꢁD, ꢂEFADꢃ = V , V
= +2.5V, 4.7µF capacitor at ꢂEF pin, f
= 7.6MHz (50ꢀ duty
DD
LOGIC
CLK
DD ꢂEF
cycle), T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIꢁ
PARAMETER
DC ACCURACY (ꢁote 1)
ꢂesolution
LYMBO5
CONDITIONL
MIN
TYP
MAX
UNITL
ꢂES
IꢁL
10
Bits
MAX109_A
MAX109_B
0.5
1
ꢂelative Accuracy (ꢁote 2)
LSB
Differential ꢁonlinearity
Offset Error
DꢁL
ꢁo missing codes over temperature
1
LSB
LSB
2
Gain Error (ꢁote 3)
Gain Temperature Coefficient
2
LSB
2.0
0.1
ppm/°C
Channel-to-Channel Offset
Matching
LSB
DYNAMIC LPECIFICATIONL (f
= 50kHz, V = 2.5Vp-p, 400ksps, external f
CLK
= 7.6MHz, bipolar input mode)
60
Iꢁ
Iꢁ
(sine wave)
SIꢁAD
Signal-to-ꢁoise Plus Distortion
dB
dB
Total Harmonic Distortion
(including 5th-order harmonic)
THD
-72
Spurious-Free Dynamic ꢂange
Intermodulation Distortion
Channel-to-Channel Crosstalk
Full-Linear Bandwidth
SFDꢂ
IMD
72
76
dB
dB
f
f
= 49kHz, f
= 52kHz
Iꢁ1
Iꢁ2
= 175kHz, V = 2.5Vp-p (ꢁote 4)
-78
350
6
dB
Iꢁ
Iꢁ
SIꢁAD > 56dB
-3dB rolloff
kHz
MHz
Full-Power Bandwidth
CONVERLION RATE
External clock mode
2.1
Conversion Time (ꢁote 5)
t
External acquisition/internal clock mode
Internal acquisition/internal clock mode
2.5
3.2
3.0
3.6
3.5
4
µs
COꢁV
T/H Acquisition Time
Aperture Delay
t
400
ns
ns
ACQ
External acquisition or external clock mode
External acquisition or external clock mode
Internal acquisition/internal clock mode
25
<50
<200
Aperture ꢃitter
ps
External Clock Frequency
Duty Cycle
f
0.1
30
7.6
70
MHz
ꢀ
CLK
2
_______________________________________________________________________________________
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
E5ECTRICA5 CHARACTERILTICL (continued)
(V
= V
= +5V 10ꢀ, COM = GꢁD, ꢂEFADꢃ = V , V
= +2.5V, 4.7µF capacitor at ꢂEF pin, f
= 7.6MHz (50ꢀ duty
DD
LOGIC
CLK
DD ꢂEF
cycle), T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIꢁ
PARAMETER
ANA5OG INPUTL
LYMBO5
CONDITIONL
MIN
TYP
MAX
UNITL
Analog Input Voltage ꢂange,
Single Ended and Differential
(ꢁote 6)
Unipolar, V
= 0
0
V
ꢂEF
COM
V
Iꢁ
V
Bipolar, V
= V
/ 2
-V
/2
+V
/2
ꢂEF
COM
ꢂEF
ꢂEF
Multiplexer Leakage Current
Input Capacitance
On/off-leakage current, V = 0 or V
0.01
12
1
µA
pF
Iꢁ
DD
C
Iꢁ
INTERNA5 REFERENCE
ꢂEF Output Voltage
2.49
2.5
15
2.51
V
mA
ꢂEF Short-Circuit Current
ꢂEF Temperature Coefficient
ꢂEFADꢃ Input ꢂange
TC
T
= 0°C to +70°C
20
ppm/°C
mV
A
ꢂEF
For small adjustments
100
ꢂEFADꢃ High Threshold
Load ꢂegulation (ꢁote 7)
Capacitive Bypass at ꢂEFADꢃ
Capacitive Bypass at ꢂEF
EXTERNA5 REFERENCE AT REF
To power down the internal reference
0 to 0.5mA output load
V
DD
- 1.0
V
0.2
0.5
1
mV/mA
µF
0.01
4.7
1.0
10
µF
V
+
DD
50mV
ꢂEF Input Voltage ꢂange
V
ꢂEF
V
V
= 2.5V, f
= 400ksps
SAMPLE
200
300
2
ꢂEF
Shutdown ꢂEF Input Current
DIGITA5 INPUTL AND OUTPUTL
Input Voltage High
I
µA
ꢂEF
Shutdown mode
V
V
V
= 4.5V
4.0
2.0
LOGIC
LOGIC
LOGIC
V
V
IH
= 2.7V
Input Voltage Low
Input Hysteresis
V
= 4.5V or 2.7V
0.8
1
V
mV
µA
pF
V
IL
V
200
0.1
15
HYS
Input Leakage Current
Input Capacitance
Output Voltage Low
Output Voltage High
I
Iꢁ
V
Iꢁ
= 0 or V
DD
C
Iꢁ
OL
OH
V
I
I
= 1.6mA
0.4
1
SIꢁK
V
= 1mA
V
- 0.5
V
SOUꢂCE
LOGIC
Three-State Leakage Current
I
0.1
15
µA
pF
CS = V
CS = V
LEAKAGE
DD
DD
Three-State Output Capacitance
C
OUT
_______________________________________________________________________________________
3
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
E5ECTRICA5 CHARACTERILTICL (continued)
(V
= V
= +5V 10ꢀ, COM = GꢁD, ꢂEFADꢃ = V , V
= +2.5V, 4.7µF capacitor at ꢂEF pin, f
= 7.6MHz (50ꢀ duty
DD
LOGIC
CLK
DD ꢂEF
cycle), T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIꢁ
PARAMETER
POWER REQUIREMENTL
Analog Supply Voltage
LYMBO5
CONDITIONL
MIN
TYP
MAX
UNITL
V
DD
4.5
2.7
5.5
V
V
V
DD
+
Digital Supply Voltage
V
LOGIC
0.3
Internal reference
2.6
2.2
1.0
0.5
2
2.9
2.5
1.2
0.8
10
Operating mode,
= 400ksps
f
SAMPLE
External reference
Internal reference
External reference
mA
Positive Supply Current
I
DD
Standby mode
Shutdown mode
µA
µA
mV
f
= 400ksps
200
10
SAMPLE
V
Current
I
C = 20pF
L
LOGIC
LOGIC
ꢁonconverting
= 5V 10ꢀ, full-scale input
2
Power-Supply ꢂejection
PSꢂ
V
DD
0.3
0.7
TIMING CHARACTERILTICL
(V
= V
= +5V 10ꢀ, COM = GꢁD, ꢂEFADꢃ = V , V
= +2.5V, 4.7µF capacitor at ꢂEF pin, f
= 7.6MHz (50ꢀ duty
DD
LOGIC
CLK
DD ꢂEF
cycle), T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIꢁ
PARAMETER
CLK Period
LYMBO5
CONDITIONL
MIN
132
40
40
40
0
TYP
MAX
UNITL
ns
t
CP
CH
CLK Pulse Width High
t
ns
CLK Pulse Width Low
t
ns
CL
DS
t
t
ns
Data Valid to WR ꢂise Time
WR ꢂise to Data Valid Hold Time
WR to CLK Fall Setup Time
CLK Fall to WR Hold Time
CS to CLK or WR Setup Time
CLK or WR to CS Hold Time
CS Pulse Width
ns
DH
t
t
40
40
60
0
ns
CWS
ns
CWH
t
ns
CSWS
t
ns
CSWH
t
100
60
ns
CS
t
ns
WR Pulse Width (ꢁote 8)
Wꢂ
4
_______________________________________________________________________________________
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
TIMING CHARACTERILTICL (continued)
(V
= V
= +5V 10ꢀ, COM = GꢁD, ꢂEFADꢃ = V , V
= +2.5V, 4.7µF capacitor at ꢂEF pin, f
= 7.6MHz (50ꢀ duty
DD
LOGIC
CLK
DD ꢂEF
cycle), T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIꢁ
PARAMETER
LYMBO5
CONDITIONL
= 20pF, Figure 1
MIN
10
TYP
MAX
60
UNITL
ns
t
TC
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
CS ꢂise to Output Disable
RD ꢂise to Output Disable
RD Fall to Output Data Valid
HBEꢁ ꢂise to Output Data Valid
HBEꢁ Fall to Output Data Valid
RD Fall to INT High Delay
CS Fall to Output Data Valid
t
Tꢂ
= 20pF, Figure 1
= 20pF, Figure 1
= 20pF, Figure 1
= 20pF, Figure 1
= 20pF, Figure 1
= 20pF, Figure 1
10
40
ns
t
10
50
ns
DO
t
t
t
10
50
ns
DO1
DO1
10
80
ns
50
ns
IꢁT1
t
100
ns
DO2
Note 1: Tested at V
= +5V, COM = GꢁD, unipolar single-ended input mode.
DD
Note 2: ꢂelative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note .: Conversion time is defined as the number of clock cycles times the clock period; clock has 50ꢀ duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GꢁD to V
Note 7: External load should not change during conversion for specified accuracy.
.
DD
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
V
LOGIC
3k
DOUT
DOUT
C
LOAD
20pF
C
LOAD
20pF
3k
a) HIGH-Z TO V AND V TO V
OH
b) HIGH-Z TO V AND V TO V
OL
OH
OL
OL
OH
Figure 1. Load Circuits for Enable/Disable Times
_______________________________________________________________________________________
.
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Characteristics
(V
= V
= +5V, V
= +2.500V, f
= 7.6MHz, C = 20pF, T = +25°C, unless otherwise noted.)
DD
LOGIC
CLK L A
ꢂEF
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
SUPPLY CURRENT
vs. SAMPLE FREQUENCY
0.25
0.20
0.15
0.10
0.05
0
0.25
0.20
0.15
0.10
0.05
0
10k
1k
WITH INTERNAL
REFERENCE
100
10
1
-0.05
-0.10
-0.15
-0.20
-0.25
-0.05
-0.10
-0.15
-0.20
-0.25
WITH EXTERNAL
REFERENCE
0
200
400
600
800 1000 1200
0
200
400 600
800 1000 1200
0.1
1
10 100
1k 10k 100k 1M
(Hz)
OUTPUT CODE
OUTPUT CODE
f
SAMPLE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
STANDBY CURRENT vs. SUPPLY VOLTAGE
2.2
2.1
2.0
2.3
2.2
2.1
2.0
1.9
1.8
1.7
990
980
970
960
950
940
930
R = ∞
R = ∞
L
L
CODE = 1010100000
CODE = 1010100000
1.9
1.8
4.50
4.75
5.00
(V)
5.25
5.50
-40
-15
10
35
60
85
4.50
4.75
5.00
(V)
5.25
5.50
V
TEMPERATURE (°C)
V
DD
DD
POWER-DOWN CURRENT
vs. SUPPLY VOLTAGE
POWER-DOWN CURRENT
vs. TEMPERATURE
STANDBY CURRENT vs. TEMPERATURE
3.0
2.5
2.0
1.5
1.0
2.2
2.1
2.0
990
980
970
960
950
940
930
1.9
1.8
4.50
4.75
5.00
(V)
5.25
5.50
-40
-15
10
35
60
85
-40
-15
10
35
60
85
V
TEMPERATURE (°C)
TEMPERATURE (°C)
DD
6
_______________________________________________________________________________________
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Characteristics (continued)
(V
= V
= +5V, V
= +2.500V, f
= 7.6MHz, C = 20pF, T = +25°C, unless otherwise noted.)
DD
LOGIC
CLK L A
ꢂEF
OFFSET ERROR
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.53
2.53
2.52
2.51
2.50
2.49
2.48
1.0
0.5
0
2.52
2.51
2.50
2.49
2.48
-0.5
-1.0
4.50
4.75
5.00
(V)
5.25
5.50
-40
-15
10
35
60
85
4.50
4.75
5.00
(V)
5.25
5.50
V
TEMPERATURE (°C)
V
DD
DD
OFFSET ERROR
vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
1.0
0.5
0
0.50
0.25
0
0.500
0.375
0.250
0.125
0
-0.5
-1.0
-0.25
-0.50
-40
-15
10
35
60
85
4.50
4.75
5.00
(V)
5.25
5.50
-40
-15
10
35
60
85
TEMPERATURE (°C)
V
TEMPERATURE (°C)
DD
LOGIC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
LOGIC SUPPLY CURRENT
vs. TEMPERATURE
FFT PLOT
250
200
150
20
0
250
200
150
100
50
V
= 5V
DD
= 50kHz
f
f
IN
SAMPLE
= 400ksps
-20
-40
-60
-80
-100
-120
-140
100
50
0
4.50
4.75
5.00
(V)
5.25
5.50
0
200
400
600
800 1000 1200
-40
-15
10
35
60
85
V
FREQUENCY (kHz)
TEMPERATURE (°C)
DD
_______________________________________________________________________________________
7
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description
PIN
NAME
FUNCTION
MAX1090 MAX1092
High Byte Enable. Used to multiplex the 10-bit conversion result.
1: 2 MSBs are multiplexed on the data bus.
1
1
HBEꢁ
0: 8 LSBs are available on the data bus.
2
3
2
3
D7
D6
Three-State Digital I/O Line (D7)
Three-State Digital I/O Line (D6)
4
4
D5
Three-State Digital I/O Line (D5)
5
5
D4
Three-State Digital I/O Line (D4)
6
6
D3
Three-State Digital I/O Line (D3)
7
7
D2
Three-State Digital I/O Line (D2)
8
8
D1/D9
D0/D8
INT
Three-State Digital I/O Line (D1, HBEꢁ = 0; D9, HBEꢁ = 1)
Three-State Digital I/O Line (D0, HBEꢁ = 0; D8, HBEꢁ = 1)
INT goes low when the conversion is complete and the output data is ready.
9
9
10
10
Active-Low ꢂead Select. If CS is low, a falling edge on RD will enable the read operation on
the data bus.
11
12
13
11
12
13
RD
Active-Low Write Select. When CS is low in internal acquisition mode, a rising edge on WR
latches in configuration data and starts an acquisition plus a conversion cycle. When CS is
low in external acquisition mode, the first rising edge on WR ends acquisition and starts a
conversion.
WR
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock.
CLK
In internal clock mode, connect this pin to either V
or GꢁD.
DD
14
15
16
17
18
19
20
21
22
14
—
—
—
—
15
16
17
18
CS
Active-Low Chip Select. When CS is high, digital outputs (INT, D7–D0) are high impedance.
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
Analog Input Channel 7
Analog Input Channel 6
Analog Input Channel 5
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
Ground ꢂeference for Analog Inputs. Sets zero-code voltage in single-ended mode and
must be stable to 0.5LSB during conversion.
23
24
19
20
COM
GꢁD
Analog and Digital Ground
Bandgap ꢂeference Output/Bandgap ꢂeference Buffer Input. Bypass to GꢁD with a 0.01µF
25
21
ꢂEFADꢃ
ꢂEF
capacitor. When using an external reference, connect ꢂEFADꢃ to V
bandgap reference.
to disable the internal
DD
Bandgap ꢂeference Buffer Output/External ꢂeference Input. Add a 4.7µF capacitor to GꢁD
when using the internal reference.
26
27
28
22
23
24
V
DD
Analog +5V Power Supply. Bypass with a 0.1µF capacitor to GꢁD.
Digital Power Supply. V
powers the digital outputs of the data converter and can range
LOGIC
V
LOGIC
from +2.7V to V
+ 300mV.
DD
8
_______________________________________________________________________________________
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
REF
REFADJ
17k
1.22V
REFERENCE
A =
V
2.05
(CH7)
(CH6)
(CH5)
(CH4)
CH3
CH2
CH1
CH0
ANALOG
INPUT
MULTIPLEXER
T/H
CHARGE REDISTRIBUTION
10-BIT DAC
COMP
10
SUCCESSIVE-
COM
APPROXIMATION
REGISTER
CLK
CLOCK
MAX1090
MAX1092
2
8
CS
WR
RD
2
8
CONTROL LOGIC
AND
MUX
8
LATCHES
HBEN
INT
V
DD
8
V
LOGIC
THREE-STATE, BIDIRECTIONAL
I/O INTERFACE
GND
D0–D7
8-BIT DATA BUS
( ) ARE FOR MAX1090 ONLY.
Figure 2. Simplified Functional Diagram of 8-/4-Channel MAX1090/MAX1092
In differential mode, Iꢁ- and Iꢁ+ are internally switched to
either of the analog inputs. This configuration is pseudo-
differential in that only the signal at Iꢁ+ is sampled. The
return side (Iꢁ-) must remain stable within 0.5LSB
( 0.1LSB for best performance) with respect to GꢁD
during a conversion. To accomplish this, connect a
0.1µF capacitor from Iꢁ- (the selected input) to GꢁD.
Detailed Description
Converter Operation
The MAX1090/MAX1092 ADCs use a successive-
approximation (SAꢂ) conversion technique and an
input track-and-hold (T/H) stage to convert an analog
input signal to a 10-bit digital output. Their parallel 8+2
output format provides an easy interface to standard
microprocessors (µPs). Figure 2 shows the simplified
internal architecture of the MAX1090/MAX1092.
During the acquisition interval, the channel selected as
the positive input (Iꢁ+) charges capacitor C
. At
HOLD
the end of the acquisition interval, the T/H switch
opens, retaining the charge on C
the signal at Iꢁ+.
as a sample of
HOLD
Single-Ended and
Pseudo-Differential Operation
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuits in
Figures 3a and 3b. In single-ended mode, Iꢁ+ is inter-
nally switched to channels CH0–CH7 for the MAX1090
(Figure 3a) and to CH0–CH3 for the MAX1092 (Figure
3b), while Iꢁ- is switched to COM (Table 3). In differen-
tial mode, Iꢁ+ and Iꢁ- are selected from analog input
pairs (Table 4).
The conversion interval begins with the input multiplex-
er switching C from the positive input (Iꢁ+) to the
HOLD
negative input (Iꢁ-). This unbalances node ZEꢂO at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node ZEꢂO to 0V within
the limits of 10-bit resolution. This action is equivalent to
transferring a 12pF [(V ) - (V )] charge from C
HOLD
Iꢁ+
Iꢁ-
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
_______________________________________________________________________________________
9
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
10-BIT CAPACITIVE DAC
10-BIT CAPACITIVE DAC
REF
REF
COMPARATOR
COMPARATOR
INPUT
MUX
INPUT
MUX
C
C
HOLD
HOLD
ZERO
ZERO
–
+
–
+
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
CH0
CH1
12pF
12pF
R
R
IN
IN
800Ω
800Ω
C
C
SWITCH
SWITCH
CH2
CH3
HOLD
HOLD
TRACK
TRACK
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
T/H
SWITCH
T/H
SWITCH
COM
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7
SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1 AND CH2/CH3
Figure 3a. MAX1090 Simplified Input Structure
Figure 3b. MAX1092 Simplified Input Structure
allowed between conversions. The acquisition time,
ACQ
the signal and is also the minimum time required for the
signal to be acquired. Calculate this with the following
equation:
Analog Input Protection
t
, is the maximum time the device takes to acquire
Internal protection diodes, which clamp the analog
input to V
and GꢁD, allow each input channel to
DD
swing within (GꢁD - 300mV) to (V
+ 300mV) without
DD
damage. However, for accurate conversions near full
scale, neither input should exceed (V
less than (GꢁD - 50mV).
+ 50mV) or be
DD
t
= 7 (ꢂ + ꢂ )C
S Iꢁ Iꢁ
ACQ
where ꢂ is the source impedance of the input signal,
S
If ꢁn off-chꢁnnel ꢁnꢁlog input voltꢁge exceeds the
supplies bꢂ moae thꢁn .0mV, limit the foawꢁad-biꢁs
input cuaaent to 4mAꢀ
ꢂ
(800Ω) is the input resistance, and C (12pF) is
Iꢁ
Iꢁ
the input capacitance of the ADC. Source impedances
below 3kΩ have no significant impact on the MAX1090/
MAX1092’s AC performance.
Track/Hold
The MAX1090/MAX1092 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part enters
its hold mode on the fourth falling edge of the clock after
writing the control byte. ꢁote that in internal clock mode,
this is approximately 1µs after writing the control byte.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Along with the input impedance, this capacitor forms
an ꢂC filter, limiting the ADC’s signal bandwidth.
Input Bandwidth
The MAX1090/MAX1092 T/H stage offers a 350kHz full-
linear and a 6MHz full-power bandwidth. These fea-
tures make it possible to digitize high-speed transients
and measure periodic signals with bandwidths exceed-
ing the ADC’s sampling rate by using undersampling
techniques. To avoid aliasing high-frequency signals
into the frequency band of interest, anti-alias filtering is
recommended.
In single-ended operation, Iꢁ- is connected to COM
and the converter samples the positive (+) input. In
pseudo-differential operation, Iꢁ- connects to the nega-
tive input (-) and the difference of (Iꢁ+) - (Iꢁ-) is sam-
|
|
pled. At the beginning of the next conversion, the
positive input connects back to Iꢁ+ and C
charges to the input signal.
HOLD
Starting a Conversion
Initiate a conversion by writing a control byte that
selects the multiplexer channel and configures the
MAX1090/MAX1092 for either unipolar or bipolar opera-
tion. A write pulse (WR + CS) can either start an acqui-
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
10 ______________________________________________________________________________________
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
sition interval or initiate a combined acquisition plus
conversion. The sampling interval occurs at the end of
the acquisition interval. The ACQMOD (acquisition
mode) bit in the input control byte (Table 1) offers two
options for acquiring the signal: an internal and an
external acquisition. The conversion period lasts for 13
clock cycles in either the internal or external clock or
acquisition mode. Writing a new control byte during a
conversion cycle will abort the conversion and start a
new acquisition interval.
and start-of-conversion with two separate write pulses.
The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0 (all other bits in
the control byte are unchanged), terminates acquisition
and starts conversion on WR rising edge (Figure 5).
The address bits for the input multiplexer must have the
same values on the first and second write pulses.
Power-down mode bits (PD0, PD1) can assume new
values on the second write pulse (see the Power-Down
Modes section). Changing other bits in the control byte
will corrupt the conversion.
Internal Acquisition
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this acquisition interval (three external clock
cycles or approximately 1µs in internal clock mode)
ends (Figure 4). When the internal acquisition is com-
bined with the internal clock, the aperture jitter can be
as high as 200ps. Internal clock users wishing to
achieve the 50ps jitter specification should always use
external acquisition mode.
Reading a Conversion
A standard interrupt signal, INT, is provided to allow the
MAX1090/MAX1092 to flag the µP when the conversion
has ended and a valid result is available. INT goes low
when the conversion is complete and the output data
is ready (Figures 4 and 5). INT returns high on the first
read cycle or if a new control byte is written.
Selecting Clock Mode
The MAX1090/MAX1092 operate with an internal or
external clock. Control bits D6 and D7 select either
internal or external clock mode. The part retains the
last-requested clock mode if a power-down mode is
selected in the current input word. For both internal and
external clock modes, internal or external acquisition
External Acquisition
Use external acquisition mode for precise control of the
sampling aperture and/or dependent control of acquisi-
tion and conversion times. The user controls acquisition
Tꢁble 1ꢀ Contaol Bꢂte Functionꢁl Descaiption
BIT
NAME
FUNCTION
PD1 and PD0 select the various clock and power-down modes.
0
0
1
1
0
1
0
1
Full Power-Down Mode. Clock mode is unaffected.
D7, D6
PD1, PD0
Standby Power-Down Mode. Clock mode is unaffected.
ꢁormal Operation Mode. Internal clock mode is selected.
ꢁormal Operation Mode. External clock mode is selected.
ACQMOD = 0: Internal Acquisition Mode
ACQMOD = 1: External Acquisition Mode
D5
D4
ACQMOD
SGL/DIF = 0: Pseudo-Differential Analog Input Mode
SGL/DIF = 1: Single-Ended Analog Input Mode
In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
SGL/DIF
UꢁI/BIP = 0: Bipolar Mode
UꢁI/BIP = 1: Unipolar Mode
In unipolar mode, an analog input signal from 0 to V
D3
UꢁI/BIP
can be converted; in bipolar mode, the
ꢂEF
signal can range from -V /2 to +V
ꢂEF
/2.
ꢂEF
Address bits A2–A0 select which of the 8/4 (MAX1090/MAX1092) channels is to be converted
(Tables 3 and 4).
D2, D1, D0
A2, A1, A0
______________________________________________________________________________________ 11
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
t
CS
CS
t
ACQ
t
CONV
t
t
CSWH
CSWS
t
WR
WR
t
DH
t
DS
CONTROL
BYTE
D7–D0
ACQMOD = "0"
t
INT1
INT
RD
HBEN
t
t
t
TR
D0
D01
HIGH-Z
HIGH-Z
HIGH/LOW
HIGH/LOW
BYTE VALID
BYTE VALID
DOUT
Figure 4. Conversion Timing Using Internal Acquisition Mode
t
CS
CS
t
t
t
CONV
CSWS
ACQ
t
WR
t
t
CSHW
WR
DH
t
DS
CONTROL
BYTE
ACQMOD = "1"
CONTROL
BYTE
ACQMOD = "0"
D7–D0
INT
t
INT1
RD
HBEN
t
D01
t
D0
t
TR
HIGH-Z
HIGH-Z
HIGH/LOW
HIGH/LOW
BYTE VALID
BYTE VALID
DOUT
Figure 5. Conversion Timing Using External Acquisition Mode
12 ______________________________________________________________________________________
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
can be used. At power-up, the MAX1090/MAX1092
enter the default external clock mode.
CLK pin either high or low to prevent the pin from float-
ing.
Internal Clock Mode
Select internal clock mode to release the µP from the
burden of running the SAꢂ conversion clock. To select
this mode, bit D7 of the control byte must be set to 1
and bit D6 must be set to 0; the internal clock frequen-
cy is then selected, resulting in a 3.6µs conversion
time. When using the internal clock mode, connect the
External Clock Mode
To select the external clock mode, bits D6 and D7 of
the control byte must be set to one. Figure 6 shows the
clock and WR timing relationship for internal (Figure 6a)
and external (Figure 6b) acquisition modes with an
external clock. Proper operation requires a 100kHz to
7.6MHz clock frequency with 30ꢀ to 70ꢀ duty cycle.
Operating the MAX1090/MAX1092 with clock frequen-
ACQUISITION STARTS
CONVERSION STARTS
ACQUISITION ENDS
t
CP
CLK
WR
t
t
CL
CH
t
CWS
WR GOES HIGH WHEN CLK IS HIGH.
ACQMOD = "0"
ACQUISITION STARTS
t
CWH
ACQUISITION ENDS
CONVERSION STARTS
CLK
WR
ACQMOD = "0"
WR GOES HIGH WHEN CLK IS LOW.
Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
t
CWS
t
DH
WR
ACQMOD = "0"
WR GOES HIGH WHEN CLK IS HIGH.
ACQMOD = "1"
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
WR
tCWH
t
DH
ACQMOD = "1"
WR GOES HIGH WHEN CLK IS LOW.
ACQMOD = "0"
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
______________________________________________________________________________________ 13
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
cies lower than 100kHz is not recommended because it
will cause a voltage droop across the hold capacitor in
the T/H stage that will result in degraded performance.
Input Format
The control byte is latched into the device on pins D7–
D0 during a write command. Table 2 shows the control
byte format.
Digital Interface
Input (control byte) and output data are multiplexed on
a three-state parallel interface. This parallel interface
(I/O) can easily be interfaced with standard µPs. The
signals CS, WR, and RD control the write and read
operations. CS represents the chip-select signal, which
enables a µP to address the MAX1090/MAX1092 as an
I/O port. When high, CS disables the CLK, WR, and RD
inputs and forces the interface into a high-impedance
(high-Z) state.
Output Format
The output format for the MAX1090/MAX1092 is binary in
unipolar mode and two’s complement in bipolar mode.
When reading the output data, CS and RD must be low.
When HBEꢁ = 0, the lower 8 bits are read. With HBEꢁ =
1, the upper 2 bits are available and the output data bits
D7–D2 are set either low in unipolar mode or to the value
of the MSB in bipolar mode (Table 5).
Tꢁble 2ꢀ Contaol Bꢂte Foamꢁt
D7 (MLB)
D6
D.
D4
D3
D2
D1
D0 (5LB)
PD1
PD0
ACQMOD
A2
A1
A0
SGL/DIF
UꢁI/BIP
Tꢁble 3ꢀ Chꢁnnel Lelection foa Lingle-Ended Opeaꢁtion (LG5/DIF = 1)
A2
A1
A0
CH0
CH1
CH2
CH3
CH4*
CH.*
CH6*
CH7*
COM
0
0
0
+
-
-
-
-
-
-
-
-
0
0
1
+
0
1
0
+
0
1
1
+
1
0
0
+
1
0
1
+
1
1
0
+
1
1
1
+
*Channels CH4–CH7 apply to MAX1090 only.
Tꢁble 4ꢀ Chꢁnnel Lelection foa Pseudo-Diffeaentiꢁl Opeaꢁtion (LG5/DIF = 0)
A2
0
A1
0
A0
0
CH0
CH1
CH2
CH3
CH4*
CH.*
CH6*
CH7*
+
-
-
0
0
1
+
0
1
0
+
-
-
0
1
1
+
1
0
0
+
-
-
1
0
1
+
1
1
0
+
-
-
1
1
1
+
*Channels CH4–CH7 apply to MAX1090 only.
14 ______________________________________________________________________________________
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Tꢁble .ꢀ Dꢁtꢁ-Bus Output (8+2 Pꢁaꢁllel
Inteafꢁce)
V
= +5V
DD
50k
50k
PIN
HBEN = 0
HBEN = 1
MAX1090
MAX1092
D0
Bit 0 (LSB)
Bit 1
Bit 8
330k
D1
Bit 9 (MSB)
REFADJ
REF
BIPO5AR
UNIPO5AR
4.7µF
(UNI/BIP = 0)
(UNI/BIP = 1)
GND
0.01µF
D2
D3
D4
D5
D6
D7
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 9
Bit 9
Bit 9
Bit 9
Bit 9
Bit 9
0
0
0
0
0
0
Figure 7. Reference Voltage Adjustment with External
Potentiometer
Using the ꢂEFADꢃ input makes buffering the external
reference unnecessary. The ꢂEFADꢃ input impedance
is typically 17kΩ.
When applying an external reference to ꢂEF, disable
the internal reference buffer by connecting ꢂEFADꢃ to
___________Applications Information
Power-On Reset
When power is first applied, internal power-on reset cir-
cuitry activates the MAX1090/MAX1092 in external
clock mode and sets INT high. After the power supplies
stabilize, the internal reset time is 10µs, and no conver-
sions should be attempted during this phase. When
using the internal reference, 500µs are required for
V
. The DC input resistance at ꢂEF is 25kΩ.
DD
Therefore, an external reference at ꢂEF must deliver up
to 200µA DC load current during a conversion and
have an output impedance less than 10Ω. If the refer-
ence has higher output impedance or is noisy, bypass
it close to the ꢂEF pin with a 4.7µF capacitor.
V
to stabilize.
ꢂEF
Power-Down Modes
To save power, place the converter in a low-current
shutdown state between conversions. Select standby
mode or shutdown mode through bits D6 and D7 of the
control byte (Tables 1 and 2). In both software power-
down modes, the parallel interface remains active, but
the ADC does not convert.
Internal and External Reference
The MAX1090/MAX1092 can be used with an internal
or external reference voltage. An external reference
can be connected directly to ꢂEF or ꢂEFADꢃ.
An internal buffer is designed to provide +2.5V at ꢂEF
for both devices. The internally trimmed +1.22V refer-
ence is buffered with a +2.05V/V gain.
Standby Mode
While in standby mode, the supply current is 1mA (typ).
The part will power up on the next rising edge on WR
and is ready to perform conversions. This quick turn-on
time allows the user to realize significantly reduced
power consumption for conversion rates below 400ksps.
Internal Reference
The full-scale range with the internal reference is +2.5V
with unipolar inputs and 1.25V with bipolar inputs. The
internal reference buffer allows for small adjustments
( 100mV) in the reference voltage (Figure 7).
Note: The reference buffer must be compensated with
an external capacitor (4.7µF min) connected between
ꢂEF and GꢁD to reduce reference noise and switching
spikes from the ADC. To further minimize reference
noise, connect a 0.01µF capacitor between ꢂEFADꢃ
and GꢁD.
Shutdown Mode
Shutdown mode turns off all chip functions that draw
quiescent current, reducing the typical supply current
to 2µA immediately after the current conversion is com-
pleted. A rising edge on WR causes the MAX1090/
MAX1092 to exit shutdown mode and return to normal
operation. To achieve full 10-bit accuracy with a 4.7µF
reference bypass capacitor, 500µs is required after
power-up. Waiting this 500µs in standby mode instead
of in full-power mode can reduce power consumption by
a factor of 3 or more. When using an external reference,
External Reference
With the MAX1090/MAX1092, an external reference can
be placed at either the input (ꢂEFADꢃ) or the output
(ꢂEF) of the internal reference-buffer amplifier.
______________________________________________________________________________________ 1.
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
only 50µs are required after power-up. Enter standby
OUTPUT CODE
mode by performing a dummy conversion with the con-
FULL-SCALE
TRANSITION
trol byte specifying standby mode.
111 . . . 111
111 . . . 110
FS = REF + COM
ZS = COM
Note: Bypass capacitors larger than 4.7µF between
ꢂEF and GꢁD will result in longer power-up delays.
Transfer Function
Table 6 shows the full-scale voltage ranges for unipolar
and bipolar modes.
100 . . . 010
100 . . . 001
100 . . . 000
REF
1024
1LSB =
Figure 8 depicts the nominal, unipolar input/output (I/O)
transfer function, and Figure 9 shows the bipolar I/O
transfer function. Code transitions occur halfway
between successive-integer LSB values. Output coding
011 . . . 111
011 . . . 110
011 . . . 101
is binary, with 1LSB = V
/ 1024.
ꢂEF
000 . . . 001
000 . . . 000
Maximum Sampling Rate/
Achieving 475ksps
When running at the maximum clock frequency of
7.6MHz, the specified 400ksps throughput is achieved
by completing a conversion every 19 clock cycles: 1
write cycle, 3 acquisition cycles, 13 conversion cycles,
and 2 read cycles. This assumes that the results of the
last conversion are read before the next control byte is
written. It’s possible to achieve higher throughputs
(Figure 10), up to 475ksps, by first writing a control
word to begin the acquisition cycle of the next conver-
sion, then reading the results of the previous conver-
sion from the bus. This technique allows a conversion
to be completed every 16 clock cycles. ꢁote that
switching the data bus during acquisition or conversion
can cause additional supply noise that may make it dif-
ficult to achieve true 10-bit performance.
0
1
2
512
FS
(COM)
FS - 3/2LBS
INPUT VOLTAGE (LSB)
Figure 8. Unipolar Transfer Function
OUTPUT CODE
REF
FS
=
+ COM
+ COM
011 . . . 111
011 . . . 110
2
ZS = COM
-REF
2
-FS =
000 . . . 010
000 . . . 001
000 . . . 000
REF
1024
1LSB =
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wire-
wrap configurations are not recommended since the lay-
out should ensure proper separation of analog and digital
traces. Do not run analog and digital lines parallel to each
other, and do not lay out digital signal paths underneath
the ADC package. Use separate analog and digital PC
board ground sections with only one star point (Figure
11) connecting the two ground systems (analog and digi-
tal). For lowest noise operation, ensure the ground return
to the star ground’s power supply is low impedance and
as short as possible. ꢂoute digital signals far away from
sensitive analog and reference inputs.
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
COM*
INPUT VOLTAGE (LSB)
- FS
+FS - 1LSB
≤
V
*COM
/ 2
REF
Figure 9. Bipolar Transfer Function
Tꢁble 6ꢀ Full Lcꢁle ꢁnd Zeao Lcꢁle foa Unipolꢁa ꢁnd Bipolꢁa Opeaꢁtion
UNIPO5AR MODE
BIPO5AR MODE
Full Scale
Zero Scale
—
V
ꢂEF
+ COM
Positive Full Scale
V
/2 + COM
ꢂEF
COM
Zero Scale
COM
/2 + COM
—
ꢁegative Full Scale
-V
ꢂEF
16 ______________________________________________________________________________________
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
High-frequency noise in the power supply (V ) could
DD
MAX1090/MAX1092’s IꢁL is measured using the end-
point method.
influence the proper operation of the ADC’s fast com-
parator. Bypass V
to the star ground with a network
DD
Differential Nonlinearity
Differential nonlinearity (DꢁL) is the difference between
an actual step width and the ideal value of 1LSB. A
DꢁL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
of two parallel capacitors, 0.1µF and 4.7µF, located as
close as possible to the MAX1090/MAX1092 power-
supply pin. Minimize capacitor lead length for best sup-
ply-noise rejection, and add an attenuation resistor (5Ω)
if the power supply is extremely noisy.
Aperture Jitter
__________________________Definitions
Aperture jitter (t ) is the sample-to-sample variation in
Aꢃ
Integral Nonlinearity
Integral nonlinearity (IꢁL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
the time between the samples.
Aperture Delay
Aperture delay (t ) is the time between the rising
AD
edge of the sampling clock and the instant when an
actual sample is taken.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
WR
RD
HBEN
D7–D0
D9–D8
CONTROL
BYTE
D7–D0 D9–D8
CONTROL BYTE
CONVERSION
D7–D0
LOW HIGH
BYTE BYTE
HIGH
BYTE
LOW
BYTE
ACQUISITION
STATE
ACQUISITION
SAMPLING INSTANT
Figure 10. Timing Diagram for Fastest Conversion
______________________________________________________________________________________ 17
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SIꢁAD) is the ratio of the
fundamental input frequency’s ꢂMS amplitude to ꢂMS
equivalent of all other ADC output signals.
SUPPLIES
SIꢁAD (dB) = 20 · log (Signal
/ ꢁoise
)
ꢂMS
ꢂMS
+3V
V
= +3V/+5V
GND
LOGIC
Effective Number of Bits
Effective number of bits (EꢁOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the
ADC’s full-scale range, calculate the EꢁOB as follows:
4.7µF
0.1µF
R* = 5Ω
EꢁOB = (SIꢁAD - 1.76) / 6.02
GND
V
COM
+3V/+5V DGND
DD
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the ꢂMS
sum of the input signal’s first five harmonics to the fun-
damental itself. This is expressed as:
DIGITAL
CIRCUITRY
MAX1090
MAX1092
*OPTIONAL
2
2
2
2
THD = 20 ⋅ log
V
+ V + V + V
/V
1
2
3
4
5
Figure 11. Power-Supply and Grounding Connections
where V is the fundamental amplitude, and V through
1
2
V
are the amplitudes of the 2nd- through 5th-order
harmonics.
5
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (Sꢁꢂ) is the ratio of full-
scale analog input (ꢂMS value) to the ꢂMS quantization
error (residual error). The ideal theoretical minimum
analog-to-digital noise is caused by quantization error
only and results directly from the ADC’s resolution (ꢁ
bits):
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDꢂ) is the ratio of ꢂMS
amplitude of the fundamental (maximum signal compo-
nent) to the ꢂMS value of the next-largest distortion
component.
Sꢁꢂ = (6.02 · ꢁ + 1.76)dB
Chip Information
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, Sꢁꢂ is computed by taking
the ratio of the ꢂMS signal to the ꢂMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
TꢂAꢁSISTOꢂ COUꢁT: 5781
18 ______________________________________________________________________________________
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Circuits
+2.7V TO +5.5V
+5V
+2.7V TO +5.5V
+5V
CLK
CLK
V
V
LOGIC
LOGIC
MAX1090
V
MAX1092
V
DD
DD
+2.5V
+2.5V
CS
REF
CS
REF
µP
CONTROL
INPUTS
µP
CONTROL
INPUTS
WR
REFADJ
WR
REFADJ
4.7µF
4.7µF
0.1µF
0.1µF
RD
RD
HBEN
HBEN
INT
OUTPUT STATUS
INT
OUTPUT STATUS
CH7
CH6
CH5
D7
D6
D7
D6
CH4
D5
D4
D3
D5
D4
D3
ANALOG
INPUTS
CH3
CH2
CH1
CH3
CH2
CH1
ANALOG
INPUTS
D2
D2
CH0
CH0
D1/D9
D0/D8
D1/D9
D0/D8
COM
COM
GND
GND
GND
GND
µP DATA BUS
µP DATA BUS
Pin Configurations (continued)
Ordering Information (continued)
IN5
(5LB)
TOP VIEW
PART
TEMPꢀ RANGE PIN-PACKAGE
HBEN
D7
1
2
3
4
5
6
7
8
9
28
27
V
V
LOGIC
DD
MAX1092ACEG 0°C to +70°C 24 QSOP
MAX1092BCEG 0°C to +70°C 24 QSOP
MAX1092AEEG -40°C to +85°C 24 QSOP
MAX1092BEEG -40°C to +85°C 24 QSOP
0.5
1
D6
26 REF
25 REFADJ
24 GND
23 COM
22 CH0
21 CH1
20 CH2
19 CH3
18 CH4
17 CH5
16 CH6
15 CH7
0.5
1
D5
D4
MAX1090
D3
D2
D1/D9
D0/D8
INT 10
RD 11
WR 12
CLK 13
CS 14
QSOP
______________________________________________________________________________________ 19
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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