MAX1084ACSA+T [MAXIM]
ADC, Successive Approximation, 10-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO8, ROHS COMPLIANT, SOIC-8;
| 型号： | MAX1084ACSA+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 10-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO8, ROHS COMPLIANT, SOIC-8 |
| 文件： | 总16页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1686; Rev 0; 5/00
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
General Description
Features
The MAX1084/MAX1085 10-bit analog-to-digital convert-
ers (ADCs) combine a high-bandwidth track/hold, a serial
interface with high conversion speed, an internal +2.5V
reference, and low power consumption. The MAX1084
operates from a single +4.5V to +5.5V supply; the
MAX1085 operates from a single +2.7V to +3.6V supply.
o Single-Supply Operation
+4.5V to +5.5V (MAX1084)
+2.7V to +3.6V (MAX1085)
o 10-Bit Resolution
o 400ksps Sampling Rate (MAX1084)
o Internal Track/Hold
The 3-wire serial interface connects directly to
SPI™/QSPI™/MICROWIRE™ devices without external
logic. The devices use an external serial-interface clock to
perform successive-approximation analog-to-digital con-
versions.
o Internal +2.5V Reference
o Low Power: 2.5mA (400ksps)
o SPI/QSPI/MICROWIRE 3-Wire Serial Interface
Low power combined with ease of use and small pack-
age size make these converters ideal for remote-sensor
and data-acquisition applications, or for other circuits with
demanding power consumption and space requirements.
The MAX1084/MAX1085 are available in 8-pin SO
packages.
o Pin-Compatible, High-Speed Upgrade to
MAX1242/MAX1243
o 8-Pin SO Package
These devices are pin-compatible, higher-speed versions
of the MAX1242/MAX1243; for more information, refer to
the respective data sheets.
Ordering Information
TEMP.
PIN-
INL
PART
RANGE
PACKAGE
(LSB)
Applications
MAX1084ACSA
MAX1084BCSA
MAX1084AESA
MAX1084BESA
MAX1085ACSA
MAX1085BCSA
MAX1085AESA
MAX1085BESA
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
8 SO
8 SO
8 SO
8 SO
8 SO
8 SO
8 SO
8 SO
1/2
1
Portable Data Logging
Data Acquisition
1/2
1
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
1/2
1
1/2
1
Process Control
Pin Configuration
Functional Diagram
V
DD
TOP VIEW
1
7
CS
8
SCLK
3
V
CONTROL
LOGIC
INT
DD
SCLK
CS
1
2
3
4
8
7
6
5
SHDN
CLOCK
OUTPUT
SHIFT
REGISTER
6
AIN
DOUT
MAX1084
MAX1085
SHDN
REF
DOUT
GND
2
10-BIT
SAR
T/H
AIN
2.5V
REFERENCE
SO
MAX1084
MAX1085
4
REF
SPI and QSPI are trademarks of Motorola, Inc.
5
GND
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
ABSOLUTE MAXIMUM RATINGS
DD
V
to GND.............................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
AIN to GND................................................-0.3V to (V + 0.3V)
8-Pin SO (derate 5.88mW/°C above +70°C) ..............471mW
Operating Temperature Ranges
DD
REF to GND ...............................................-0.3V to (V + 0.3V)
DD
Digital Inputs to GND...............................................-0.3V to +6V
MAX1084_CSA/MAX1085_CSA.........................0°C to +70°C
MAX1084_ESA/MAX1085_ESA ......................-40°C to +85°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10s)................................+300°C
DOUT to GND............................................-0.3V to (V + 0.3V)
DD
DOUT Current.................................................................. 25mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX1084
(V
= +4.5V to +5.5V, f
= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), 4.7µF capacitor at REF, T = T
to
MIN
DD
SCLK
A
T
MAX
, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
10
Bits
MAX1084A
MAX1084B
0.5
1.0
1.0
4.0
3.0
Relative Accuracy (Note 2)
INL
LSB
Differential Nonlinearity
Offset Error
DNL
No missing codes over temperature
LSB
LSB
LSB
Gain Error (Note 3)
Gain-Error Temperature
Coefficient
0.8
60
ppm/°C
DYNAMIC SPECIFICATIONS (100kHz sine wave, 2.5Vp-p, clock = 6.4MHz)
Signal-to-Noise Plus Distortion
Ratio
SINAD
dB
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Conversion Time (Note 4)
Track/Hold Acquisition Time
Aperture Delay
THD
SFDR
IMD
Up to the 5th harmonic
= 99kHz, f =102kHz
-70
70
76
6
dB
dB
f
dB
IN1
IN2
-3dB point
SINAD > 58dB
MHz
kHz
350
t
2.5
µs
ns
CONV
t
468
ACQ
10
ns
Aperture Jitter
<50
ps
Serial Clock Frequency
Duty Cycle
f
0.5
40
6.4
60
MHz
%
SCLK
ANALOG INPUT (AIN)
Input Voltage Range
Input Capacitance
V
AIN
0
2.5
V
18
pF
2
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1084 (continued)
(V
= +4.5V to +5.5V, f
= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), 4.7µF capacitor at REF, T = T
to
MIN
DD
SCLK
A
T
MAX
, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INTERNAL REFERENCE
REF Output Voltage
V
T
= +25°C
2.48
2.50
30
2.52
V
REF
A
REF Short-Circuit Current
REF Output Tempco
mA
TC V
15
ppm/°C
mV/mA
µF
REF
Load Regulation (Note 5)
Capacitive Bypass at REF
0 to 1.0mA output load
0.1
2.0
10
4.7
3.0
DIGITAL INPUTS (SCLK, CS, SHDN)
Input High Voltage
V
V
V
INH
Input Low Voltage
V
0.8
1
INL
Input Hysteresis
V
HYST
0.2
15
V
Input Leakage
I
V
= 0 or V
DD
µA
pF
IN
IN
Input Capacitance
C
IN
DIGITAL OUTPUT (DOUT)
Output Voltage Low
V
I
I
= 5mA
0.4
10
V
V
OL
SINK
Output Voltage High
V
OH
= 1mA
SOURCE
4
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLY
I
µA
pF
CS = 5V
CS = 5V
L
C
OUT
15
Positive Supply Voltage (Note 6)
Positive Supply Current (Note 7)
Shutdown Supply Current
Power-Supply Rejection
V
4.5
5.5
4.0
10
V
DD
I
V
= 5.5V
2.5
2
mA
µA
mV
DD
DD
I
SCLK = V , SHDN = GND
SHDN
DD
PSR
V
DD
= 5V 10%, midscale input
0.5
2.0
ELECTRICAL CHARACTERISTICS—MAX1085
(V
= +2.7V to +3.6V, f
= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), 4.7µF capacitor at REF, T = T
to
MIN
DD
SCLK
A
T
MAX
, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
10
Bits
MAX1085A
MAX1085B
0.5
1.0
1.0
3.0
3.0
Relative Accuracy (Note 2)
INL
LSB
Differential Nonlinearity
Offset Error
DNL
No missing codes over temperature
LSB
LSB
LSB
Gain Error (Note 3)
Gain-Error Temperature
Coefficient
1.6
ppm/°C
_______________________________________________________________________________________
3
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1085 (continued)
(V
= +2.7V to +3.6V, f
= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), 4.7µF capacitor at REF, T = T
to
MIN
DD
SCLK
A
T
MAX
, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
= 300ksps, f
MIN
TYP
MAX
UNITS
DYNAMIC SPECIFICATIONS (75kHz sinewave, 2.5Vp-p, f
= 4.8MHz)
SCLK
SAMPLE
Signal-to-Noise Plus Distortion
Ratio
SINAD
60
dB
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Conversion Time (Note 4)
Track/Hold Acquisition Time
Aperture Delay
THD
SFDR
IMD
Up to the 5th harmonic
= 99kHz, f =102kHz
-70
70
76
3
dB
dB
f
dB
IN1
IN2
-3dB point
SINAD > 58dB
MHz
kHz
250
t
3.3
µs
ns
CONV
t
625
ACQ
10
ns
Aperture Jitter
<50
ps
Serial Clock Frequency
Duty Cycle
f
0.5
40
4.8
60
MHz
%
SCLK
ANALOG INPUT
Input Voltage Range
Input Capacitance
V
0
2.5
V
AIN
C
18
pF
IN
INTERNAL REFERENCE
REF Output Voltage
V
T
= +25°C
2.48
2.50
15
2.52
V
REF
A
REF Short Circuit Current
REF Output Tempco
Load Regulation (Note 5)
Capacitive Bypass at REF
mA
TC V
15
ppm/°C
mV/mA
µF
REF
0 to 0.75mA output load
0.1
2.0
10
4.7
2.0
DIGITAL INPUTS (SCLK,CS, SHDN)
Input High Voltage
V
V
V
INH
Input Low Voltage
V
0.8
1
INL
Input Hysteresis
V
HYST
0.2
15
V
Input Leakage
I
V
= 0 or V
DD
µA
pF
IN
IN
Input Capacitance
C
IN
DIGITAL OUTPUTS (DOUT)
Output Voltage Low
V
V
I
I
= 5mA
0.4
10
V
V
OL
SINK
Output Voltage High
= 0.5mA
V 0.5V
DD
-
OH
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
I
µA
pF
CS = 3V
CS = 3V
L
C
OUT
15
POWER SUPPLY
Positive Supply Voltage (Note 6)
Positive Supply Current (Note 7)
Shutdown Supply Current
Power-Supply Rejection
V
2.7
3.6
3.5
10
V
DD
I
V
= 3.6V
2.5
2
mA
µA
mV
DD
DD
I
SCLK = V , SHDN = GND
SHDN
DD
PSR
V
DD
= 2.7V to 3.6V, midscale input
0.5
2.0
4
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
TIMING CHARACTERISTICS—MAX1084
(Figures 1, 2, 8, 9; V
= +4.5V to +5.5V, T = T
A
to T , unless otherwise noted.)
MAX
DD
MIN
PARAMETER
SCLK Period
SYMBOL
CONDITIONS
MIN
156
62
62
35
0
TYP
MAX
UNITS
ns
t
CP
CH
SCLK Pulse Width High
SCLK Pulse Width Low
t
ns
t
CL
ns
t
ns
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Rise to CS Fall Ignore
CS Rise to SCLK Rise Ignore
SCLK Rise to DOUT Hold
SCLK Rise to DOUT Valid
CS Rise to DOUT Disable
CS Fall to DOUT Enable
CS Pulse Width High
CSS
CSH
t
t
ns
35
35
10
ns
CSO
t
ns
CS1
t
C
= 20pF
= 20pF
= 20pF
= 20pF
ns
DOH
LOAD
LOAD
LOAD
LOAD
t
t
C
C
C
80
65
65
ns
DOV
10
ns
DOD
t
ns
DOE
CSW
t
100
ns
TIMING CHARACTERISTICS—MAX1085
(Figures 1, 2, 8, 9; V
= +2.7V to +3.6V, T = T
A
to T , unless otherwise noted.)
MAX
DD
MIN
PARAMETER
SCLK Period
SYMBOL
CONDITIONS
MIN
208
83
83
45
0
TYP
MAX
UNITS
ns
t
CP
CH
SCLK Pulse Width High
SCLK Pulse Width Low
t
ns
t
CL
ns
t
ns
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Rise to CS Fall Ignore
CS Rise to SCLK Rise Ignore
SCLK Rise to DOUT Hold
SCLK Rise to DOUT Valid
CS Rise to DOUT Disable
CS Fall to DOUT Enable
CS Pulse Width High
CSS
CSH
t
t
ns
45
45
13
ns
CSO
t
ns
CS1
t
C
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
ns
DOH
LOAD
LOAD
LOAD
LOAD
LOAD
t
C
C
C
C
100
85
ns
DOV
t
13
ns
DOD
t
85
ns
DOE
t
100
ns
CSW
Note 1: Tested at V
= V
.
DD
DD,MIN
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Internal reference, offset, and reference errors nulled.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: External load should not change during conversion for specified accuracy. Guaranteed specification limit of 2mV/mA due to
production test limitation.
Note 6: Electrical characteristics are guaranteed from V
to V
. For operations beyond this range, see Typical Operating
DD,MAX
DD,MIN
Characteristics.
Note 7: MAX1084 tested with 20pF on DOUT and f
= 6.4MHz, 0 to 5V. MAX1085 tested with same loads, f
= 4.8MHz, 0 to
SCLK
SCLK
3V. DOUT = full scale.
_______________________________________________________________________________________
5
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
Typical Operating Characteristics
(MAX1084: V
= +5.0V, f
= 6.4MHz; MAX1055: V
= +3.0V, f
= 4.8MHz; C = 20pF, 4.7µF capacitor at REF,
LOAD
DD
SCLK
DD
SCLK
T = +25°C, unless otherwise noted.)
A
INTEGRAL NONLINEARLITY
vs. DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
OFFSET ERROR vs. SUPPLY VOLTAGE
0.10
0.50
0.15
0.10
0.05
0
0.08
0.06
0.04
0.02
0
0.25
0
-0.02
-0.04
-0.06
-0.08
-0.10
-0.05
-0.10
-0.15
-0.25
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
200
400
600
800 1000 1200
0
200
400
600
800 1000 1200
V
(V)
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
DD
GAIN ERROR vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
0.25
0.20
0.15
0.10
0.05
0
0.25
0
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
-0.25
-0.50
-0.05
-0.10
-0.15
-0.20
-0.25
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
TEMPERATURE (°C)
TEMPERATURE (°C)
V
DD
6
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
Typical Operating Characteristics (continued)
(MAX1084: V
= +5.0V, f
= 6.4MHz; MAX1085: V
= +3.0V, f
= 4.8MHz; C
= 20pF, 4.7µF capacitor at REF,
LOAD
DD
SCLK
DD
SCLK
T
A
= +25°C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.510
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.492
2.490
2.510
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.492
2.490
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40 -20
0
20
40
60
80 100
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
3.0
2.7
2.4
2.1
1.8
1.5
3.00
2.75
2.50
2.25
2.00
1.75
1.50
CONVERTING,
SCLK = 6.4MHz
CODE = 1111 1111 1111
L
C = 10pF
L
V
= 5V, CONVERTING
R = ∞
DD
V
V
= 3V, CONVERTING
DD
CONVERTING,
SCLK = 4.8MHz
= 5V, STATIC
DD
STATIC
V
= 3V, STATIC
DD
-40 -20
0
20
40
60
80 100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Pin Description
PIN
1
NAME
FUNCTION
V
DD
Positive Supply Voltage
Sampling Analog Input, 0 to V
2
AIN
Range
REF
Active-Low Shutdown Input. Pulling SHDN low shuts down the device and reduces the supply current
to 2µA (typ).
3
4
SHDN
Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output. Bypass with a
4.7µF capacitor.
REF
5
6
GND
Analog and Digital Ground
DOUT
Serial Data Output. DOUT changes state at SCLK’s rising edge. High impedance when CS is high.
Active-Low Chip Select. Initiates conversions on the falling edge. When CS is high, DOUT is high
impedance.
7
8
CS
Serial Clock Input. SCLK drives the conversion process and clocks data out at rates up to 6.4MHz
(MAX1084) or 4.8MHz (MAX1085).
SCLK
_______________________________________________________________________________________
7
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
V
DD
6k
DOUT
DOUT
6k
C
= 20pF
C
= 20pF
LOAD
LOAD
DGND
a) HIGH-Z TO V AND V TO V
DGND
b) HIGH-Z TO V AND V TO V
OH
OL
OH
OL
OH
OL
Figure 1. Load Circuits for DOUT Enable Time
V
DD
6k
DOUT
DOUT
6k
C
= 20pF
C
= 20pF
LOAD
LOAD
DGND
DGND
a) V TO HIGH-Z
b) V TO HIGH-Z
OH
OL
Figure 2. Load Circuits for DOUT Disable Time
Analog Input
_______________Detailed Description
Figure 4 shows the sampling architecture of the ADC’s
comparator. The full-scale input voltage is set by the
Converter Operation
The MAX1084/MAX1085 use an input track/hold (T/H)
and successive-approximation register (SAR) circuitry to
convert an analog input signal to a digital 10-bit output.
Figure 3 shows the MAX1084/MAX1085 in their simplest
configuration. The internal reference is trimmed to 2.5V.
The serial interface requires only three digital lines
(SCLK, CS, and DOUT) and provides an easy interface to
microprocessors (µPs).
The MAX1084/MAX1085 have two modes: normal and
shutdown. Pulling SHDN low shuts the device down and
reduces supply current to 2µA (typ); pulling SHDN high
puts the device into operational mode. Pulling CS low ini-
tiates a conversion that is driven by SCLK. The conver-
sion result is available at DOUT in unipolar serial format.
The serial data stream consists of three zeros, followed
by the data bits (MSB first). All transitions on DOUT
occur 20ns after the rising edge of SCLK. Figures 8 and
9 show the interface timing information.
internal reference (V
= +2.5V).
REF
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input AIN charges
capacitor CHOLD. Bringing CS low ends the acquisition
interval. At this instant, the T/H switches the input side
of CHOLD to GND. The retained charge on CHOLD repre-
sents a sample of the input, unbalancing node ZERO at
the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0 within the limits of 10-
bit resolution. This action is equivalent to transferring a
charge from CHOLD to the binary-weighted capacitive
8
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
side of CHOLD switches back to AIN, and CHOLD
charges to the input signal again.
+3V to +5V
0.1µF
10µF
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
1
2
8
7
V
SCLK
CS
DD
ANALOG INPUT
0 TO V
AIN
SERIAL
REF
INTERFACE
MAX1084
MAX1085
t
, is the maximum time the device takes to acquire
ACQ
3
4
6
5
SHUTDOWN
INPUT
the signal and the minimum time needed for the signal
to be acquired. Acquisition time is calculated by:
SHDN
DOUT
REF
GND
✕
tACQ = 7(RS + RIN) 12pF
4.7µF
where RIN = 800Ω, RS = the input signal’s source
impedance, and tACQ is never less than 468ns
(MAX1284) or 625ns (MAX1085). Source impedance
below 4kΩ does not significantly affect the ADC’s AC
performance.
Figure 3. Typical Operating Circuit
Higher source impedances can be used if a 0.01µF
capacitor is connected to the analog input. Note that
the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s input signal
bandwidth.
GND
CAPACITIVE DAC
REF
C
HOLD
12pF
AIN
Input Bandwidth
The ADC’s input tracking circuitry has a 6MHz
(MAX1084) or 3MHz (MAX1085) small-signal band-
width, so it is possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using under-
sampling techniques. To avoid aliasing of unwanted
high-frequency signals into the frequency band of inter-
est, anti-alias filtering is recommended.
ZERO
COMPARATOR
R
IN
C
*
SWITCH
6pF
800Ω
TRACK
HOLD
Analog Input Protection
AUTOZERO
RAIL
Internal protection diodes, which clamp the analog
input to V
and GND, allow the input to swing from
GND - 0.3V to VDD + 0.3V without damage.
DD
*INCLUDES ALL INPUT PARASITICS
If the analog input exceeds 50mV beyond the supplies,
limit the input current to 2mA.
Figure 4. Equivalent Input Circuit
Internal Reference
The MAX1084/MAX1085 have an on-chip voltage refer-
ence trimmed to 2.5V. The internal reference output is
connected to REF and also drives the internal capacitive
DAC. The output can be used as a reference voltage
source for other components and can source up to
800µA. Bypass REF with a 4.7µF capacitor. Larger
capacitors increase wake-up time when exiting shut-
down (see Using SHDN to Reduce Supply Current). The
internal reference is disabled in shutdown (SHDN = 0).
Serial Interface
Initialization After Power-Up and
Starting a Conversion
When power is first applied, and if SHDN is not pulled
low, it takes the fully discharged 4.7µF reference
bypass capacitor up to 1.4ms to acquire adequate
charge for specified accuracy. No conversions should
be performed during this time.
_______________________________________________________________________________________
9
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
needed to shift out these bits. Extra clock pulses occur-
ring after the conversion result has been clocked out,
and prior to a rising edge of CS, produce trailing zeros
at DOUT and have no effect on converter operation.
To start a conversion, pull CS low. At CS’s falling edge,
the T/H enters its hold mode and a conversion is initiat-
ed. Data can then be shifted out serially with the exter-
nal clock.
Pull CS high after reading the conversion’s LSB. For
maximum throughput, CS can be pulled low again to ini-
tiate the next conversion immediately after the specified
SHDN
Using
to Reduce Supply Current
Power consumption can be reduced significantly by
shutting down the MAX1084/MAX1085 between conver-
sions. Figure 6 shows a plot of average supply current
minimum time (t ).
CS
vs. conversion rate. The wake-up time, t
, is the
WAKE
Output Coding and Transfer Function
time from SHDN deasserted to the time when a conver-
sion may be initiated (Figure 5).This time depends on
the time in shutdown (Figure 7) because the external
4.7µF reference bypass capacitor loses charge slowly
during shutdown and can be as long as 1.4ms.
The data output from the MAX1084/MAX1085 is binary.
Figure 10 depicts the nominal transfer function. Code
transitions occur halfway between successive-integer
LSB values; V
1024.
= 2.5V, and 1LSB = 2.44mV or 2.5V /
REF
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CS and SCLK digital inputs. The timing
diagrams of Figures 8 and 9 outline serial-interface
operation.
Applications Information
Connection to Standard Interfaces
The MAX1084/MAX1085 serial interface is fully compat-
ible with SPI, QSPI, and MICROWIRE (Figure 11).
If a serial interface is available, set the CPU’s serial
interface in master mode so the CPU generates the ser-
ial clock. Choose a clock frequency up to 6.4MHz
(MAX1084) or 4.8MHz (MAX1085).
A
CS falling edge initiates a conversion sequence: the
T/H stage holds the input voltage, the ADC begins to
convert, and DOUT changes from high impedance to
logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of conversion
is determined.
1) Use a general-purpose I/O line on the CPU to pull CS
low. Keep SCLK low.
SCLK begins shifting out the data after the rising edge
of the third SCLK pulse. DOUT transitions 20ns after
each SCLK rising edge. The third rising clock edge
produces the MSB of the conversion at DOUT, followed
by the remaining bits. Since there are 12 data bits and
3 leading zeros, at least 15 rising clock edges are
2) Activate SCLK for a minimum of 13 clock cycles. The
first two clocks produce zeros at DOUT. DOUT output
data transitions 20ns after SCLK rising edge and is
available in MSB-first format. Observe the SCLK-to-
DOUT valid timing characteristic. Data can be clocked
into the µP on SCLK’s falling or rising edge.
COMPLETE CONVERSION SEQUENCE
CS
t
WAKE
SHDN
DOUT
CONVERSION 0
POWERED UP
CONVERSION 1
POWERED UP
POWERED DOWN
Figure 5. Shutdown Sequence
10 ______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
SUPPLY CURRENT
vs. CONVERSION RATE
10,000
1000
100
1.50
1.25
1.00
0.75
0.50
0.25
0
C
= 4.7µF
REF
V
= 3.0V
DD
DOUT = FS
R = ∞
C = 10pF
L
L
10
1
0.1
0.1
1
10
100
1k
10k 100k
0.0001 0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (s)
CONVERSION RATE (SAMPLES)
Figure 6. Supply Current vs. Conversion Rate
Figure 7. Reference Power-Up vs. Time in Shutdown
CS
1
3
4
8
12
15
SCLK
DOUT
HIGH-Z
HIGH-Z
D9 D8 D7 D6 D5 D4 D3 D23 D1 D0 S1 S0
ACQ
HOLD/CONVERT
ACQUISITION
A/D STATE
Figure 8. Interface Timing Sequence
CS
t
CSW
t
t
t
t
CSH
CL
CSS
CH
tt
CSO
t
CSI
SCLK
DOUT
t
CP
t
DOH
t
t
DOV
DOD
t
DOE
Figure 9. Detailed Serial-Interface Timing
______________________________________________________________________________________ 11
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
OUTPUT CODE
FULL-SCALE
I/O
SCK
CS
TRANSITION
11…111
11…110
11…101
SCLK
DOUT
MISO
+3V OR +5V
MAX1084
MAX1085
SS
FS = V - 1LSB
REF
V
1024
REF
1LSB =
a) SPI
CS
SCK
CS
00…011
00…010
00…001
SCLK
DOUT
MISO
+3V OR +5V
00…000
MAX1084
MAX1085
0
1
2
3
FS
INPUT VOLTAGE (LSB)
FS - 3/2LSB
SS
b) QSPI
Figure 10. Unipolar Transfer Function, Full Scale (FS) = V
1LSB, Zero Scale (ZS) = GND
-
REF
I/O
SK
SI
CS
SCLK
DOUT
3) Pull CS high at or after the 13th rising clock edge. If
CS remains low, the two sub-bits and trailing zeros
are clocked out after the LSB.
4) With CS = high, wait the minimum specified time, t
,
MAX1084
MAX1085
CS
before initiating a new conversion by pulling CS low.
If a conversion is aborted by pulling CS high before
the conversion completes, wait the minimum acquisi-
c) MICROWIRE
tion time, t
, before starting a new conversion. CS
ACQ
Figure 11. Common Serial-Interface Connections to the
MAX1084/MAX1085
must be held low until all data bits are clocked out.
Data can be output in 2 bytes or continuously, as shown
in Figure 8. The bytes contain the result of the conversion
padded with three leading zeros, 2 sub-bits, and trailing
zeros if SCLK is still active with CS kept low.
the 10 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1084/MAX1085 require 13 clock cycles
from the µP to clock out the 10 bits of data. Additional
clock cycles clock out the 2 sub-bits followed by trailing
zeros. Figure 13 shows a transfer using CPOL = 0 and
CPHA = 1. The result of conversion contains two zeros
followed by the 10 bits of data in MSB-first format.
SPI and Microwire
When using SPI or QSPI, set CPOL = 0 and CPHA = 0.
Conversion begins with a CS falling edge. DOUT goes
low, indicating a conversion is in progress. Two con-
secutive 1-byte reads are required to get the full 10+2
bits from the ADC. DOUT output data transitions on
SCLK’s rising edge and is clocked into the µP on the
following rising edge.
Layout and Grounding
For best performance, use PC boards. Wire-wrap
boards are not recommended. Board layout should
ensure that digital and analog signal lines are separat-
ed from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
The first byte contains 3 leading zeros, and 5 bits of
conversion result. The second byte contains the remain-
ing 5 bits, 2 sub-bits, and 1 trailing zero. See Figure 11
for connections and Figure 12 for timing.
Figure 14 shows the recommended system ground con-
nections. Establish a single-point analog ground (“star”
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
12 ______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
ground point) at GND, separate from the logic ground.
Connect all other analog grounds and GND to this star
ground point for further noise reduction. No other digital
system ground should be connected to this single-point
analog ground. The ground return to the power supply for
this ground should be low impedance and as short as
possible for noise-free operation.
static linearity parameters for the MAX1084/MAX1085
are measured using the endpoints method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of 1LSB or less guarantees no
missing codes and a monotonic transfer function.
High-frequency noise in the VDD power supply may affect
the ADC’s high-speed comparator. Bypass this supply to
the single-point analog ground with 0.1µF and 10µF
bypass capacitors. Minimize capacitor lead lengths for
best supply-noise rejection. To reduce the effect of sup-
ply noise, a 10Ω resistor can be connected as a lowpass
filter to attenuate supply noise (Figure 14).
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
falling edge of CS and the instant when an actual sam-
ple is taken.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The theoretical minimum analog-
to-digital noise is caused by quantization error and
results directly from the ADC’s resolution, (N bits):
CS
8
9
1
SCLK
DOUT
HIGH-Z
HIGH-Z
D8
D7
D3
D2
D1
D0
S1
S0
D9
D6
D5
D4
FIRST BYTE READ
SECOND BYTE READ
Figure 12. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0)
CS
12
14
1
SCLK
DOUT
HIGH-Z
HIGH-Z
D8
D7
D4
D3
D2
D1
D0
S1
S0
D9
D6
D5
Figure 13. QSPI Serial Interface Timing (CPOL = 0, CPHA = 1)
______________________________________________________________________________________ 13
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
SUPPLIES
V
DD
V
GND
DD
of bits as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
R* = 10Ω
4.7µF
0.1µF
2
2
2
2
V
DD
V
GND
DGND
DD
V
+ V + V + V
3 4 5
2
THD = 20 × LOG
DIGITAL
CIRCUITRY
V
1
MAX1084
MAX1085
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics, respectively.
*OPTIONAL
Figure 14. Power-Supply Grounding Condition
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component.
✕
SNR = (6.02 N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is computed by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
___________________Chip Information
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
TRANSISTOR COUNT: 4286
PROCESS: BiCMOS
✕
SINAD (dB) = 20 log (SignalRMS / NoiseRMS)
14 ______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
________________________________________________________________Package Information
______________________________________________________________________________________ 15
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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