DS5001FP-16N [MAXIM]
128k Soft Microprocessor Chip;
| 型号： | DS5001FP-16N |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 128k Soft Microprocessor Chip 微控制器 |
| 文件： | 总27页 (文件大小：939K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS5001FP
128k Soft Microprocessor Chip
www.maxim-ic.com
FEATURES
PIN CONFIGURATIONS
Cꢀ 8051-Compatible Microprocessor Adapts to Its
Task
TOP VIEW
ꢀꢁ Accesses up to 128kB of nonvolatile SRAM
ꢀꢁ In-system programming through on-chip
serial port
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
ꢀꢁ Can modify its own program or data memory
ꢀꢁ Accesses memory on a separate byte-wide bus
ꢀꢁ Performs CRC-16 check of NV RAM
memory
P0.4AD4
CE2
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P2.6/A14
CE3
2
PE2
3
CE4
BA9
4
BD3
P0.3/AD3
BA8
5
P2.5/A13
BD2
6
P0.2/AD2
BA13
P0.1/AD1
R/W
7
P2.4/A12
BD1
ꢀꢁ Decodes memory and peripheral chip enables
8
9
P2.3/A11
BD0
Cꢀ High-Reliability Operation
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DS5001FP
P0.0/AD0
VCC0
VCC
VLI
–
Maintains all nonvolatile resources for over
10 years
BA15
GND
MSEL
P1.0
P2.2/A10
P2.1/A9
P2.0/A8
XTAL1
XTAL2
P3.7/RD
P3.6/WR
P3.5/TI
PF
–
–
–
–
Power-fail reset
BA14
P1.1
Early warning power-fail interrupt
Watchdog timer
BA12
P1.2
BA7
Lithium backs user SRAM for program/data
storage
P1.3
PE3
PE4
VRST
P3.4/T0
–
Precision bandgap reference for power
BA6
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
monitor
Cꢀ Fully 8051 Compatible
–
–
–
–
128kB scratchpad RAM
Two timer/counters
On-chip serial port
MQFP
32 parallel I/O port pins
CꢀSoftware Security Available with DS5002FP
Secure Microprocessor
This data sheet must be used in conjunction with the Secure
Microcontroller User’s Guide, available on our website at
www.maxim-ic.com/microcontrollers. The user’s guide contains
operating information, whereas the data sheet contains ordering
information, pinout, and electrical specifications
MQFP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 27
REV: 070605
DS5001FP
ORDERING INFORMATION
MAX CLOCK PIN-
PART
TEMP RANGE
SPEED (MHz) PACKAGE
DS5001FP-16
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
16
16
16
16
12
12
80 MQFP
80 MQFP
80 MQFP
80 MQFP
44MQFP
44 MQFP
DS5001FP-16+
DS5001FP-16N
DS5001FP-16N+
DS5001FP-12-44
DS5001FP-12-44+
+ Denotes a Pb-free/RoHS-compliant device.
DESCRIPTION
The DS5001FP 128k soft microprocessor chip is an 8051-compatible microprocessor based on NV RAM
technology and designed for systems that need large quantities of nonvolatile memory. It provides full
compatibility with the 8051 instruction set, timers, serial port, and parallel I/O ports. By using NV RAM
instead of ROM, the user can program and then reprogram the microprocessor while in-system. The
application software can even change its own operation, which allows frequent software upgrades,
adaptive programs, customized systems, etc. In addition, by using NV SRAM, the DS5001FP is ideal for
data logging applications. It also connects easily to a Dallas real-time clock.
The DS5001FP provides the benefits of NV RAM without using I/O resources. It uses a nonmultiplexed
byte-wide address and data bus for memory access. This bus performs all memory access and provides
decoded chip enables for SRAM, which leaves the 32 I/O port pins free for application use. The
DS5001FP uses ordinary SRAM and battery-backs the memory contents for over 10 years at room
temperature with a small external battery. A DS5001FP also provides high-reliability operation in harsh
environments. These features include the ability to save the operating state, power-fail reset, power-fail
interrupt, and watchdog timer.
A user programs the DS5001FP through its on-chip serial bootstrap loader. The bootstrap loader
supervises the loading of software into NV RAM, validates it, and then becomes transparent to the user.
Software can be stored in multiple 32kB or one 128kB CMOS SRAM(s). Using its internal partitioning,
the DS5001FP can divide a common RAM into user-selectable program and data segments. This partition
can be selected at program loading time, but can then be modified later at any time. The microprocessor
decodes memory access to the SRAM and addresses memory through its byte-wide bus. Memory portions
designated code or ROM are automatically write-protected by the microprocessor. Combining program
and data storage in one device saves board space and cost.
The DS5001FP offers several bank switches for access to even more memory. In addition to the primary
data area of 64kB, a peripheral selector creates a second 64kB data space with four accompanying chip
enables. This area can be used for memory-mapped peripherals or more data storage. The DS5001FP can
also use its expanded bus on ports 0 and 2 (like an 8051) to access an additional 64kB of data space.
Lastly, the DS5001FP provides one additional bank switch that changes up to 60kB of the NV RAM
program space into data memory. Thus, with a small amount of logic, the DS5001 accesses up to 252kB
of data memory.
The DS2251T is available (Refer to the data sheet at www.maxim-ic.com/microcontrollers.) for users
who want a preconstructed module using the DS5001FP, RAM, lithium cell, and a real-time clock. For
more details, refer to the Secure Microcontroller User’s Guide. For users desiring software security, the
DS5002FP is functionally identical to the DS5001FP but provides superior firmware security. The 44-pin
version of the device is functionally identical to the 80-pin version but sports a reduced pin count and
footprint.
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DS5001FP
Figure 1. BLOCK DIAGRAM
3 of 27
DS5001FP
PIN DESCRIPTION
PIN
NAME
FUNCTION
80 PIN 44 PIN
11, 9, 7,
31
General-Purpose I/O Port 0. This port is open-drain and cannot drive a logic 1. It
requires external pullups. Port 0 is also the multiplexed expanded address/data bus.
When used in this mode, it does not require pullups.
P0.0–
P0.7
5, 1, 79,
(P0.5)
77, 75
15, 17,
19, 21,
25, 27,
29, 31
49, 50,
51, 56,
58, 60,
64, 66
44
P1.0–
P1.7
General-Purpose I/O Port 1
(P1.3)
General-Purpose I/O Port 2. Also serves as the MSB of the address in expanded
P2.0–
P2.7
—
memory accesses, and as pins of the RPC mode when used.
General-Purpose I/O Port Pin 3.0. Also serves as the receive signal for the on
board UART. This pin should not be connected directly to a PC COM port.
P3.0/RX
D
36
8
General-Purpose I/O Port Pin 3.1. Also serves as the transmit signal for the on
P3.1/TX
D
38
10
board UART. This pin should not be connected directly to a PC COM port.
P3.2/
General-Purpose I/O Port Pin 3.2. Also serves as the active-low external interrupt
39
40
—
11
0.
INT0
P3.3/
INT1
General-Purpose I/O Port Pin 3.3. Also serves as the active-low external interrupt
1.
41
44
—
12
General-Purpose I/O Port Pin 3.4. Also serves as the timer 0 input.
General-Purpose I/O Port Pin 3.5. Also serves as the timer 1 input.
P3.4/T0
P3.5/T1
General-Purpose I/O Port Pin. Also serves as the write strobe for expanded bus
operation.
45
46
13
—
P3.6/ WR
P3.7/ RD
General-Purpose I/O Port Pin. Also serves as the read strobe for expanded bus
operation.
Program Store Enable. This active-low signal is used to enable an external
program memory when using the expanded bus. It is normally an output and should
be unconnected if not used. PSEN also is used to invoke the bootstrap loader. At this
time, PSEN is pulled down externally. This should only be done once the DS5001FP
is already in a reset state. The device that pulls down should be open drain since it
must not interfere with PSEN under normal operation.
68
34
25
6
PSEN
Active-High Reset Input. A logic 1 applied to this pin will activate a reset state.
This pin is pulled down internally so this pin can be left unconnected if not used. An
RC power-on reset circuit is not needed and is not recommended.
Address Latch Enable. Used to demultiplex the multiplexed expanded address/data
bus on port 0. This pin is normally connected to the clock input on a ’373 type
transparent latch.
RST
ALE
70
27
Crystal Connections. Used to connect an external crystal to the internal oscillator.
XTAL2,
XTAL1
GND
47, 48
14, 15
XTAL1 is the input to an inverting amplifier and XTAL2 is the output.
52
13
16
39
Logic Ground
Power Supply, +5V
VCC
VCC Output. This is switched between VCC and VLI by internal circuits based on the
level of VCC. When power is above the lithium input, power will be drawn from VCC.
The lithium cell remains isolated from a load. When VCC is below VLI, the VCCO
switches to the VLI source. VCCO should be connected to the VCC pin of an SRAM.
12
54
38
17
VCCO
Lithium Voltage Input. Connect to a lithium cell greater than VLIMIN and no greater
VLI
than VLImax as shown in the electrical specifications. Nominal value is +3V.
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DS5001FP
PIN DESCRIPTION (continued)
PIN
NAME
FUNCTION
80 PIN 44 PIN
53, 16,
41, 36,
42, 32,
30, 34,
35, 43,
1, 2, 3,
4, 5, 7,
9
Byte-Wide Address Bus Bits 14–0. This bus is combined with the nonmultiplexed
data bus (BD7–0) to access NV SRAM. Decoding is performed using CE1 through
CE4 . Therefore, BA15 is not actually needed. Read/write access is controlled by
R/ W . BA14–0 connect directly to an 8k, 32k, or 128k SRAM. If an 8k RAM is
used, BA13 and BA14 are unconnected. If a 128k SRAM is used, the micro converts
CE2 and CE3 to serve as A16 and A15 respectively.
8, 18,
80, 76,
4, 6, 20,
24, 26,
28, 30,
33, 35,
37
BA14–
BA0
Byte-Wide Data Bus Bits 7–0. This 8-bit, bidirectional bus is combined with the
nonmultiplexed address bus (BA14–0) to access NV SRAM. Decoding is performed
on CE1 and CE2 . Read/write access is controlled by R/ W . BD7–0 connect directly to
an SRAM, and optionally to a real-time clock or other peripheral.
Read/Write. This signal provides the write enable to the SRAMs on the byte-wide
bus. It is controlled by the memory map and partition. The blocks selected as
program (ROM) are write-protected.
71, 69,
67, 65,
61, 59,
57, 55
28, 26,
24, 23,
21, 20,
19, 18
BD7–0
R/ W
10
37
Chip Enable 1. This is the primary decoded chip enable for memory access on the
byte-wide bus. It connects to the chip enable input of one SRAM. CE1 is lithium-
backed. It remains in a logic high inactive state when VCC falls below VLI.
Non-Battery-Backed Version of Chip Enable 1. This can be used with a 32kB
EPROM. It should not be used with a battery-backed chip.
74
72
29
—
CE1
CE1N
Chip Enable 2. This chip enable is provided to access a second 32k block of
memory. It connects to the chip enable input of one SRAM. When MSEL = 0, the
micro converts CE2 into A16 for a 128k x 8 SRAM. CE2 is lithium-backed and
remains at a logic high when VCC falls below VLI.
2
33
CE2
Chip Enable 3. This chip enable is provided to access a third 32k block of memory.
It connects to the chip enable input of one SRAM. When MSEL = 0, the micro
converts CE3 into A15 for a 128k x 8 SRAM. CE3 is lithium-backed and remains at
a logic high when VCC falls below VLI.
63
62
78
3
22
—
—
—
—
CE3
CE4
PE1
PE2
PE3
Chip Enable 4. This chip enable is provided to access a fourth 32k block of
memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, this
signal is unused. CE4 is lithium-backed and remains at a logic high when VCC < VLI.
Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh
when the PES bit is set to a logic 1. Commonly used to chip enable a byte-wide real-
time clock such as the DS1283. PE1 is lithium-backed and remains at a logic high
when VCC falls below VLI. Connect PE1 to battery-backed functions only.
Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh
when the PES bit is set to a logic 1. PE2 is lithium-backed and remains at a logic
high when VCC falls below VLI. Connect PE2 to battery-backed functions only.
Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh
when the PES bit is set to a logic 1. PE3 is not lithium-backed and can be connected
to any type of peripheral function. If connected to a battery-backed chip, it needs
additional circuitry to maintain the chip enable in an inactive state when VCC < VLI.
Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh
when the PES bit is set to a logic 1. PE4 is not lithium-backed and can be connected
to any type of peripheral function. If connected to a battery-backed chip, it needs
additional circuitry to maintain the chip enable in an inactive state when VCC < VLI.
Invokes the bootstrap loader on a falling edge. This signal should be debounced
so that only one edge is detected. If connected to ground, the micro enters bootstrap
loading on power-up. This signal is pulled up internally.
22
23
32
—
—
PE4
PROG
5 of 27
DS5001FP
PIN DESCRIPTION (continued)
PIN
NAME
FUNCTION
80 PIN 44 PIN
This I/O pin (open drain with internal pullup) indicates that the power supply
(VCC) has fallen below the VCCmin level and the micro is in a reset state. When
this occurs, the DS5001FP drives this pin to a logic 0. Because the micro is lithium-
backed, this signal is guaranteed even when VCC = 0V. Because it is an I/O pin, it
also forces a reset if pulled low externally. This allows multiple parts to synchronize
their power-down resets.
42
43
—
—
VRST
PF
This output goes to a logic 0 to indicate that VCC < VLI and the micro has
switched to lithium backup. Because the micro is lithium-backed, this signal is
guaranteed even when VCC = 0V. The normal application of this signal is to control
lithium-powered current to isolate battery-backed functions from non-battery-backed
functions.
Memory Select. This signal controls the memory size selection. When MSEL =
+5V, the DS5001FP expects to use 32k x 8 SRAMs. When MSEL = 0V, the
DS5001FP expects to use a 128k x 8 SRAM. MSEL must be connected regardless of
partition, mode, etc.
14
73
40
—
MSEL
N.C.
No Connection
INSTRUCTION SET
The DS5001FP executes an instruction set that is object code-compatible with the industry standard 8051
microcontroller. As a result, software development packages such as assemblers and compilers that have
been written for the 8051 are compatible with the DS5001FP. A complete description of the instruction
set and operation are provided in the Secure Microcontroller User’s Guide. Also note that the DS5001FP
is embodied in the DS2251T module. The DS2251T combines the DS5001FP with between 32k and 128k
of SRAM, a lithium cell, and a real-time clock. This is packaged in a 72-pin SIMM module.
MEMORY ORGANIZATION
Figure 2 illustrates the memory map accessed by the DS5001FP. The entire 64k of program and 64k of
data are potentially available to the byte-wide bus. This preserves the I/O ports for application use. The
user controls the portion of memory that is actually mapped to the byte-wide bus by selecting the program
range and data range. Any area not mapped into the NV RAM is reached by the expanded bus on ports 0
and 2. An alternate configuration allows dynamic partitioning of a 64k space as shown in Figure 3.
Selecting PES=1 provides another 64k of potential data storage or memory-mapped peripheral space as
shown in Figure 4. These selections are made using special function registers. The memory map and its
controls are covered in detail in the Secure Microcontroller User’s Guide.
6 of 27
DS5001FP
Figure 2. MEMORY MAP IN NONPARTITIONABLE MODE (PM = 1)
7 of 27
DS5001FP
Figure 3. MEMORY MAP IN PARTITIONABLE MODE (PM = 0)
NOTE: PARTITIONABLE MODE IS NOT SUPPORTED WHEN MSEL PIN = 0 (128kB MODE).
8 of 27
DS5001FP
Figure 4. MEMORY MAP WITH PES = 1
9 of 27
DS5001FP
Figure 5 illustrates a typical memory connection for a system using a 128kB SRAM. Note that in this
configuration, both program and data are stored in a common RAM chip Figure 6 shows a similar system
with using two 32kB SRAMs. The byte-wide address bus connects to the SRAM address lines. The
bidirectional byte-wide data bus connects the data I/O lines of the SRAM.
Figure 5. CONNECTION TO 128k x 8 SRAM
10 of 27
DS5001FP
Figure 6. DS5001FP CONNECTION TO 64k x 8 SRAM
POWER MANAGEMENT
The DS5001FP monitors VCC to provide power-fail reset, early warning power-fail interrupt, and switch
over to lithium backup. It uses an internal bandgap reference in determining the switch points. These are
called VPFW, VCCMIN, and VLI, respectively. When VCC drops below VPFW, the DS5001FP performs an
interrupt vector to location 2Bh if the power-fail warning was enabled. Full processor operation continues
regardless. When power falls further to VCCMIN, the DS5001FP invokes a reset state. No further code
execution is performed unless power rises back above VCCMIN. All decoded chip enables and the R/ W
signal go to an inactive (logic 1) state. VCC is still the power source at this time. When VCC drops further
to below VLI, internal circuitry switches to the lithium cell for power. The majority of internal circuits are
disabled and the remaining nonvolatile states are retained. Any devices connected VCCO are powered by
the lithium cell at this time. VCCO is at the lithium battery voltage minus approximately 0.45V. This drop
varies depending on the load. Low power SRAMs should be used for this reason. When using the
DS5001FP, the user must select the appropriate battery to match the RAM data retention current and the
desired backup lifetime. Note that the lithium cell is only loaded when VCC < VLI. The User’s Guide has
more information on this topic. The trip points VCCMIN and VPFW are listed in the Electrical Specifications
section.
11 of 27
DS5001FP
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground…………………………..…………………….-0.3V to (VCC + 0.5V)
Voltage Range on VCC Related to Ground………………………………………………………………-0.3V to 6.0V
Operating Temperature Range………………………………………………………………………...-40LC to +85LC
Storage Temperature Range (Note 1)………………………………………………………………..-55LC to +125LC
Soldering Temperature…………………………………………………….See IPC/JEDEC J-STD-020 Specification
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
Note 1: Storage temperature is defined as the temperature of the device when VCC = 0V and VLI = 0V. In
this state, the contents of SRAM are not battery-backed and are undefined.
DC CHARACTERISTICS
(VCC = 5V ±10%, TA = 0°C to +70°C.)
PARAMETER
SYMBOL
VIL
MIN
-0.3
2.0
TYP
MAX
+0.8
UNITS
NOTES
Input Low Voltage
V
V
1
1
Input High Voltage
VIH1
VCC + 0.3
Input High Voltage
VIH2
3.5
VCC + 0.3
V
1
(RST, XTAL1, PROG )
Output Low Voltage
VOL1
0.15
0.15
4.8
0.45
V
1, 11
at IOL = 1.6mA (Ports 1, 2, 3, PF )
Output Low Voltage
at IOL = 3.2mA (Ports 0, ALE, PSEN ,
BA15–0, BD7–0, R/ W , CE1N ,
VOL2
VOH1
VOH2
0.45
V
V
V
1
1
1
CE 1–4, PE 1–4, VRST
)
Output High Voltage
2.4
2.4
at IOH = -80µA (Ports 1, 2, 3)
Output High Voltage
at IOH = -400µA (Ports 0, ALE, PSEN ,
PF , BA15–0, BD7–0, R/ W , CE1N ,
4.8
CE 1–4, PE 1–4, VRST
)
Input Low Current
IIL
-50
µA
µA
VIN = 0.45V (Ports 1, 2, 3)
Transition Current; 1 to 0
VIN = 2.0V (Ports 1, 2, 3)
(0°C to +70°C)
ITL
-500
Transition Current; 1 to 0
VIN = 2.0V (Ports 1, 2, 3)
(-40°C to +85°C)
ITL
-600
µA
10
12 of 27
DS5001FP
DC CHARACTERISTICS (continued)
(VCC = 5V ±10%, TA = 0°C to +70°C.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Leakage Current
IIL
+10
µA
0.45 < VIN < VCC (Port 0, MSEL)
RST Pulldown Resistor
(0°C to +70°C)
RRE
RRE
40
30
150
180
kꢀ
kꢀ
RST Pulldown Resistor
10
(-40°C to +85°C)
RVR
RPR
4.7
40
kꢀ
kꢀ
VRST Pullup Resistor
PROG Pullup Resistor
Power-Fail Warning Voltage
(0°C to +70°C)
VPFW
VPFW
4.25
4.1
4.37
4.37
4.12
4.09
4.50
4.6
V
V
V
V
1
Power-Fail Warning Voltage
(-40°C to +85°C)
1, 10
1
Minimum Operating Voltage
(0°C to +70°C)
VCCMIN
4.00
3.85
4.25
4.25
Minimum Operating Voltage
(-40°C to +85°C)
VCCMIN
1, 10
Operating Voltage
VCC
VLI
ICC
VCCMIN
2.5
5.5
4.0
36
V
V
mA
1
1
2
Lithium Supply Voltage
Operating Current at 16MHz
Idle Mode Current at 12MHz
(0°C to +70°C)
IIDLE
7.0
mA
3
Idle Mode Current at 12MHz
(-40°C to +85°C)
IIDLE
8.0
mA
3, 10
Stop Mode Current
ISTOP
CIN
80
10
µA
pF
4
5
Pin Capacitance
VCC
Output Supply Voltage (VCCO
)
VCCO1
V
1, 2
-0.45
Output Supply Battery-Backed Mode
VLI
VCCO2
V
1, 8
(VCCO, CE 1-4, PE 1-2)
-0.65
(0°C to +70°C)
Output Supply Battery-Backed Mode
VLI
VCCO2
V
1, 8, 10
(VCCO, CE 1-4, PE 1-2)
-0.9
(-40°C to +85°C)
Output Supply Current
at VCCO = VCC - 0.45V
Lithium-Backed Quiescent Current
(0°C to +70°C)
ICCO1
ILI
75
mA
nA
nA
6
5
75
7
7
Lithium-Backed Quiescent Current
(-40°C to +85°C)
ILI
75
500
4.25
4.25
4.65
With BAT = 3.0V
4.0
3.85
4.4
1
(0°C to +70°C)
Reset Trip Point
in Stop Mode
With BAT = 3.0V
(-40°C to +85°C)
With BAT = 3.0V
(0°C to +70°C)
1, 10
1
13 of 27
DS5001FP
AC CHARACTERISTICS: EXPANDED BUS MODE TIMING SPECIFICATIONS
(VCC = 5V ±10%, TA = 0°C to +70°C.)
#
1
2
3
4
PARAMETER
SYMBOL
1/ tCLK
tALPW
MIN
1.0
MAX
UNITS
MHz
ns
Oscillator Frequency
16
ALE Pulse Width
2tCLK - 40
tCLK - 40
tCLK - 35
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In at 12MHz
at 16MHz
tAVALL
ns
tAVAAV
ns
4tCLK - 150
4tCLK - 90
5
tALLVI
ns
6
7
tALLPSL
tPSPW
tCLK - 25
3tCLK - 35
ns
ns
ALE Low to PSEN Low
PSEN Pulse Width
at 12MHz
at 16MHz
3tCLK - 150
3tCLK - 90
PSEN Low to Valid Instruction
8
tPSLVI
ns
In
9
10
11
tPSIV
tPSIX
tPSAV
0
ns
ns
ns
Input Instruction Hold After PSEN Going High
Input Instruction Float After PSEN Going High
Address Hold After PSEN Going High
tCLK - 20
tCLK - 8
at 12MHz
at 16MHz
5tCLK - 150
5tCLK - 90
Address Valid to Valid
12
tAVVI
ns
Instruction In
13
14
15
tPSLAZ
tRDPW
tWRPW
0
ns
ns
ns
PSEN Low to Address Float
RD Pulse Width
WR Pulse Width
6tCLK - 100
6tCLK - 100
at 12MHz
at 16MHz
5tCLK - 165
5tCLK - 105
16
tRDLDV
ns
RD Low to Valid Data In
17
18
tRDHDV
tRDHDZ
0
ns
ns
Data Hold After RD High
Data Float After RD High
2tCLK - 70
at 12MHz
at 16MHz
at 12MHz
at 16MHz
8tCLK - 150
8tCLK - 90
9tCLK - 165
9tCLK - 105
3tCLK + 50
19 ALE Low to Valid Data In
tALLVD
ns
20 Valid Address to Valid Data In
tAVDV
ns
21
22
23
tALLRDL
tAVRDL
tDVWRL
3tCLK - 50
4tCLK - 130
tCLK - 60
7tCLK - 150
7tCLK - 90
tCLK - 50
ns
ns
ns
ALE Low to RD or WR Low
Address Valid to RD or WR Low
Data Valid to WR Going Low
at 12MHz
at 16MHz
24
tDVWRH
ns
Data Valid to WR High
25
26
27
tWRHDV
tRDLAZ
tRDHALH
ns
ns
ns
Data Valid After WR High
RD Low to Address Float
RD or WR High to ALE High
0
tCLK - 40
tCLK + 50
14 of 27
DS5001FP
EXPANDED PROGRAM-MEMORY READ CYCLE
EXPANDED DATA-MEMORY READ CYCLE
15 of 27
DS5001FP
EXPANDED DATA-MEMORY WRITE CYCLE
16 of 27
DS5001FP
AC CHARACTERISTICS: EXTERNAL CLOCK DRIVE
(VCC = 5V ±10%, TA = 0°C to +70°C.)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
at 12MHz
at 16MHz
at 12MHz
at 16MHz
at 12MHz
at 16MHz
at 12MHz
at 16MHz
20
28
External Clock-High Time
tCLKHPW
ns
15
20
15
29
30
31
External Clock-Low Time
External Clock-Rise Time
External Clock-Fall Time
tCLKLPW
ns
ns
ns
20
15
20
15
tCLKR
tCLKF
EXTERNAL CLOCK TIMING
17 of 27
DS5001FP
AC CHARACTERISTICS: POWER CYCLE TIME
(VCC = 5V ±10%, TA = 0°C to +70°C.)
#
PARAMETER
Slew Rate from VCCMIN to VLI
Crystal Startup Time
SYMBOL
MIN
MAX
UNITS
32
33
34
tF
130
µs
tCSU
tPOR
(Note 9)
21,504
Power-On Reset Delay
tCLK
POWER CYCLE TIMING
18 of 27
DS5001FP
AC CHARACTERISTICS: SERIAL PORT TIMING—MODE 0
(VCC = 5V ±10%, TA = 0°C to +70°C.)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
35
Serial-Port Clock-Cycle Time
tSPCLK
12tCLK
µs
36
37
38
39
Output-Data Setup to Rising-Clock Edge
Output-Data Hold After Rising-Clock Edge
Clock-Rising Edge to Input-Data Valid
Input-Data Hold After Rising-Clock Edge
tDOCH
tCHDO
tCHDV
tCHDIV
10tCLK - 133
2tCLK - 117
ns
ns
ns
ns
10tCLK - 133
0
SERIAL PORT TIMING—MODE 0
19 of 27
DS5001FP
AC CHARACTERISTICS: BYTE-WIDE ADDRESS/DATA BUS TIMING
(VCC = 5V ±10%, TA = 0°C to +70°C.)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
Delay to Byte-Wide Address Valid from
40
tCE1LPA
30
ns
CE1 , CE2 , or CE1N Low During Op Code Fetch
41
42
tCEPW
4tCLK - 35
2tCLK - 20
ns
ns
Pulse Width of CE 1-4, PE 1-4 or CE1N
Byte-Wide Address Hold After CE1 , CE2 , or
CE1N High During Op Code Fetch
tCE1HPA
Byte-Wide Data Setup to CE1 , CE2 , or CE1N
43
44
tOVCE1H
tCE1HOV
1tCLK + 40
0
ns
ns
High During Op Code Fetch
Byte-Wide Data Hold After CE1 , CE2 or CE1N
High During Op Code Fetch
Byte-Wide Address Hold After CE 1-4,
PE 1-4, or CE1N High During MOVX
Delay from Byte-Wide Address Valid
CE 1-4, PE 1-4, or CE1N Low During MOVX
Byte-Wide Data Setup to CE 1-4, PE 1-4, or
CE1N High During MOVX (read)
Byte-Wide Data Hold After CE 1-4,
PE 1-4, or CE1N High During MOVX (read)
45
46
47
48
tCEHDA
tCELDA
tDACEH
tCEHDV
4tCLK - 30
4tCLK - 35
1tCLK + 40
0
ns
ns
ns
ns
Byte-Wide Address Valid to R/ W Active
49
50
tAVRWL
tRWLDV
3tCLK - 35
20
ns
ns
During MOVX (write)
Delay from R/ W Low to Valid Data Out
During MOVX (write)
Valid Data-Out Hold Time from CE 1-4,
PE 1-4, or CE1N High
51
tCEHDV
1tCLK - 15
ns
52
53
tRWHDV
tRWLPW
0
ns
ns
Valid Data-Out Hold Time from R/ W High
6tCLK - 20
Write Pulse Width (R/ W Low Time)
20 of 27
DS5001FP
BYTE-WIDE BUS TIMING
RPC AC CHARACTERISTICS: DBB READ
(VCC = 5V ±10%, TA = 0°C to +70°C.)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
54
tAR
0
ns
CS , A0 Setup to RD
55
56
57
58
59
tRA
tRR
tAD
tRD
tRDZ
0
160
ns
ns
ns
ns
ns
CS , A0 Hold After RD
RD Pulse Width
CS , A0 to Data-Out Delay
RD to Data-Out Delay
RD to Data-Float Delay
130
130
85
0
RPC AC CHARACTERISTICS: DBB WRITE
(VCC = 5V ±10%, TA = 0°C to +70°C.)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
60
tAW
0
ns
CS , A0 Setup to WR
61A
61B
62
63
64
tWA
tWA
tWW
tDW
tWD
0
20
160
130
20
ns
ns
ns
ns
ns
CS , Hold After WR
A0, Hold After WR
WR Pulse Width
Data Setup to WR
Data Hold After WR
21 of 27
DS5001FP
AC CHARACTERISTICS: DMA
(VCC = 5V ±10%, TA = 0°C to +70°C.)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
65
tACC
0
ns
DACK to WR or RD
66
67
68
tCAC
tACD
tCRQ
0
0
ns
ns
ns
RD or WR to DACK
DACK to Data Valid
RD or WR to DRQ Cleared
130
110
AC CHARACTERISTICS: PROG
(VCC = 5V ±10%, TA = 0°C to +70°C.)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
69
70
tPRA
48
CLKS
PROG Low to Active
tPRI
48
CLKS
PROG High to Inactive
22 of 27
DS5001FP
RPC TIMING MODE
23 of 27
DS5001FP
NOTES:
All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
1) All voltages are referenced to ground.
2) Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR
tCLKF = 10ns, VIL = 0.5V; XTAL2 disconnected; RST = PORT0 = VCC, MSEL = VSS.
3) Idle mode, IIDLE, is measured with all output pins disconnected; XTAL1 driven with tCLKR
,
,
t
CLKF = 10ns, VIL = 0.5V; XTAL2 disconnected; PORT0 = VCC, RST = MSEL = VSS.
4) Stop mode, ISTOP, is measured with all output pins disconnected; PORT0 = VCC; XTAL2 not
connected; RST = MSEL = XTAL1 = VSS.
5) Pin capacitance is measured with a test frequency: 1MHz, TA = +25°C.
6) ICCO1 is the maximum average operating current that can be drawn from VCCO in normal operation.
7) ILI is the current drawn from VLI input when VCC = 0V and VCCO is disconnected.
8) VCCO2 is measured with VCC < VLI, and a maximum load of 10µA on VCCO
.
9) Crystal startup time is the time required to get the mass of the crystal into vibrational motion from the
time that power is first applied to the circuit until the first clock pulse is produced by the on-chip
oscillator. The user should check with the crystal vendor for a worst-case specification on this time.
10) This parameter applies to industrial temperature operation.
11) PF pin operation is specified with VBAT O 3.0V.
24 of 27
DS5001FP
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information, go to www.maxim-ic.com/DallasPackInfo.)
80-PIN MQFP
MM
DIM
MIN
-
MAX
3.40
-
A
A1
A2
B
0.25
2.55
0.30
0.13
23.70
19.90
17.70
13.90
2.87
0.50
0.23
24.10
20.10
18.10
14.10
C
D
D1
E
E1
e
0.80 BSC
L
0.65
0.95
56-G4005-001
25 of 27
DS5001FP
44-PIN MQFP
26 of 27
DS5001FP
REVISION HISTORY
The following represent the key differences between the 112795 and 073096 version of the DS5001FP
data sheet. Please review this summary carefully.
1) Change VCC02 specification from VLI - 0.5 to VLI - 0.65 (PCN F62501).
2) Update mechanical specifications.
The following represent the key differences between the 073096 and 111996 version of the DS5001FP
data sheet. Please review this summary carefully.
1) Change VCC01 from VCC - 0.3 to VCC - 0.35.
The following represent the key differences between the 111996 and 061297 version of the DS5001FP
data sheet. Please review this summary carefully.
PF
1)
signal moved from VOL2 test specification to VOL1. PCN No. (D72502)
2) AC characteristics for battery-backed SDI pulse specification added.
The following represent the key differences between the 061297 and 051099 version of the DS5001FP
data sheet. Please review this summary carefully.
1) Reduced absolute maximum voltage to VCC + 0.5V.
2) Added note clarifying storage temperature specification is for non-battery-backed state.
3) Changed RRE min (industrial temp range) from 40kꢀ to 30kꢀ.
4) Changed VPFW max (industrial temp range) from 4.5V to 4.6V.
5) Added industrial specification for ILI.
6) Reduced tCE1HOV and tCEHDV from 10ns to 0ns.
The following represent the key differences between the 051099 and 052499 version of the DS5001FP
data sheet. Please review this summary carefully.
1) Minor markups and ready for approval.
The following represent the key differences between the 052499 and 052302 version of the DS5001FP
data sheet. Please review this summary carefully.
1) Added information relating to 44-pin package.
2) Updated VCCO1 and ICCO1 specifications to reflect 0.45V internal voltage drop instead of 0.35V.
The following represent the key differences between the 052302 and 070605 version of the DS5001FP
data sheet. Please review this summary carefully.
1) Added Pb-free part to Ordering Information table.
2) Added operating voltage specification. (This is not a new specification because operating voltage is
implied in the testing limits, but rather a clarification.)
3) Updated Absolute Maximum Ratings soldering temperature to reference JEDEC standard.
27 of 27
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products S Printed USA
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
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