DS4510U-10/R [MAXIM]
CPU Supervisor with Nonvolatile Memory and Programmable I/O; CPU监控器，非易失性存储器和可编程I / O
| 型号： | DS4510U-10/R |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | CPU Supervisor with Nonvolatile Memory and Programmable I/O |
| 文件： | 总12页 (文件大小：580K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 2; 8/04
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
General Description
Features
The DS4510 is a CPU supervisor with integrated 64-
byte EEPROM memory and four programmable, non-
volatile (NV) I/O pins. It is configured with an
industry-standard I2C™ interface using either fast-
mode (400kbps) or standard-mode (100kbps) commu-
nication. The I/O pins can be used as general-purpose
I2C-to-parallel I/O expander with unlimited read/write
capability. EEPROM registers allow the power-on value
of the I/O pins to be adjusted to keep track of the sys-
tem’s state through power cycles, and the CPU supervi-
sor’s timer can be adjusted between 125ms and
1000ms to meet most any application need.
♦ Accurate 5%, 10%, or 15% 5V Power-Supply
Monitoring
♦ Programmable Reset Timer Maintains Reset After
V
Returns to an In-Tolerance Condition
CC
♦ Four Programmable, NV, Digital I/O Pins with
Selectable Internal Pullup Resistor
♦ 64 Bytes of User EEPROM
♦ Reduces Need for Discrete Components
♦ I2C-Compatible Serial Interface
♦ 10-Pin µSOP Package
Applications
Ordering Information
RAM-Based FPGA Bank Switching for
Multiple Profiles
V
TRIP
PIN-
PACKAGE
CC
PART
TEMP RANGE
POINT
Industrial Controls
Cellular Telephones
PC Peripherals
PDAs
DS4510U-5
5%
-40°C to +85°C 10 µSOP
-40°C to +85°C 10 µSOP
-40°C to +85°C 10 µSOP
-40°C to +85°C 10 µSOP
-40°C to +85°C 10 µSOP
-40°C to +85°C 10 µSOP
DS4510U-10
10%
15%
5%
DS4510U-15
DS4510U-5/T&R
DS4510U-10/T&R
DS4510U-15/T&R
10%
15%
Pin Configuration
Typical Operating Circuit
2.7V TO 5.5V
TOP VIEW
4.7kΩ
A
1
2
3
4
5
10
9
RST
V
V
CC
0
CC
4.7kΩ
4.7kΩ
RST
RESET
SDA
SCL
I/O
0
I/O
1
I/O
2
I/O
3
A0
I/O
I/O
I/O
CONFIG0
0
8
FROM
SYSTEM
CONTROLLER
DS4510
SDA
SCL
CONFIG1 FPGA
CONFIG2
1
V
7
CC
DS4510
2
3
GND
6
CONFIG3
GND
I/O
GND
µSOP
I2C is a registered trademark of Philips Corp. Purchase of I2C components of Maxim Integrated Products, Inc. or one of its
Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
the system conforms to the I2C Standard Specifications as defined by Philips.
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V , SDA, and SCL
EEPROM Programming Temperature.....................0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature .......................................See IPC/JEDEC
J-STD-020A Specification
CC
Pins Relative to Ground.....................................-0.5V to +6.0V
Voltage Range on A , I/O , I/O , I/O , I/O Relative
0
0
1
CC
2
3
to Ground ..............-0.5V to V
+ 0.5V, not to exceed +6.0V.
Operating Temperature Range ...........................-40°C to +85°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T = -40°C to +85°C)
A
PARAMETER
Supply Voltage
Input Logic 1
SYMBOL
CONDITIONS
MIN
2.7
TYP
MAX
5.5
UNITS
V
(Notes 1)
(Note 2)
V
V
V
CC
V
0.7 x V
-0.3
V + 0.3
CC
IH
CC
Input Logic 0
V
+0.3 x V
CC
IL
DC ELECTRICAL CHARACTERISTICS
(V
= 2.7V to 5.5V, T = -40°C to +85°C.)
A
CC
PARAMETER
Trip Point
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DS4510U-5
DS4510U-10
DS4510U-15
4.5
4.625
4.375
4.125
50
4.75
4.49
4.24
75
V
V
V
4.25
4.0
CC
CCTP
Standby Current
Input Leakage
I
V
= 5.0V (Note 3)
µA
µA
STBY
CC
I
-1.0
4.0
+1.0
0.4
L
3mA sink current
SDA Low-Level Output Voltage
V
V
OL
6mA sink current
0.6
I/O Low-Level Output Voltage
X
V
4mA sink current
0.4
V
V
OLIOX
RST Pin Low-Level Output
V
10mA sink current (Note 4)
0.4
OLRST
I/O Pullup Resistors
X
R
5.0
6.5
kΩ
pF
P
I/O Capacitance
C
(Note 5)
10
I/O
2
_____________________________________________________________________
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
CPU SUPERVISOR AC ELECTRICAL CHARACTERISTICS (See Figure 1)
(V
= 2.7V to 5.5V, T = -40°C to +85°C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
TD1= 0, TD0 = 0
MIN
112
225
450
900
112
225
450
900
TYP
125
250
500
1000
125
250
500
1000
4
MAX
138
275
550
1100
138
275
550
1100
10
UNITS
TD1= 0, TD0 = 1
TD1= 1, TD0 = 0
TD1= 1, TD0 = 1
TD1= 0, TD0 = 0
TD1= 0, TD0 = 1
TD1= 1, TD0 = 0
TD1= 1, TD0 = 1
RST Active Time
t
ms
RST
V
V
Detect to RST
Fail to RST
t
t
ms
µs
CC
CC
RPU
RPD
AC ELECTRICAL CHARACTERISTICS (See Figure 5)
(V
= 2.7V to 5.5V, T = -40°C to +85°C, timing referenced to V
IL(MAX)
and V .)
IH(MIN)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
(Note 6)
0
400
kHz
SCL
Bus Free Time Between Stop and
Start Conditions
t
1.3
0.6
µs
µs
BUF
Hold Time (Repeated) Start
Condition
t
HD:STA
Low Period of SCL
High Period of SCL
Data Hold Time
t
1.3
0.6
µs
µs
µs
ns
µs
ns
ns
µs
LOW
t
HIGH
t
0
0.9
HD:DAT
Data Setup Time
t
100
SU:DAT
Start Setup time
t
0.6
SU:STA
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Setup Time
t
(Note 7)
(Note 7)
20 + 0.1C
20 + 0.1C
0.6
300
300
R
B
t
F
B
t
SU:STO
SDA and SCL Capacitive
Loading
C
(Note 7)
(Note 7)
400
20
pF
B
EEPROM Write Time
t
10
ms
W
_____________________________________________________________________
3
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
NONVOLATILE MEMORY CHARACTERISTICS
(V
= 2.7V to 5.5V, T = 0°C to +70°C.)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Writes
+70°C (Note 5)
50,000
Note 1: All voltages referenced to ground.
Note 2: The DS4510 does not obstruct the SDA and SCL lines if V
is switched off, as long as the voltages applied to these
CC
inputs do not violate their min and max input voltage levels.
Note 3:
I
specified with V
equal to 5.0V, and control port-logic pins are driven to ground or V for the corresponding
STBY
CC
CC
inactive state (SDA = SCL = V ), does not include pullup resistor current.
CC
Note 4: See Typical Operating Characteristics for the RST output voltage vs. supply voltage.
Note 5: This parameter is guaranteed by design.
2
2
Note 6: I C interface timing shown for is for fast-mode (400kHz) operation. This device is also backward compatible with I C
standard-mode timing.
Note 7: C —total capacitance of one bus line in picofarads.
B
Note 8: EEPROM write time applies to all the EEPROM memory and SEEPROM memory when SEE = 0. The EEPROM write time
begins at the occurrence of a stop condition.
Typical Operating Characteristics
(V
= +5.0V, T = +25°C, unless otherwise noted.)
A
CC
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. SCL FREQUENCY
50
60
70
60
50
40
30
20
10
0
V
(10%)
50
40
30
20
10
0
CC
TRIP POINT
45
40
35
30
SDA = SCL = V
I/O CONTROL BITS = 0
I/O PULLUPS DISABLED
CC
SDA = V
300
CC
SDA = SCL = V
CC
3.0
3.5
4.0
4.5
5.0
-40
-20
0
20
40
60
80
0
100
200
400
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SCL FREQUENCY (kHz)
4
_____________________________________________________________________
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
Typical Operating Characteristics (continued)
(V
= +5.0V, T = +25°C, unless otherwise noted.)
A
CC
V
CC
TRIP POINT vs. TEMPERATURE
RST OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
I/O PULLUP RESISTANCE vs. TEMPERATURE
5.0
6.0
5.25
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
5.6kΩ PULLUP
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
4.75
RESISTOR ON RST
SDA = SCL = V
CC
-40
-20
0
20
40
60
80
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Pin Description
PIN
NAME
FUNCTION
I2C Address Input. This input pin determines the chip address of the device. A = 0 sets the slave
address to 1010000b, A = 1 sets the slave address to 1010001b.
0
0
1
A
0
2
3
SDA
SCL
Serial Data Input/Output. Bidirectional I2C data pin.
Serial Clock Input. I2C clock input.
4
V
Power Input
CC
5
GND
I/O3
I/O2
I/O1
I/O0
RST
Ground
6
Input/Output 3. I2C accessible bidirectional I/O pin.
Input/Output 2. I2C accessible bidirectional I/O pin.
Input/Output 1. I2C accessible bidirectional I/O pin.
Input/Output 0. I2C accessible bidirectional I/O pin.
Active-Low Reset Output. Open-drain CPU supervisor reset output.
7
8
9
10
_____________________________________________________________________
5
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
Functional Diagram
V
CC
SDA
SCL
A0
DS4510
2-WIRE
INTERFACE
RST
PROGRAMMABLE
RESET
TIMER
INTERNAL
VOLTAGE
V
CC
REFERENCE
V
CC
V
CC
4x
GND
4 BIDIRECTIONAL
NONVOLATILE I/O LATCHES
EEPROM
64 BYTES
USER
R
P
PULLUP ENABLE (F0h)
4 NV
I/O PINS
MEMORY
I/O CONTROL (F4h-F7h)
X
I/O STATUS (F8h)
determines if the power-on reset level of the DS4510 is
surpassed by V . The trip point bit determines if V
CCTP
in its active state.
Detailed Description
CC
CC
The DS4510 contains a CPU supervisor, four program-
mable I/O pins, and a 64-byte EEPROM memory. All
functions are configurable or controllable through an
industry-standard I2C-compatible bus. DS4510 NV reg-
isters that are likely to require frequent modification are
implemented using SRAM-shadowed EEPROM (SEEP-
ROM) memory. This memory is configurable to act as
volatile SRAM or NV EEPROM by adjusting the SEE bit
in the Config register. Configuring the SEEPROM as
SRAM eliminates the EEPROM write time and allows
infinite write cycles to these registers. Configuring the
registers as EEPROM allows the application to change
the power-on values that are recalled during power-up.
is above V
, and the reset status bit is set if RST is
Note: The RST pin is an open-drain output, therefore an
external pullup resistor must be used to realize high
logic levels.
Programmable NV Digital I/O Pins
Each programmable I/O pin contains an input, open-
X
collector output, and a selectable internal pullup resis-
tor. The DS4510 stores changes to the I/O pin in
X
SEEPROM memory. Using the SEEPROM as SRAM is
conducive to applications such as I/O expansion that
generally require fast access times and frequent modi-
fication of the I/O pin. Configuring the SEEPROM to
X
Programmable CPU Supervisor
The timeout period is adjusted by writing the reset
delay register (SEEPROM). The delay for each setting
is shown in the CPU Supervisor AC Electrical
Characteristics. If the SEE bit is set, changes are writ-
ten to SRAM. On power-up the last value written to the
EEPROM is recalled. The I2C bus is also used to acti-
vate the RST by setting the SWRST bit in the Config
register. This bit automatically returns to zero after the
timeout period. The Config register also contains the
ready, trip point, and reset status bits. The ready bit
behave as EEPROM allows the modification of the
power-on state of the I/O pin. During power-up the
X
I/O pins are high impedance until V
exceeds 2.0V
X
CC
(typically), which is when the last value programmed is
recalled from EEPROM. On power-down, the I/O state
X
is maintained until V
drops below 1.9V (typically).
CC
The internal pullups for each I/O pin are controlled by
X
the pullup-enable register (F0h). Similarly, the individual
I/O control registers (F4h to F7h) adjust the pulldown
X
6
_____________________________________________________________________
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
transistors. Read the I/O status register (F8h) to deter-
mine the logic levels present at the I/O pins.
t
R
t
F
V
CCTP (MAX)
V
V
CCTP (MAX)
CCTP
User Memory
Three types of memory are present in the DS4510
(EEPROM, SEEPROM, and SRAM). The main user
memory is 64 bytes of EEPROM starting at address
00h. This memory is not SRAM shadowed, so all writes
to these locations result in EEPROM write cycles
regardless of the state of the SEE bit. Additional memo-
ry for storing application data includes 6 bytes of SRAM
(FAh–FFh), and 2 bytes of SEEPROM (F2h, F3h). Refer
to the register memory map (Figure 3) for register
addresses and memory types. Figure 4 shows the bit
names for the memory-mapped I/O bytes and their fac-
tory default values.
V
V
CCTP (MIN)
CCTP
V
CCTP (MIN)
t
RPU
t
RPD
V
OH
V
OL
Figure 1. CPU Supervisor Power-Up and Power-Down Timing
The higher-order bits of the I/O registers that are not
used, such as the four most significant bits of the
pullup-enable byte (address F0h), can be used as
additional memory. It is the responsibility of the appli-
cation to ensure that writes to these bytes do not
adversely affect bits controlling special functions of the
DS4510.
REGISTER ADDRESS (HEX)
MEMORY TYPE
F8
SRAM
I/O STATUS
REGISTER NAME
Figure 2. How to Read the Memory Map
00
EE 01
USER BYTE
EE 09
USER BYTE
EE 11
USER BYTE
EE 19
USER BYTE
EE 21
USER BYTE
EE 29
USER BYTE
EE 31
USER BYTE
EE 39
USER BYTE
EE 02
User byte
EE 0A
USER BYTE
EE 12
USER BYTE
EE 1A
USER BYTE
EE 22
USER BYTE
EE 2A
USER BYTE
EE 32
USER BYTE
EE 3A
USER BYTE
EE 03
USER BYTE
EE 0B
USER BYTE
EE 13
USER BYTE
EE 1B
USER BYTE
EE 23
USER BYTE
EE 2B
USER BYTE
EE 33
USER BYTE
EE 3B
USER BYTE
EE 04
USER BYTE
EE 0C
USER BYTE
EE 14
USER BYTE
EE 1C
USER BYTE
EE 24
USER BYTE
EE 2C
USER BYTE
EE 34
USER BYTE
EE 3C
USER BYTE
EE 05
USER BYTE
EE 0D
USER BYTE
EE 15
USER BYTE
EE 1D
USER BYTE
EE 25
USER BYTE
EE 2D
USER BYTE
EE 35
USER BYTE
EE 3D
USER BYTE
EE 06
USER BYTE
EE 0E
USER BYTE
EE 16
USER BYTE
EE 1E
USER BYTE
EE 26
USER BYTE
EE 2E
USER BYTE
EE 36
USER BYTE
EE 3E
USER BYTE
EE 07
USER BYTE
EE 0F
USER BYTE
EE 17
USER BYTE
EE 1F
EE
EE
EE
EE
EE
EE
EE
EE
USER BYTE
08
USER BYTE
10
USER BYTE
18
USER BYTE
20
USER BYTE
28
USER BYTE
30
USER BYTE
38
USER BYTE
EE 27
USER BYTE
EE 2F
USER BYTE
EE 37
USER BYTE
EE 3F
USER BYTE
40
USER BYTE
47
41
42
43
44
45
46
RESERVED
E8
E9
EA
EB
EC
ED
EE
EF
F0
SEE F1
SEE F2
SEE F3
SEE F4
SEE F5
SEE F6
SEE F7
SEE
PULLUP ENABLE
RESET DELAY
USER BYTE
SRAM FA
USER BYTE
USER BYTE
SRAM FB
USER BYTE
I/O CONTROL
I/O CONTROL
I/O CONTROL
I/O CONTROL
3
2
1
0
F8
SRAM F9
CONFIG
SRAM FC
USER BYTE
SRAM FD
USER BYTE
SRAM FE
USER BYTE
SRAM FF
USER BYTE
SRAM
I/O STATUS
*ITALICIZED BYTES HAVE BIT DESCRPTIONS, REFER TO FIGURE 3.
Figure 3. Register Memory Map
_____________________________________________________________________
7
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
FACTORY OR
REGISTER BIT NAMES
REGISTER
LOCATION
(HEX)
REGISTER
NAME
POWER-ON
DEFAULT
(BIN)
Bit 7
Bit 6
Bit5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User
EEPROM
00-3F
40-EF
F0
EE
n/a
EE
n/a
EE
n/a
EE
n/a
EE
EE
EE
EE
00000000
n/a
Reserved
n/a
n/a
n/a
n/a
Pullup
Enable
I/O3
pullup
I/O2
pullup
I/O1
pullup
I/O0
pullup
SEE
SEE
SEE
SEE
00000000
RST Delay
User SEE
User SEE
F1
F2
F3
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
TD1
SEE
SEE
TD0
SEE
SEE
00000011
00000000
00000000
I/O3
Control
F4
F5
F6
F7
F8
SEE
SEE
SEE
SEE
0
SEE
SEE
SEE
SEE
0
SEE
SEE
SEE
SEE
0
SEE
SEE
SEE
SEE
0
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
I/O3
I/O2
I/O1
I/O0
00000001
00000001
00000001
00000001
n/a
I/O2
Control
I/O1
Control
I/O0
Control
I/O3
Status
I/O2
Status
I/O1
Status
I/O0
Status
I/O Status
reset
status
Config
F9
ready
trip point
SRAM
SEE
SWRST
SRAM
0
0
0
XXX00000
00000000
User SRAM
FA-FF
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
Figure 4. Register Bit Names
SDA from low to high while SCL remains high gener-
ates a stop condition. See the I2C Timing Diagram for
applicable timing.
2
I C Definitions
The following terminology is commonly used to
describe I2C data transfers.
Repeated Start Condition: The master can use a
repeated start condition at the end of one data transfer
to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a
specific memory address to begin a data transfer. A
repeated start condition is issued identically to a nor-
mal start condition. See the I2C Timing Diagram for
applicable timing.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, start, and stop conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL (see
Figure 5) plus the setup and hold-time requirements.
Data is shifted into the device during the rising edge of
the SCL.
Start Condition: A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition. See the timing dia-
gram for applicable timing.
Stop Condition: A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
Bit Read: At the end a write operation, the master must
release the SDA bus line for the proper amount of setup
8
_____________________________________________________________________
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
Table 1. Register Definitions
REGISTER
LOCATION (HEX)
REGISTER
NAME
FUNCTION
00 to 3F
40 to EF
User EEPROM
Reserved
64 bytes of EEPROM memory.
These memory locations are reserved for future products.
The four least significant bits of this register each enable/disable one of the internal pullup
resistors. Set the bit to enable the pullup, clear it to disable the pullup.
F0
Pullup Enable
The two LSBs of this register (TD1 and TD0) select the reset delay (t
CPU Supervisor AC Timing Characteristics.
) as shown in the
RST
F1
RST Delay
F2 to F3
F4 to F7
User SEEPROM SRAM Shadowed EEPROM user byte.
Clearing the LSB of the register enables the I/O pulldown transistor; setting the bit disables
X
I/O Control
X
the pulldown transistor.
This register reflects the logic level of the I/O pins. The upper four bits of this register
X
always read zero.
F8
F9
I/O Status
Config
This register contains 5 bits that read and control the behavior of the part as follows:
Bit Name
ready
Bit Function
Reads zero when V
is above the DS4510's power-on reset voltage.
CC
Trip Point
Reset Status
Reads one when V
below V
.
CC
CCTP
Reads one when the RST pin is active.
When zero, writes to the SEEPROM registers behave like EEPROM. When one, writes to the
SEEPROM registers behave like SRAM.
SEE
Setting this bit activates the RST output. This bit automatically returns to zero during the
RST active time.
SWRST
FA to FF
User SRAM
6 bytes of SRAM memory
time (see Figure 5) before the next rising edge of SCL
during a bit read. The device shifts out each bit of data
on SDA at the falling edge of the previous SCL pulse
and the data bit is valid at the rising edge of the current
SCL pulse. Remember that the master generates all
SCL clock pulses, including when it is reading bits from
the slave.
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit-write definition and the
acknowledgement is read using the bit-read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the
bit-read definition above, and the master transmits an
ACK using the bit-write definition to receive additional
data bytes. The master must NACK the last byte read
to terminate communication so the slave will return con-
trol of SDA to the master.
Slave Address and the R/W Bit: Each slave on the I2C
bus responds to a slave addressing byte sent immedi-
ately following a start condition. The slave address byte
contains the slave address and the R/W bit. The slave
address (see Figure 6) is the most significant 7 bits and
the R/W bit is the least significant bit.
Acknowledgement (ACK and NACK): An
Acknowledgement (ACK) or Not Acknowledge (NACK)
is always the 9th bit transmitted during a byte transfer.
The device receiving data (the master during a read or
the slave during a write operation) performs an ACK by
transmitting a zero during the 9th bit. A device per-
forms a NACK by transmitting a one during the 9th bit.
Timing (Figure 5) for the ACK and NACK is identical to
all other bit writes. An ACK is the acknowledgment that
the device is properly receiving data. A NACK is used
to terminate a read sequence or as an indication that
the device is not receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from the
The DS4510’s slave address is 101000A (binary),
0
where A is the value of the A address pin. The
0
0
_____________________________________________________________________
9
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
SDA
t
BUF
t
SP
t
HD:STA
t
F
t
R
t
LOW
SCL
t
t
HD:STA
SU:STA
t
HIGH
t
t
REPEATED
START
STOP
START
SU:STO
SU:DAT
t
HD:DAT
NOTE: TIMING IS REFERENCE TO V
AND V
IH(MIN)
IL(MAX)
2
Figure 5. I C Timing Diagram
address pin allows for the DS4510 to respond to one of
two slave addresses (1010000X, or 1010001X). If the
R/W bit is zero, the master writes data to the slave. If
the R/W is one, the master reads data from the slave.
Memory Address: During an I2C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte (R/W = 0).
2
I C Communications
Writing a Single Byte to a Slave: The master must
generate a start condition, write the slave address
(R/W= 0), write the memory address, write the byte of
data and generate a stop condition. Remember the
master must read the slave’s acknowledgement during
all byte write operations.
Writing a Multiple Bytes to a Slave: To write multiple
bytes to a slave the master generates a start condition,
writes the slave address (R/W = 0), writes the memory
address, writes up to 8 data bytes, and generates a
stop condition.
The DS4510 can write 1 to 8 bytes (one page or row)
with a single write transaction. This is internally con-
trolled by an address counter that allows data to be
written to consecutive addresses without transmitting a
memory address before each data byte is sent. The
address counter limits the write to one 8-byte page
(one row of the memory table, see Figure 3). Attempts
to write to additional pages of memory without sending
a stop condition between pages results in the address
counter wrapping around to the beginning of the pre-
sent row.
Example: A 3-byte write starts at address 06h and
writes three data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result would be address-
es 06h and 07h would contain 11h and 22h, respective-
ly, and the third data byte, 33h, would be written to
address 00h.
7-BIT SLAVE ADDRESS
A
1
0
1
0
0
0
R/W
0
MOST
SIGNIFICANT BIT
A0 PIN
VALUE
DETERMINES
READ OR WRITE
To prevent address wrapping from occurring, the mas-
ter must send a stop condition at the end of the page,
then wait for the bus-free or EEPROM-write time to
elapse. The master may then generate a new start con-
Figure 6. DS4510’s Slave Address and the R/W Bit
10
____________________________________________________________________
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
Reading Multiple Bytes from a Slave: The read oper-
ation can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the mas-
ter reads the last byte it NACKs to indicate the end of
the transfer and generates a stop condition. This can
be done with or without modifying the address
counter’s location before the read cycle. The DS4510
does not wrap on page boundaries during read opera-
tions, but the counter rolls from its upper-most memory
address FFh to 00h if the last memory location is read
during the read transaction.
dition, write the slave address (R/W = 0), and the first
memory address of the next page before continuing to
write data.
Acknowledge Polling: Any time an EEPROM page is
written, the DS4510 requires the EEPROM write time
(t ) after the stop condition to write the contents of the
W
page to EEPROM. During the EEPROM write time, the
DS4510 does not acknowledge its slave address
because it is busy. It is possible to take advantage of
that phenomenon by repeated addressing the DS4510,
which allows the next page to be written as soon as the
DS4510 is ready to receive the data. The alternative to
acknowledge polling is to wait for maximum period of
Example: The entire memory contents of the DS4510
can be read with a single transfer starting at address
F0h that reads 80 bytes of data. Addresses F0h to FFh
are read sequentially, the address counter rolls to 00h,
and then addresses 00h to 3Fh can be read sequential-
ly. This allows the entire memory contents to be read in
a single operation without reading the undefined con-
tents of the reserved area of the memory.
t
to elapse before attempting to write again to the
W
DS4510.
EEPROM Write Cycles: When EEPROM writes occur,
the DS4510 writes the whole EEPROM memory page
even if only a single byte on the page was modified.
Writes that do not modify all 8 bytes on the page are
allowed and do not corrupt the remaining bytes of
memory on the same page. Because the whole page is
written, bytes on the page that were not modified dur-
ing the transaction are still subject to a write cycle. This
can result in a whole page being worn out over time by
writing a single byte repeatedly. Writing a page one
byte at a time wears the EEPROM out eight times faster
than writing the entire page at once. The DS4510’s
EEPROM memory is guaranteed to handle 50,000 write
cycles at +70°C. Writing to SEEPROM memory with
SEE = 1 does not count as an EEPROM write cycle
when evaluating the EEPROM’s estimated lifetime.
Application Information
Advantages of Using the SEE Bit to Disable
EEPROM Writes
The SEE bit allows EEPROM writes to be disabled for
the SRAM-shadowed EEPROM bytes, allowing the
SRAM of SEE registers to change without writing the
EEPROM to the same value. This prevents write opera-
tions from changing the power-on value of the I/O pins,
reduces the number of EEPROM write cycles, and
speeds up I/O operations because the DS4510 does
not require an internally timed EEPROM write cycle to
complete the operation.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the memory address byte to define
where the data is to be written, the read operation
occurs at the present value of the memory address
counter. To read a single byte from the slave the mas-
ter generates a start condition, writes the slave address
with R/W = 1, reads the data byte with a NACK to indi-
cate the end of the transfer, and generates a stop con-
dition.
Power-Supply Decoupling
To achieve the best results when using the DS4510,
decouple the power supply with a 0.01µF or a 0.1µF
capacitor. Use high-quality, ceramic, surface-mount
capacitors, and mount the capacitors as close as pos-
sible to the V
and GND pins of the DS4510 to mini-
CC
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master gen-
erates a start condition, writes the slave address (R/W
= 0), writes the memory address where it desires to
read, generates a repeated start condition, writes the
slave address (R/W = 1), reads data with ACK or NACK
as applicable, and generates a stop condition.
mize lead inductance.
SDA and SCL Pullup Resistors
SDA is an open-collector output on the DS4510 that
requires a pullup resistor to realize high logic levels.
Because the DS4510 does not utilize clock cycle
stretching, a master using either an open-collector out-
put with a pullup resistor or a normal output driver can
be utilized for SCL. Pullup resistor values should be
chosen to ensure that the rise and fall times listed in the
AC Electrical Characteristics are within specification.
See Figure 7 for a read example using the repeated
start condition dummy write cycle.
____________________________________________________________________ 11
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
COMMUNICATIONS KEY
NOTES:
WHITE BOXES INDICATED THE MASTER IS
CONTROLLING SDA
START
STOP
ACK
1) ALL BYTES ARE SENT MOST SIGNIFICANT
BIT FIRST.
S
A
NOT
ACK
SHADED BOXES INDICATED THE SLAVE IS
CONTROLLING SDA
2) THE FIRST BYTE SENT AFTER A START
CONDITION IS ALWAYS THE SLAVE ADDRESS
FOLLOWED BY THE READ/WRITE BIT.
P
N
REPEATED
START
Sr
X
X
X
0
X
X
X
X
X
8-BITS ADDRESS OR DATA
WRITE A SINGLE BYTE
1
0
1
0
0
0 A
MEMORY ADDRESS
DATA
DATA
1
S
A
A
A
A
A
P
0
WRITE UP TO AN 8-BYTE PAGE WITH A SINGLE TRANSACTION
0 A MEMORY ADDRESS
1
0
1
0
0
0
DATA
S
A
A
P
0
READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO MOVE THE ADDRESS COUNTER
0 A MEMORY ADDRESS
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
A
A
1
1
DATA
DATA
P
S
A
A
Sr
A
A
N
A
P
0
0
READ MULTIPLE BYTES WITH A DUMMY WRITE CYCLE TO MOVE THE ADDRESS COUNTER
1
0
1
0
0
0 A
0
0
MEMORY ADDRESS
1
1
S
A
A
Sr
0
DATA
DATA
DATA
A
A
N
2
Figure 7. I C Communications Examples
Chip Topology
TRANSISTOR COUNT: 16559
SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
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is a registered trademark of Maxim Integrated Products.
is a registered trademark of Dallas Semiconductor Corporation.
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