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DS3906U+ [MAXIM]

Digital Potentiometer, 3 Func, 10000ohm, 3-wire Serial Control Interface, PDSO10, LEAD FREE, MICRO, SOP-10;
DS3906U+
型号： DS3906U+
厂家： MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述：

Digital Potentiometer, 3 Func, 10000ohm, 3-wire Serial Control Interface, PDSO10, LEAD FREE, MICRO, SOP-10

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Rev 0; 4/05  
Triple NV Low Step Size Variable  
Resistor Plus Memory  
General Description  
Features  
♦ Three Programmable Resistors for Low Step-Size  
The DS3906 is intended for low resistance, small step-  
size applications. It contains three nonvolatile (NV), low-  
temperature coefficient, variable digital resistors that  
are capable of ohm and subohm increments when  
used in parallel with a fixed external resistor. All three of  
the DS3906’s resistors have 64 positions (plus a high-Z  
state) with a pseudo-log response cleverly chosen to  
have a linear equivalent resistance when paired with an  
external resistor (see graphs below). The DS3906 also  
contains 16 bytes of user EEPROM that, in addition to  
the resistors, are controlled through an I2C™-compati-  
ble serial interface. Three address pins allow up to  
eight DS3906s to be placed on the same I2C bus.  
Applications (Ohm and Subohm)  
♦ Resistor Settings are NV  
♦ 16-Byte NV User Memory (EEPROM)  
2
♦ I C-Compatible Serial Interface  
♦ Up to 8 Devices Can be Multidropped on the  
2
Same I C Bus  
♦ Low Power Consumption  
♦ Wide Operating Voltage (2.7V to 5.5V)  
♦ Operating Temperature Range: -40°C to +85°C  
Ordering Information  
The DS3906 can also be factory cutomized to provide a  
variety of transfer functions depending on user  
requirements. Contact mixedsignal.apps@dalsemi.com  
for additional information.  
PART  
DS3906U  
DS3906U+  
TEMP RANGE  
-40°C to +85°C  
-40°C to +85°C  
PACKAGE  
10-Pin µSOP  
10-Pin µSOP  
+Denotes lead-free package.  
Add “/T&R” for Tape-and-Reel orders  
Applications  
Low Ohm, Fine Resolution Driver Control for LED  
Display Panels  
Pin Configuration  
TOP VEIW  
Low Ohm, Fine Resolution Instrumentation Control  
A1  
1
2
3
4
5
10 A2  
SDA  
9
8
7
6
A0  
H0  
H1  
H2  
SCL  
DS3906  
V
CC  
Typical Operating Circuit appears at end of data sheet.  
GND  
10-PIN µSOP  
Resistor Plots  
RESISTOR 0 AND 1 RESISTANCE vs. POSITION  
(WITH AND WITHOUT EXTERNAL RESISTOR)  
RESISTOR 2 RESISTANCE vs. POSITION  
(WITH AND WITHOUT EXTERNAL RESISTOR)  
200  
180  
160  
140  
120  
100  
80  
3000  
2500  
2000  
1500  
100  
500  
20  
350  
1600  
R0  
R1  
R2  
R
R
R
EXT0  
EXT1  
EXT2  
R || (R = 400Ω)  
2
EXT  
300  
250  
200  
150  
100  
50  
1400  
1200  
1000  
800  
R || (R = 310Ω)  
2
EXT  
R
|| (R = 150Ω)  
EXT  
0, 1  
R
0, 1  
|| (R = 105Ω)  
EXT  
DS3906  
R || (R = 250Ω)  
2
EXT  
R
0, 1  
|| (R = 50Ω)  
EXT  
60  
R WITHOUT R  
2
EXT  
40  
600  
20  
R
WITHOUT R  
48  
0, 1  
EXT  
0
0
0
400  
0
16  
32  
64  
0
16  
32  
48  
64  
RESISTOR POSITION (dec)  
RESISTOR POSITION (dec)  
2
2
I C is a trademark of Philips Corp. Purchase of I C components of Maxim Integrated Products, Inc., or one of its sublicensed  
2
2
Associated Companies, conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided  
that the system conforms to the I C Standard Specification as defined by Philips Corp.  
2
______________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  
Triple NV Low Step Size Variable  
Resistor Plus Memory  
ABSOLUTE MAXIMUM RATINGS  
Voltage on V , SDA, SCL, and H0-H2 Pins  
Operating Temperature Range ...........................-40°C to +85°C  
EEPROM Programming Temperature Range .........0°C to +70°C  
Storage Temperature Range ............................-55°C to +125°C  
Soldering Temperature...................See J-STD-020 Specification  
CC  
Relative to Ground.............................................-0.5V to +6.0V  
Voltage on A0, A1, and A2  
Relative to Ground.....-0.5V to V + 0.5V, not to exceed +6.0V  
CC  
Resistor Current ....................................................................5mA  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS  
(T = -40°C to +85°C)  
A
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Supply Voltage  
V
(Note 1)  
+2.7  
+5.5  
V
CC  
0.7 x  
V
+
CC  
0.3  
Input Logic 1  
Input Logic 0  
V
V
V
IH  
V
CC  
0.3 x  
V
V
-0.3  
-0.3  
IL  
CC  
Resistor Inputs  
Resistor Current  
H0, H1, H2  
V
= 2.7V to 5.5V  
+5.5  
5
V
CC  
I
R
mA  
DC ELECTRICAL CHARACTERISTICS  
(V  
CC  
= +2.7V to +5.5V, T = -40°C to +85°C, unless otherwise noted.)  
A
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
130  
160  
MAX  
UNITS  
µA  
3V  
Standby Current (Note 2)  
Input Leakage for All Pins  
Low-Level Output Voltage (SDA)  
I/O Capacitance  
I
STBY  
5V  
250  
+1.0  
0.4  
I
(Note 3)  
-1.0  
0
µA  
L
3mA sink current  
6mA sink current  
V
V
OL SDA  
0
0.6  
C
10  
pF  
I/O  
ANALOG RESISTOR CHARACTERISTICS  
(V  
CC  
= +2.7V to +5.5V, T = -40°C to +85°C, unless otherwise noted.)  
A
PARAMETER  
SYMBOL  
CONDITIONS  
From nominal values in Table 3  
(Note 4)  
MIN  
-20  
-2  
TYP  
MAX  
+20  
+2  
UNITS  
%
Resistor Tolerance  
INL  
LSB  
DNL  
(Note 4)  
-0.5  
+0.5  
LSB  
Temperature Coefficient  
Resistor High-Z  
Resistors  
At position 3Fh (Note 8)  
60  
ppm/°C  
MΩ  
R
5.5  
HIGH-Z  
Guaranteed monotonic by design  
2
_____________________________________________________________________  
Triple NV Low Step Size Variable  
Resistor Plus Memory  
AC ELECTRICAL CHARACTERISTICS (See Figure 2)  
(V  
= +2.7V to 5.5V, T = -40°C to +85°C, unless otherwise noted. Timing referenced to V  
and V  
.)  
CC  
A
IL(MAX)  
IH(MIN)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
SCL Clock Frequency  
f
(Note 5)  
0
400  
kHz  
SCL  
Bus Free Time Between Stop and  
Start Conditions  
t
1.3  
µs  
µs  
BUF  
Hold Time (Repeated) Start  
Condition  
t
0.6  
HD:STA  
Low Period of SCL  
High Period of SCL  
Data Hold Time  
t
1.3  
0.6  
0
µs  
µs  
µs  
ns  
µs  
LOW  
t
HIGH  
t
0.9  
HD:DAT  
Data Set-up Time  
Start Set-up time  
t
100  
0.6  
SU:DAT  
t
SU:STA  
20 +  
SDA and SCL Rise Time  
t
(Note 6)  
(Note 6)  
300  
300  
ns  
R
0.1C  
B
20 +  
SDA and SCL Fall Time  
Stop Set-up Time  
t
ns  
µs  
F
0.1C  
B
t
0.6  
SU:STO  
SDA and SCL Capacitive  
Loading  
C
(Note 6)  
(Note 7)  
400  
20  
pF  
ms  
B
EEPROM Write Time  
t
WR  
NONVOLATILE MEMORY CHARACTERISTICS  
(V  
CC  
= +2.7V to 5.5V)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
0°C to +70°C. The room temperature  
specification is at least 4x better than  
specification over 0°C to +70°C.  
EEPROM Writes  
50,000  
Note 1: All voltages referenced to ground.  
Note 2: I is specified with SDA = SCL = V , resistor pins floating, and inputs tied to V or GND.  
CC  
STBY  
CC  
Note 3: The DS3906 will not obstruct the SDA and SCL lines if V  
is switched off as long as the voltages applied to these input do  
CC  
not violate their minimum and maximum input voltage levels.  
Note 4: Tested with external resistor of 87Ω for R and R and 258Ω for R at 25°C.  
0
1
2
Note 5: Timing shown is for fast mode (400kHz) operation. This device is also backward compatible with I2C standard mode timing.  
Note 6: C ⎯total capacitance of one bus line in picofarads.  
B
Note 7: The EEPROM write time begins after a stop condition occurs.  
Note 8: Guaranteed by design.  
_____________________________________________________________________  
3
Triple NV Low Step Size Variable  
Resistor Plus Memory  
Typical Operating Characteristics  
(V = +5.0V, T = +25°C, unless otherwise noted.)  
CC  
A
SUPPLY CURRENT  
vs. SUPPLY VOLTAGE  
SUPPLY CURRENT  
vs. TEMPERATURE  
SUPPLY CURRENT  
vs. SCL FREQUENCY  
180  
160  
140  
120  
100  
80  
200  
200  
180  
160  
140  
120  
100  
80  
V
= 5V  
CC  
180  
160  
140  
120  
100  
80  
V
CC  
= 3.3V  
60  
60  
60  
40  
40  
SDA/SCL = V  
ADDRESS PINS  
CONNECTED TO GND  
CC  
40  
V
= SDA = 5V  
CC  
ADDRESS PINS  
CONNECTED TO GND  
20  
20  
20  
0
0
0
3.70  
4.20  
5.20  
-40  
-15  
10  
35  
60  
85  
2.70  
3.20  
4.70  
0
50 100 150 200 250 300 350 400  
SCL FREQUENCY (kHz)  
TEMPERATURE (°C)  
SUPPLY VOLTAGE (V)  
RESISTANCE (R ⎥⎥R  
)
EXT  
0,1  
RESISTORS (R  
vs. RESISTOR SETTING  
)
RESISTOR R  
2
vs. RESISTOR SETTING  
0,1  
vs. RESISTOR SETTING  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
3000  
2500  
2000  
1500  
1000  
500  
1600  
1400  
1200  
1000  
800  
600  
400  
200  
0
R
= 87Ω  
EXT  
0
50  
60  
0
10  
20  
30  
40  
70  
0
10  
20  
30  
40  
50  
60  
70  
30  
RESISTOR SETTING (dec)  
60  
0
10  
20  
40  
50  
70  
RESISTOR SETTING (dec)  
RESISTOR SETTING (dec)  
RESISTANCE (R ⎥⎥R  
)
EXT  
2
RESISTOR R TEMPERATURE COEFFICIENT  
0,1  
vs. RESISTOR SETTING  
(-40°C TO +25°C) vs. RESISTOR SETTING  
250  
200  
150  
100  
50  
250  
200  
150  
100  
50  
R
= 258Ω  
EXT  
-40°C TO +25°C  
0
0
-50  
0
10  
20  
30  
40  
50  
60  
70  
50  
60  
0
10  
20  
30  
40  
70  
RESISTOR SETTING (dec)  
RESISTOR SETTING (dec)  
4
_____________________________________________________________________  
Triple NV Low Step Size Variable  
Resistor Plus Memory  
Typical Operating Characteristics (continued)  
(V = +5.0V, T = +25°C, unless otherwise noted.)  
CC  
A
RESISTOR R TEMPERATURE COEFFICIENT  
0,1  
(+25°C TO +85°C) vs. RESISTOR SETTING  
RESISTOR R TEMPERATURE COEFFICIENT  
2
(-40°C TO +25°C) vs. RESISTOR SETTING  
RESISTOR R TEMPERATURE COEFFICIENT  
2
(+25°C TO +85°C) vs. RESISTOR SETTING  
400  
15  
10  
5
180  
160  
140  
120  
100  
80  
350  
300  
250  
200  
150  
100  
50  
+25°C TO +85°C  
+25°C TO +85°C  
-40°C TO +25°C  
0
-5  
-10  
-15  
-20  
-25  
60  
40  
20  
0
0
0
10  
20  
30  
RESISTOR SETTING (dec)  
40  
50  
60  
70  
0
10  
20  
30  
RESISTOR SETTING (dec)  
40  
50  
60  
70  
0
10  
20  
30  
40  
50  
60  
70  
RESISTOR SETTING (dec)  
RESISTANCE  
vs. SUPPLY VOLTAGE  
R
RESISTANCE AT POSITION 2Fh  
vs. POWER-UP VOLTAGE  
0,1  
5000  
4500  
4000  
3500  
3000  
2500  
2000  
1500  
1000  
500  
>5.5MΩ  
RESISTORS R  
0,1  
2000  
1500  
1000  
500  
EEPROM  
RECALL  
RESISTOR R AT POSITION 1Fh  
2
PROGRAMMED  
VALUE  
RESISTOR R AT POSITION 2Fh  
0,1  
0
0
3
4
5
0
1
2
4.20  
4.70  
5.20  
2.70  
3.20  
3.70  
POWER-SUPPLY VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
R RESISTANCE AT POSITION 1Fh  
2
R
RESISTANCE AT POSITION 2Fh  
vs. POWER-UP VOLTAGE  
0,1  
vs. POWER-UP VOLTAGE  
4000  
3500  
3000  
2500  
2000  
1500  
1000  
500  
500  
450  
400  
350  
300  
250  
200  
150  
100  
50  
RESISTOR R  
>5.5MΩ  
2
>5.5MΩ  
RESISTOR R  
0,1  
EEPROM  
RECALL  
EEPROM  
RECALL  
PROGRAMMED  
VALUE  
PROGRAMMED  
VALUE  
0
0
0
1
2
3
4
5
4
3
0
5
2
1
0
POWER-UP VOLTAGE (V)  
POWER-DOWN VOLTAGE (V)  
_____________________________________________________________________  
5
Triple NV Low Step Size Variable  
Resistor Plus Memory  
Typical Operating Characteristics (continued)  
(V = +5.0V, T = +25°C, unless otherwise noted.)  
CC  
A
R RESISTANCE AT POSITION 1Fh  
2
INL vs. RESISTOR SETTING FOR  
DNL vs. RESISTOR SETTING FOR  
vs. POWER-UP VOLTAGE  
(R ⎥⎥R  
0
)
EXT  
(R ⎥⎥R  
0
)
EXT  
4000  
2.0  
1.5  
1.0  
0.8  
>5.5MΩ  
RESISTOR R  
(R ⎥⎥R  
EXT  
)
EXT  
= 87Ω  
2
0
(R ⎥⎥R  
EXT  
)
EXT  
= 87Ω  
0
3500  
3000  
2500  
2000  
1500  
1000  
500  
R
R
0.6  
1.0  
0.4  
0.5  
EEPROM  
RECALL  
0.2  
0
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.5  
-1.0  
-1.5  
-2.0  
PROGRAMMED  
VALUE  
0
4
3
2
5
1
0
0
10  
20  
30  
40  
60  
50  
30  
0
20  
40  
50  
60  
10  
POWER-DOWN VOLTAGE (V)  
RESISTOR SETTING (dec)  
RESISTOR SETTING (dec)  
INL vs. RESISTOR SETTING FOR  
DNL vs. RESISTOR SETTING FOR  
(R ⎥⎥R  
)
(R ⎥⎥R  
)
1
EXT  
1
EXT  
2.0  
1.5  
1.0  
0.8  
(R ⎥⎥R  
EXT  
)
EXT  
= 87Ω  
1
(R ⎥⎥R  
EXT  
)
1
EXT  
R
R
= 87Ω  
0.6  
1.0  
0.4  
0.5  
0.2  
0
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.5  
-1.0  
-1.5  
-2.0  
10  
20  
40  
0
30  
50  
60  
10  
0
20  
30  
40  
50  
60  
RESISTOR SETTING (dec)  
RESISTOR SETTING (dec)  
INL vs. RESISTOR SETTING FOR  
DNL vs. RESISTOR SETTING FOR  
(R ⎥⎥R  
)
2
EXT  
(R ⎥⎥R  
)
2
EXT  
2.0  
1.5  
1.0  
0.8  
(R ⎥⎥R  
EXT  
)
(R ⎥⎥R  
EXT  
)
EXT  
= 258Ω  
2
EXT  
2
R
= 258Ω  
R
0.6  
1.0  
0.4  
0.5  
0.2  
0
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.5  
-1.0  
-1.5  
-2.0  
0
10  
20  
30  
40  
50  
60  
0
30  
40  
50  
10  
20  
60  
RESISTOR SETTING (dec)  
RESISTOR SETTING (dec)  
6
_____________________________________________________________________  
Triple NV Low Step Size Variable  
Resistor Plus Memory  
Pin Description  
PIN  
1
NAME  
A1  
FUNCTION  
I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device.  
I2C Serial Data Open-Drain Input/Output  
I2C Serial Clock Input  
2
SDA  
SCL  
3
4
V
Power Supply Voltage  
CC  
5
GND  
H2  
Ground  
6
High Terminal of Resistor 2  
7
H1  
High Terminal of Resistor 1  
8
H0  
High Terminal of Resistor 0  
9
A0  
I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device.  
10  
A2  
Block Diagram  
Detailed Description  
The DS3906 contains three variable resistors plus a  
user EEPROM. The block diagram illustrates these in  
addition to the registers that control the resistors. The  
following sections provide detailed information about  
the DS3906.  
V
CC  
EEPROM  
RHIZ CONTROL  
H0  
H1  
V
CC  
Memory Organization  
The DS3906 contains 16 bytes of User EEPROM plus 3  
NV resistor registers. Refer to Table 1. Communication  
RES 0  
2.54kΩ  
F8h  
F9h  
RESISTOR 0  
DS3906  
MSB  
LSB  
6
2
with the memory/registers is achieved through the I C-  
GND  
SCL  
RHIZ CONTROL  
compatible serial interface and is described in subse-  
quent sections.  
Resistor Registers/Settings  
Each of the three resistors in the DS3906 has its own  
control register used to set the resistor position. Refer  
to the block diagram and Table 2. Each resistor has 64  
positions plus a high impedance state. The nominal  
resistance values for each position is listed in Table 3.  
Resistors 0 and 1 have the same full-scale resistance,  
which is different than resistor 2. As shown in Table 3,  
the resistors have a pseudo-log response (resistance  
vs. position) when used without an external parallel  
resistor. Valid resistor settings are 00h to 3Fh. Writing a  
value greater than 3Fh to any of the resistor registers  
RES 1  
2.54kΩ  
RESISTOR 1  
SDA  
A0  
2
I C  
MSB  
LSB  
6
INTERFACE  
A1  
RHIZ CONTROL  
H2  
A2  
FAh  
RES 2  
1.45kΩ  
RESISTOR 2  
USER  
EEPROM  
16 BYTES  
(00h-0Fh)  
MSB  
LSB  
6
_____________________________________________________________________  
7
Triple NV Low Step Size Variable  
Resistor Plus Memory  
makes the corresponding resistor go High-Z. Plots for  
both resistor sizes are shown on the front page of this  
data sheet. It can be seen that, when an external resis-  
tor is connected in parallel with the DS3906’s resistors,  
the effective resistance is linear and capable of achiev-  
ing sub-ohm and ohm steps.  
reading from the device or when performing single byte  
writes. However, this limits the maximum number of  
bytes that can be written in one I2C transaction to two.  
Furthermore, the multiple byte writes must begin on  
even memory addresses (00h, 02h, …., F8h, etc).  
Additional information is provided later in the I2C  
Communication section . Example communication  
transactions are provided in Figure 3.  
The resistor settings are stored in EEPROM memory. It  
is important to point out that the DS3906 EEPROM is  
organized in 2-byte pages. This is transparent when  
Table 1. DS3906 Memory Map  
FACTORY  
ADDRESS  
TYPE  
NAME  
FUNCTION  
DEFAULT  
00h to 0Fh  
EEPROM  
EEPROM  
EEPROM  
EEPROM  
User memory 16 bytes of general-purpose user EEPROM.  
Resistor 0  
00h  
3Fh  
3Fh  
3Fh  
F8h  
Resistor 0-2 settings. See Table 2 and the Resistor  
F9h  
Resistor 1  
Registers/Settings section.  
FAh  
Resistor 2  
FBh-FFh  
Reserved  
Table 2. DS3906 Resistor Registers  
POSITION 3FH RESISTANCE  
ADDRESS  
VARIABLE RESISTOR  
NUMBER OF POSITIONS*  
(kΩ)  
F8h  
F9h  
FAh  
Resistor 0  
Resistor 1  
Resistor 2  
2.54  
2.54  
1.45  
64 (00h to 3Fh) + High-Z  
* Writing a value greater than 3Fh to any of the resistor registers makes the corresponding resistor go High-Z. Position 3Fh is the  
maximum position.  
8
_____________________________________________________________________  
Triple NV Low Step Size Variable  
Resistor Plus Memory  
Table 3. DS3906 Resistor Settings (without external resistor)  
NOMINAL RESISTOR VALUES  
WITHOUT EXT RESISTOR (25°C)  
NOMINAL RESISTOR VALUES  
WITHOUT EXT RESISTOR (25°C)  
POSITION  
POSITION  
Dec  
Dec Hex  
Resistors 0, 1  
175.0  
178.8  
182.7  
186.8  
190.9  
195.2  
199.6  
204.2  
208.9  
213.7  
218.8  
223.9  
229.3  
234.9  
240.6  
246.6  
252.8  
259.2  
265.9  
272.8  
280.0  
287.5  
295.3  
303.5  
312.0  
320.8  
330.1  
339.8  
350.0  
360.7  
371.9  
383.7  
Resistor 2  
469.7  
476.4  
483.2  
490.1  
497.2  
504.4  
511.7  
519.2  
526.8  
534.6  
542.5  
550.6  
558.8  
567.3  
575.9  
584.6  
593.6  
602.8  
612.1  
621.7  
631.5  
641.5  
651.7  
662.2  
672.9  
683.8  
695.0  
706.5  
718.3  
730.3  
742.7  
755.4  
Hex  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
2A  
2B  
2C  
2D  
2E  
2F  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
3A  
3B  
3C  
3D  
3E  
3F  
Resistors 0, 1  
396.1  
Resistor 2  
768.4  
0
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
1
409.1  
781.7  
2
422.9  
795.4  
3
437.5  
809.4  
4
452.9  
823.9  
5
469.3  
838.7  
6
486.7  
853.9  
7
505.2  
869.6  
8
525.0  
885.7  
9
546.1  
902.3  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
568.8  
919.4  
593.1  
936.9  
619.2  
955.1  
647.5  
973.7  
678.1  
993.0  
711.4  
1012.8  
1033.3  
1054.5  
1076.4  
1099.0  
1122.4  
1146.6  
1171.7  
1197.7  
1224.7  
1252.7  
1281.7  
1311.9  
1343.3  
1376.0  
1410.1  
1445.6  
747.7  
787.5  
831.3  
879.6  
933.3  
993.4  
1060.9  
1137.5  
1225.0  
1326.0  
1443.8  
1583.0  
1750.0  
1954.2  
2209.4  
2537.5  
_____________________________________________________________________  
9
Triple NV Low Step Size Variable  
Resistor Plus Memory  
Figure 1. Address pins tied to GND result in a ‘0’ in the  
corresponding bit position in the slave address.  
External Resistor  
Selection/Considerations  
Conversely, address pins tied to V  
result in a ‘1’ in  
Using an external resistor in parallel with any of the  
DS3906’s resistors makes the effective resistance linear  
with small increments from position to position. Typical  
values for the external resistors are 87Ω for Resistor 0  
and 1 and 258Ω for Resistor 2. The effective resistance  
will be the most linear when these values are used. Of  
course these values may be tweaked to achieve the  
desired step size and range. The effects of changing  
CC  
the corresponding bit positions. I2C communication is  
described in detail in the following section.  
2
I C Serial Interface  
Description  
2
I C Definitions  
The following terminology is commonly used to  
describe I2C data transfers.  
R
is shown on the front page. Likewise, a series  
EXT  
resistor may be used to further customize the desired  
response. If the DS3906’s transfer function does not  
meet the applications needs, contact the factory at the  
email address provided on the front page to inquire  
about custom resistance values.  
Master Device: The master device controls the slave  
devices on the bus. The master device generates SCL  
clock pulses, start and stop conditions.  
Slave Devices: Slave devices send and receive data  
at the master’s request.  
2
I C Slave Address and Address Pins  
The DS3906’s I2C slave address is determined by the  
Bus Idle or Not Busy: Time between stop and start  
conditions when both SDA and SCL are inactive and in  
their logic high states. When the bus is idle it often initi-  
ates a low power mode for slave devices.  
state of the A0, A1, and A2 address pins as shown in  
Start Condition: A start condition is generated by the  
master to initiate a new data transfer with a slave.  
Transitioning SDA from high to low while SCL remains  
high generates a start condition. See the timing dia-  
gram for applicable timing.  
MSB  
1
LSB  
R/W  
0
1
0
A1  
A0  
A2  
READ/WRITE  
BIT  
SLAVE  
ADDRESS*  
Stop Condition: A stop condition is generated by the  
master to end a data transfer with a slave. Transitioning  
SDA from low to high while SCL remains high gener-  
ates a stop condition. See the timing diagram for  
applicable timing.  
*THE SLAVE ADDRESS IS DETERMINED BY  
ADDRESS PINS A0, A1, AND A2.  
Figure 1. DS3906 Slave Address Byte  
SDA  
t
BUF  
t
SP  
t
HD:STA  
t
LOW  
t
t
F
R
SCL  
t
SU:STA  
t
HD:STA  
t
HIGH  
t
REPEATED  
START  
t
SU:STO  
SU:DAT  
STOP  
START  
t
HD:DAT  
NOTE: TIMING IS REFERENCE TO V  
AND V  
.
IL(MAX)  
IH(MIN)  
2
Figure 2. I C Timing Diagram  
10  
____________________________________________________________________  
Triple NV Low Step Size Variable  
Resistor Plus Memory  
Repeated Start Condition: The master can use a  
Slave Address Byte: Each slave on the I2C bus  
responds to a slave address byte sent immediately fol-  
lowing a start condition. The slave address byte con-  
tains the slave address in the most significant 7-bits  
and the R/W bit in the least significant bit.  
repeated start condition at the end of one data transfer to  
indicate that it will immediately initiate a new data trans-  
fer following the current one. Repeated starts are com-  
monly used during read operations to identify a specific  
memory address to begin a data transfer. A repeated  
start condition is issued identically to a normal start con-  
dition, See the timing diagram for applicable timing.  
The DS3906’s slave address is determined by the state  
of the A0, A1, and A2 address pins as shown in Figure  
1. Address pins tied to GND result in a ‘0’ in the corre-  
sponding bit position in the slave address. Conversely,  
Bit Write: Transitions of SDA must occur during the low  
state of SCL. The data on SDA must remain valid and  
unchanged during the entire high pulse of SCL plus the  
setup and hold time requirements (see Figure 2). Data is  
shifted into the device during the rising edge of the SCL.  
address pins tied to V  
sponding bit positions.  
result in a ‘1’ in the corre-  
CC  
When the R/W bit is 0 (such as in A0h), the master is  
indicating it writes data to the slave. If R/W = 1, (A1h in  
this case), the master is indicating it wants to read from  
the slave.  
Bit Read: At the end a write operation, the master must  
release the SDA bus line for the proper amount of setup  
time (see Figure 2) before the next rising edge of SCL  
during a bit read. The device shifts out each bit of data  
on SDA at the falling edge of the previous SCL pulse  
and the data bit is valid at the rising edge of the current  
SCL pulse. Remember that the master generates all  
SCL clock pulses including when it is reading bits from  
the slave.  
If an incorrect slave address is written, the DS3906  
assumes the master is communicating with another I2C  
device and ignore the communication until the next  
start condition is sent.  
Memory Address: During an I2C write operation, the  
master must transmit a memory address to identify the  
memory location where the slave is to store the data.  
The memory address is always the second byte trans-  
mitted during a write operation following the slave  
address byte.  
Acknowledgement (ACK and NACK): An  
Acknowledgement (ACK) or Not Acknowledge (NACK)  
is always the 9th bit transmitted during a byte transfer.  
The device receiving data (the master during a read or  
the slave during a write operation) performs an ACK by  
transmitting a zero during the 9th bit. A device per-  
forms a NACK by transmitting a one during the 9th bit.  
Timing (Figure 2) for the ACK and NACK is identical to  
all other bit writes. An ACK is the acknowledgment that  
the device is properly receiving data. A NACK is used  
to terminate a read sequence or as an indication that  
the device is not receiving data.  
2
I C Communication  
Writing a Single Byte to a Slave: The master must  
generate a start condition, write the slave address byte  
(R/W = 0), write the memory address, write the byte of  
data and generate a stop condition. Remember the  
master must read the slave’s acknowledgement during  
all byte write operations.  
Writing Multiple Bytes to a Slave: The DS3906 is  
capable of writing up to 2 bytes (1-page or row) in a  
single write transaction. This is internally controlled by  
an address counter that allows data to be written to  
consecutive addresses without transmitting a memory  
address before each data byte is sent. The address  
counter limits the write to one 2-byte page. Pages  
begin on even addresses (00h, 02h, 04h, etc).  
Attempts to write more than 2 bytes of memory without  
at once without sending a stop condition between  
pages results in the address counter wrapping around  
to the beginning of the present row.  
Byte Write: A byte write consists of 8 bits of informa-  
tion transferred from the master to the slave (most sig-  
nificant bit first) plus a 1-bit acknowledgement from the  
slave to the master. The 8 bits transmitted by the mas-  
ter are done according to the bit write definition and the  
acknowledgement is read using the bit read definition.  
Byte Read: A byte read is an 8-bit information transfer  
from the slave to the master plus a 1-bit ACK or NACK  
from the master to the slave. The 8 bits of information  
that are transferred (most significant bit first) from the  
slave to the master are read by the master using the bit  
read definition above, and the master transmits an ACK  
using the bit write definition to receive additional data  
bytes. The master must NACK the last byte read to ter-  
minated communication so the slave will return control  
of SDA to the master.  
To write multiple bytes to a slave in one transaction, the  
master generates a start condition, writes the slave  
address byte (R/W =0), writes the memory address (must  
be even), writes two data bytes, and generates a stop  
condition. Remember the master must read the slave’s  
acknowledgement during all byte write operations.  
____________________________________________________________________ 11  
Triple NV Low Step Size Variable  
Resistor Plus Memory  
Acknowledge Polling: Any time an EEPROM page is  
Reading a Single Byte from a Slave: Unlike the write  
written, the DS3906 requires the EEPROM write time  
operation that uses the specified memory address byte  
to define where the data is to be written, the read oper-  
ation occurs at the present value of the memory  
address counter. To read a single byte from the slave,  
the master generates a start condition, writes the slave  
address byte with R/W = 1, reads the data byte with a  
NACK to indicate the end of the transfer, and generates  
a stop condition. However, since requiring the master  
to keep track of the memory address counter is imprac-  
tical, the following method should be used to perform  
reads from a specified memory location.  
(t ) after the stop condition to write the contents of the  
W
page to EEPROM. During the EEPROM write time, the  
device does not acknowledge its slave address  
because it is busy. It is possible to take advantage of  
this phenomenon by repeatedly addressing the  
DS3906, which allows communication to continue as  
soon as the DS3906 is ready. The alternative to  
acknowledge polling is to wait for a maximum period of  
t
W
to elapse before attempting to access the device.  
EEPROM Write Cycles: When EEPROM writes occur,  
the DS3906 internally writes the whole EEPROM page (2-  
bytes) even if only a single byte write was performed.  
Writes that do not modify all 2 bytes on the page are  
valid and do not corrupt any of other bytes on the same  
page. Because the whole page is written, even bytes on  
the page that were not modified during the transaction  
are still subject to a write cycle. The DS3906’s EEPROM  
write cycles are specified in the Nonvolatile Memory  
Characteristics table. The specification shown is at the  
worst-case temperature. It is capable of handling many  
additional writes at room temperature.  
Manipulating the Address Counter for Reads: A  
dummy write cycle can be used to force the address  
counter to a particular value. To do this the master gen-  
erates a start condition, writes the slave address byte  
(R/W =0), writes the memory address where it desires  
to read, generates a repeated start condition, writes the  
slave address byte (R/W = 1), reads data with ACK or  
NACK as applicable, and generates a stop condition.  
See Figure 3 for a read example using the repeated  
start condition to specify the starting memory location.  
2
TYPICAL I C WRITE TRANSACTION  
MSB  
1
LSB  
MSB  
LSB  
MSB  
LSB  
SLAVE  
ACK  
SLAVE  
ACK  
SLAVE  
ACK  
START  
0
1
0
A2 A1 A0 R/W  
b7 b6 b5 b4 b3 b2 b1 b0  
b7 b6 b5 b4 b3 b2 b1 b0  
STOP  
READ/  
WRITE  
REGISTER/MEMORY ADDRESS  
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2.  
SLAVE  
ADDRESS*  
DATA  
2
EXAMPLE I C TRANSACTIONS (WHEN A0, A1, AND A2 ARE CONNECTED TO GND)  
A0h  
F9h  
A) SINGLE BYTE WRITE  
-WRITE RESISTOR 1  
TO 00h  
SLAVE  
ACK  
SLAVE  
ACK  
SLAVE  
ACK  
1 0 1 0 0 0 0 0  
1 1 1 1 1 0 0 1  
0 0 0 0 0 0 0 0  
START  
STOP  
A0h  
F8h  
A1h  
DATA  
B) SINGLE BYTE READ  
-READ RESISTOR 0  
MASTER  
NACK  
SLAVE  
ACK  
SLAVE  
ACK  
REPEATED  
START  
SLAVE  
ACK  
1 0 1 0 0 0 0 1  
START 1 0 1 0 0 0 0 0  
RES 0  
STOP  
1 1 1 1 1 0 0 0  
A0h  
00h  
FFh  
C) SINGLE BYTE WRITE  
-WRITE FIRST BYTE OF  
USER EEPROM TO FFh  
SLAVE  
ACK  
SLAVE  
ACK  
SLAVE  
ACK  
1 0 1 0 0 0 0 0  
0 0 0 0 0 0 0 0  
1 1 1 1 1 1 1 1  
START  
START  
START  
STOP  
A0h  
00h  
00h  
00h  
D) TWO BYTE WRITE  
-WRITE TWO BYTES OF  
USER EEPROM TO 00h  
SLAVE  
ACK  
SLAVE  
ACK  
SLAVE  
ACK  
SLAVE  
ACK  
1 0 1 0 0 0 0 0  
0 0 0 0 0 0 0 0  
0 0 0 0 0 0 0 0  
0 0 0 0 0 0 0 0  
STOP  
A0h  
00h  
A1h  
LOCATION 00h  
DATA  
LOCATION 01h  
DATA  
E) TWO BYTE READ  
-READ TWO BYTES OF  
USER EEPROM  
STARTING  
SLAVE  
ACK  
SLAVE  
ACK  
REPEATED  
START  
SLAVE  
1 0 1 0 0 0 0 1  
MASTER  
ACK  
MASTER  
NACK  
1 0 1 0 0 0 0 0  
0 0 0 0 0 0 0 0  
STOP  
ACK  
FROM 00h  
2
Figure 3. I C Communication Examples  
12  
____________________________________________________________________  
Triple NV Low Step Size Variable  
Resistor Plus Memory  
Reading Multiple Bytes from a Slave: The read oper-  
and 0.1µF. Use a high-quality, ceramic, surface-mount  
ation can be used to read multiple bytes with a single  
transfer. When reading bytes from the slave, the master  
simply ACKs the data byte if it desires to read another  
byte before terminating the transaction. After the mas-  
ter reads the last byte it must NACK to indicate the end  
of the transfer and generates a stop condition.  
capacitor, and mount it as close as possible to the V  
and GND pins of the I.C. to minimize lead inductance.  
CC  
High Resistor Terminal Voltage  
It is permissible to have a voltage on the resistor-high  
terminals that is higher than the voltage connected to  
V
CC  
. For instance, connecting V  
to 3.0V while one or  
CC  
Application Information  
more of the resistor high terminals are connected to  
5.0V allows a 3V system to control a 5V system. The  
5.5V maximum still applies to the limit on the resistor  
Power Supply Decoupling  
To achieve best results, it is highly recommended that a  
decoupling capacitor is used on the I.C. power supply  
pins. Typical values of decoupling capacitors are 0.01µF  
high terminals regardless of the voltage present on V  
.
CC  
Typical Operating Circuit  
GREEN LED PANEL  
RED LED PANEL  
BLUE LED PANEL  
LED  
DRIVERS  
LED  
LED  
DRIVERS  
DRIVERS  
H0  
V
CC  
R0  
R1  
R2  
R
= 105Ω  
EXT0  
V
0.1µF  
CC  
H1  
H2  
DS3906  
4.7kΩ  
4.7kΩ  
R
= 105Ω  
EXT1  
FROM SYSTEM  
CONTROLLER  
SCL  
SDA  
A0  
A1  
A2  
R
= 310Ω  
EXT2  
GND  
DESIGN NOTES:  
1. IN THIS APPLICATION A NUMBER OF LED DRIVERS ARE SET USING THE DS3906'S VARIABLE RESISTORS.  
2. THE PARALLEL COMBINATION OF THE DS3906 VARIABLE RESISTOR R0 AND 105Ω (R ) IS EQUIVALENT TO A VARIABLE  
EXT0  
RESISTOR WITH LINEAR STEP INCREMENTS OF 0.6Ω RANGING FROM 66Ω TO 101Ω. THE SAME APPLIES FOR RESISTOR 1 (R1).  
THE PARALLEL COMBINATION OF R2 AND 310Ω (R  
1Ω RANGING FROM 187Ω TO 255Ω.  
) IS EQUIVALENT TO A VARIABLE RESISTOR WITH LINEAR STEP INCREMENTS OF  
EXT2  
3. VALUES LARGER THAN THE SHOWN EXTERNAL RESISTORS (R  
, R  
, AND R  
) RESULT IN LARGER STEP INCREMENTS AND  
EXT2  
EXT0 EXT1  
RESISTOR VALUES LOWER THAN THE SHOWN VALUES RESULT IN SMALLER STEP INCREMENTS. REFER TO THE RESISTOR TABLES AND  
COMPUTE EQUIVALENT RESISTANCE TO FIND OUT THE RANGES.  
____________________________________________________________________ 13  
Triple NV Low Step Size Variable  
Resistor Plus Memory  
Package Information  
Chip Topology  
For the latest package outline information, go to  
www.maxim-ic.com/DallasPackInfo.  
TRANSISTOR COUNT: 16,200  
SUBSTRATE CONNECTED TO GROUND  
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are  
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.  
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600  
© 2005 Maxim Integrated Products  
Printed USA  
is a registered trademark of Maxim Integrated Products, Inc.  
is a registered trademark of Dallas Semiconductor Corporation.  

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