DS3905 [MAXIM]
Triple 128-Position Nonvolatile Digital; 三重128非易失数字
| 型号： | DS3905 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Triple 128-Position Nonvolatile Digital |
| 文件： | 总11页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 3; 3/07
Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch
4/DS3905
General Description
Features
The DS3904/DS3905 contain three nonvolatile (NV) low
temperature coefficient, variable digital resistors. Each
resistor has 128 user-selectable positions. Additionally,
the DS3904/DS3905 have a high-impedance setting that
allows each resistor to function as a digital switch. The
DS3904/DS3905 can operate over a 2.7V to 5.5V supply
voltage range, and communication with the device is
achieved through a 2-wire serial interface. Address pins
allow multiple DS3904/DS3905s to operate on the same
two-wire bus. The DS3904 has one address pin, allow-
ing two DS3904s to share the bus, while the DS3905
has three address pins, allowing up to eight DS3905s to
share a common bus. The low-cost and small size of the
DS3904/DS3905 make them ideal replacements for con-
ventional mechanical trimming resistors.
♦ Three 20kΩ, or Two 20kΩ and One 10kΩ, 128-
Position Linear Digital Resistors
♦ Resistor Settings are Stored in NV Memory
♦ Each Resistor has a High-Impedance Setting for
Switch Operation to Control Digital Logic
♦ Low Temperature Coefficient
♦ 2-Wire Serial Interface
♦ 2.7V to 5.5V Operating Range
♦ -40°C to +85°C Industrial Temperature
♦ Packaging: 8-Pin µSOP for DS3904, 10-pin µSOP
for DS3905
Ordering Information
PIN-
(R0/R1/R2)
PART
TEMP RANGE
PACKAGE RESISTANCE (kꢀ)
Applications
DS3904U-010 -40°C to +85°C 8 μSOP
DS3904U-020 -40°C to +85°C 8 μSOP
DS3905U-020 -40°C to +85°C 10 μSOP
20/10/20 + High-Z
20/20/20 + High-Z
20/20/20 + High-Z
Power-Supply Calibration
Cell Phones and PDAs
Fibre Optic Transceiver Modules
Portable Electronics
Pin Configurations
TOP VEIW
Small and Low-Cost Replacement for
Conventional Mechanical Trimming Resistors/
Dip Switches
A1
1
2
3
4
5
10 A2
SDA
SCL
1
2
3
4
8
7
6
5
A0
H0
H1
H2
SDA
9
8
7
6
A0
H0
H1
H2
SDL
Test Equipment
DS3904
DS3905
V
CC
V
CC
GND
GND
μSOP
μSOP
Typical Operating Circuit
INTERFACE EXAMPLES
V
V
CC
V
CC
DS3904/DS3905
VARIABLE RESISTANCE
FOR ADJUSTABLE
CURRENT SOURCE
R
R
10
V
0.1μF
CC
RHIZ
RHIZ
H0
H1
RESISTOR 0
ADDR F8h
4.7kΩ 4.7kΩ
CC
SCL
SDA
2-WIRE
MASTER
11
DIGITAL
LOGIC
2-WIRE
ADDRESSABLE
SWITCH (USING 00h
AND RHIZ SETTINGS)
RESISTOR 1
ADDR F9h
A0
V
IN
A1
A2
(DS3905 ONLY)
RHIZ
GAIN
CONTROL
H2
RESISTOR 2
ADDR FAh
GND
R
12
_____________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Triple 128-Position Nonvolatile
Variable Digital Resistor/Switch
ABSOLUTE MAXIMUM RATINGS
Voltage on V
Pin Relative to Ground.................-0.5V to +6.0V
Operating Temperature Range ...........................-40°C to +85°C
Programming Temperature Range.........................0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...................See J-STD-020 Specification
CC
Voltage on SDA, SCL, A0, A1, A2
Relative to Ground*...................................-0.5V to V
Voltage on H0, H1, and
+ 0.5V
CC
H2 Relative to Ground.......................................-0.5V to +6.0V
Current Through H0, H1, and H2..........................................3mA
*This voltage must not exceed 6.0V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T = -40°C to +85°C)
A
4/DS3905
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
V
(Note 1)
2.7
5.5
V
CC
0.7 x
V
+
CC
0.3
Input Logic 1
Input Logic 0
V
V
V
IH
V
CC
0.3 x
V
V
-0.3
-0.3
IL
CC
Resistor Current
I
3
mA
V
R
Resistor Terminals H0, H1, H2
V
= +2.7V to +5.5V
+5.5
CC
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Leakage
I
(Note 2)
-1
+1
µA
L
V
V
= 3V (Note 3)
95
200
200
0.4
0.6
CC
CC
Standby Supply Current
I
µA
V
STBY
= 5V (Note 3)
145
V
V
3mA sink current
6mA sink current
0
0
OL1
OL2
Low-Level Output Voltage (SDA)
ANALOG RESISTOR CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
20kꢀ resistor
10kꢀ resistor
20kꢀ resistor
10kꢀ resistor
-1
+1
Absolute Linearity (Note 4)
Relative Linearity (Note 5)
Temperature Coefficient (Note 6)
INL
LSB
-1
+1
-0.5
-0.5
-200
-150
+0.5
+0.5
+400
+450
DNL
LSB
Position 7Fh (20kꢀ resistor)
Position 7Fh (10kꢀ resistor)
+123
+173
ppm/°C
2
______________________________________________________________________
Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch
4/DS3905
ANALOG RESISTOR CHARACTERISTICS (continued)
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
T
A
T
A
T
A
= +25°C (20kꢀ resistor)
14.5
20
25.5
Position 7Fh Resistance
R
kꢀ
MAX
= +25°C (10kꢀ resistor)
8
10
12
Position 00h Resistance
High Impedance
R
= +25°C
200
5.5
500
ꢀ
MIN
R
Mꢀ
HIZ
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fast mode
0
400
SCL Clock Frequency
(Note 7)
f
kHz
SCL
Standard mode
Fast mode
0
1.3
100
Bus Free Time between STOP
and START Conditions (Note 7)
t
µs
µs
µs
µs
µs
ns
µs
ns
ns
µs
pF
BUF
Standard mode
Fast mode
4.7
0.6
Hold Time (Repeated) START
Condition (Notes 7, 8)
t
HD:STA
Standard mode
Fast mode
4.0
1.3
Low Period of SCL Clock
(Note 7)
t
LOW
Standard mode
Fast mode
4.7
0.6
High Period of SCL Clock
(Note 7)
t
HIGH
Standard mode
Fast mode
4.0
0
0.9
0.9
Data Hold Time
(Notes 7, 9)
t
HD:DAT
Standard mode
Fast mode
0
100
Data Setup Time
(Note 7)
t
SU:DAT
Standard mode
Fast mode
250
0.6
Start Setup Time
t
SU:STA
Standard mode
Fast mode
4.7
20 + 0.1C
20 + 0.1C
20 + 0.1C
20 + 0.1C
0.6
300
1000
300
B
Rise Time of Both SDA and SCL
Signals (Note 10)
t
R
Standard mode
Fast mode
B
B
B
Fall Time of Both SDA and SCL
Signals (Note 10)
t
F
Standard mode
Fast mode
300
Setup Time for STOP Condition
t
SU:STO
Standard mode
4.0
Capacitive Load for Each Bus
Line
C
(Note 10)
(Note 11)
400
B
EEPROM Write Time
Startup Time
t
10
20
2
ms
ms
W
t
ST
_____________________________________________________________________
3
Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch
NONVOLATILE MEMORY CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = +70°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EEPROM Writes
50,000
Note 1: All voltages are referenced to ground.
Note 2: Applies to A0, SDA, SCL for the DS3904 and A0, A1, A2, SDA, SCL for the DS3905. Also applies to H0, H1,
H2 for both DS3904 and DS3905 when in the high-impedance state.
Note 3:
I
specified with SDA = SCL = V
and A0 = GND.
STBY
CC
Note 4: Absolute linearity is used to determine expected resistance. Absolute linearity is defined as the deviation
from the straight line drawn from the value of the resistance at position 00h to the value of the resistance at
position 7Fh.
Note 5: Relative linearity is used to determine the change of resistance between two adjacent resistor positions.
Note 6: Temperature coefficient specifies the change in resistance as a function of temperature. The temperature
coefficient varies with resistor position. Limits are guaranteed by design.
4/DS3905
Note 7: A fast-mode device can be used in a standard-mode system, but the requirement t
> 250ns must
SU:DAT
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line t
+ t
= 1000ns + 250ns =1250ns before the SCL line is released.
RMAX
SU:DAT
Note 8: After this period, the first clock pulse is generated.
Note 9: The maximum t
has only to be met if the device does not stretch the LOW period (t
) of the SCL
HD:DAT
LOW
signal.
Note 10: C —total capacitance of one bus line in picofarads, timing referenced to 0.9 x V
and 0.1 x V
.
B
CC
CC
Note 11: EEPROM write begins after a stop condition occurs.
4
______________________________________________________________________
Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch
4/DS3905
Typical Operating Characteristics
(V
CC
= +5.0V, T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. SCL FREQUENCY
RESISTANCE vs.
RESISTOR SETTING
25
20
15
10
5
200
180
160
140
120
100
80
160
V
= SDA = +5V
CC
V
= +5V
= +3V
CC
CC
140
120
100
80
ADDRESS PINS
CONNECTED TO GND
V
20kΩ RESISTOR
60
60
SDA = SCL =V
ADDRESS PINS
CONNECTED TO GND
CC
40
40
20
20
10kΩ RESISTOR
0
0
0
0
25
50
75
100
125
0
0
0
50 100 150 200 250 300 350 400
SCL FREQUENCY (kHz)
-40
-20
0
20
40
60
80
RESISTOR SETTING (DEC)
TEMPERATURE (°C)
TEMPERATURE COEFFICIENT vs.
RESISTOR SETTING
TEMPERATURE COEFFICIENT vs.
RESISTOR SETTING
POSITION 7Fh RESISTANCE PERCENT CHANGE
FROM +25°C vs. TEMPERATURE
600
500
400
300
200
100
0
900
800
700
600
500
400
300
200
100
0
1.0
10kΩ RESISTOR
20kΩ RESISTOR
0.8
0.6
0.4
0.2
0
10kΩ RESISTOR
20kΩ RESISTOR
TC OF +25°C TO +85°C
TC OF +25°C TO -40°C
TC OF +25°C TO +85°C
TC OF +25°C TO -40°C
-0.2
-0.4
-100
-200
0
20
40
60
80
100
120
20
40
60
80
100 120
-40
-20
0
20
40
60
80
RESISTOR SETTING (DEC)
RESISTOR SETTING (DEC)
TEMPERATURE (°C)
POSITION 00h RESISTANCE PERCENT CHANGE
FROM +25°C vs. TEMPERATURE
RESISTANCE vs. POWER-UP VOLTAGE
RESISTANCE vs. POWER-DOWN VOLTAGE
3.5
100
90
80
70
60
50
40
30
20
10
0
100
>5.5MΩ
>5.5MΩ
3.0
2.5
90
80
70
60
50
40
30
20
10
0
10kΩ RESISTOR
2.0
EEPROM RECALL
EEPROM RECALL
1.5
1.0
0.5
0
20kΩ RESISTOR
-0.5
-1.0
-1.5
-2.0
-2.5
PROGRAMMED RESISTANCE
PROGRAMMED RESISTANCE
-40
-20
0
20
40
60
80
1
2
3
4
5
6
0
1
2
3
4
5
6
TEMPERATURE (°C)
POWER-UP VOLTAGE (V)
POWER-DOWN VOLTAGE (V)
_____________________________________________________________________
5
Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch
Typical Operating Characteristics (continued)
(V
CC
= +5.0V, T = +25°C, unless otherwise noted.)
A
POSITION 3Fh RESISTANCE vs.
SUPPLY VOLTAGE
ABSOLUTE LINEARITY vs.
RESISTOR 0 POSITION
RELATIVE LINEARITY vs.
RESISTOR 0 POSITION
25
20
15
10
5
0.5
0.4
0.5
0.4
RESISTOR 0
20kΩ
RESISTOR 0
20kΩ
0.3
0.3
0.2
0.2
0.1
0.1
20kΩ RESISTOR
10kΩ RESISTOR
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
4/DS3905
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
0
0
0
20
40
60
80
100 120
0
0
0
20
40
60
80
100 120
RESISTOR 0 POSITION (DEC)
RESISTOR 0 POSITION (DEC)
ABSOLUTE LINEARITY vs.
RESISTOR 1 POSITION
RELATIVE LINEARITY vs.
RESISTOR 1 POSITION
ABSOLUTE LINEARITY vs.
RESISTOR 2 POSITION
0.5
0.4
0.5
0.4
0.5
0.4
RESISTOR 1
20kΩ
RESISTOR 1
20kΩ
RESISTOR 2
20kΩ
0.3
0.3
0.3
0.2
0.2
0.2
0.1
0.1
0.1
0
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
0
20
40
60
80
100 120
20
40
60
80
100 120
20
40
60
80
100 120
RESISTOR 1 POSITION (DEC)
RESISTOR 1 POSITION (DEC)
RESISTOR 2 POSITION (DEC)
RELATIVE LINEARITY vs.
RESISTOR 2 POSITION
ABSOLUTE LINEARITY vs.
RESISTOR 1 POSITION
RELATIVE LINEARITY vs.
RESISTOR 1 POSITION
0.5
0.4
0.5
0.4
0.5
0.4
RESISTOR 2
20kΩ
RESISTOR 1
10kΩ
RESISTOR 1
10kΩ
0.3
0.3
0.3
0.2
0.2
0.2
0.1
0.1
0.1
0
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
0
20
40
60
80
100 120
20
40
60
80
100 120
20
40
60
80
100 120
RESISTOR 2 POSITION (DEC)
RESISTOR 1 POSITION (DEC)
RESISTOR 1 POSITION (DEC)
6
______________________________________________________________________
Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch
4/DS3905
Pin Description
Table 1. Variable Resistor Registers
PIN
VARIABLE
RESISTOR
POSITION 7Fh NUMBER OF
NAME
SDA
DESCRIPTION
ADDRESS
DS3904 DS3905
RESISTANCE
POSITIONS*
2-Wire Serial Data. Open-drain
input/output for 2-wire data.
20kꢀ
(nominal)
128 (00h to
7Fh) + Hi-Z
1
2
2
3
F8h
Resistor 0
Resistor 1
Resistor 2
2-Wire Serial Clock. Input for
2-wire clock.
20kꢀ or 10kꢀ
(nominal)
128 (00h to
7Fh) + Hi-Z
SCL
F9h
V
3
4
4
5
Supply Voltage Terminal
Ground Terminal
CC
20kꢀ
(nominal)
128 (00h to
7Fh) + Hi-Z
FAh
GND
H2
H1
H0
A0
5
6
Resistor 2 High Terminals
Resistor 1 High Terminals
Resistor 0 High Terminals
Address-Select Pin
*Writing a value greater than 7Fh to any of the resistor registers
sets the high-impedance mode control bit (RHIZ, the MSB of
the resistor register) resulting in the resistor going into high-
impedance mode. Position 0 is the minimum position. Position
7Fh is the maximum position.
6
7
7
8
8
9
A1
—
—
1
Address-Select Pin (DS3905 Only)
Address-Select Pin (DS3905 Only)
A2
10
Device Operation
Detailed Description
Clock and Data Transitions
The SDA pin is normally pulled high with an external
resistor or device. Data on the SDA pin can only change
during SCL low time periods. Data changes during SCL
high periods indicate a start or stop condition depend-
ing on the conditions discussed below. See the timing
diagrams for further details (Figures 2 and 3).
The DS3904/DS3905 contain three, 128-position, NV,
low temperature coefficient, variable digital resistors. All
three resistors also feature a Hi-Z function. The variable
resistor registers (F8h, F9h, and FAh) are factory pro-
grammed with a default value of 7Fh. They are con-
trolled through a 2-wire serial interface, and can serve
as a low-cost replacement for designs using conven-
tional trimming resistors. Furthermore, the DS3904
address pin (A0) allows two DS3904s to be placed on
the same 2-wire bus. The three address pins on the
DS3905 allow up to eight DS3905s to be placed on the
same 2-wire bus.
Start Condition
A high-to-low transition of SDA with SCL high is a start
condition, which must precede any other command. See
the timing diagrams for further details (Figures 2 and 3).
Stop Condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read or write sequence, the stop com-
mand places the DS3904/DS3905 into a low-power
mode. See the timing diagrams for further details
(Figures 2 and 3).
With their low cost and small size, the DS3904/DS3905
are well tailored to replace larger mechanical trimming
variable resistors. This allows the automation of calibra-
tion in many instances because the 2-wire interface can
easily be adjusted by test/production equipment.
Variable Resistor Memory Organization
The variable resistors of the DS3904/DS3905 are
addressed by communicating with the registers in
Table 1.
Acknowledge
All address and data bytes are transmitted through a
serial protocol. The DS3904/DS3905 pull the SDA line
low during the ninth clock pulse to acknowledge that
they have received each byte.
Using the Resistor as a Switch
By taking advantage of the high-impedance mode, a
switch can be created to produce a digital output.
Setting a resistor register to 00h creates the low state.
Writing 80h into the same resistor register enables the
high-impedance state. When used with an external
pullup resistor, such as a 4.7kΩ pullup, a high state
is generated.
Standby Mode
The DS3904/DS3905 feature a low-power mode that is
automatically enabled after power-on, after a stop com-
mand, and after the completion of all internal operations.
_____________________________________________________________________
7
Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch
where the data is to be written. After the byte has been
received, the DS3904/DS3905 transmit a zero for one
clock cycle to acknowledge that the memory address
has been received. The master must then transmit an 8-
bit data word to be written into this memory address. The
DS3904/DS3905 again transmit a zero for one clock
cycle to acknowledge the receipt of the data byte. At this
point, the master must terminate the write operation with
a stop condition. The DS3904/DS3905 then enter an
V
CC
EEPROM
H0
DS3905
RHIZ CONTROL
V
CC
RES 0
20kΩ
F8h
RESISTOR 0
MSB
LSB
7
GND
SCL
H1
RHIZ CONTROL
RES 1
20kΩ
OR
internally timed write process t to the EEPROM memo-
w
DATA
F9h
RESISTOR 1
SDA
A0
ry. All inputs are disabled during this write cycle.
2-WIRE
MSB
LSB
7
10kΩ
INTERFACE
A1
Acknowledge Polling
Once a EEPROM write is initiated, the part will not
acknowledge until the cycle is complete. Another
option is to wait the maximum write cycle delay before
initiating another write cycle.
(DS3905 ONLY)
H2
A2
RHIZ CONTROL
FAh
RES 2
20kΩ
RESISTOR 2
4/DS3905
MSB
LSB
7
Read Operations
After receiving a matching address byte with the R/W bit
set high, the device goes into the read mode of opera-
tion. A read requires a dummy byte write sequence to
load in the register address. Once the device address
and data address bytes are clocked in by the master,
and acknowledged by the DS3904/ DS3905, the master
must generate another start condition (repeated start).
The master now initiates a read by sending the device
address with the R/W bit set high. The DS3904/DS3905
acknowledge the device address and serially clock out
the data byte. The master responds with a NACK and
generates a stop condition afterwards.
Figure 1. DS3904/DS3905 Block Diagram
Bus Reset
After any interruption in protocol, power loss, or system
reset, the following steps reset the DS3904/DS3905:
1) Clock up to nine cycles.
2) Look for SDA high in each cycle while SCL is high.
3) Create a start condition while SDA is high.
Device Addressing
The DS3904/DS3905 must receive an 8-bit device
address byte following a start condition to enable a
specific device for a read or write operation. The
address byte is clocked into the DS3904/DS3905 MSB
to LSB. For the DS3904, the address byte consists of
101000 binary followed by A0 then the R/W bit. If the
R/W bit is high, a read operation is initiated. For the
DS3905, the address byte consists of 1010 binary fol-
lowed by A2, A1, A0 then the R/W bit. If the R/W bit is
low, a write operation is initiated. For a device to
become active, the value of the address bits must be
the same as the hard-wired address pins on the
DS3904/DS3905. Upon a match of written and hard-
wired addresses, the DS3904/DS3905 output a zero for
one clock cycle as an acknowledge. If the address
does not match, the DS3904/DS3905 return to a low-
power mode.
See Figures 4 and 5 for command and data byte struc-
tures as well as read and write examples.
2-Wire Serial Port Operation
The 2-wire serial port interface supports a bidirectional
data transmission protocol with device addressing. A
device that sends data on the bus is defined as a trans-
mitter, and a device receiving data as a receiver. The
device that controls the message is called a master. The
devices that are controlled by the master are slaves. The
bus must be controlled by a master device that gener-
ates the SCL, controls the bus access, and generates
the start and stop conditions. The DS3904/DS3905 oper-
ate as slaves on the 2-wire bus. Connections to the bus
are made through SCL and open-drain SDA lines. The
following I/O terminals control the 2-wire serial port: SDA,
SCL, and A0. The DS3905 uses two additional address
pins A1 and A2 to control the 2-wire serial port. Timing
diagrams for the 2-wire serial port can be found in
Figures 2 and 3. Timing information for the 2-wire serial
port is provided in the AC Electrical Characteristics table
for 2-wire serial communications.
Write Operations
After receiving a matching device address byte with the
R/W bit set low, the device goes into the write mode of
operation. The master must transmit an 8-bit EEPROM
memory address to the device to define the address
8
______________________________________________________________________
Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch
4/DS3905
SDA
MSB
SLAVE ADDRESS
R/W
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
1
2
6
7
8
9
1
2
3–7
8
9
ACK
ACK
START
CONDITION
STOP
CONDITION
OR REPEATED
START
REPEATED IF MORE BYTES
ARE TRANSFERRED
CONDITION
Figure 2. 2-Wire Data Transfer Protocol
SDA
t
BUF
t
SP
t
HD:STA
t
LOW
t
t
F
R
SCL
t
SU:STA
t
HD:STA
t
HIGH
t
REPEATED
START
t
SU:DAT
SU:STO
STOP
START
t
HD:DAT
Figure 3. 2-Wire AC Characteristics
The following bus protocol has been defined:
Bus Not Busy: Both data and clock lines remain
high.
Data transfer can be initiated only when the bus is
not busy.
Start Data Transfer: A change in the state of the
data line from high to low while the clock is high
defines a start condition.
During data transfer, the data line must remain sta-
ble whenever the clock line is high. Changes in the
data line while the clock line is high are interpreted
as control signals.
Stop Data Transfer: A change in the state of the
data line from low to high while the clock line is
high defines the stop condition.
Accordingly, the following bus conditions have been
defined:
Data Valid: The state of the data line represents
valid data when, after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line can be changed
during the low period of the clock signal. There is
_____________________________________________________________________
9
Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch
A device that acknowledges must pull down the
SDA line during the acknowledge clock pulse in
such a way that the SDA line is a stable low during
the high period of the acknowledge-related clock
pulse. Of course, setup and hold times must be
taken into account. A master must signal an end of
data to the slave by not generating an acknowl-
edge bit on the last byte that has been clocked out
of the slave. In this case, the slave must leave the
data line high to enable the master to generate the
stop condition.
COMMAND BYTE
DATA BYTE
MSB
1
LSB
A2* A1* A0 R/W
MSB
LSB
START
0
1
0
DEVICE IDENTIFIER SLAVE
RHIZ
CONTROL BIT
RESISTOR SETTING
OR
ADDRESS
"FAMILY CODE"
*DS3904, USE 0's INSTEAD OF A2 AND A1 FOR THE DEVICE ADDRESS
Figure 4. Command and Data Byte Structures
one clock pulse per bit of data. Figures 2 and 3
detail how data transfer is accomplished on the 2-
wire bus. Depending upon the state of the R/W bit,
two types of data transfer are possible.
Data transfer from a master transmitter to a
slave receiver. The first byte transmitted by the
master is the command/control byte. Next follows a
number of data bytes. The slave returns an
acknowledge bit after each received byte.
4/DS3905
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between start and stop
conditions is not limited and is determined by the
master device. The information is transferred byte-
wise and each receiver acknowledges with a ninth
bit.
Data transfer from a slave transmitter to a mas-
ter receiver. The master transmits the first byte (the
command/control byte) to the slave. The slave then
returns an acknowledge bit. Next follows the data
byte transmitted by the slave to the master. The
master returns NACK followed by a stop.
Within the bus specifications, a regular mode
(100kHz clock rate) and a fast mode (400kHz clock
rate) are defined. The DS3904/DS3905 work in both
modes.
The master device generates all serial clock pulses
and the start and stop conditions. A transfer is
ended with a stop condition or with a repeated start
condition. Since a repeated start condition is also
the beginning of the next serial transfer, the bus is
not released.
Acknowledge: Each receiving device, when
addressed, generates an acknowledge after the
byte has been received. The master device must
generate an extra clock pulse that is associated
with this acknowledge bit.
EXAMPLE 2-WIRE TRANSACTIONS
FROM
SLAVE
FROM
SLAVE
FROM
SLAVE
MSB
0
LSB
0
MSB
1
A0h
A0h
LSB
0
MSB
1
F8h
F9h
LSB
0
00h
80h
WRITE RESISTOR 0
TO MIN POSITION
ACK
ACK
ACK
ACK
ACK
ACK
ACK
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
STOP
STOP
START
START
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
MSB
1
LSB
0
MSB
1
LSB
1
MSB
1
LSB
0
1
ACK
SET RESISTOR 1 TO Hi-Z
MSB
0
LSB
1
MSB
1
A0h
LSB
0
MSB
1
FAh
F9h
LSB
0
7Fh
WRITE RESISTOR 2 TO
MAX POSITION
STOP
START
START
0
1
0
0
0
0
1
1
1
1
ACK
ACK
MSB
1
LSB
0
MSB
1
LSB
1
A0h
A1h
REPEATED
START
ACK
ACK
READ RESISTOR 1 VALUE
0
0
1
1
0
0
0
0
0
0
0
0
MSB
1
LSB
1
MSB
LSB
MASTER
NACK
STOP
RESISTOR DATA
A0 = GND FOR DS3904
A0, A1, A2 = GND FOR DS3905
Figure 5. Example 2-Wire Transactions
10 _____________________________________________________________________
Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch
4/DS3905
The DS3904/DS3905 can operate in the following three
modes:
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS3904/
DS3905, decouple the power supply with a 0.01µF or
0.1µF capacitor. Use a high-quality ceramic surface-
mount capacitor. Surface-mount components minimize
lead inductance, which improves performance, and
ceramic capacitors tend to have adequate high-fre-
quency response for decoupling applications.
1) Slave Receiver Mode: Serial data and clock are
received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is trans-
mitted. Start and stop conditions are recognized as
the beginning and end of a serial transfer. Address
recognition is performed by hardware after the
slave (device) address and direction bit has been
received.
High Resistor Terminal Voltage
2) Slave Transmitter Mode: The first byte is received
and handled as in the slave receiver mode.
However, in this mode the direction bit indicates
that the transfer direction is reversed. Serial data is
transmitted on SDA by the DS3904/DS3905 while
the serial clock is input on SCL. Start and stop con-
ditions are recognized as the beginning and end of
a serial transfer.
It is possible to have a voltage on the resistor-high termi-
nals that is higher than the voltage connected to V
.
CC
For instance, connecting V
to 3.0V while one or more
CC
of the resistor high terminals are connected to 5.0V
allows a 3V system to control a 5V system. The 5.5V
maximum still applies to the limit on the resistor high ter-
minals regardless of the voltage present on V
.
CC
3) Slave Address: The command/control byte is the
first byte received following the start condition from
the master device. The command/control byte con-
sists of a 4-bit device identifier. For the DS3904, the
identifier is followed by the device-select bits 0, 0,
and A0. For the DS3905, the identifier is followed by
the device-select bits A2, A1, A0. The device identi-
fier is used by the master device to select which
device is to be accessed. When reading or writing
the DS3904/DS3905, the device-select bits must
match the device-select pin(s). The last bit of the
command/control byte (R/W) defines the operation
to be performed. When set to a ‘1’, a read operation
is selected, and when set to a ‘0’, a write operation
is selected.
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
Following the start condition, the DS3904/DS3905 moni-
tor the SDA bus checking the device-type identifier
being transmitted. Upon receiving the control code, the
appropriate device address bit, and the read/write bit,
the slave device outputs an acknowledge signal on the
SDA line.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
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