DS33X162+ [MAXIM]
Support Circuit, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, CSBGA-256;
| 型号： | DS33X162+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Support Circuit, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, CSBGA-256 电信 电信集成电路 |
| 文件： | 总375页 (文件大小：2649K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev: 063008
DS33X162/DS33X161/DS33X82/DS33X81/
DS33X42/DS33X41/DS33X11/DS33W41/DS33W11
Ethernet Over PDH Mapping Devices
General Description
Features
The DS33X162 family of semiconductor devices
extend 10/100/1000Mbps Ethernet LAN segments by
encapsulating MAC frames in GFP-F, HDLC, cHDLC,
or X.86 (LAPS) for transmission over PDH/TDM data
streams. The devices support the Ethernet over PDH
(EoPDH) standards for the delivery of Ethernet
Access Services, including eLAN, eLINE, and VLAN.
The multiport devices support VCAT/LCAS for
dynamic link aggregation. The serial links support
bidirectional synchronous interconnect up to 52Mbps
over xDSL, T1/E1/J1, T3/E3, or V.35/Optical.
♦
10/100/1000 IEEE 802.3 MAC (MII/RMII/GMII)
with Autonegotiation and Flow Control
♦
♦
GFP-F/LAPS/HDLC/cHDLC Encapsulation
VCAT/LCAS Link Aggregation for Up to 16
Links
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
Supports Up to 200ms Differential Delay
Quality of Service (QoS) Support
VLAN, Q-in-Q, 802.1p, and DSCP Support
Ethernet Bridging and Filtering
Add/Drop OAM Frames from μP Interface
Traffic Shaping Through CIR/CBS Policing
External 256Mb, 125MHz DDR SDRAM Buffer
Parallel and SPI™ Microprocessor Interfaces
1.8V, 2.5V, 3.3V Supplies
The devices perform store-and-forward of frames
with Ethernet traffic conditioning and bridging
functions at wire speed. The programmability of
classification, priority queuing, encapsulation, and
bundling allows great flexibility in providing various
Ethernet services. OAM flows can be extracted and
inserted by an external processor to manage the
Ethernet service.
IEEE 1149.1 JTAG Support
Features continued in Section 2.
The voice ports of the DS33W41 and DS33W11
easily connect to external codecs for integrated voice
and data service applications.
Ordering Information
PORTS
PIN-
PART
PACKAGE
TDM
16
16
8
ETHERNET VOICE
DS33X162+
DS33X161+
DS33X82+
DS33X81+
DS33X42+
DS33X41+
DS33X11+
DS33W41+
DS33W11+
2
1
2
1
2
1
1
1
1
0
0
0
0
0
0
0
1
1
256 CSBGA
256 CSBGA
256 CSBGA
256 CSBGA
256 CSBGA
256 CSBGA
144 CSBGA
256 CSBGA
256 CSBGA
Applications
Bonded Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1, T3/E3,
OC-1/EC-1, G.SHDSL, or HDSL2/4
8
4
4
1
Functional Diagram
4
PROCESSOR
1
Note: All devices are specified over the -40°C to +85°C industrial
operating temperature range.
+Denotes a lead-free/RoHS-compliant package.
8-BIT & SPI μP INTERFACE
QoS
POLICY
WAN
SERIAL
PORTS
CLAD
ENET
PHYs
TDM LIU/
FRAMER
BRIDGING
BUFFER MANAGER
SPI is a trademark of Motorola, Inc.
SDRAM CONTROLLER
VOICE PORT
DS33X162
DDR SDRAM
Maxim Integrated Products
1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of
any device may be simultaneously available through various sales channels. For information about device errata, go to:
www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or
visit Maxim’s website at www.maxim-ic.com.
_________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Table of Contents
1.
DETAILED DESCRIPTION ..............................................................................................................9
FEATURE HIGHLIGHTS................................................................................................................10
2.
2.1 GENERAL......................................................................................................................................10
2.2 VCAT/LCAS LINK AGGREGATION (INVERSE MULTIPLEXING) ..........................................................10
2.3 HDLC...........................................................................................................................................10
2.3.1
cHDLC.................................................................................................................................................. 10
2.4 GFP-F..........................................................................................................................................11
2.5 X.86 SUPPORT .............................................................................................................................11
2.6 DDR SDRAM INTERFACE.............................................................................................................11
2.7 MAC INTERFACES.........................................................................................................................11
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.7.8
2.7.9
Ethernet Bridging for 10/100................................................................................................................ 12
Ethernet Traffic Classification .............................................................................................................. 12
Ethernet Bandwidth Policing................................................................................................................ 12
Ethernet Traffic Scheduling.................................................................................................................. 12
Connection Endpoints.......................................................................................................................... 12
Virtual Connection................................................................................................................................ 12
Connection and Aggregation ............................................................................................................... 12
Ethernet Control Frame Processing..................................................................................................... 12
Q-in-Q .................................................................................................................................................. 12
2.8 SERIAL PORTS ..............................................................................................................................13
2.8.1 Voice Ports........................................................................................................................................... 13
2.9 MICROPROCESSOR INTERFACE......................................................................................................13
2.10
2.11
2.12
SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES ............................................................13
TEST AND DIAGNOSTICS.............................................................................................................13
SPECIFICATIONS COMPLIANCE....................................................................................................13
3.
4.
5.
APPLICABLE EQUIPMENT TYPES..............................................................................................14
ACRONYMS & GLOSSARY..........................................................................................................17
DESIGNING WITH THE DS33X162 FAMILY OF DEVICES..........................................................18
5.1 IDENTIFICATION OF APPLICATION REQUIREMENTS ..........................................................................18
5.2 DEVICE SELECTION .......................................................................................................................18
5.3 ANCILLARY DEVICE SELECTION......................................................................................................19
5.4 CIRCUIT DESIGN............................................................................................................................19
5.5 BOARD LAYOUT.............................................................................................................................19
5.6 SOFTWARE DEVELOPMENT............................................................................................................19
6.
7.
BLOCK DIAGRAMS ......................................................................................................................20
PIN DESCRIPTIONS......................................................................................................................21
7.1 PIN FUNCTIONAL DESCRIPTION......................................................................................................21
FUNCTIONAL DESCRIPTION.......................................................................................................34
8.1 PARALLEL PROCESSOR INTERFACE................................................................................................35
8.
8.1.1
8.1.2
8.1.3
8.1.4
Read-Write/Data Strobe Modes........................................................................................................... 35
Clear on Read...................................................................................................................................... 35
Interrupt and Pin Modes....................................................................................................................... 35
Multiplexed Bus Operation................................................................................................................... 35
8.2 SPI SERIAL PROCESSOR INTERFACE .............................................................................................36
8.3 CLOCK STRUCTURE.......................................................................................................................37
8.3.1
8.3.2
Serial Interface Clock Modes............................................................................................................... 39
Ethernet Interface Clock Modes........................................................................................................... 39
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8.4 RESETS AND LOW-POWER MODES ................................................................................................39
8.5 INITIALIZATION AND CONFIGURATION..............................................................................................41
8.6 GLOBAL RESOURCES ....................................................................................................................41
8.7 PER-PORT RESOURCES ................................................................................................................41
8.8 DEVICE INTERRUPTS .....................................................................................................................41
8.9 FORWARDING MODES AND WAN CONNECTIONS ............................................................................43
8.9.1
8.9.2
8.9.3
8.10
8.11
Forwarding Modes ............................................................................................................................... 43
WAN Connections................................................................................................................................ 49
Queue Configuration............................................................................................................................ 50
BANDWIDTH CAPABILITIES (THROUGHPUT)..................................................................................51
SERIAL (WAN)...........................................................................................................................52
8.11.1 Voice Support (DS33W11 and DW33W41 Only)................................................................................. 52
8.12
LINK AGGREGATION AND LINK CAPACITY ADJUSTMENT (VCAT/LCAS) ........................................53
8.12.1 VCAT/LCAS Control Frame for T3/E3 ................................................................................................. 54
8.12.2 VCAT/LCAS Configuration and Operation........................................................................................... 55
8.12.3 Link Capacity Adjustment Scheme (LCAS) ......................................................................................... 56
8.12.4 Alarms and Conditions related to VCAT/LCAS.................................................................................... 57
8.13
8.14
ARBITER/BUFFER MANAGER.......................................................................................................57
FLOW CONTROL.........................................................................................................................58
8.14.1 Full Duplex Flow control....................................................................................................................... 59
8.14.2 Half Duplex Flow control...................................................................................................................... 59
8.15
ETHERNET INTERFACES .............................................................................................................60
8.15.1 GMII Mode ........................................................................................................................................... 62
8.15.2 MII Mode .............................................................................................................................................. 63
8.15.3 DTE and DCE Mode ............................................................................................................................ 65
8.15.4 RMII Mode............................................................................................................................................ 66
8.16
QUALITY OF SERVICE (QOS) FEATURES .....................................................................................67
8.16.1 VLAN Forwarding by VID (IEEE 802.1q)............................................................................................. 67
8.16.2 Programming the VLAN ID Table ........................................................................................................ 68
8.16.3 Priority Coding with VLAN Tags (IEEE 802.1p)................................................................................... 69
8.16.4 Priority Coding with Multiple (Q-in-Q) VLAN Tags............................................................................... 70
8.16.5 Priority Coding with DSCP................................................................................................................... 71
8.16.6 Programming the Priority Table ........................................................................................................... 72
8.17
OAM SUPPORT WITH FRAME TRAPPING, EXTRACTION, AND INSERTION .......................................74
8.17.1 Frame Trapping.................................................................................................................................... 76
8.17.2 Frame Extraction and Frame Insertion ................................................................................................ 77
8.17.3 OAM by Ethernet Destination Address (DA)........................................................................................ 78
8.17.4 OAM by IP Address.............................................................................................................................. 78
8.17.5 OAM by VLAN Tag............................................................................................................................... 78
8.17.6 SNMP Support ..................................................................................................................................... 78
8.18
BRIDGING AND FILTERING...........................................................................................................79
8.18.1 Bridge Filter Table Reset ..................................................................................................................... 79
8.19
ETHERNET MAC ........................................................................................................................80
8.19.1 PHY MII Management Block and MDIO Interface ............................................................................... 83
8.19.2 Ethernet MAC Management Counters for RFC2819 RMON............................................................... 84
8.19.3 Programmable Ethernet Destination Address Filtering........................................................................ 85
8.20
ETHERNET FRAME ENCAPSULATION ...........................................................................................86
8.20.1 Transmit Packet Processor (Encapsulator) ......................................................................................... 86
8.20.2 Receive Packet Processor (Decapsulator).......................................................................................... 87
8.20.3 GFP-F Encapsulation and Decapsulation............................................................................................ 89
8.20.4 X.86 Encoding and Decoding .............................................................................................................. 94
8.20.5 HDLC Encoding and Decoding............................................................................................................ 96
8.20.6 cHDLC Encoding And Decoding.......................................................................................................... 98
8.21
CIR/CBS CONTROLLER .............................................................................................................99
9.
APPLICATIONS INFORMATION.................................................................................................101
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
9.1 INTERFACING TO MAXIM T1/E1 TRANSCEIVERS............................................................................101
9.2 INTERFACING TO MAXIM T3/E3 TRANSCEIVERS............................................................................103
10. DEVICE REGISTERS...................................................................................................................105
10.1
REGISTER BIT MAPS ................................................................................................................106
10.1.1 Global Register Bit Map..................................................................................................................... 106
10.1.2 MAC Indirect Register Bit Map........................................................................................................... 131
10.2
GLOBAL REGISTER DEFINITIONS...............................................................................................141
10.2.1 Microport Registers............................................................................................................................ 147
10.2.2 MAC 1 Interface Access Registers .................................................................................................... 152
10.2.3 MAC 2 Interface Access Registers .................................................................................................... 156
10.2.4 VLAN Control Registers..................................................................................................................... 160
10.3
ETHERNET INTERFACE REGISTERS ...........................................................................................164
10.3.1 WAN Extraction and Transmit LAN registers..................................................................................... 164
10.3.2 Receive LAN Register Definitions...................................................................................................... 175
10.3.3 Bridge Filter Registers........................................................................................................................ 188
10.4
ARBITER REGISTERS................................................................................................................189
10.4.1 Arbiter Register Bit Descriptions........................................................................................................ 189
10.5
10.6
10.7
PACKET PROCESSOR (ENCAPSULATOR) REGISTERS.................................................................230
DECAPSULATOR REGISTERS ....................................................................................................236
VCAT/LCAS REGISTERS.........................................................................................................245
10.7.1 Transmit VCAT Registers .................................................................................................................. 245
10.7.2 VCAT Receive Register Description.................................................................................................. 252
10.8
SERIAL INTERFACE REGISTERS ................................................................................................265
10.8.1 Serial Interface Transmit and Common Registers............................................................................. 265
10.8.2 Serial Interface Transmit Register Bit Descriptions ........................................................................... 265
10.8.3 Transmit Per Serial Port Register Description................................................................................... 269
10.8.4 Transmit Voice Port Register Description.......................................................................................... 270
10.8.5 Receive Per Serial Port Register Description.................................................................................... 273
10.8.6 Receive Voice Port Register Description........................................................................................... 274
10.8.7 MAC Registers................................................................................................................................... 275
11. FUNCTIONAL TIMING.................................................................................................................330
11.1
FUNCTIONAL SPI INTERFACE TIMING ........................................................................................330
11.1.1 SPI Transmission Format and CPHA Polarity ................................................................................... 330
11.2
11.3
11.4
FUNCTIONAL SERIAL INTERFACE TIMING ...................................................................................333
VOICE PORT FUNCTIONAL TIMING DIAGRAMS............................................................................335
MII/RMII AND GMII INTERFACES ..............................................................................................336
12. OPERATING PARAMETERS ......................................................................................................339
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
THERMAL CHARACTERISTICS....................................................................................................341
TRANSMIT AND RECEIVE GMII INTERFACE ................................................................................342
TRANSMIT AND RECEIVE MII INTERFACE...................................................................................344
TRANSMIT AND RECEIVE RMII INTERFACE ................................................................................346
MDIO INTERFACE ....................................................................................................................348
TRANSMIT AND RECEIVE WAN INTERFACE................................................................................349
TRANSMIT AND RECEIVE VOICE PORT INTERFACE .....................................................................351
DDR SDRAM INTERFACE........................................................................................................353
AC CHARACTERISTICS—MICROPROCESSOR BUS INTERFACE TIMING........................................355
12.10 JTAG INTERFACE ....................................................................................................................362
13. JTAG INFORMATION..................................................................................................................363
13.1
JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION .........................................................364
13.1.1 TAP Controller State Machine ........................................................................................................... 364
13.2
INSTRUCTION REGISTER...........................................................................................................367
13.2.1 SAMPLE:PRELOAD .......................................................................................................................... 367
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4 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
13.2.2 BYPASS............................................................................................................................................. 367
13.2.3 EXTEST ............................................................................................................................................. 367
13.2.4 CLAMP............................................................................................................................................... 367
13.2.5 HIGHZ................................................................................................................................................ 367
13.2.6 IDCODE ............................................................................................................................................. 367
13.3
13.4
JTAG ID CODES......................................................................................................................368
TEST REGISTERS .....................................................................................................................368
13.4.1 Boundary Scan Register.................................................................................................................... 368
13.4.2 Bypass Register................................................................................................................................. 368
13.4.3 Identification Register......................................................................................................................... 368
13.5
JTAG FUNCTIONAL TIMING ......................................................................................................369
14. PIN CONFIGURATION ................................................................................................................370
14.1
14.2
14.3
DS33X162/X161/X82/X81/X42/X41 PIN CONFIGURATION—256-BALL CSBGA.......................370
DS33W41/DS33W11 PIN CONFIGURATION—256-BALL CSBGA .............................................371
DS33X11 PIN CONFIGURATION—144-BALL CSBGA................................................................372
15. PACKAGE INFORMATION .........................................................................................................373
15.1
15.2
256-BALL CSBGA, 17MM X 17MM (56-G6017-001) .................................................................373
144-BALL CSBGA, 10MM X 10MM (56-G6008-003) .................................................................374
16. DOCUMENT REVISION HISTORY..............................................................................................375
Rev: 063008
5 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
List of Figures
Figure 3-1. Standardized Ethernet Transport over Multiple T1/E1 Lines .................................................................. 14
Figure 3-2. Standardized Ethernet Transport over a Single T1/E1 Line ................................................................... 15
Figure 3-3. Remote IP DSLAM T1/E1 Trunk Card .................................................................................................... 16
Figure 6-1. Simplified Logical Block Diagram............................................................................................................ 20
Figure 7-1. 256-Ball, 17mm x 17mm CSBGA Pinout (DS33X162/X161/X82/X81/X42/X41).................................... 31
Figure 7-2. 256-Ball, 17mm x 17mm CSBGA Pinout (DS33W41/DS33W11)........................................................... 32
Figure 7-3. 144-Ball, 10mm x 10mm, CSBGA Pinout (DS33X11) ............................................................................ 33
Figure 8-1. Clocking Diagram.................................................................................................................................... 38
Figure 8-2. Device Interrupt Information Flow Diagram ............................................................................................ 42
Figure 8-3. Forwarding Mode 1: Single Ethernet Port with Priority Forwarding........................................................ 44
Figure 8-4. Forwarding Mode 2: One or Two Ethernet Port Forwarding with Scheduling......................................... 45
Figure 8-5. Forwarding Mode 3: Single Ethernet Port with LAN-VLAN Forwarding.................................................. 46
Figure 8-6. Forwarding Mode 4: 1 Ethernet port with Port ID and LAN-VLAN Forwarding....................................... 47
Figure 8-7. Forwarding Mode 5: Full LAN-to-WAN and WAN-to-LAN VLAN Forwarding......................................... 48
Figure 8-8. IEEE 802.3 Ethernet Frame.................................................................................................................... 60
Figure 8-9. Example Configuration of GMII Interface (DTE Mode Only)................................................................... 62
Figure 8-10. Example Configuration as DTE connected to an Ethernet PHY in MII Mode....................................... 63
Figure 8-11. Example Configuration as a DCE in MII Mode ..................................................................................... 65
Figure 8-12. RMII Interface (DTE Mode Only)........................................................................................................... 66
Figure 8-13. IEEE 802.1Q and 802.1p Field Format................................................................................................. 69
Figure 8-14. VLAN Q-in-Q Field Format.................................................................................................................... 70
Figure 8-15. Differentiated Services Code Point (DSCP) Header Information.......................................................... 71
Figure 8-16. Supported Trapped Ethernet Frame Types .......................................................................................... 75
Figure 8-17. MII Management Frame........................................................................................................................ 83
Figure 8-18. GFP-F NULL Encapsulated Frame Format .......................................................................................... 91
Figure 8-19. GFP-F LINEAR EXTENSION Encapsulated Frame Format................................................................. 93
Figure 8-20. LAPS / X.86 Encapsulated Frame Format............................................................................................ 94
Figure 8-21. HDCL Encapsulated Frame Format...................................................................................................... 97
Figure 8-22. cHDLC Encapsulated Frame Format.................................................................................................... 98
Figure 9-1. Interfacing with T1/E1 Transceivers...................................................................................................... 101
Figure 9-2. Example Functional Timing: DS2155 E1 Transmit-Side Boundary Timing .......................................... 101
Figure 9-3. Example Functional Timing: DS2155 T1 Transmit-Side Boundary Timing........................................... 102
Figure 9-4. Example Functional Timing: DS2155 E1 Receive-Side Boundary Timing ........................................... 102
Figure 9-5. Example Functional Timing: DS2155 T1 Receive-Side Boundary Timing............................................ 102
Figure 9-6. Interfacing with T3/E3 Transceivers...................................................................................................... 103
Figure 9-7. Example Functional Timing: DS3170 DS3 Transmit-Side Boundary Timing........................................ 103
Figure 9-8. Example Functional Timing: DS3170 DS3 Receive-Side Boundary Timing......................................... 104
Figure 11-1. SPI Serial Port Access For Read Mode, SPI_CPOL=0, SPI_CPHA = 0............................................ 330
Figure 11-2. SPI Serial Port Access For Read Mode, SPI_CPOL = 1, SPI_CPHA = 0.......................................... 330
Figure 11-3. SPI Serial Port Access For Read Mode, SPI_CPOL = 0, SPI_CPHA = 1.......................................... 331
Figure 11-4. SPI Serial Port Access For Read Mode, SPI_CPOL = 1, SPI_CPHA = 1.......................................... 331
Figure 11-5. SPI Serial Port Access For Write Mode, SPI_CPOL = 0, SPI_CPHA = 0 .......................................... 331
Figure 11-6. SPI Serial Port Access For Write Mode, SPI_CPOL = 1, SPI_CPHA = 0 .......................................... 331
Figure 11-7. SPI Serial Port Access For Write Mode, SPI_CPOL = 0, SPI_CPHA = 1 .......................................... 332
Figure 11-8. SPI Serial Port Access For Write Mode, SPI_CPOL = 1, SPI_CPHA = 1 .......................................... 332
Figure 11-9. Transmit Serial Port Interface, without VCAT ..................................................................................... 333
Figure 11-10. Transmit Serial Port Interface with VCAT ......................................................................................... 333
Figure 11-11. Transmit Serial Port Interface, with Gapped Clock........................................................................... 333
Figure 11-12. Transmit Serial Port Interface with VCAT, early TSYNC (2 cycles).................................................. 334
Figure 11-13. Receive Serial Port Interface, without VCAT, rising edge sampling................................................. 334
Figure 11-14. Receive Serial Port Interface with VCAT, rising edge sampling....................................................... 334
Figure 11-15. Receive Serial Port Interface with Gapped Clock (T1) ..................................................................... 334
Figure 11-16. Transmit Voice Port Interface with PCM Octets................................................................................ 335
Figure 11-17. Receive Voice Port Interface with PCM Octets................................................................................. 335
Figure 11-18. GMII Transmit Interface Functional Timing....................................................................................... 336
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 11-19. GMII Receive Interface Functional Timing........................................................................................ 336
Figure 11-20. MII Transmit Functional Timing......................................................................................................... 337
Figure 11-21. MII Transmit Half Duplex with a Collision Functional Timing............................................................ 337
Figure 11-22. MII Receive Functional Timing.......................................................................................................... 337
Figure 11-23. RMII Transmit Interface Functional Timing....................................................................................... 338
Figure 11-24. RMII Receive Interface Functional Timing........................................................................................ 338
Figure 12-1. Transmit GMII Interface Timing........................................................................................................... 342
Figure 12-2. Receive GMII Interface Timing............................................................................................................ 343
Figure 12-3. Transmit MII Interface Timing ............................................................................................................. 344
Figure 12-4. Receive MII Interface Timing .............................................................................................................. 345
Figure 12-5. Transmit RMII Interface Timing........................................................................................................... 346
Figure 12-6. Receive RMII Interface Timing............................................................................................................ 347
Figure 12-7. MDIO Interface Timing........................................................................................................................ 348
Figure 12-8. Transmit WAN Timing (Noninverted TCLK)........................................................................................ 349
Figure 12-9. Receive WAN Timing (Noninverted RCLK) ........................................................................................ 350
Figure 12-10. Transmit Voice Port Interface Timing................................................................................................ 351
Figure 12-11. Receive Voice Port Interface Timing................................................................................................. 352
Figure 12-12. DDR SDRAM Interface Timing.......................................................................................................... 354
Figure 12-13. Intel Bus Read Timing (MODE = 0) .................................................................................................. 356
Figure 12-14. Intel Bus Write Timing (MODE = 0)................................................................................................... 356
Figure 12-15. Motorola Bus Read Timing (MODE = 1) ........................................................................................... 357
Figure 12-16. Motorola Bus Write Timing (MODE = 1) ........................................................................................... 357
Figure 12-17. Multiplexed Intel Bus Read Timing (MODE = 0) ............................................................................... 359
Figure 12-18. Multiplexed Intel Bus Write Timing (MODE = 0) ............................................................................... 359
Figure 12-19. Multiplexed Motorola Bus Read Timing (MODE = 1)........................................................................ 360
Figure 12-20. Multiplexed Motorola Bus Write Timing (MODE = 1)........................................................................ 360
Figure 12-21. SPI Interface Timing Diagram........................................................................................................... 361
Figure 12-22. JTAG Interface Timing ...................................................................................................................... 362
Figure 13-1. JTAG Functional Block Diagram......................................................................................................... 363
Figure 13-2. TAP Controller State Diagram............................................................................................................. 366
Figure 13-3. JTAG Functional Timing...................................................................................................................... 369
Rev: 063008
7 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
List of Tables
Table 1-1. Product Selection Matrix............................................................................................................................. 9
Table 7-1. Detailed Pin Descriptions ......................................................................................................................... 21
Table 8-1. Clocking Options for the Ethernet Interface ............................................................................................. 37
Table 8-2. Software Reset Functions ........................................................................................................................ 39
Table 8-3. Block Enable Functions............................................................................................................................ 40
Table 8-4. Forwarding Modes Supported by Device ................................................................................................. 49
Table 8-5. Maximum Number of T3/E3 Lines Per Encapsulator (DS33X162 and DS33X82 Only).......................... 51
Table 8-6. VCAT/LCAS Control Frame for T1/E1...................................................................................................... 53
Table 8-7. VCAT/LCAS Control Frame for T3/E3...................................................................................................... 54
Table 8-8. Configuration Recommendations for Maximum Frame Length................................................................ 61
Table 8-9. Selection of MAC Interface Modes for Port 1........................................................................................... 61
Table 8-10. Selection of MAC Interface Modes for Port 2......................................................................................... 61
Table 8-11. MII Mode Options ................................................................................................................................... 64
Table 8-12. Example Priority Table Configuration for DSCP .................................................................................... 72
Table 8-13. Example Priority Table Configuration for PCP....................................................................................... 73
Table 8-14. MAC Control Registers........................................................................................................................... 81
Table 8-15. MAC Status Registers ............................................................................................................................ 81
Table 8-16. MAC Counter Registers.......................................................................................................................... 82
Table 8-17. GFP Type/tHEC Field (Payload Header) Definition ............................................................................... 89
Table 8-18. GFP UPI Definitions ............................................................................................................................... 89
Table 8-19. Example GFP Type + tHEC Values ....................................................................................................... 90
Table 8-20. GFP CID/Spare/eHEC (Extension Header) Field Definition................................................................... 92
Table 8-21. Example CID + Spare + eHEC Values................................................................................................... 92
Table 8-22. Credit Threshold Settings with Resulting Bandwidths.......................................................................... 100
Table 10-1. Register Address Map.......................................................................................................................... 105
Table 10-2. Global Register Bit Map........................................................................................................................ 106
Table 10-3. MAC Indirect Register Bit Map............................................................................................................. 131
Table 10-4. Default GL.IDR Values......................................................................................................................... 141
Table 10-5. Valid Conditions for MPL > 2048.......................................................................................................... 182
Table 12-1. Recommended DC Operating Conditions............................................................................................ 339
Table 12-2. DC Electrical Characteristics................................................................................................................ 340
Table 12-3. Thermal Characteristics........................................................................................................................ 341
Table 12-4. Transmit GMII Interface........................................................................................................................ 342
Table 12-5. Receive GMII Interface......................................................................................................................... 343
Table 12-6. Transmit MII Interface........................................................................................................................... 344
Table 12-7. Receive MII Interface............................................................................................................................ 345
Table 12-8. Transmit RMII Interface........................................................................................................................ 346
Table 12-9. Receive RMII Interface......................................................................................................................... 347
Table 12-10. MDIO Interface ................................................................................................................................... 348
Table 12-11. Transmit WAN Interface..................................................................................................................... 349
Table 12-12. Receive WAN Interface...................................................................................................................... 350
Table 12-13. Transmit Voice Port Interface............................................................................................................. 351
Table 12-14. Receive Voice Port Interface.............................................................................................................. 352
Table 12-15. DDR SDRAM Interface....................................................................................................................... 353
Table 12-16. Parallel Microprocessor Bus............................................................................................................... 355
Table 12-17. Multiplexed Microprocessor Bus ........................................................................................................ 358
Table 12-18. SPI Microprocessor Bus Mode........................................................................................................... 361
Table 12-19. JTAG Interface ................................................................................................................................... 362
Table 13-1. Instruction Codes for IEEE 1149.1 Architecture................................................................................... 367
Table 13-2. ID Code Structure................................................................................................................................. 368
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
1.
Detailed Description
The DS33X162 family of devices provide interconnection and mapping functionality between Ethernet Systems and
WAN Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, T3/E3, and SONET/SDH. The device is
composed of up to two 10/100/1000 Ethernet MACs, up to 16 Serial Ports, a Arbiter, GFP-F /HDLC/cHDLC/X.86
(LAPS) Mappers, a DDR SDRAM interface, and control ports. Ethernet traffic is encapsulated with GFP-F, HDLC,
cHDLC, or X.86 (LAPS) to be transmitted over the WAN Serial Interfaces. The WAN Serial Interfaces also receive
encapsulated Ethernet frames and transmit the extracted frames over the Ethernet ports. The LAN frame interface
consists of Ethernet interfaces using one of two physical layer protocols. It can be configured with up to two
10/100Mbps MII/RMII ports or a single GbE GMII port. The WAN Serial Interface can be configured for up to eight
serial data streams at up to 52Mbps each, or 16 serial data streams at up to 2.5Mbps each. The Serial Interfaces
can be seamlessly connected to the Maxim T1/E1/J1 Framers, Line Interface Units (LIUs), and Single-Chip
Transceivers (SCTs). The WAN interfaces can also be seamlessly connected to the Maxim T3/E3/STS-1 Framers,
LIUs, and SCTs to provide T3, E3, or STS1 connectivity.
Microprocessor control can be accomplished through a 8-bit Micro controller port or SPI Bus. The device has a
125MHz DDR SDRAM controller and interfaces to a 32-bit wide 256Mb DDR SDRAM via a 16-bit data bus. The
DDR SDRAM is used to buffer data from the Ethernet and WAN ports for transport.
The power supplies consist of a 1.8V core supply, a 2.5V DDR SDRAM supply, and 3.3V I/O supply. The DDR
interface also requires a 1.25V reference voltage that can be obtained through a resistor-divider network.
Table 1-1. Product Selection Matrix
VLAN
Supported
WAN
Groups
(VCGs)
Ordering
Number
Ethernet
Ports
TDM
Ports
Voice
Ports
μP
Control
Forwarding Forwarding
Support
Package
Modes
1
10mm 144
CSBGA
17mm 256
CSBGA
17mm 256
CSBGA
17mm 256
CSBGA
17mm 256
CSBGA
17mm 256
CSBGA
17mm 256
CSBGA
17mm 256
CSBGA
DS33X11+
DS33W11+
DS33X41+
DS33W41+
DS33X42+
DS33X81+
DS33X82+
DS33X161+
DS33X162+
1
1
0
1
0
1
0
0
0
0
0
No
2
1
SPI
10/100/GbE
1
SPI or
Parallel
SPI or
Parallel
SPI or
Parallel
SPI or
Parallel
SPI or
Parallel
SPI or
Parallel
SPI or
Parallel
SPI or
Parallel
No
No
2
1
1
10/100/GbE
1
10/100/GbE
4
2
1, 2, 3
1, 2, 3, 5
2
1
4
No
1 & 3
1 & 3
1
10/100/GbE
2 10/100
or 1 GbE
1
10/100/GbE
2 10/100
or 1 GbE
1
4
Yes
No
8
8
Yes
No
1, 2, 3, 4, 5
2
1, 2, 3, 4
1
16
16
10/100/GbE
2 10/100
or 1 GbE
17mm 256
CSBGA
Yes
1, 2, 3, 4, 5
1, 2, 3, 4
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
2.
Feature Highlights
General
2.1
•
17mm 256 pin CSBGA Package (DS33X162/X161/X82/X81/X41/W41/W11)
10mm 144 pin CSBGA Package (DS33X11)
1.8V, 2.5V, 3.3V supplies
IEEE 1149.1 JTAG boundary scan
Software access to device ID and silicon revision
Development support includes evaluation kit, driver source code, and reference designs
•
•
•
•
•
2.2
VCAT/LCAS Link Aggregation (Inverse Multiplexing)
•
•
•
•
•
•
•
•
Link aggregation for up to 16 links per ITU-T G.7043/G.7042
Up to 16 members per VCG
4 VCGs for the DS33X162/X82, 2 VCGs for the DS33X42, 1 VCG for the DS33X161/X81/X41/W41
Differential delay compensation for up to 200 ms among members of a VCG
Receive and Transmit are independent (asymmetry support)
User programmable configuration of WAN ports used for VCG
Supports Virtual Concatenation of up to 8 T3/E3 or 16 T1/E1
VCAT/LCAS link aggregation not available in the DS33X11 and DS33W11
2.3
HDLC
•
•
•
•
•
•
•
•
•
•
•
Up to 4 HDLC Controller Engines
Compatible with polled or interrupt driven environments
Supports Bit stuffing/destuffing without Address/Control/PID fields
Programmable FCS insertion and extraction, with removal of payload FCS
16-bit or 32-bit FCS, with support for FCS error insertion
Programmable frame size limits (Minimum 64 bytes and maximum 2016 bytes)
Selectable self-synchronizing X43+1 frame scrambling/descrambling
Separate valid and invalid frame counters
Programmable inter-frame fill for transmit HDLC
Supports Transparency Processing and Abort Sequence
Programmable frame filtering for FCS errors, aborts, or frame length errors
2.3.1 cHDLC
•
•
•
•
•
•
•
Bit stuffing with Address/Control/PID/FCS fields
Programmable Interframe fill length.
Transparency processing
Counters: Number of received valid frames and erred frames
Incoming Frame Discard due to FCS error, abort or frame length longer than preset max.
The default maximum frame length is associated with the maximum PDU length of MAC frame
Extract SLARP for external processor interpretation
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
2.4
GFP-F
•
•
•
•
•
•
•
•
GFP Frame mode per ITU-T G.7041
GFP idle frame insertion and extraction
Supports Null and Linear headers
cHEC based frame delineation
X
43 +1 payload and Barker Sequence scrambling/descrambling
CSF frame generation and detection
Error detection over core header and type headers
Programmable CRC-32 generation and verification
2.5
X.86 Support
•
•
•
•
•
•
•
•
•
•
Encapsulation Per ITU-T X.86 (Link Access Procedure for SONET/SDH), with 32 bit FCS
Transmit Transparency processing - 7E is replaced by 7D, 5E
Transmit Transparency processing – 7D replaced by 7D, 5D
Receive rate adaptation (7D, DD) removal.
Receive Transparency processing - 7D, 5E is replaced by 7D
Receive Transparency processing – 7D, 5D is replaced by 7D
Receive Abort Sequence - frame is dropped if 7D7E is detect
Selectable self-synchronizing X43+1 frame scrambling/descrambling
Counters: Number of received valid frames and erred frames
Frame filtering due to bad Address/Control/SAPI, FCS error, abort, or frame length errors
2.6
DDR SDRAM Interface
•
•
•
•
•
•
•
•
16-bit wide data bus with dual edge transfers and Auto Refresh Timing
Designed to interface with 256Mbit JEDEC JESD79D compliant DDR SDRAMs with a 16-bit data bus
Addressable memory range up to 256 Mbits
JESD79D compliant device sizes other than 256 Mbits may be used, limited to 256 Mbit utilization
Compatible with DDR266+
SDRAM Interface Clock output of 125MHz
Direct connection to external DDR SDRAM (P2P Mode Support)
Example devices: Micron MT46V16M16, Samsung K4H561638F and Hynix HY5DU561622CF
2.7
MAC Interfaces
•
•
•
•
•
•
•
•
•
•
Two E/FE MAC ports with MII/RMII or one GbE port with GMII.
10Mbps/100Mbps/1000Mbps Data rates
Configurable for DTE or DCE mode
Facilitates auto-negotiation by host microprocessor
Programmable half and full-duplex modes
Flow control per 802.3 half-duplex (back-pressure) and full-duplex (pause) modes
Auto Negotiation for Rates and duplex modes
Programmable max MAC frame Lengths up to 2016 Bytes for E/FE, 12KB for GbE.
Minimum MAC frame length: 64 bytes
Discards frames larger than the max MAC frame size, Runt, non-octet bounded, or bad-FCS frames upon
reception
•
•
•
•
•
Programmable threshold for SDRAM queues to initiate flow control, with status indication
Terminal and Facility Loopbacks at MAC port (without SA/DA swapping)
Ethernet management interface (MDIO)
Supports all applicable RMON (RFC2819) 32 bit counters with saturation at max count.
Configurable for promiscuous mode and broadcast-discard mode.
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
2.7.1 Ethernet Bridging for 10/100
•
•
4K Address and VLAN ID lookup table for Learning and Filtering
Programmable Aging between 1 to 300 seconds in 1 second intervals
2.7.2 Ethernet Traffic Classification
•
•
Ingress Classification according to Ethernet COS
Programmable class map to 4 queues for each Ethernet port
2.7.3 Ethernet Bandwidth Policing
•
•
•
•
•
Bandwidth Policing with programmable CIR/CBS on Ethernet Ingress direction.
Bandwidth Policing based on a per port basis.
Programmable IEEE 802.3 Pause flow control or discard based on CIR/CBS
Programmable Non-conforming Ethernet frame discard based on CIR/CBS
See Section 8.21 for details on the granularity of CIR/CBS.
2.7.4 Ethernet Traffic Scheduling
Programmable scheduler for Ethernet flows toward PDH port(s):
•
o
o
Strict priority, or
Weighted Queuing
2.7.5 Connection Endpoints
Connection between Ethernet port(s) and Serial(s) based on
•
•
Ethernet side:
o
o
o
per Ethernet port, or
per VLAN ID (sub-interface)
Priority (VLAN PCP or DSCP)
•
WAN side (Serial):
o
o
per Serial port, or
per VCG bundle
2.7.6 Virtual Connection
•
Each connection configured for bi-directional flow with selected encapsulation.
2.7.7 Connection and Aggregation
•
Forwarding between Endpoints based on the following options:
o
o
Per Ethernet port ꢀꢁper serial port or per VCG
Per VLAN ID ꢀꢁper Serial port or port VCG
•
VLAN Forwarding supported only in the DS33X42, DS33X82, and DS33X162
2.7.8 Ethernet Control Frame Processing
•
•
Control Frames, except PAUSE and OAM, shall be forwarded without processing.
PAUSE and OAM frames can be programmed to be intercepted, discarded or forwarded.
2.7.9 Q-in-Q
•
Programmable Carrier VLAN tag insertion.
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
2.8
Serial Ports
•
•
•
•
•
Four, Eight or Sixteen Serial ports with Synchronous Clock/Data at 128kbps to 52MHz.
Independently clock inputs for RX and TX operations on the per port bases.
Input clock supports either continuous or gapped clock
Seamless interconnect with Maxim LIU/Framer/Transceiver devices for T1/E1/J1, and T3/E3
Terminal and Facility Loopbacks per port
2.8.1 Voice Ports
•
•
•
The DS33W41 supports up to four voice ports; DS33W11 supports one voice port
Each voice port supports up to 16 DS0s of voice to be multiplexed with Ethernet traffic
Devices supporting voice input are restricted to T1/E1 WAN data rates
2.9
Microprocessor Interface
•
•
•
•
Selectable 8-bit Parallel or SPI Serial data bus
Multiplexed/Non-multiplexed Intel and Motorola Timing Modes
Internal software reset and External Hardware reset input pin
Global interrupt output pin
2.10 Slave Serial Peripheral Interface (SPI) Features
•
•
Four-signal synchronous serial data link operating in full duplex slave mode up to 10Mbps
Direct connection and fully compliant to popular communication processors such as MPC8260 and
microcontrollers such as M68HC11
2.11 Test and Diagnostics
•
•
IEEE 1149.1 Support
Diagnostic Loopbacks
2.12 Specifications Compliance
The DS33X162 family of products adhere to the applicable telecommunications standards. The following list
provides the specifications and relevant sections.
IEEE:
802.3-2002, CSMA/CD access method and physical layer specifications.
802.1D (1998): MAC Bridge
802.1Q (1998): Virtual LANs
802.1v-2001: VLAN Classification by Protocol and Port
802.1ag: Ethernet OAM (extract/insert support)
802.3ah: Ethernet First Mile (OAM extract/insert support)
RFC1662, PPP in HDLC-like Framing
IETF:
RFC2615, PPP over SONET/SDH
RFC2918, RMON MIB (Hardware counters, extract/insert support)
X.86 Ethernet over LAPS
ITU-T:
G.707 Network node interface for the synchronous digital hierarchy (SDH)
G.7041 Generic Framing Procedure (GFP) (12/2001)
G.7042 LCAS for VCAT signal (02/2004)
G.7043 VCAT of PDH signals (07/2004)
G.8040 GFP over PDH
Y.1303 Framed GFP
Y.1323 Ethernet over LAPS
Y.1731 Ethernet OAM (extract/insert support)
T1X1/2000-0243R Generic Framing Procedure
ANSI:
Other:
RMII: Industry Implementation Agreement for “Reduced MII Interface,” Sept 1997
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
3.
Applicable Equipment Types
♦
♦
♦
Bonded Transparent LAN Service
LAN Extension
Ethernet Delivery over T1/E1/J1, T3/E3, xDSL, V.35/Optical
Figure 3-1. Standardized Ethernet Transport over Multiple T1/E1 Lines
E1/T1 #1
E1/T1 #2
DS26521
T1/E1
SCT #1
10/100/
10/100/1000
DS33X162
1000
ETHERNET
ETHERNET-TO-SERIAL
PHY
CONVERSION, QoS,
VCAT/LCAS
AGGREGATION,
MII,
RMII,
GMII
DS26521
T1/E1
SCT #2
10/100
ETHERNET
10/100/
PHY
BRIDGING & FILTERING,
BUFFERING, RATE
MATCHING, ERROR
DETECTION, STATISTICS
GATHERING,
•
•
E1/T1 #16
DS26521
T1/E1
SCT #16
OAM EXTRACT/INSERT
DDR
SDRAM
MAX3232e
DS80C320 μC FOR
CONFIGURATION
RS-232
CONFIG
MAX809L
μC RESET
SOLUTION ADVANTAGES:
•
Up to 200ms of Differential Delay Tolerance, with VCAT/LCAS (ITU-T G.7042/G.7043) Link
Aggregation
•
•
•
•
•
Ethernet Transport Over Up to 16 T1/E1s or 8 DS3s with QoS and Ethernet OAM Capability!
No Data Path Code Development Required!
Committed Information Rate (CIR) Controller Can Be Used to Throttle Subscriber Bandwidth Usage!
GFP, HDLC, LAPS, or cHDLC Encapsulation
Advanced Forwarding Modes Allow Use of VLAN or Priority for Physical Port Assignment of
Frames
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 3-2. Standardized Ethernet Transport over a Single T1/E1 Line
E1/T1
DS33X11
10/100/1000
ETHERNET
MII,
RMII,
GMII
DS26521
T1/E1
SCT #1
ETHERNET-TO-SERIAL
CONVERSION, QoS,
BRIDGING & FILTERING,
BUFFERING, RATE
10/100/
1000
PHY
MATCHING, ERROR
DETECTION, STATISTICS
GATHERING, OAM
PROGRAMMABLE
GAPPED CLOCK,
DATA, AND
FRAME SYNC
EXTRACT/INSERT
DDR
SDRAM
MAX3232
DS80C320 μC
RS-232
CONFIG
FOR CONFIGURATION
MAX809L
μC RESET
SOLUTION ADVANTAGES:
•
•
•
•
•
Ethernet Transport Over Single or Fractional E1/T1 with QoS and Ethernet OAM Capability!
Flexible Fractional E1/T1 (Nx64kbps in Any DS0s) Support, Using DS26521 Channel Blocking
No Data Path Code Development Required!
GFP, HDLC, LAPS, or cHDLC Encapsulation
Solution Extends Easily to DS3/E3
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 3-3. Remote IP DSLAM T1/E1 Trunk Card
8 AGGREGATED
T1/E1/J1s
xDSL LINE CARD
MII/
RMII/
GMII
DS33X81
ETHERNET-TO-
SERIAL LINK
xDSL LINE CARD
xDSL LINE CARD
DS26528
OCTAL T1/E1/J1
SINGLE-CHIP
AGGREGATION
GFP/VCAT/LCAS
VLAN, Q-IN-Q,
10/100/GbE
TRANSCEIVER
TO
SUBSCRIBERS
DS80C320 μC
SDRAM
1000BASE-LX
GbE TRANSCEIVER
xDSL LINE CARD
SOLUTION ADVANTAGES:
•
•
•
•
•
•
Standards Compliant Ethernet Transport Over Multiple E1/T1 Links
QoS and Ethernet OAM Capability!
No Data Path Code Development Required!
GFP, HDLC, LAPS, or cHDLC Encapsulation
Cost-Optimized Ethernet Transport
Solution Extends Easily to DS3/E3
Rev: 063008
16 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
4.
Acronyms & Glossary
•
•
CLE - Customer Located Equipment.
CoS - Class of Service, 802.1Q defined three User priority bits in Tag control Info Field.
•
•
•
DCE - Data Communication Interface.
DSCP - Diff Serve Code Point, IETF defined six bits in the IP ToS field.
DTE - Data Terminating Interface.
•
•
EoPDH - Ethernet over PDH. Ethernet encapsulated in HDLC or GFP, transported via one or more PDH lines.
EoPoS - Ethernet transport over PDH over SONET/SDH. Maintaining a PDH framing layer enables re-use of
existing Ethernet-over-SSONET/SDH and PDH-over-SONET/SDH equipment for delivering Ethernet services.
EoS – Ethernet over SONET/SDH.
•
•
•
•
•
•
•
FCS - Frame Check Sequence.
Frame – A Layer-2 Protocol Data unit. (In general, Layer 2 frames carry Layer 3 packets).
Gapped Clock - Non-continuous clock used to strobe the associated synchronous Data at certain times.
HDLC - High Level Data Link Control.
LAN - Local Area Network. Usually used to refer to a local Ethernet segment.
MAC - Media Access Control. Lowest Digital Layer of Protocol Stack. Performs Framing, Sequencing, and
Addressing.
•
•
•
•
MII - Media Independent Interface. One type of data bus between the physical layer (PHY) and the MAC.
Packet – A Layer 3 Protocol Data unit.
PDH - Plesiochronous Digital Hierarchy. The existing telephone network’s “last mile.” Primarily T1/E1 lines.
PHY - A device that interfaces an OSI logical layer to a physical media (Cat-5, twisted-pair, etc.). In this
document, interfaces an Ethernet MAC to copper or fiber.
•
•
•
RMII - Reduced Media Independent Interface.
VID- Virtual LAN Identifier.
VCAT - Virtual Concatenation. Used in conjunction with the Link Capacity Adjustment Scheme for transporting
Ethernet over bonded PDH or SDH/SONET tributaries.
•
WAN - Wide Area Network. Typically T1(DS1), E1, T3(DS3), E3, or xDSL.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
5.
Designing with the DS33X162 Family of Devices
The DS33X162 family of products provide the required flexibility and complexity to meet the needs of a very broad
range of applications. Although typical applications using these devices are very complex and each application has
a unique set of needs, most application developments follow a predictable set of steps:
1. Identification of Application Requirements
2. Device Selection
3. Ancillary Device Identification
4. Circuit Design
5. Board Layout
6. Software Development
7. Production
5.1
Identification of Application Requirements
The designer of an application using one of the devices in the DS33X162 product line should begin by answering
several high-level questions.
The solutions to these questions, in conjunction with referencing Table 1-1, will lead to a proper device selection:
How many and what type of TDM links are needed?
How does data need to move between the various interfaces of the mapping device?
What traffic prioritization methodologies will be needed?
How many Ethernet ports are needed?
Is direct multiplexing of PCM encoded voice traffic a requirement.
5.2
Device Selection
The answer to “How many and what type of TDM links are needed?” will normally narrow the selection to devices
that contain at least that many ports. For example, if 16 E1 links are required, the applicable solutions are the
DS33X161 and DS33X162. If 4 DS-3 links are required, the applicable solutions are the DS33X41, DS33X42,
DS33X81, DS33X82, DS33X161, and DS33X162.
The answer to “How does data need to move between the various interfaces of the mapping device?” will usually
further narrow the selection. The path any given frame takes through the device can be determined by the contents
of the frame, the port of entry, the user configured WAN Connections, and the user configured Forwarding Mode.
Note that all devices in the product family allow insertion and extraction of frames for inspection, (including ITU-T
Y.1731 OAM frames) by the host microprocessor, based on a number of conditions outlined in Section 8.17
If traffic flow is to be governed by VLAN tag information, the choices are narrowed to only those devices that
support VLAN forwarding: DS33X42, DS33X82, and DS33X162. If ingress traffic is to be segregated by VLAN ID or
DSCP Priority into separate WAN flows, the available number of WAN Groups in Table 1-1 should be considered.
Several Forwarding Modes govern the flow of frames through the device. See Table 8-4 in Section 8.9 for more
information.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
5.3
Ancillary Device Selection
All devices in the product family require an external DDR SDRAM for operation. The user must select a JEDEC
JESD79D compliant DDR SDRAM. DDR 266 or faster may be used. The recommended size is 256 Mbit (4 Meg x
16 x 4 banks), although it is possible to use other sizes (see Section 5.4). P2P operation is supported, and 0-ohm
series termination is possible with proper PCB layout.
All devices in the product family require an external microprocessor for configuration and status monitoring.
Because the DS33X162 family of devices are designed to require only a minimal amount of processor support, an
inexpensive microcontroller can normally be used. In applications which make extensive use of the support for
higher-layer protocols may require additional protocol processing capability, microprocessor selection can normally
be determined by evaluating the management frame processing requirements of the particular application. All
devices in the product family are designed to support both polled and interrupt-driven environments.
Microprocessor control is possible through the 8-bit parallel control port or SPI Slave port. More information on
microprocessor control is available in Section 8.1. Note that the parallel bus is not available in the 144 pin
DS33X11, and the SPI Slave port must be used for processor control.
Depending on the application, external PDH framers and LIUs may be required. Maxim offers a broad range of
framers, LIUs, and single-chip transceivers compatible with the DS33X162 family of products.
The Ethernet interface will normally be connected to an external Ethernet PHY or Ethernet switch device. Many
commercially-available products are available and will seamlessly interface with the device’s MII, RMII, or GMII
options.
Several external clock sources are required for proper operation. See Section 8.3 for more information.
5.4
Circuit Design
Note that all devices except the DS33X11, DS33W11, and DS33W41 share a common footprint. This is intended to
make it very easy to design a circuit that easily scales from 4 to 16 WAN ports with alternate assembly BOMs.
When designing a PCB for 4 or 8 ports, care should be taken to tie the unused input pins for serial ports 5-16 or 9-
16 to ground. This will allow for use of the higher density device for prototype purposes. Care should be taken that
outputs from the DS33X162 family device that are present in the high-port count option but not in the low port-count
option may potentially leave inputs on other devices floating, and should be pulled appropriately to a known
voltage.
The device’s DDR SDRAM interface is designed to use a JESD79D 256 Mbit (4 Meg x 16 x 4 bank) DDR SDRAM
with a 16 bit data bus. If a larger DDR SDRAM must be used, the lowest 13 address lines (A0-A12) should be
used, and care should be taken to ground any unused address inputs on the DDR SDRAM. Note that in such a
case, only 256 Mbits are addressable by the device. If a smaller JESD79D DDR SDRAM is to be used (such as the
128 Mbit MT46V8M16), the unused address outputs should be left unconnected, and care should be taken in
software to keep the starting and ending addresses of each queue within the same memory bank. In all cases, P2P
operation is supported, and 0Ω series termination is possible with proper PCB layout.
5.5
Board Layout
The DDR SDRAM interface has particularly stringent layout requirements. Traces should have matched
impedances, be of equal length, and should not have stubs. Refer to the DDR SDRAM’s data sheet for more
information. Supply decoupling should be placed as close to the device as possible.
5.6
Software Development
All devices in the product family have a common register set. An example initialization sequence is shown in
Section 8.5. Software drivers and demonstration kit software are both available from Maxim. Go to
www.maxim-ic.com/support for the latest information.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
6.
Block Diagrams
Figure 6-1. Simplified Logical Block Diagram
SPI
μP Port
CLAD
TCLK1
TDATA1
TSYNC1
SYSCLKI
TRANSMIT SERIAL
PORT 1
(MII MODE)
RXD[0:4]
RX_CLK
RX_CRS
RX_ERR
COL1
TCLK2
TDATA2
TSYNC2
TRANSMIT SERIAL
PORT 2
TX_CLK
TX_EN
TXD[0:4]
TMCLK4
TDATA16
TMSYNC4
TRANSMIT SERIAL
PORT 16
MDC
MDIO
ARBITER/
BUFFER MANAGER
Add/Drop
OAM Frames
(MII MODE)
RXD[0:4]
RX_CLK
RX_CRS
RX_ERR
COL2
RCLK1
RDATA1
RSYNC1
RECEIVE SERIAL
PORT 1
RCLK2
RDATA2
RSYNC2
TX_CLK
TX_EN
TXD[0:4]
RECEIVE SERIAL
PORT 2
MDC
MDIO
RCLK16
RDATA16
RSYNC16
RECEIVE SERIAL
PORT 16
JTAG
DDR SDRAM PORT
VOICE PORT(W41/W11)
Rev: 063008
20 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
7.
Pin Descriptions
7.1
Pin Functional Description
Note that all digital pins are inout pins in JTAG mode. This feature increases the effectiveness of board level ATPG
patterns.
Table 7-1. Detailed Pin Descriptions
PACKAGE PINS
NAME
TYPE
FUNCTION
256
144
MICROPROCESSOR PORT
Address Bit 0. Address bit 0 of the microprocessor interface. Least
Significant Bit. Note that the parallel bus is not available in the 144 pin
DS33X11, and the SPI Slave port must be used for processor control.
A0
K10
—
I
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
L9
—
—
—
—
—
—
—
—
—
—
I
I
I
I
I
I
I
I
I
I
Address Bit 1. Address bit 1 of the microprocessor interface.
Address Bit 2. Address bit 2 of the microprocessor interface.
Address Bit 3. Address bit 3 of the microprocessor interface.
Address Bit 4. Address bit 4 of the microprocessor interface.
Address Bit 5. Address bit 5 of the microprocessor interface.
Address Bit 6. Address bit 6 of the microprocessor interface.
Address Bit 7. Address bit 7 of the microprocessor interface.
Address Bit 8. Address bit 8 of the microprocessor interface.
Address Bit 9. Address bit 9 of the microprocessor interface.
Address Bit 10. Address bit 10 of the microprocessor interface.
K11
L10
K13
L11
K12
L12
G10
L13
G11
Data Bit 0. Bi-directional data bit 0 of the microprocessor interface. Least
Significant Bit. Not driven when CS=1 or RST=0.
SPI_MISO (SPI_SEL=1). SPI Serial Data Output (Master-in Slave-Out).
D0/
SPI_MISO
K6
J4
IOz
Data Bit 1. Bi-directional data bit 1 of the microprocessor interface. Not
driven when CS=1 or RST=0.
SPI_MOSI (SPI_SEL=1). SPI Serial Data Input (Master-out Slave-in)
Data Bit 2. Bi-directional data bit 2 of the microprocessor interface. Not
driven when CS=1 or RST=0.
SPI_CLK (SPI_SEL=1). SPI Serial Clock Input.
Data Bit 3. Bi-directional data bit 3 of the microprocessor interface. Not
driven when CS=1 or RST=0.
D1/
SPI_MOSI
L6
K7
K4
L4
IOz
IOz
D2/
SPI_CLK
D3
D4
L7
—
—
IOz
IOz
Data Bit 4. Bi-directional data bit 4 of the microprocessor interface. Not
driven when CS=1 or RST=0.
K8
Rev: 063008
21 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
PACKAGE PINS
NAME
TYPE
FUNCTION
256
144
Data Bit 5. Bi-directional data bit 5 of the microprocessor interface. Not
driven when CS=1 or RST=0.
SPI_SWAP (SPI_SEL=1). Controls the address and data bit order of the
SPI interface. The R/W and B bit positions do not change.
0 = LSB is transmitted and received first. The resulting bit order is:
R/W, A7, A8, A9, A10, A11, A12, A13,
D5/
SPI_SWAP
L8
J5
IOz
A0, A1, A2, A3, A4, A5, A6, Burst,
D0, D1, D2, D3, D4, D5, D6, D7...
1 = MSB is transmitted and received first. The resulting bit order is:
R/W, A13, A12, A11, A10, A9, A8, A7,
A6, A5, A4, A3, A2, A1, A0, Burst,
D7, D6, D5, D4, D3, D2, D1, D0…
Data Bit 6. Bi-directional data bit 6 of the microprocessor interface. Not
driven when CS=1 or RST=0.
SPI_CPHA (SPI_SEL=1). When in SPI mode, setting this bit to 1 inverts
the phase of the clock signal on SPICK. See Section 2.10 for detailed
timing and functionality information. Default setting is low.
Data Bit 7. Bi-directional data bit 7 of the microprocessor interface. Not
driven when CS=1 or RST=0.
SPI_CPOL (SPI_SEL=1). When in SPI mode, setting this bit to 1 inverts
the clock signal on SPICK. See Section 2.10 for detailed timing and
functionality information. Default setting is low.
Chip Select. This pin must be taken low for read/write operations. When
CS is high, the RD/DS and WR signals are ignored.
Read Data Strobe (Intel Mode). The device drives the data bus with the
contents of the addressed register while RD and CS are both low.
Data Strobe (Motorola Mode). Used to latch data through the
microprocessor interface. DS must be low during read and write
operations.
D6/
SPI_CPHA
K9
K5
IOz
D7/
SPI_CPOL
M9
J8
L5
J3
—
IOz
I
I
CS
RD/DS
J9
Write (Intel Mode). The device captures the contents of the data bus on
the rising edge of WR and writes them to the addressed register location.
CS must be held low during write operations.
Read Write (Motorola Mode). Used to indicate read or write operation.
RW must be set high for a register read cycle and low for a register write
cycle.
WR/RW
J10
—
I
Address Latch Enable. This signal is used to internally latch an address,
allowing multiplexing of the parallel interface address and data lines.
When ALE is high, the values of the A[10:0] pins are used for read/write
operations. On the falling edge of ALE, the values of the A[10:0] pins are
latched internally, and the latched value is used for read/write operations
until the next rising edge of ALE. ALE should be tied high for non-
multiplexed address systems.
ALE
J7
—
—
I
I
Mode. Selects RD/WR or DS strobe mode.
0 = Read/Write Strobe Mode
1 = Data Strobe Mode
MODE
J12
Interrupt Output. Outputs a logic zero when an unmasked interrupt event
is detected. INT is de-asserted when all interrupts have been
acknowledged and serviced. Active low. Inactive state is configured with
the GL.CR2.INTM bit.
J11
J16
G5
—
Oz
I
INT
Parallel/SPI Interface Select
0 = Parallel Interface
SPI_SEL
1 = SPI Interface Selected
Rev: 063008
22 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
PACKAGE PINS
NAME
TYPE
FUNCTION
256
144
GMII/MII/RMII PORT
Transmit Data 0 through 7(GMII Mode). TXD[0:7] is presented
synchronously with the rising edge of TX_CLK1. TXD[0] is the least
significant bit of the data. When TX_EN1 is low the data on TXD should
be ignored.
MAC 1 Transmit Data 0 through 3(MII Mode – TXD1[0:3]). Four bits of
data TXD1[0:3] presented synchronously with the rising edge of
TX_CLK1.
TXD[0]/TXD1[0],
TXD[1]/TXD1[1],
TXD[2]/TXD1[2],
TXD[3]/TXD1[3],
TXD[4]/TXD2[0],
TXD[5]/TXD2[1],
TXD[6]/TXD2[2],
TXD[7]/TXD2[3]
J13,
K15,
J15,
H13,
N15,
P15,
R15,
T15
J8,
J9,
H8,
H9,
L8,
K8,
L9,
K9
MAC 1 Transmit Data 0 through 1(RMII Mode – TXD1[0:1]). Two bits of
data TXD1[0:1] presented synchronously with the rising edge of
TX_CLK1.
O
MAC 2 Transmit Data 0 through 3(MII Mode– TXD2[0:3]).Four bits of
data TXD2[0:3] presented synchronously with the rising edge of
TX_CLK2. Note that TXD2[0:3] is only available on devices with two
Ethernet ports.
MAC 2 Transmit Data 0 through 1(RMII Mode– TXD2[0:1]). Two bits of
data TXD2[0:1] presented synchronously with the rising edge of
TX_CLK2. Note that TXD2[0:1] is only available on devices with two
Ethernet ports.
MAC 1 Receive Data 0 through 7(GMII Mode). Eight bits of received
data, sampled synchronously with the rising edge of RX_CLK. For every
clock cycle, the PHY transfers 8 bits to the device. RXD[0] is the least
significant bit of the data. Data is not considered valid when RX_DV is
low.
RXD[0]/RXD1[0],
RXD[1]/RXD1[1],
RXD[2]/RXD1[2],
RXD[3]/RXD1[3],
RXD[4]/RXD2[0],
RXD[5]/RXD2[1],
RXD[6]/RXD2[2],
RXD[7]/RXD2[3]
G14,
F13,
F14,
H14,
N16,
M16,
L15,
K16
J10,
J11,
H10,
H11,
L10,
L11,
K10,
K11
MAC 1 Receive Data 0 through 3(MII Mode – RXD1[0:3]). Four bits of
received data, sampled synchronously with RX_CLK1. Accepted when
RX_CRS1 is asserted.
I
MAC 1 Receive Data 0 through 1(RMII Mode – RXD1[0:1]). Two bits of
received data, sampled synchronously with RX_CLK1. Accepted when
RX_CRS1 is asserted.
MAC 2 Receive Data 0 through 3(MII Mode – RXD2[0:3]): Four bits of
received data, sampled synchronously with RX_CLK2. Accepted when
RX_CRS2 is asserted.
MAC 2 Receive Data 0 through 1(RMII Mode – RXD2[0:1]). Two bits of
received data, sampled synchronously with RX_CLK2. Accepted when
RX_CRS2 is asserted.
Receive Clock 1 (GMII). 125MHz clock. This clock is used to sample the
RXD[7:0] data.
Receive Clock 1 (MII). Timing reference for RX_DV, RX_ERR and
RXD[3:0], which are clocked on the rising edge. RX_CLK frequency is
25MHz for 100Mbps operation and 2.5MHz for 10Mbps operation. In DTE
mode, this is a clock input provided by the PHY.
Receive Clock 2 (MII Only). Timing reference for RX_DV2, RX_ERR2 and
RXD2[3:0], which are clocked on the rising edge. RX_CLK2 frequency is
25MHz for 100Mbps operation and 2.5MHz for 10Mbps operation. In DTE
mode, this is a clock input provided by the PHY. Note that RX_CLK2 is
only available on devices with two Ethernet ports.
RX_CLK1,
RX_CLK2
G16,
N13
J12
IO
Transmit Clock 1 (MII). Timing reference for TX_EN1 and TXD1[3:0].
The TX_CLK1 frequency is 25MHz for 100Mbps operation and 2.5MHz
for 10Mbps operation. In DTE mode, this is a clock input provided by the
PHY. Sourced from REF_CLK Input.
Transmit Clock 2 (MII Only). Timing reference for TX_EN2 and TXD2[3:0].
The TX_CLK2 frequency is 25MHz for 100Mbps operation and 2.5MHz
for 10Mbps operation. In DTE mode, this is a clock input provided by the
PHY. Note that TX_CLK2 is only available on devices with two Ethernet
ports. Sourced from REF_CLK Input.
TX_CLK1,
TX_CLK2
M15,
T16
L12
IO
Rev: 063008
23 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
PACKAGE PINS
NAME
TYPE
FUNCTION
256
144
Transmit Enable 1(GMII). When this signal is asserted, the data on
TXD[7:0] is valid.
Transmit Enable 1, 2 (MII/RMII). In MII mode, this pin is asserted high
when data TXD[3:0] is being provided by the device. In RMII mode, this
pin is asserted high when data TXD[1:0] is being provided by the device.
The signal is deasserted prior to the first nibble of the next frame. This
signal is synchronous with the rising edge TX_CLK. It is asserted with the
first bit of the preamble.
TX_EN1,
TX_EN2
K14,
P16
F8
O
Note that TX_EN2 is only available on devices with two Ethernet ports.
Unused output pins should not be connected.
Receive Data Valid 1 (GMII). This signal is synchronous to the RX_CLK1
and provides a valid signal for the RXD[7:0].
Receive Data Valid 1, 2 (MII/RMII). This active-high signal indicates valid
data from the PHY. In MII mode the data RXD[3:0] is ignored if RX_DV is
not asserted high. In RMII mode the data RXD[1:0] is ignored if RX_DV is
not asserted high.
RX_DV1,
RX_DV2
G15,
M11
F9
I
I
Note that RX_DV2 is only available on devices with two Ethernet ports.
Receive Carrier Sense 1 (GMII). This signal is asserted (high) when data
is valid from the PHY. This signal is asserted by the PHY when either
transmit or receive medium is active. This signal is not synchronous to
any of the clocks.
Receive Carrier Sense 1, 2 (MII). This signal is asserted by the PHY when
either transmit or receive medium is active. This signal is not synchronous
to any of the clocks.
RX_CRS1,
RX_CRS2
E13,
J14
G12
Note that RX_CRS2 is only available on devices with two Ethernet ports.
Receive Error 1 (GMII). This signal indicates a receive error or a carrier
extension in the GMII Mode.
Receive Error 1, 2 (MII). Asserted by the MAC PHY for one or more
RX_CLK periods indicating that an error has occurred. Active High
indicates Receive code group is invalid. If RX_CRS is low, RX_ERR has
no effect. This is synchronous with RX_CLK. In DCE mode, this signal
must be grounded.
RX_ERR1,
RX_ERR2
H15,
M12
G9
I
Note that RX_ERR2 is only available on devices with two Ethernet ports.
Transmit Error 1(GMII). When this signal is asserted, the PHY will
respond by sending one or more code groups in error.
Transmit Error 1, 2(GMII, MII). When this signal is asserted, the PHY will
respond by sending one or more code groups in error.
TX_ERR1,
TX_ERR2
L14,
R16
G8
O
Note that TX_ERR2 is only available on devices with two Ethernet ports.
Collision Detect 1, 2 (MII). Asserted by the Ethernet PHY to indicate that
a collision is occurring. In DCE Mode this signal should be connected to
ground. This signal is only valid in half duplex mode, and is ignored in full
duplex mode.
COL1,
COL2
E14,
L16
G10
I
Note that COL2 is only available on devices with two Ethernet ports.
DCE or DTE Selection (MII). Setting this pin high places all Ethernet
ports in DCE Mode. Setting this pin low places the Ethernet ports in DTE
Mode.
In DCE Mode, the MII interface can be directly connected to another
MAC. In DCE Mode, the Transmit clock (TX_CLK) and Receive clock
(RX_CLK) are outputs.
DCEDTES
P13
M14
L7
I
I
Note that there is no software bit selection of DCEDTES. Note that DCE
operation is only valid for 10/100, MII mode.
RMII Selection Input. Set this pin to 1 for RMII operation. In devices with
2 Ethernet ports, both ports will operate in RMII mode. REF_CLK must be
50MHz. Set this pin to 0 for GMII or MII operation.
RMII_SEL
K7
Rev: 063008
24 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
PACKAGE PINS
NAME
TYPE
FUNCTION
256
144
Reference Clock Input. REF_CLK must be 125MHz for GMII operation.
REF_CLK must be 25MHz for MII DCE operation. REF_CLK must be
50MHz for RMII operation.
REF_CLK
GTX_CLK
T13
M8
I
GbE Transmit Clock Output (GMII). 125MHz clock output available for
GMII operation. This clock is sourced from the 125MHz REF_CLK input.
R14
F15
M10
H5
O
PHY MANAGEMENT BUS
Management Data Clock. Clocks management data to and from the PHY.
The clock is derived from SYSCLKI, with a maximum frequency is
1.67MHz.
O
MDC
MII Management Data IO. Data path for control information between the
device and the PHY. Pull to logic high externally through a 1.5 kΩ resistor.
The MDC and MDIO pins are used to write or read up to 32 Control and
Status Registers in PHY Controllers. This port can also be used to initiate
Auto-Negotiation for the PHY.
MDIO
G13
H4
IO
SDRAM CONTROLLER
SDATA[0]
SDATA[1]
SDATA[2]
SDATA[3]
SDATA[4]
SDATA[5]
SDATA[6]
SDATA[7]
SDATA[8]
SDATA[9]
SDATA[10]
SDATA[11]
SDATA[12]
SDATA[13]
SDATA[14]
SDATA[15]
SDA[0]
C16
B16
B15
C15
A14
C12
A13
B13
D9
A11
B11
D11
C11
A10
B10
D10
C10
C8
D8
B8
SDRAM Data Bus Bits 0 through 15. The 16 pins of the SDRAM data
bus are inputs for read operations and outputs for write operations. At all
other times, these pins are high impedance.
IOz
C9
D12
C10
B10
B11
C11
B12
C3
E9
C9
D9
B9
A9
A3
SDA[1]
C2
D2
B2
SDA[2]
B2
SDA[3]
A2
D1
C1
E1
SDA[4]
D3
SDRAM Address Bus 0 through 12. The 13 pins of the SDRAM address
bus output the row address first, followed by the column address. The row
address is determined by SDA[0] to SDA[12] at the rising edge of clock.
Column address is determined by SDA[0]-SDA[9] and SDA[11] at the
rising edge of the clock. SDA[10] is used as an auto-precharge signal.
SDA[5]
D4
O
SDA[6]
B5
C2
E2
SDA[7]
C5
SDA[8]
D5
B3
SDA[9]
B6
A4
SDA[10]
SDA[11]
SDA[12]
A3
C3
B4
C6
A5
D3
SBA[0],
SBA[1]
SDRAM Bank Select. These 2 bits select 1 of 4 banks for the
read/write/precharge operations.
B4, B3 D4, C4
I
SDRAM Chip Select.All commands are masked when SDCS is registered
high. SDCS provides for external bank selection on systems with multiple
banks. SDCS is considered part of the command code.
A4 A5
O
SDCS
Rev: 063008
25 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
PACKAGE PINS
NAME
TYPE
FUNCTION
256
144
SDRAM Row Address Strobe. Active-low output, used to latch the row
address on rising edge of SD_CLK. It is used with commands for Bank
Activate, Precharge, and Mode Register Write.
A6
B5
O
SRAS
SDRAM Column Address Strobe. Active low output, used to latch the
column address on the rising edge of SD_CLK. It is used with commands
for Bank Activate, Precharge, and Mode Register Write.
B7
A7
D7
D5
C5
E7
O
O
O
SCAS
SWE
SDRAM Write Enable. This active low output enables write operation and
auto precharge.
SDRAM Upper Data Mask. SD_UDM is an active high output mask
signal for write data. SD_UDM is updated on both edges of SD_UDQS.
SD_UDM corresponds to data on SDATA15-SDATA8.
SD_UDM
SDRAM Lower Data Mask. SD_LDM is an active high output mask signal
for write data. SD_LDM is updated on both edges of SD_LDQS. SD_LDM
corresponds to data on SDATA7-SDATA0.
SD_LDM
D13
E6
O
Lower Data Strobe. Output with write data, input with read data.
SD_LDQS corresponds to data on SDATA7-SDATA0.
SD_LDQS
SD_UDQS
C13
D8
E8
D7
IOz
IOz
Upper Data Strobe. Output with write data, input with read data.
SD_UDQS corresponds to data on SDATA15-SDATA8.
SDRAM Clock. SD_CLK and SD_CLK are differential clock outputs. All
address and control input signals are sampled on the crossing of the
positive edge of SD_CLK and negative edge of SD_CLK. Output (write)
data is referenced to the crossings of SD_CLK and SD_CLK (both
directions of crossing).
SD_CLK
A8
A8
O
SDRAM Clock (Inverted). SD_CLK and SD_CLK are differential clock
outputs. All address and control input signals are sampled on the crossing
of the positive edge of SD_CLK and negative edge of SD_CLK. Output
(write) data is referenced to the crossings of SD_CLK and SD_CLK (both
directions of crossing).
A9
C4
A7
E5
O
O
SD_CLK
SDRAM Clock Enable. Active High. SD_CLKEN must be active
throughout DDR SDRAM READ and WRITE accesses.
SD_CLKEN
SERIAL INTERFACE IO PINS
TDATA1
TDATA2
TDATA3
TDATA4
TDATA5
TDATA6
TDATA7
TDATA8
TDATA9
TDATA10
TDATA11
TDATA12
TDATA13
TDATA14
TDATA15
TDATA16
T6
T7
L3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P6
N9
M5
N6
Transmit Serial Data Output. Output on the rising edge of TCLK. The
maximum data rate is 52Mbps.
N7
R9
Not all serial port signals are available on all products in the device family.
Unused output pins should not be connected.
O
N10
R11
N11
R12
P14
P12
N12
P11
DS33X41/X42/W41/W11: TDATA5 – TDATA16 not used.
DS33X81/X82: TDATA9 – TDATA16 not used.
Serial Interface Transmit Clock Input (TCLK[1:8]).The clock reference
for TDATA, which is output on the rising edge of the clock. TCLK supports
gapped clocking, up to a maximum frequency of 52MHz.
I
TCLK1/TMCLK1
TCLK2
R5
P5
R8
P9
M3
—
—
—
TCLK3
Note that TCLK1 is also TMCLK1, TCLK5 is also TMCLK2. TMCLK3
and TMCLK4 are stand-alone pins.
TCLK4
Rev: 063008
26 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
PACKAGE PINS
NAME
TYPE
FUNCTION
256
M7
144
—
—
—
—
—
—
TCLK5/TMCLK2
TCLK6
Transmit Master Clock (TMCLK[1:4]). Input clock that TDATA is
referenced to. This clock may be gapped. Maximum clock speed is
52MHz. This clock can be inverted.
P10
T10
R10
T11
M10
TCLK7
Not all serial port signals are available on all products in the device family.
Unused input pins should be tied to VSS.
TCLK8
TMCLK3
TMCLK4
DS33X41/X42/W41/W11: TCLK5 – TCLK8 not used.
TSYNC1/
TMSYNC1
R6
T8
M4
—
—
—
—
—
—
—
—
—
TSYNC2
TSYNC3
TSYNC4
Transmit Synchronization Input (TSYNC[1:8]). Input that indicates
frame boundaries on TDATA, referenced to TCLK. This signal may be a
frame or multiframe sync. It must be a multiframe sync for VCAT
applications. Data is octet aligned to this signal.
M6
P7
Note that TSYNC1 is also TMSYNC1, TSYNC5 is also TMSYNC2.
TMSYNC3 and TMSYNC4 are stand-alone pins.
TSYNC5/
TMSYNC2
R7
P8
I
Transmit Master Sync (TMSYNC[1:4]). This input indicates frame
boundaries on TDATA if selected via LI.TCR.TD_SEL, referenced to
TMCLK1.
TSYNC6
TSYNC7
N8
T9
Not all serial port signals are available on all products in the device family.
Unused input pins should be tied to VSS.
TSYNC8
DS33X41/X42/W41/W11: TSYNC5 – TTSYNC8 not used.
TMSYNC3
TMSYNC4
T12
N14
RDATA1
RDATA2
RDATA3
RDATA4
RDATA5
RDATA6
RDATA7
RDATA8
RDATA9
RDATA10
RDATA11
RDATA12
RDATA13
RDATA14
RDATA15
RDATA16
D1
G8
G4
H2
F3
F2
K1
L1
K2
K3
N1
L4
J2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Serial Data Input (RDATA[1:16]). Receive Serial data from a
T1/E1/T3/E3/xDSL Framer. Data input on the rising edge of RCLK.
Not all serial port signals are available on all products in the device family.
Unused input pins should be tied to VSS.
I
DS33X41/X42/W41/W11: RDATA5 – RDATA16 not used.
DS33X81/X82: RDATA9 – RDATA16 not used.
P2
R1
N3
N4
Rev: 063008
27 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
PACKAGE PINS
NAME
TYPE
FUNCTION
256
144
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
RCLK9
E1
G7
G1
H4
F4
J1
J5
J4
J3
J2
G1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
J1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Serial Interface Receive Clock Input (RCLK[1:16]). Reference clock for
receive serial data on RDATA. Gapped clocking is supported, up to the
maximum RCLK frequency of 52MHz.
I
Not all serial port signals are available on all products in the device family.
Unused input pins should be tied to VSS.
RCLK10
RCLK11
RCLK12
RCLK13
RCLK14
RCLK15
RCLK16
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSYNC5
RSYNC6
RSYNC7
RSYNC8
RSYNC9
RSYNC10
RSYNC11
RSYNC12
RSYNC13
RSYNC14
RSYNC15
RSYNC16
DS33X41/X42/W41/W11: RCLK5 – RCLK16 not used.
DS33X81/X82: RCLK9 – RCLK16 not used.
M2
N2
L5
T1
T4
R3
F1
H7
G2
H1
G3
H3
N5
L2
K4
M1
L3
P1
M4
R2
P3
T3
Receive Frame/Multiframe Synchronization Input (RSYNC[1:16]).
Receive Sync that indicates frame boundaries or multiframe boundaries
for T1/E1/T3/E3 signals present on RDATA. It must be a multiframe sync
for VCAT applications.
I
Not all serial port signals are available on all products in the device family.
Unused input pins should be tied to VSS.
DS33X41/X42/W41/W11: RSYNC5 – RSYNC16 not used.
DS33X81/X82: RSYNC9 – RSYNC16 not used.
VOICE INTERFACE IO PINS - DS33W41 AND DS33W11 ONLY
Transmit Voice Data Input. Input voice data stream containing multiple
TVDATA
TVCLK
M5
M7
—
I
DS0s. Referenced to TVCLK. Disabled when TVDEN is high. This signal
is only available on the DS33W41 and DS33W11.
Transmit Voice Clock Input. Input clock that times TVDATA. May be
gapped. Maximum clock speed 52MHz. This signal is only available on
the DS33W41 and DS33W11.
—
I
Transmit Voice Synchronization Input. Input signal that indicates frame
boundaries on voice data stream (TVDATA), sampled by TVCLK,
frequency of 8 kHz. This signal is only available on the DS33W41 and
DS33W11.
Transmit Voice Data Enable. May be used in place of a gapped TVCLK.
If low, TVDATA is valid. If a gapped TVCLK is used and this signal is not
used, tie this input low. This signal is only available on the DS33W41 and
DS33W11.
TVSYNC
R7
N6
—
—
I
I
TVDEN
Receive Voice Data Output. Outputs voice data stream from internal
FIFO using RVCLK. Maximum DS0s is dependent on WAN data rate (T1
max is 24, E1 is 31). This is a tri-state output, high impedance when
RVDEN is high. This signal is only available on the DS33W41 and
DS33W11.
Receive Voice Clock Input. Receive clock that times RVDATA signal.
May be gapped. Maximum clock speed 52MHz. This signal is only
available on the DS33W41 and DS33W11.
RVDATA
F2
F3
—
—
O
I
RVCLK
Rev: 063008
28 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
PACKAGE PINS
NAME
TYPE
FUNCTION
256
144
Receive Voice Synchronization Input. Receive sync that indicates
frame boundaries present on RVDATA – referenced to RVCLK, frequency
of 8 kHz. This signal is only available on the DS33W41 and DS33W11.
Receive Voice Data Enable: May be used in place of a gapped RVCLK.
If low, RVDATA is valid. If gapped RVCLK is used and this signal is not
used, tie this input low. This signal is only available on the DS33W41 and
DS33W11.
RVSYNC
F4
—
I
G3
—
I
RVDEN
HARDWARE AND STATUS PINS
High-Impedance Test Enable (Active Low). This signal puts all digital
output and bi-directional pins in the high impedance state when it is low
and JTRST is low. For normal operation tie high. This is an asynchronous
input.
H16
E8
F10
F2
I
I
HIZ
Reset (Active Low). An active low signal on this pin resets the internal
registers and logic. While this pin is held low, the microprocessor interface
is kept in a high-impedance state. This pin should remain low until power
is stable and then set high for normal operation.
RST
SYSTEM CLOCKS
SYSCLKI
E16
B1
E12
G4
I
System Clock In: 125MHz, ±100ppm System Clock input.
JTAG INTERFACE
JTAG Reset (Active Low). JTRST is used to asynchronously reset the
test access port controller. After power-up, a rising edge on JTRST will
reset the test port and cause the device I/O to enter the JTAG DEVICE ID
mode. Pulling JTRST low restores normal device operation. JTRST is
pulled HIGH internally via a 10kΩ resistor operation. If boundary scan is
not used, this pin should be held low.
Ipu
JTRST
JTAG Clock. This signal is used to shift data into JTDI on the rising edge
and out of JTDO on the falling edge.
JTCLK
JTDO
JTDI
A1
E2
D2
G3
H2
H3
Ipu
Oz
Ipu
JTAG Data Out. Test instructions and data are clocked out of this pin on
the falling edge of JTCLK. If not used, this pin should be left unconnected.
JTAG Data In. Test instructions and data are clocked into this pin on the
rising edge of JTCLK. This pin has a 10kΩ pullup resistor.
JTAG Mode Select. This pin is sampled on the rising edge of JTCLK and
is used to place the test access port into the various defined IEEE 1149.1
states. This pin has a 10kΩ pullup resistor.
JTMS
C1
G2
Ipu
POWER SUPPLIES
E10,
E12,
E9, F7,
G5,
K5,
M8,
F3,
F11,
H1,
H6,
H7,
K12,
M2,
M7
VDD3.3
I
Connect to 3.3V Power Supply
P4,
T14
D11,
E3, E4,
F12,
G12,
H11,
H12,
M3,
F1,
G6,
G7,
H12,
L1,
VDD1.8
I
Connect to 1.8V Power Supply
M5,
M11
R13
Rev: 063008
29 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
PACKAGE PINS
NAME
TYPE
FUNCTION
256
144
A10,
C7, F6,
F8, F9, F6, F7,
F10,
F11,
F16,
G6,
G9,
H5,
F12,
G11,
J6, J7,
K1, K2,
K6, L6,
M1,
Ground Connection for 3.3V and 1.8V Supplies. Connect to the
common supply ground.
VSS
I
H9,
M6,
H10,
M13,
R4,
M9,
M12
T5
AVDD
AVSS
F5
D12
C12
I
I
Analog PLL Power. Connect to a 1.8V power supply.
Analog PLL Ground
E11
B8, E5,
E7
VDD2.5
B1, C6
I
SDRAM Digital Power. Connect to a 2.5V power supply.
A11,
A12,
A15,
A16,
C14,
D10,
D14
B14,
C8,
A2,
B12,
C7,
E4,
E10
VDDQ
I
SDRAM Digital DQ Power. Connect to a 2.5V (±0.2V) .
A1, A6,
A12,
D6,
VSSQ
D15,
D16,
E15,
E6
B6, B7,
E3,
E11
I
SDRAM Digital Ground.
SDRAM SSTL_2 Reference Voltage for SDRAM. Must equal one-half
VDDQ. Can be derived from a resistor-divider.
VREF
DNC
B9
D6
I
H6,
H8, J6,
T2
F4, F5,
K3, L2
—
Do Not Connect. Do not connect these pins.
Notes:
I = Input
Oz = Output, with tri-state
O = Output
IO = Bi-directional pin
Ipu = Input, with pullup
IOz = Bi-directional pin, with tri-state
Rev: 063008
30 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 7-1. 256-Ball, 17mm x 17mm CSBGA Pinout (DS33X162/X161/X82/X81/X42/X41)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
F
JTCLK
SDA[3]
SDA[10]
SDCS
SDA[12]
SRAS
SWE
SD_CLK SD_CLK
VSS
VDDQ
VDDQ
SDATA[6] SDATA[4]
VDDQ
VDDQ
JTRST
JTMS
SDA[2]
SDA[1]
JTDI
SBA[1]
SDA[0]
SDA[4]
VDD1.8
SBA[0]
SDA[6]
SDA[7]
SDA[8]
VDD2.5
AVDD
SDA[9]
SDA[11]
VSSQ
VSSQ
VSS
SCAS
VSS
VDD2.5
VSSQ
VREF SDATA[12] SDATA[13] SDATA[15] SDATA[7]
SDATA[9] SDATA[11] SDATA[14] SDATA[5] SD_LDQS
VSSQ
VDDQ
VDDQ
COL1
SDATA[2] SDATA[1]
SDATA[3] SDATA[0]
SD_CLKE
N
RDATA1
RCLK1
SDA[5]
VDD1.8
RCLK5
SD_UDM SD_UDQS SDATA[8]
VDDQ
VDD3.3
VSS
VDD1.8 SDATA[10] SD_LDM
VSSQ
VSSQ
MDC
VSSQ
SYSCLKI
VSS
JTDO
VDD2.5
VDD3.3
RCLK2
RST
VSS
VDD3.3
VSS
AVSS
VSS
A10
VDD3.3 RX_CRS1
RXD[1] /
VDD1.8
RXD[2] /
RXD1[2]
RSYNC1 RDATA6 RDATA5
RXD1[1]
RXD[0] /
RXD1[0]
G
H
J
RCLK3
RSYNC3 RSYNC5 RDATA3
VDD3.3
VSS
VSS
RDATA2
DNC
CS
VSS
A8
VDD1.8
VDD1.8
MODE
A6
MDIO
RX_DV1 RX_CLK1
TXD[3] /
TXD1[3]
RXD[3] /
RXD1[3]
RSYNC4 RDATA4 RSYNC6
RCLK4
RCLK8
DNC
RSYNC2
VSS
VSS
VDD1.8
INT
RX_ERR1
HIZ
TXD[0] /
TXD1[0]
TXD[2] /
TXD1[2]
RCLK6
RCLK10
RCLK9
RCLK7
VDD3.3
DNC
D0 /
ALE
D2 /
RD / DS
WR / RW
A0
RX_CRS2
TX_EN1
SPI_SEL
D6 /
SPI_CPHA
TXD[1] /
TXD1[1]
RXD[7] /
RXD2[3]
K
L
RDATA7 RDATA9 RDATA10 RSYNC9
D4
A2
A4
A9
SPI_MISO SPI_CLK
D1 /
D3
D5 /SPI_
SWAP
RXD[6] /
RXD2[2]
RDATA8 RSYNC8 RSYNC11 RDATA12 RCLK13
RSYNC10 RCLK11
A1
A3
A5
A7
TX_ERR1
COL2
SPI_MOSI
D7 /
SPI_CPOL
RXD[5] /
RXD2[1]
M
N
P
R
T
VDD1.8 RSYNC13 TDATA5 TSYNC3
TCLK5
VDD3.3
TMCLK4 RX_DV2 RX_ERR2
VSS
RMII_SEL TX_CLK1
TXD[4] /
RXD[4] /
RXD2[0]
RDATA11 RCLK12 RDATA15 RDATA16 RSYNC7 TDATA6 TDATA7 TSYNC7 TDATA4 TDATA9 TDATA11 TDATA15 RX_CLK2 TMSYNC4
TXD2[0]
TXD[5] /
TXD2[1]
RSYNC12 RDATA13 RSYNC15 VDD3.3
TCLK2
TCLK1
VSS
TDATA3 TSYNC4 TSYNC6
TCLK4
TCLK6
TCLK8
TCLK7
TDATA16 TDATA14 DCEDTES TDATA13
TDATA10 TDATA12 VDD1.8 GTX_CLK
TMCLK3 TMSYNC3 REF_CLK VDD3.3
TX_EN2
TX_ERR2
TX_CLK2
TXD[6] /
TXD2[2]
RDATA14 RSYNC14 RCLK16
VSS
TSYNC1 TSYNC5
TCLK3
TDATA8
TXD[7] /
TXD2[3]
RCLK14
DNC
RSYNC16 RCLK15
TDATA1 TDATA2 TSYNC2 TSYNC8
Note: Shaded pins do not apply to all devices in the product family. See the pin listing for specific pin availability. In the high port
count devices, the shaded input pins DO NOT HAVE PULLUP/PUL-DOWN resistors. Consideration must be taken during board
design to bias the inputs appropriately, and to float output pins (TDATA5-TDATA16, TX_EN2, TX_ERR2) if lower port count
designs are to be potentially stuffed with higher port count devices.
Rev: 063008
31 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 7-2. 256-Ball, 17mm x 17mm CSBGA Pinout (DS33W41/DS33W11)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
F
JTCLK
SDA[3]
SDA[10]
SDCS
SDA[12]
SRAS
SWE
SD_CLK SD_CLK
VSS
VDDQ
VDDQ
SDATA[6] SDATA[4]
VDDQ
VDDQ
JTRST
JTMS
SDA[2]
SDA[1]
JTDI
SBA[1]
SDA[0]
SDA[4]
VDD1.8
RVCLK
RVDEN
SBA[0]
SDA[6]
SDA[7]
SDA[8]
VDD2.5
AVDD
SDA[9]
SDA[11]
VSSQ
VSSQ
VSS
SCAS
VSS
VDD2.5
VSSQ
VREF SDATA[12] SDATA[13] SDATA[15] SDATA[7]
SDATA[9] SDATA[11] SDATA[14] SDATA[5] SD_LDQS
VSSQ
VDDQ
VDDQ
COL1
SDATA[2] SDATA[1]
SDATA[3] SDATA[0]
SD_CLKE
N
RDATA1
RCLK1
SDA[5]
VDD1.8
RVSYNC
RDATA3
RCLK4
SD_UDM SD_UDQS SDATA[8]
VDDQ
VDD3.3
VSS
VDD1.8 SDATA[10] SD_LDM
VSSQ
VSSQ
MDC
VSSQ
SYSCLKI
VSS
JTDO
VDD2.5
VDD3.3
RCLK2
RST
VSS
VDD3.3
VSS
AVSS
VSS
A10
VDD3.3 RX_CRS1
RXD[1] /
VDD1.8
RXD[2] /
RXD1[2]
RSYNC1 RVDATA
RXD1[1]
RXD[0] /
RXD1[0]
G
H
J
RCLK3
RSYNC3
VDD3.3
VSS
VSS
RDATA2
DNC
CS
VSS
A8
VDD1.8
VDD1.8
MODE
A6
MDIO
RX_DV1 RX_CLK1
TXD[3] /
TXD1[3]
RXD[3] /
RXD1[3]
RSYNC4 RDATA4
DNC
RSYNC2
VSS
VSS
VDD1.8
INT
RX_ERR1
HIZ
TXD[0] /
TXD1[0]
TXD[2] /
TXD1[2]
DNC
D0 /
ALE
D2 /
RD / DS
WR / RW
A0
SPI_SEL
D6 /
SPI_CPHA
TXD[1] /
TXD1[1]
RXD[7] /
RXD2[3]
K
L
VDD3.3
D4
A2
A4
A9
TX_EN1
SPI_MISO SPI_CLK
D1 /
D3
D5 /SPI_
SWAP
RXD[6] /
RXD2[2]
A1
A3
A5
A7
TX_ERR1
SPI_MOSI
D7 /
SPI_CPOL
RXD[5] /
RXD2[1]
M
N
P
R
T
VDD1.8
TVDATA TSYNC3
TVDEN
TVCLK
VDD3.3
VSS
RMII_SEL TX_CLK1
TXD[4] /
TXD2[0]
RXD[4] /
RXD2[0]
TDATA4
TCLK4
TXD[5] /
TXD2[1]
VDD3.3
VSS
TCLK2
TCLK1
VSS
TDATA3 TSYNC4
TSYNC1 TVSYNC
DCEDTES
TXD[6] /
TXD2[2]
TCLK3
VDD1.8 GTX_CLK
REF_CLK VDD3.3
TXD[7] /
TXD2[3]
DNC
RCLK15
TDATA1 TDATA2 TSYNC2
Note 1: Shaded pins do not apply to all devices in the product family. See the pin listing for specific pin availability.
Note 2: The TVDEN pin is an input on the DS33W41/DS33W11, and is an output pin on other devices in the product family.
Rev: 063008
32 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 7-3. 144-Ball, 10mm x 10mm, CSBGA Pinout (DS33X11)
1
2
3
4
5
6
7
8
9
10
11
12
VSS
VDDQ
SDA[0]
SDA[9]
SDCS
VSS
SD_CLK
SD_CLK
SDATA[15]
SDATA[4]
SDATA[0]
VSS
A
B
C
D
E
F
VDD2.5
SDA[4]
SDA[3]
SDA[5]
VDD1.8
RCLK1
VDD3.3
RSYNC1
VSS
SDA[2]
SDA[6]
SDA[1]
SDA[7]
RST
SDA[8]
SDA[10]
SDA[12]
VSS
SDA[11]
SBA[1]
SRAS
SWE
VSS
VDD2.5
VREF
SD_LDM
VSS
VSS
VDDQ
SDATA[10]
SDATA[8]
SDATA[9]
SD_LDQS
TX_EN1
TX_ERR1
TXD[2]
SDATA[14]
SDATA[12]
SDATA[13]
SDATA[11]
RX_DV1
RX_ERR1
TXD[3]
SDATA[5]
SDATA[7]
SDATA[6]
VDDQ
SDATA[1]
SDATA[3]
SDATA[2]
VSS
VDDQ
AVSS
SBA[0]
SCAS
SD_UDQS
SD_UDM
VSS
AVDD
VDDQ
SD_CLKEN
DNC
SYSCLKI
VSS
VDD3.3
JTCLK
JTDI
DNC
HIZ
VDD3.3
VSS
JTMS
JTRST
INT
VDD1.8
VDD3.3
VSS
VDD1.8
VDD3.3
VSS
COL1
RX_CRS1
VDD1.8
RX_CLK1
VDD3.3
TX_CLK1
VSS
G
H
J
JTDO
MDIO
MDC
RXD[2]
RXD[0]
RXD[6]
RXD[4]
GTX_CLK
RXD[3]
RXD[1]
RXD[7]
RXD[5]
VDD1.8
RDATA1
VSS
CS
SPI_MISO
SPI_MOSI
SPI_CLK
TSYNC1
SPI_SWAP
SPI_CPHA
SPI_CPOL
VDD1.8
TXD[0]
TXD[1]
DNC
VSS
RMII_SEL
DCEDTES
VDD3.3
TXD[5]
TXD[7]
K
L
VDD1.8
VSS
DNC
TDATA1
TCLK1
VSS
TXD[4]
TXD[6]
VDD3.3
VSS
REF_CLK
VSS
M
Note that the parallel bus is not available in the 144-pin DS33X11, and the SPI slave port must be used for processor control.
Rev: 063008
33 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
8.
Functional Description
The DS33X162 family of devices provide interconnection and mapping functionality between Ethernet Systems and
WAN Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, T3/E3, and SONET/SDH. The device is
composed of up to two 10/100/1000 Ethernet MACs, up to 16 Serial Ports, a Arbiter, GFP/HDLC/cHDLC/X.86
(LAPS) Mappers, a DDR SDRAM interface, and control ports.
Ethernet traffic is encapsulated with GFP-F, HDLC, cHDLC, or X.86 (LAPS) to be transmitted over the WAN Serial
Interfaces. The WAN Serial Interfaces also receive encapsulated Ethernet frames and transmit the extracted
frames over the Ethernet ports.
The LAN interface consists of Ethernet MACs using one of two physical layer protocols. The interface can be
configured with up to two 10/100Mbps MII/RMII ports or a single GbE GMII port. The MII/RMII and GMII interfaces
allow connection to commercially available Ethernet PHY and MAC devices.
The WAN physical interface supports 8 serial data streams up to 52Mbps each. The DS33X162 and DS33X161
support an additional 8 serial data streams with data rates up to 2.5Mbps each. The WAN serial interfaces receive
encapsulated Ethernet frames and transmit the extracted frames over the Ethernet ports. The WAN serial ports can
operate with a gapped clock, and can be connected to a framer, electrical LIU, optical transceiver, or T/E-Carrier
transceiver for transmission to the WAN. The Serial Interfaces can be seamlessly connected to the Maxim
T1/E1/J1 Framers, Line Interface Units (LIUs), and Single-Chip Transceivers (SCTs). The WAN interfaces can also
be seamlessly connected to the Maxim T3/E3/STS-1 Framers, LIUs, and SCTs to provide T3, E3, and STS1
connectivity.
Ethernet frames are queued and stored in an external 32-bit DDR SDRAM. The DDR SDRAM controller enables
connection to a 256Mb SDRAM without external glue logic, at clock frequencies up to 125MHz. The SDRAM is
used for the LAN Data, WAN Data, Frame Extraction, and Frame Insertion Queues. The user can program a “near
full threshold” (watermark) for the LAN and WAN queues that can be used to initiate automatic flow control. The
device also provides the capability for X43 +1 payload and Barker sequence scrambling.
Microprocessor control can be accomplished through a 8-bit Micro controller port or SPI Bus. The device has a
125MHz DDR SDRAM controller and interfaces to a 32-bit wide 256Mb DDR SDRAM via a 16-bit data bus. The
DDR SDRAM is used to buffer data from the Ethernet and WAN ports for transport.
The power supplies consist of a 1.8V core supply, a 2.5V DDR SDRAM supply, and 3.3V I/O supply.
Rev: 063008
34 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
8.1
Parallel Processor Interface
Configuration and control can be accomplished through the 8-bit parallel microprocessor port. The device’s 16-bit
registers are accessed as sequential byte addresses. The 8-bit parallel data bus can be configured for Intel or
Motorola modes of operation. The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation
with the MODE pin. When MODE = 0, bus timing is in Intel mode, as shown in Figure 12-13 and Figure 12-14.
When MODE = 1, bus timing is in Motorola mode, as shown in Figure 12-15 and Figure 12-16. The address space
is mapped through the use of 11 address lines, A0-A10. An address latch enable [ALE] pin is provided to allow for
multiplexing of the data and address signals. Note that the parallel bus is not available in the 144 pin DS33X11,
and the SPI Slave port must be used for processor control.
The Chip Select (CS) pin must be brought to a logic low level to gain read and write access to the microprocessor
port. With Intel timing selected, the Read (RD) and Write (WR) pins are used to indicate read and write operations
and latch data through the interface. With Motorola timing selected, the Read-Write (RW) pin is used to indicate
read and write operations while the Data Strobe (DS) pin is used to latch data through the interface.
The interrupt output pin (INT) is an open-drain output that will assert a logic-low level upon a number of software
maskable interrupt conditions. The inactive state of this pin can be configured with the GL.CR2.INTM bit. This pin is
normally connected to the microprocessor interrupt input. The register map is shown in Table 10-1 on Page 105.
8.1.1 Read-Write/Data Strobe Modes
The processor interface can operate in either read-write strobe mode or data strobe mode. When MODE = 0 the
read-write strobe mode is enabled and a negative pulse on RD performs a read cycle, and a negative pulse on WR
performs a write cycle. When MODE pin = 1, the data strobe mode is enabled and a negative pulse on DS when
RW is high performs a read cycle, and a negative pulse on DS when RW is low performs a write cycle. The read-
write strobe mode is commonly called the “Intel” mode, and the data strobe mode is commonly called the
“Motorola” mode.
8.1.2 Clear on Read
The latched status registers will clear on a read access. It is important to note that in a multi-task software
environment, the user should handle all status conditions of each register at the same time to avoid inadvertently
clearing status conditions. The latched status register bits are carefully designed so that an event occurrence
cannot collide with a user read access.
8.1.3 Interrupt and Pin Modes
The interrupt (INT) pin is configurable to drive high or float when not active. The GL.CR2.INTM bit controls the pin
configuration, when it is set to 1, the INT pin will drive high when inactive. After reset, the INT pin is in high
impedance mode until an interrupt source is active and enabled to drive the interrupt pin.
8.1.4 Multiplexed Bus Operation
An address latch enable [ALE] pin is provided to allow for multiplexing of the data and address signals. For
multiplexed operation, each of the eight data lines (D0-D7) must be externally connected to each of the lower eight
address lines (A0-A7). The remaining address lines (A8-A10) are connected as normal. Address inputs are latched
upon the falling edge of the ALE signal. ALE must remain low until the read or write operation is complete.
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8.2
SPI Serial Processor Interface
The SPI interface is a four-signal serial interface that allows configuration and monitoring of the device with a
minimal number of electrical connections. The SPI interface uses Full-Duplex SPI Slave operation. The maximum
clock frequency of the SPI interface is 10MHz. Each access (read or write) takes approximately 2.4μs. With two
Address/Control bytes required for each data byte, the maximum data throughput rate is approximately 3.3
megabits per second. See the Section 11.1 for functional timing diagrams, and Section 12 for AC parametric
timing. Note that the parallel bus is not available in the 144-pin DS33X11, and the SPI Slave port must be used for
processor control.
The SPI bus is implemented using four signals: Clock (SPI_CLK), Master-Out Slave-In data (SPI_MOSI), Master-In
Slave-Out data (SPI_MISO), and Chip Select (CS). SPI_CLK polarity and phase can be set by the SPI_CPOL and
SPI_CPHA pins. The order of the address and data bits in the serial stream is selectable using the SPI_SWAP pin.
The Read/Write (R/W) bit is always the first bit and the Burst (B) bit is always last bit of the Address/Control Bytes
and their location is not affected by the SPI_SWAP pin setting.
Note that SPI “Burst mode” is not applicable for OAM frame insertion or extraction, due to the indirect access of the
extract and insert queues. The interface overhead associated with frame insertion and extraction is 5 register
accesses per frame.
The SPI protocol defines four combinations of SCK phase and polarity with respect to the data controlled by CPOL
(clock polarity) and CPHA (clock phase):
SPI_CPOL SPI_CPHA
Transfer
SPI_CLK rising-edge transfer.
SPI_CLK transitions in middle of bit timing.
0
1
0
1
0
0
1
1
SPI_CLK falling-edge transfer.
SPI_CLK transitions in middle of bit timing.
SPI_CLK falling-edge transfer.
SPI_CLK transitions at beginning of bit timing.
SPI_CLK rising-edge transfer.
SPI_CLK transitions at beginning of bit timing.
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8.3
Clock Structure
The clock sources and functions are as follows:
•
•
•
•
Serial Transmit Data (TCLKn) and Serial Receive Data (RCLKn) clock inputs are used to transfer data from
the serial interface. These clocks can be continuous or gapped.
The Serial Transmit Clock for ports 9-12 is a shared clock (TMCLK3). The Serial Transmit Sync for ports 9-
12 is also shared (TMSYNC3).
The Serial Transmit Clock for ports 13-16 is a shared clock (TMCLK4). The Serial Transmit Sync for ports
13-16 is also shared (TMSYNC4).
System Clock (SYSCLKI) input. Used for internal operation. This clock input cannot be a gapped clock. A
clock supply with +/- 100 ppm frequency accuracy is suggested. A buffered version of this clock is provided
on the SD_CLK pin for the operation of the SDRAM.
•
•
The Transmit and Receive clocks for the MII/RMII Interface (TX_CLK and RX_CLK). In DTE mode, these
are input pins and accept clocks provided by an Ethernet PHY.
A Management Data Clock (MDC) output is derived from SYSCLKI and is used for information transfer
between the internal Ethernet MAC and external PHY. The MDC clock frequency is 1.67MHz.
The device expects gapped clocks for T3/E3/T1/E1 data streams, minimally gapped for line overhead periods
The following table provides the different clocking options for the Ethernet interface.
Table 8-1. Clocking Options for the Ethernet Interface
Ethernet Interface Mode MII
Speed 100Mbps
MII
RMII
GMII
10Mbps
2.5MHz
2.5MHz
25MHz
N/A
10/100 Mbps 1000 Mbps
N/A
N/A
50MHz
N/A
TX_CLKn Frequency
RX_CLKn Frequency
REF_CLK Frequency
GTX_CLK
25MHz
25MHz
25MHz
N/A
N/A
I/O
I/O
125MHz
125MHz
125MHz
1.67MHz
0
Input
Output
Output
Input
Register
MDC Output Clock Frequency
RMII_SEL Input Pin
1.67MHz
0
1.67MHz
0
1.67MHz
1
GL.CR1.P1SPD /
GL.CR1.P2SPD
SU.MACCR.GMIIMIIS
1
0
0=10Mbps
1=100Mbps
1
N/A
1
1
0
Register
*Clock sources should be accurate to ±100ppm.
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Figure 8-1. Clocking Diagram
SPI
μP Port
CLAD
SYSCLKI
TCLK1
TCLK2
TRANSMIT SERIAL
PORT 1
(MII MODE)
RX_CLK
TRANSMIT SERIAL
PORT 2
TX_CLK
MDC
TMCLK4
TRANSMIT SERIAL
PORT 16
ARBITER/
BUFFER MANAGER
Add/Drop
OAM Frames
(MII MODE)
RX_CLK
RCLK1
RCLK2
RECEIVE SERIAL
PORT 1
RECEIVE SERIAL
PORT 2
TX_CLK
MDC
RCLK16
RECEIVE SERIAL
PORT 16
JTAG
DDR SDRAM PORT
VOICE PORT(W41/W11)
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8.3.1 Serial Interface Clock Modes
Serial Interface timing is determined by the line clocks. Both the transmit and receive clocks (TCLK and RCLK) are
inputs, and can be gapped.
8.3.2 Ethernet Interface Clock Modes
The Ethernet interfaces can be configured for MII, RMII, or GMII operation with the GL.CR1.P1SPD,
GL.CR1.P2SPD, SU.MACCR.GMIIMIIS bits and the RMII_SEL input pin. See Table 8-1 for details of the clock
requirements for the various Ethernet Interface configurations.
8.4
Resets and Low-Power Modes
The external RST pin and the reset bit GL.CR2.RST generate global reset signals. A global reset signal resets the
status and control registers on the chip (except the GL.CR2.RST bit) to their default values and resets all the other
flops to their reset values. The processor bus output signals are also placed in high-impedance mode when the
RST pin is active (low). The global reset bit (GL.CR2.RST) stays set after a one is written to it, but is reset to zero
when the external RST pin is active or when a zero is written to it. The system clock must be active for the device to
properly execute the reset. Allow 5 milliseconds after initiating a reset condition for the reset operation to complete.
The DS33X162 family of devices contain up to 54 individual software reset bits, depending on the port count of the
device. These functions of the various reset bits are outlined in the table below.
Table 8-2. Software Reset Functions
Bit Location
Function
GL.CR2.RST
Global Device Reset.
SU.BFC.BFTR
Resets each of the 4096 Bridge Filter Table entries.
LAN port FIFO Reset
SU.LP1C.LP1FR
SU.LP2C.LP2FR
AR.LQ1SA – AR.LQ16SA.LQnPR
LAN port FIFO Reset
LAN Queue Pointer Reset
AR.WQ1SA – AR.WQ16SA.WQnPR WAN Queue Pointer Reset
AR.LIQSA.LIQPR
AR.LEQSA.LEQPR
AR.WIQSA.WIQPR
AR.WEQSA.WEQPR
AR.MQC.ASQPR
LAN Insert Queue Pointer Reset
LAN Extract Queue Pointer Reset
WAN Insert Queue Pointer Reset
WAN Extract Queue Pointer Reset
LAN Queue, WAN Queue, LAN Insert Queue, LAN
Extract Queue, WAN Insert Queue, and WAN Extract
Queue Reset.
PP.DFSCR.DSMR (1-4)
PP.DFSCR.DEPRE (1-4)
VCAT.RCR4.RFRST (1-16)
LI.TVPCR.TVFRST
Decapsulator Reset
Pointer Reset Enable
VCAT Receive FIFO Reset/Power-Down.
Transmit Voice FIFO Reset/Power-Down.
Receive FIFO Reset/Power-Down.
Receive Voice FIFO Reset/Power-Down.
LI.RCR1.RFRST (1-16)
LI.RVPCR.RVRST
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There are several features included to reduce power consumption. The reset bits of the LI.RCR1.RFRST,
LI.RVPCR.RVRST, LI.TVPCR.TVFRST, and VCAT.RCR4.RFRST registers also place the associated circuitry in a
low-power mode. Additionally, the RST pin may be held low indefinitely to keep the entire device in a low-power
mode. Note that exiting the low-power condition requires re-initialization and configuration.
Table 8-3. Block Enable Functions
Block Enables
SU.LP1C.LP1E
LAN Port 1 Enable
SU.LP2C.LP2E
LAN Port 2 Enable
VCAT.TCR1.TVBLKEN
VCAT.RCR1.RVBLKEN
VCAT.RCR1.RVEN1-RVEN4
LI.TVPCR.TPE
Transmit VCAT Enable
Receive VCAT Enable (Global)
Receive VCAT Enable (Per WAN Group)
Transmit Voice Port Enable
Receive Voice Port Enable
Bridge Filter Enable
LI.RVPCR.RPE
SU.BFC.BFE
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8.5
Initialization and Configuration
EXAMPLE DEVICE INITIALIZATION SEQUENCE:
STEP 1: Reset the device
STEP 2: Configure Serial Ports, TX VCAT, RX VCAT, Encapsulator, Decapsulator
STEP 3: Enable transmit serial, transmit VCAT, Encapsulator, Receive LAN
STEP 4: Enable transmit and receive MAC1 (SU.MACCR.TE, SU.MACCR.RE)
STEP 5: Enable transmit and receive MAC2 (SU.MACCR.TE, SU.MACCR.RE)
STEP 6: Enable receive VCAT, Decapsulator, Transmit LAN
STEP 7: Enable Interrupts
8.6
Global Resources
The set of Global Registers begin at address location 000h. The global registers include Global resets, global
interrupt status, interrupt masking, clock configuration, and the Device ID registers. See the Global Register
Definitions in Table 10-2.
8.7
Per-Port Resources
The device contains a common set of global registers. The Serial (Line) Interfaces each have a set of registers for
configuration and control, denoted in this document with the “LI.” prefix. The Ethernet (Subscriber) Interfaces each
have a set of registers for configuration and control, denoted in this document with the “SU.” prefix.
8.8
Device Interrupts
Figure 8-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of
information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the Global
Interrupt Status register GL.ISR to initially determine the source of the interrupt. The host can then read the higher-
level status registers to further identify the source of the interrupt(s). All global status bits (GL.ISR) and
intermediate status bits (AR.BMIS, VCAT.RISR) are real-time bits that will clear once all appropriate interrupts
have been serviced and cleared. The interrupts from any source can be blocked at a global level by the writing a
zero in appropriate location in the global interrupt enable register GL.IER. Some portions of the device use interrupt
mask registers. Placing a “1” in the associated bit location associated with an interrupt condition prevents that
condition from causing a device interrupt. Some portions of the device use interrupt enable registers. Placing a “1”
in the associated bit location associated with an interrupt condition allows that condition to cause a device interrupt.
Latched Status bits that have been enabled or are un-masked are allowed to pass their interrupt conditions to the
Global Interrupt Status Registers. The Interrupt enable registers allow individual Latched Status conditions to
generate an interrupt, but when set to zero, they do not prevent the Latched Status bits from being set. Therefore,
when servicing interrupts, the user should AND the Latched Status with the associated Interrupt Enable Register in
order to exclude bits for which the user wished to prevent interrupt service. The user should NAND the Latched
Status bits with the associated Interrupt Mask Register. Latched Status Registers clear once read as described in
Section 8.1.2. This architecture allows the application host to periodically poll the latched status bits for non-
interrupt conditions, while using only one set of registers.
Note that the inactive state of the interrupt output pin is configurable. The GL.CR2.INTM bit controls the inactive
state of the interrupt pin, allowing selection of high-impedance or active driver.
The interrupt structure is designed to efficiently guide the user to the source of an enabled interrupt source. The
latched status bits for the interrupting entity must be read to clear the interrupt. Note that reading one latched status
bit will reset all bits in that register. During a reset condition, interrupts cannot be generated.
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Figure 8-2. Device Interrupt Information Flow Diagram
RCV LAN 1
MAC 1
SU.LIQOS
Drawing Legend:
SU.MMCRSR
(MAC1)
Status / Interrupt
Register /
Bit Name
Source
RCV LAN 2
MAC 2
SU.LIQOS
Interrupt Enable/
Mask Registers
SU.MMCRSR
(MAC2)
XMT LAN
SU.WOS
SU.WOM
ENCAPSULATOR
PP.ESMLS[1-4]
PP.DMLSR[1-4]
PP.ESMIE[1-4]
PP.DMLSIE[1-4]
DECAPSULATOR
0
1
RXLANIS
TXLANIS
ECIS1
DECIS1
TSPIS
-
XMT SERIAL
LI.TVFLSR
LI.TVFSRIE
2
3
ARBITER
AR.LQOS
AR.WQOS
AR.LQNFS
AR.WQNFS
AR.EQOS
AR.LQOIM
AR.WQOIM
AR.LQNFIM
AR.WQNFIM
AR.EQOIM
4
5
6
BUFIS
-
7
8
9
RVCATIS
ECIS2
ECIS3
ECIS4
DECIS2
DECIS3
DECIS4
10
11
12
13
14
RCV VCAT
VCAT.RSLSR[1-16]
VCAT.RRLSR
VCAT.RSIE[1-16]
VCAT.RRSIE
VCAT.RISR
MICROPORT
15
MICIS
GL.MLSR3
GL.MSIER3
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8.9
Forwarding Modes and WAN Connections
The path any given frame takes through the device can be determined by the contents of the frame, the port of
entry, the user configured WAN Connections, and the user configured Forwarding Mode.
8.9.1 Forwarding Modes
The set of rules that determine the route of frames between the Ethernet Interface(s) and WAN data stream(s) is
called the Forwarding Mode. The forwarding mode is selected in the GL.CR1 register. The five Forwarding Modes
are listed below. The connections between the Serial (WAN) Interfaces and the logical WAN data streams
described below are independent of these Forwarding Modes and will be described later. See Table 8-4 for
forwarding modes supported by each device.
Mode 1 - Single Ethernet Port with Priority Forwarding
Mode 2 - Per-Ethernet-Port Forwarding with Priority Scheduling
Mode 3 - Single Ethernet Port with VLAN Forwarding and Priority Scheduling
Mode 4 - Per-Ethernet-Port Forwarding, with VLAN Forwarding and Priority Scheduling within each VLAN group
Mode 5 – Full VLAN Forwarding in both the LAN-to-WAN and WAN-to-LAN directions.
Forwarding Mode 1 is Single Ethernet Port with Priority Forwarding. In this mode, Ethernet frames are segregated
into up to four priority queues and transmitted in separate WAN data streams. One example application is an
Ethernet Switch that forwards its traffic according to each frame’s priority encoding, as in an IP DSLAM or ISAM
that has a WAN connection with a VoIP Gateway on WAN Interface #1, a Video Stream device on WAN Interface
#2, and an internet POP on WAN Interface #3.
Forwarding Mode 2 is Per-Ethernet-Port Forwarding with Priority Scheduling. In this mode, frames from each
Ethernet port are forwarded to their own group of four priority queues, generating two separate WAN data streams
with priority scheduled traffic. One example application is a Leased Line Service for two independent Ethernet
subscribers. Each subscriber pays its own leased line fee and is guaranteed the full bandwidth of the WAN line
from end to end. This is the only mode that supports 1000Mbps Jumbo Frames (must use single Ethernet port
operation).
Forwarding Mode 3 is Single Ethernet Port with VLAN Forwarding and Priority Scheduling. In this mode, Ethernet
frames are forwarded by VLAN tag (VID) into up to four groups of four priority queues (WAN Groups) each. Each
WAN Group forms a separate WAN data stream with priority scheduled traffic. One example application is an
Service Router that is connected to four IP DSLAMs via DS3s. In the LAN-to-WAN direction, VLAN IDs are used to
distinguish the forwarding path while Priority coding is used to schedule the selection of frames within a Queue
Group.
Forwarding Mode 4 is Per-Ethernet-Port Forwarding, with VLAN Forwarding and Priority Scheduling within each
VLAN Group. In this mode, Ethernet frames from each Ethernet port are forwarded separately, by VLAN tag, into
two sets of four priority queues (WAN Groups) each. The two WAN Groups form separate WAN data streams with
priority scheduled traffic. One example application is 2 Leased Lines for 2 independent Ethernet subscribers (one
route might go to Chicago and the other to Santa Clara). VLAN tagging is used to segregate the traffic bound for
each route, and Priority coding can be used to provide prioritized scheduling within a VLAN group.
Forwarding Mode 5 is Full VLAN Forwarding in both the LAN-to-WAN and WAN-to-LAN directions. In this mode,
Ethernet frames from both ports can be forwarded by VLAN tag (VID) to one of two shared WAN groups. Within
each shared WAN group, there are two sets of four strict priority queues. The two sets of strict priority queues are
serviced with a round-robin algorithm. Frames are then encapsulated by Encapsulator #1 or #3. Frames received
from the WAN side can be forwarded by VLAN tag to either Ethernet port. The LAN-to-WAN and WAN-to-LAN
mappings are independent and can be configured separately. One example application is Central Office traffic
grooming where the time sensitive voice and video are segregated from a network and combined with other data
streams of similar priority.
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Figure 8-3. Forwarding Mode 1: Single Ethernet Port with Priority Forwarding
WAN Ports
LAN Queue 1
Priority 1
Serial
Port 1
Serial
Port 2
Serial
Port 3
Serial
Port 4
Serial
Port 5
Serial
Port 6
Serial
Port 7
Serial
Port 8
Serial
Port 9
Serial
Port 10
Serial
Port 11
Serial
Port 12
Serial
Port 13
Serial
Port 14
Serial
Port 15
Serial
Port 16
WAN
Group 1
LAN Queue 5
Priority 2
Frames from the
Ethernet Interface
are forwarded to
the LAN Queues
based on Priority
(802.1p or DSCP).
LAN Ports
WAN
Group 2
LAN Queue 9
Priority 3
TRANSMIT:
The 16 Serial Ports
are assigned to the
four Encapsulator
WAN Groups with
VCAT.TCR3.TVGS
WAN
Group 3
LAN Queue 13
Priority 4
WAN
Group 4
RECEIVE:
The 16 Serial Ports
are assigned to the
four Decapsulator
WAN Groups with
VCAT.RCR4.RVGS
LAN Insert
Queue
Priority Lookup Table
Frames toward
the Ethernet
Interface
are forwarded
based on the
order of
WAN Insert
Queue
LAN Extract
Queue
WAN Extract
Queue
receipt.
Decapsulator #1 WAN Trap
Decapsulator #2 WAN Trap
Decapsulator #3 WAN Trap
Decapsulator #4 WAN Trap
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Figure 8-4. Forwarding Mode 2: One or Two Ethernet Port Forwarding with Scheduling
WAN Ports
LAN Queue 1
Priority 1
Serial
Port 1
Serial
Port 2
Serial
Port 3
Serial
Port 4
Serial
Port 5
Serial
Port 6
Serial
Port 7
Serial
Port 8
Serial
Port 9
Serial
Port 10
Serial
Port 11
Serial
Port 12
Serial
Port 13
Serial
Port 14
Serial
Port 15
Serial
Port 16
LAN Queue 2-P2
LAN Queue 3-P3
LAN Queue 4-P4
WAN
Group 1
LAN Ports
Frames from the
Ethernet Interfaces
are forwarded to
the WAN groups
based on physical
port, then
scheduled by
Priority (802.1p
or DSCP).
LAN Queue 9
Priority 1
TRANSMIT:
LAN Queue 10-P2
LAN Queue 11-P3
LAN Queue 12-P4
The 16 Serial Ports
are assigned to the
four Encapsulator
WAN Groups with
VCAT.TCR3.TVGS
WAN
Group 3
RECEIVE:
The 16 Serial Ports
are assigned to the
four Decapsulator
WAN Groups with
VCAT.RCR4.RVGS
LAN Insert
Queue
Priority Lookup Table
WAN Insert
Queue
LAN Extract
Queue
Frames toward
the Ethernet
WAN Extract
Queue
Interface are
forwarded based
on the physical
port.
Decapsulator #1 WAN Trap
Decapsulator #3 WAN Trap
* Note that Forwarding Mode 2 is the only forwarding mode available in the DS33X11.
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Figure 8-5. Forwarding Mode 3: Single Ethernet Port with LAN-VLAN Forwarding
WAN Ports
LAN Queue 1
Priority 1
Serial
Port 1
Serial
Port 2
Serial
Port 3
Serial
Port 4
Serial
Port 5
Serial
Port 6
Serial
Port 7
Serial
Port 8
Serial
Port 9
Serial
Port 10
Serial
Port 11
Serial
Port 12
Serial
Port 13
Serial
Port 14
Serial
Port 15
Serial
Port 16
LAN Queue 2-P2
LAN Queue 3-P3
LAN Queue 4-P4
WAN
Group 1
LAN Queue 5
Priority 1
LAN Ports
LAN Queue 6-P2
LAN Queue 7-P3
LAN Queue 8-P4
WAN
Group 2
LAN Queue 9
Priority 1
Frames from the
Ethernet Interface
are forwarded to
the WAN groups
based on VLAN
Tag, then
TRANSMIT:
LAN Queue 10-P2
LAN Queue 11-P3
LAN Queue 12-P4
The 16 Serial Ports
are assigned to the
four Encapsulator
WAN Groups with
VCAT.TCR3.TVGS
WAN
Group 3
LAN Queue 13
Priority 1
scheduled by
Priority
LAN Queue 14-P2
LAN Queue 15-P3
LAN Queue 16-P4
WAN
Group 4
RECEIVE:
The 16 Serial Ports
are assigned to the
four Decapsulator
WAN Groups with
VCAT.RCR4.RVGS
LAN Insert
Queue
Priority Lookup Table
WAN Insert
Queue
LAN Extract
Queue
VLAN (VID)
Lookup Table
Frames
toward the
WAN Extract
Queue
Ethernet
Interface are
forwarded based
on the order of
receipt.
Decapsulator #1 WAN Trap
Decapsulator #2 WAN Trap
Decapsulator #3 WAN Trap
Decapsulator #4 WAN Trap
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Figure 8-6. Forwarding Mode 4: 1 Ethernet port with Port ID and LAN-VLAN Forwarding
WAN Ports
LAN Queue 1
Priority 1
Serial
Port 1
Serial
Port 2
Serial
Port 3
Serial
Port 4
Serial
Port 5
Serial
Port 6
Serial
Port 7
Serial
Port 8
Serial
Port 9
Serial
Port 10
Serial
Port 11
Serial
Port 12
Serial
Port 13
Serial
Port 14
Serial
Port 15
Serial
Port 16
LAN Queue 2-P2
LAN Queue 3-P3
LAN Queue 4-P4
WAN
Group 1
LAN Queue 5
Priority 1
LAN Ports
LAN Queue 6-P2
LAN Queue 7-P3
LAN Queue 8-P4
WAN
Group 2
Frames
from the Ethernet
Interfaces are
forwarded to the
LAN Queue 9
Priority 1
WAN groups based
on physical port,
then by VLAN Tag,
and are scheduled
by Priority
TRANSMIT:
LAN Queue 10-P2
LAN Queue 11-P3
LAN Queue 12-P4
The 16 Serial Ports
are assigned to the
four Encapsulator
WAN Groups with
VCAT.TCR3.TVGS
WAN
Group 3
LAN Queue 13
Priority 1
(802.1p or
DSCP).
LAN Queue 14-P2
LAN Queue 15-P3
LAN Queue 16-P4
WAN
Group 4
RECEIVE:
The 16 Serial Ports
are assigned to the
four Decapsulator
WAN Groups with
VCAT.RCR4.RVGS
LAN Insert
Queue
Priority Lookup Table
WAN Insert
Queue
LAN Extract
Queue
VLAN (VID)
Lookup Table
WAN Extract
Queue
Frames
toward
the Ethernet
Interface are
Decapsulator #1 WAN Trap
Decapsulator #2 WAN Trap
Decapsulator #3 WAN Trap
Decapsulator #4 WAN Trap
forwarded based
on physical port, in
order of receipt.
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Figure 8-7. Forwarding Mode 5: Full LAN-to-WAN and WAN-to-LAN VLAN Forwarding
WAN Ports
LAN Queue 1
Priority 1
Note: Frames in
each pair of WAN
groups are
scheduled by a
round-robin
Serial
Port 1
Serial
Port 2
Serial
Port 3
Serial
Port 4
Serial
Port 5
Serial
Port 6
Serial
Port 7
Serial
Port 8
Serial
Port 9
Serial
Port 10
Serial
Port 11
Serial
Port 12
Serial
Port 13
Serial
Port 14
Serial
Port 15
Serial
Port 16
LAN Queue 2-P2
LAN Queue 3-P3
LAN Queue 4-P4
WAN
Group 1
scheduler.
LAN Queue 5
Priority 1
LAN Ports
LAN Queue 6-P2
LAN Queue 7-P3
LAN Queue 8-P4
WAN
Group 3
Frames from
MAC 1 are sent to
LAN Queue 9
Priority 1
WAN groups 1 or 2
based on VID.
Frames from MAC 2
are sent to WAN
Groups 3 or 4. All
are scheduled
by Priority
TRANSMIT:
LAN Queue 10-P2
LAN Queue 11-P3
LAN Queue 12-P4
The 16 Serial Ports
are assigned to the
four Encapsulator
WAN Groups with
VCAT.TCR3.TVGS
WAN
Group 2
LAN Queue 13
Priority 1
(802.1p or
DSCP)
LAN Queue 14-P2
LAN Queue 15-P3
LAN Queue 16-P4
WAN
Group 4
RECEIVE:
The 16 Serial Ports
are assigned to the
four Decapsulator
WAN Groups with
VCAT.RCR4.RVGS
LAN Insert
Queue
Priority Lookup Table
WAN Insert
Queue
LAN Extract
Queue
VLAN (VID)
Lookup Table
WAN Extract
Queue
Frames
toward
the Ethernet
Interface are
forwarded based
on the VLAN TAG
Decapsulator #1 WAN Trap
Decapsulator #3 WAN Trap
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The user may choose to disable unused features in a forwarding mode. In the forwarding modes with Priority
Forwarding or Priority Scheduling, both 802.1p VLAN PCP and DSCP are supported. The user-programmable
Priority Table is accessed through the SU.PTC, SU.PTAA, SU.PTWD, SU.PTRD, and SU.PTSA registers. The
Priority and Quality of Service (QoS) features of the device are discussed further in Section 8.16. Gigabit Ethernet
applications may only use Forwarding modes that support 1 Ethernet Port (modes 1, 2, or 3). In all forwarding
modes, VCAT/LCAS can be used to aggregate multiple physical serial ports for each WAN Group’s data stream,
except on the devices in the product family that do not support VCAT/LCAS. More information on the use of
VCAT/LCAS for link aggregation can be found in Section 8.12.
In the forwarding modes that use VLAN VID tags, the device references a user-programmable lookup table to
make forwarding decisions. Through the SU.VTC, SU.VTAA, SU.VTWD, and SU.VTRD registers, the user must
program a lookup table that maps up to 4096 VLAN VID tags each to one of the four WAN Groups in the LAN-to-
WAN direction, and from the WAN Groups to the two Ethernet Interfaces in the WAN-to-LAN direction. More
information on VLAN mapping can be found in Section 8.16. Within each WAN Queue group, 802.1p VLAN Priority
coding or DSCP Priority Coding can be used to assign traffic to 4 different priority queues. More information on
priority forwarding and scheduling for quality of service can be found in Section 8.16.
Table 8-4. Forwarding Modes Supported by Device
DS33X161
DS33X81
DS33X41
Forwarding
Mode
DS33X11
DS33W11
DS33X162
DS33X82
DS33W41
Yes
DS33X42
Yes
1
2
3
4
5
No
Yes
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
Yes
8.9.2 WAN Connections
Each Serial (WAN) Interface is mapped to a WAN Group through the VCAT.TCR3(1-16) and VCAT.RCR4(1-16)
registers. A WAN interface can only be assigned to one WAN Group. In devices in the product family that support
VCAT operation, if enabled, more than one WAN interface can be assigned to a WAN Group. Whenever a WAN
Group has more than one member, VCAT must be enabled for that group. A VCAT enabled WAN Group can
include up to 16 WAN Interfaces. More information on the use of VCAT/LCAS for link aggregation can be found in
Section 8.12.
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8.9.3 Queue Configuration
The starting and ending locations for each queue in DDR SDRAM are user-configured. The address space of a 256
Mbit DDR SDRAM is 24-bits, providing an address range covering 16M 16-bit words. To reduce the complexity of
the user interface, only the upper 10 bits of each start/end queue address are user-configured. This provides a
minimum queue size granularity of 16K 16-bit words, or 32 Kbytes. The 10-bit values programmed into the queue
configuration registers can be multiplied by 32,768 in order to convert to bytes.
Each Serial (WAN) interface has an associated receive WAN Queue in external DDR SDRAM. The WAN Queues
receive data from the WAN interfaces and buffer it for processing. The user configures the size and location of
these queues through control registers in the Arbiter. Starting WAN queue addresses are configured in
AR.WQ1SA-AR.WQ16SA, and ending addresses in AR.WQ1EA-AR.WQ16EA. When using VCAT/LCAS, the
WAN queues are also used for differential delay compensation between members of a VCG. The user-configured
depth of these queues should provide for approximately 200 ms of data at the WAN line rate. This translates to
approximately 10Mb at a 52Mbps rate, and 300kb at 1.544Mbps. While it is possible to configure larger WAN
queues, note that limitations of the VCAT protocol only allow the resolution of 200ms at the line rate, and aliasing
may occur at larger WAN queue depths.
Data from the LAN interface is received into an internal buffer monitored by the SU.LIQOS.LIQOS bits. It is then
immediately processed and placed into one of 16 LAN Queues in external SDRAM, based on the forwarding mode
and information within the frame. Starting WAN queue addresses are configures in AR.LQ1SA-AR.WQ16SA and
ending addresses are configured in AR.LQ1EA-AR.LQ16EA.
The user defines a LAN queue threshold (watermark) that is used to trigger Ethernet flow control or device
interrupts in the AR.LQW register. Because WAN standards do not have a method for interactive flow-control, the
WAN queues do not have user-programmable watermark. The device provides overflow status for the WAN
queues in AR.WQOS and for the LAN queues in AR.LQOS. The device provides an indication that frame
discarding has been triggered due to the level of the WAN queues in AR.WQNFS. The interrupt operation related
to these functions is further defined in Section 8.8.
There are also four special-purpose external SDRAM queues used for frame insertion and extraction. The user
configures the size and location of these through control registers in the Arbiter. The LAN Insert queue is defined
by AR.LIQSA and AR.LIQEA. The LAN Extract Queue is defined by AR.LEQSA and AR.LEQEA. The WAN insert
queue is defined by AR.WIQSA and AR.WIQEA. The WAN Extract queue is defined by AR.WEQSA and
AR.WEQEA. Overflow status for the extraction queues is provided in AR.EQOS
An additional portion of the external SDRAM must be allocated for the Bridge/Filter function when in use. The 4k x
6-byte table used for DA lookup operations will be constructed at the location in the AR.BFTOA register.
The device does not provide error indication if the user creates a connection and queue that overwrites
data for another connection queue. The user must take care in setting the queue sizes.
The LAN and WAN queue pointers must be reset before traffic flow can begin. If this procedure is not followed,
incorrect data may be transmitted. The proper procedure for setting up a connection follows:
•
•
•
•
•
Set up the queue sizes for both LAN and WAN queues.
Set up the LAN Queue threshold and associated interrupt enables if desired.
Reset the pointers for the associated queues
Enable the associated ports.
If a port is disconnected, reset the queue pointer after the disconnection.
Each queue can be individually reset as needed through the starting address register for that queue. All queue
pointers can be reset simultaneously through the AR.MQC register. This register also configures the behavior of
the WAN frame insertion.
Two scheduling algorithms can be used for prioritizing traffic to be transmitted from the LAN queues to the WAN
interface: Strict Priority and Weighted Round-Robin (WRR). WRR scheduling is available only in Forwarding Mode
2, with one Ethernet port. This is configured in the AR.LQSC register.
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8.10 Bandwidth Capabilities (Throughput)
All devices in the product family support approximately 416Mbps aggregate throughput. However, on the high-port
count devices with dual Ethernet Interfaces (the DS33X162 and DS33X82), it is necessary to conform to certain
constraints when interfacing with T3/E3 WAN lines. These constraints do not apply for T1/E1 transport. Also, these
constraints do not apply to devices other than the DS33X162 and DS33X82.
Table 8-5. Maximum Number of T3/E3 Lines Per Encapsulator (DS33X162 and DS33X82 Only)
Enabled
Encapsulators
DS33X82
DS33X162
(with 8 ports enabled)
8 T3/E3
DS33X162
(with more than 8 ports enabled)
Not Applicable
3 T3/E3
1
2
3
4
8 T3/E3
5 T3/E3
3 T3/E3
2 T3/E3
5 T3/E3
3 T3/E3
2 T3/E3
2 T3/E3
2 T3/E3
Attempting operation of the DS33X162 or DS33X82 outside of these constraints may cause data loss. If the user
wishes to operate outside of the device’s designed capabilities, it is recommended that the user evaluate the
device performance under the specific application conditions and determine if the measured performance is
acceptable.
Note that the WAN Groups support the following rates:
•
•
Maximum data rate for WAN Groups 1 and 2 = up to 416Mbps total (Group 1 + Group 2 ≤ 418Mbps)
Maximum data rate for WAN Groups 3 and 4 = 180Mbps each
Note that the individual WAN ports support the following rates:
•
•
Maximum line rate for WAN ports 1-8 = 52Mbps each
Maximum line rate for WAN ports 9-16 = 2.044Mbps each
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8.11 Serial (WAN)
The Serial Interfaces support time-division multiplexed, serial data I/O up to 52Mbps. The Serial Interface receives
and transmits encapsulated Ethernet frames, and consists of a physical serial port with a GFP/X.86/HDLC/cHDLC
engine. Each physical interface consists of a data pin, clock pin, and a synchronization pin in both the transmit and
receive directions. The Serial Interface can operate with a gapped clock, and can be connected to a framer,
electrical LIU, optical transceiver, or T/E-Carrier transceiver for WAN transmission. The Serial Interface can be
seamlessly connected to the Maxim T1/E1/J1 Framers, Line Interface Units (LIUs), and Single-Chip Transceivers
(SCTs). The interface can also be seamlessly connected to the Maxim T3/E3/STS-1 Framers, LIUs, and SCTs to
provide T3, E3, and STS1 connectivity.
Receive features:
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
User configurable receive serial ports (up to 16)
User configurable receive voice port(s) (DS33W41/DS33W11 only)
Programmable clock inversion
Serial data is byte-aligned with reference to Receive Frame Sync (MSB follows Frame Sync)
Demuxes Voice traffic from T1/E1/xDSL (maximum of 16 DS0s per port) and output on voice port
(DS33W41/DS33W11 only)
ꢂ
ꢂ
ꢂ
ꢂ
Buffers demuxed voice traffic and realign with RVSYNC and RVCLK (DS33W41/DS33W11 only)
Reports Loss of RCLKn
Capability of RDATA to TDATA loopback
Reports FIFO underflow/overflow
Transmit features:
ꢂ
ꢂ
Data is byte-aligned to TMSYNC/TSYNC (MSB follows TMSYNC/TSYNC)
TMSYNC/TSYNC is an input that may be lined up with the framing overhead of the T1/E1/T3/E3 frame or
programmable to be expected three cycles early.
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
User configurable transmit ports (up to 16)
User configurable transmit voice port(s) (DS33W41/DS33W11 only)
Programmable clock inversion
Muxes Voice traffic to T1/E1/xDSL (DS33W41/DS33W11 only, ports 1-4)
Buffers voice traffic(maximum 16 DS0s per port) to mux in with frame data and retime to TMCLK/TCLK and
TMSYNC/TSYNC (DS33W41/DS33W11 only)
ꢂ
ꢂ
Reports Loss of TCLK
Capable of TDATA to RDATA loopback (replaces RCLK with TMCLK/TCLK)
8.11.1 Voice Support (DS33W11 and DW33W41 Only)
Voice demuxing is done on Frame Sync boundaries, with a programmable number of octets (with a maximum of
16) to be demuxed to the Voice FIFO. These are the octets immediately following the Frame Sync boundary. Voice
octets are read from Voice FIFO one frame later after written to FIFO.
Voice Muxing occurs on Frame Sync boundaries and a programmable number of octets(with a maximum of 16) are
read from the Voice FIFO. These octets will appear on TDATA immediately following the TMSYNC/TSYNC signal.
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8.12 Link Aggregation and Link Capacity Adjustment (VCAT/LCAS)
Virtual Concatenation (VCAT) allows information to be transmitted over up to 16 aggregated WAN links. The VCAT
function aligns all members of the VCG to the link with the most transmission delay. The information on all
members of the VCG must be buffered until the last data is received from the link with the most transmission delay.
The maximum differential delay allowed between the link with the most delay and the link with the least delay is
200 ms. Note that the queue size is user-programmed and could potentially be configured for values larger than
200 ms of data. In VCAT mode, the maximum recommended queue size is 200 ms worth of data. If the user
configures a queue size larger than 200ms while in VCAT mode, errors may occur due to aliasing. Note that link
aggregation is not possible using the DS33X11 and DS33W11, but the insertion of VCAT overhead is supported on
these devices.
VCAT Features:
•
•
•
•
•
4 VCGs for the DS33X162/X82, 2 VCGs for the DS33X42, 1 VCG for the DS33X161/X81/X41/W41
Max differential delay = 200 ms
Receive and Transmit are independent (asymmetrical support)
User programmable configuration of WAN ports used for VCG
Supports Virtual Concatenation of up to 8 T3/E3 or 16 T1/E1
•
RCLKs of a VCG must be frequency locked.
•
All TMCLKs/TCLKs used for a VCG must be frequency locked.
Table 8-6. VCAT/LCAS Control Frame for T1/E1
Concatenation Overhead Octet Definition
Bit 4 Bit 5 Bit 6
Bit 1
Bit 2
Bit 3
Control Packet
MST (1-4)
Bit 7
MFI1
Bit 8
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
MST (5-8)
0
0
0
RS-ACK
RESERVED (0000)
RESERVED (0000)
RESERVED (0000)
RESERVED (0000)
SQ Bits 1-4
MFI2 MSBs (1-4)
MFI2 LSBs (5-8)
CTRL
0
0
0
GID
RESERVED (0000)
RESERVED (0000)
C1
C5
C2
C6
C3
C7
C4
C8
0
1
1
1
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8.12.1 VCAT/LCAS Control Frame for T3/E3
Table 8-7. VCAT/LCAS Control Frame for T3/E3
Concatenation Overhead Octet Definition
Bit 1
Bit 2
Bit 3
Control Packet
MST (1-4)
Bit 4
Bit 5
Bit 6
Bit 7
MFI1
Bit 8
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
MST (5-8)
0
0
0
RS-ACK
RESERVED (0000)
RESERVED (0000)
RESERVED (0000)
RESERVED (0000)
SQ Bits 1-3
0
MFI2 MSBs (1-4)
MFI2 LSBs (5-8)
CTRL
0
0
0
GID
RESERVED (0000)
RESERVED (0000)
C1
C5
C2
C6
C3
C7
C4
C8
0
1
1
1
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8.12.2 VCAT/LCAS Configuration and Operation
VCAT/LCAS setup requires an external Micro to issue an instruction to setup and tear down the IMUX function.
The microprocessor can turn off links that are not participating. Once any changes to the transmit VCAT
configuration are made, a zero-to-one transition on VCAT.TCR1.TLOAD is required in order to load the updated
configuration.
8.12.2.1Receive VCAT Initialization
1. Configure the VCG Frame Mode via VCAT.RCR1.T3T1
2. Configure VCAT.RCR3 with the number of members per VCG.
3. Assign each port to the appropriate VCG via VCAT.RCR4.RVGS[2:0] and VCAT.RCR4.RPA.
4. Enable the Receive VCAT Blocks via VCAT.RCR1.RVBLKEN and VCAT.RCR1.RVENn.
5. Clear the FIFO Reset in VCAT.RCR4.
6. If needed, enable LCAS via VCAT.RCR2.LE[4:1].
8.12.2.2Transmit VC Group Initialization – LCAS Enabled
1. Assign each port to the appropriate VCG via VCAT.TCR3.TVGS[2:0] and VCAT.TCR3.TPA.
2. Assign the Sequence number to each port via VCAT.TCR3.SQ[3:0].
3. Configure VCAT.TCR2 with the number of members per VCG.
4. Configure the VCG Frame Mode via VCAT.TCR1.VnFM[1:0].
5. Write the LCAS Control word via VCAT.TLCR8.CTRL[3:0] to IDLE for participating links.
6. Enable LCAS through VCAT.RCR2.LE[4:1].
7. Enable the Transmit VCAT Block via VCAT.TCR1.TVBLKEN.
8. Initiate a zero-to-one transition on VCAT.TCR1.TLOAD in order to load the configuration.
8.12.2.3Transmit VC Group Initialization (LCAS Disabled)
1. Assign each port to the appropriate VCG via VCAT.TCR3.TVGS[2:0] and VCAT.TCR3.TPA.
2. Assign the Sequence number to each port via VCAT.TCR3.SQ[3:0].
3. Configure each VCG Frame Mode via VCAT.TCR1.VnFM[1:0].
4. Configure VCAT.TCR2 with the number of members per VCG.
5. Enable the Transmit VCAT Block via VCAT.TCR1.TVBLKEN.
6. Initiate a zero-to-one transition on VCAT.TCR1.TLOAD in order to load the configuration.
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8.12.3 Link Capacity Adjustment Scheme (LCAS)
The Link Capacity Adjustment Scheme (LCAS) provides the capability to add and remove members from a VCAT
VCG. If LCAS is enabled viaVCAT.RCR2.LE[3:0], the receive LCAS block will extract all LCAS frame information
from the VCAT overhead. The LCAS status registers report the CTRL, GID, RS-ACK, and MST fields of the VCAT
frame. The LCAS CTRL field communicates the intent to add or remove a member from the group. The device
coordinates the addition or removal of links from the group of active members so that changes are hitless.
The transmit MST values are automatically controlled by the device by default. Optionally, this function can be
controlled by user software via the VCAT.TLCR3–VCAT.TLCR6 registers. The Transmit MST field communicates
the condition of the line (e.g., an LOM alarm), the reception of an Add command (and subsequent successful
alignment to the VCG), and the reception of a Remove command.
To enable Transmit LCAS, follow the initialization steps outlined in Section 8.12.2.2. Note that the
VCAT.TLCR8.CTRL[3:0] bits should be initialized with a CTRL command of IDLE. All changes to the CTRL[3:0]
register bits must be followed with a zero-to-one transition on VCAT.TCR1.TLOAD for the change to take effect.
Receive LCAS Functions:
• Aligns all members of the VCG
• Reports relevant fields and alarms to status registers
• Automatically transmits MST back to the Source (Manual control also configurable)
Transmit LCAS Functions:
• Outputs CTRL, MST, GID, RS-Ack to be inserted into VCAT overhead
• GID PRBS generator and insertion
• User-Configured GID insertion
• CRC generation and insertion
8.12.3.1Example LCAS Operation
1. Initial CTRL command of IDLE, SQ value = max (16 for T1/E1, 8 for T3/E3)
2. Addition of Member:
a. Send ADD command, Change SQ value to 1+ SQ value(active link with the highest SQ)
b. Wait for MST=OK on Receive LCAS (VCAT.RLSR1 register)
c. Send EOS on this port; Port that was sending EOS now sends NORM
3. Removal of Member
a. Change command from NORM/EOS to IDLE; Change SQ value to max; Reorder other active
members’ SQ; If change was from EOS to IDLE, then next highest member changes from NORM
to EOS
4. Response to Receive LCAS reporting MST=FAIL
a. If the Receive LCAS reports that a MST value changed from OK to FAIL, the Transmit LCAS
should send DNU on that port.
b. The SQ value remains the same.
c. If the member that changes to DNU was EOS, EOS must be assigned to the member next in line.
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8.12.4 Alarms and Conditions related to VCAT/LCAS
The latched status bits for the VCAT/LCAS sequence (VCAT.RSLSR.SQL), control (VCAT.RSLSR.CTRL) and
RS-Ack (VCAT.RSLSR.RSACKL) bits can be used to generate device interrupts on a change of state.
The latched Loss of Multiframe Sync (VCAT.RSLSR.LOML), Realign (VCAT.RRLSR.REALIGN[1-4]) and
Differential Delay (VCAT.RRLSR.DDE[1-4]) bits can be used to generate an interrupt upon transition from the
inactive (normal) to the active (alarm) state. If the user’s application requires an indication of the transition from the
active to inactive condition, the host processor should poll the (non-latched) status bits to determine when the
alarm becomes inactive.
8.13 Arbiter/Buffer Manager
The Arbiter manages the transport between the Ethernet and Serial ports. It is responsible for queuing and
dequeuing frames to a single external SDRAM. The arbiter handles requests from the Packet Processor and MAC
to transfer data to and from the SDRAM. For more information of how the Arbiter settings affect QoS, see Section
8.16. For more information on configuring the Arbiter’s interactions with the SDRAM queues, see Section 8.9.3.
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8.14 Flow Control
In some applications, Flow Control may be required to ensure that data queues do not overflow and frames are not
dropped. The device allows for optional IEEE 802.3 Compliant flow control. There are 2 basic mechanisms of flow
control:
•
In half duplex mode, a jam sequence is sent that causes a collision detection at the far end. The collision
causes the transmitting node to reduce the rate of transmission.
•
In full duplex mode, flow control is initiated by the receiving node sending a pause frame. The pause frame
contains a time parameter that determines the pause timeout to be used by the transmitting node.
Several conditions can initiate the flow control mechanism:
•
Flow Control can be initiated by a LAN Queue filling above the Watermark programmed in AR.LQW. Flow
Control for each LAN Queue is independanty enabled in the SU.LQXPC register. Note that the LAN
Queues are external DDR SDRAM buffers used to store data that has arrived on the MII/RMII/GMII
interface(s) and has been processed by the receive MAC.
•
•
Flow Control can be initiated by the CIR Policing function. More information on this function can be found
in Section 8.21.
Transmission of a pause frame can be manually initiated by writing a 1 to SU.MACFCR.FCB.
The Pause time value that is transmitted in outgoing Pause frames is user-programmable in the SU.MACFCR
register. Note that Pause control frame transmission must also be enabled with the SU.MACFCR.TFE bit. Pause
frame receipt must be enabled with SU.MACFCR.RFE. Although not commonly used, Unicast Pause frame
reception can be enabled with SU.MACFCR.UP.
The Watermark value programmed into AR.LQW is in units of memory from the top of the queue, thus a larger
value in AR.LQW indicates that more memory will remain available in the queue when flow control is exerted. Note
that in order to use flow control, the minimum LAN queue size is 2 frames (of maximum size) deep and the LAN
queue watermark threshold (AR.LQW) must be set to allow a minimum of 1 frame of maximum size to be received
after the threshold is crossed. If the Watermark is set too close to the top of the queue to allow time for the remote
node to respond, automatic flow control will not be effective.
In some applications, Ethernet flow control can interfere with higher-layer flow control protocols. For example,
TCP/IP flow control depends on lost frames in order to detect when it has exceeded a system’s capabilities. TCP/IP
flow control uses an increasing flow rate until lost frames are detected, at which point a back-off & resend algorithm
is used, based on the number of lost frames until a steady stream is maintained. If no frames are lost, TCP/IP will
continue attempting to increase the flow rate. If TCP/IP flow control is used in conjunction with Ethernet Flow
control, the results may be undesirable for some applications. The system architect should carefully study this
topic to determine if the system in design should use Ethernet flow control or frame discarding. The
DS33X162 family of devices support both flow control and frame discarding.
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8.14.1 Full Duplex Flow control
Automatic flow control is governed by the LAN Queue high watermark in AR.LQW, and is enabled per LAN Queue
in the SU.LQXPC register. This allows the user to enable or disable flow control for each of the four mapped
PCP/DSCP priorities. When the LAN queue threshold is exceeded on which flow control is enabled, the device will
send a pause frame with the timer value programmed in SU.MACFCR.PT[15:0] when in full duplex, or a jamming
signal in half duplex. More information on configuring the queues, see Section 8.9.3. Also see the SU.MACFCR
register definition for recommended flow control settings.
The pause frame causes the distant transmitter to “pause for a time” before starting transmission again. The device
will send a pause frame as the queue has crossed the threshold defined in AR.LQW. The pause control frame is
retransmitted every 16.4us, 164us, or 1.64ms, depending on the settings in SU.MACFCR.PLT. The receive queue
could keep growing if the round trip delay is greater than the Pause time. Pause control will only take care of
temporary congestion it does not take care of systems where the traffic throughput is too high for the queue sizes
selected. If the flow control is not effective the receive queue will eventually overflow. This is indicated in
SU.LIQOS. If the receive queue is overflowed any new frames will not be received until the overflow condition is
corrected..
The user has the option of not enabling automatic flow control. In this case the thresholds and corresponding
interrupt mechanism to send pause frame by writing to the FCB bit in the MAC flow control register SU.MACFCR.
This allows the user to set not only the watermarks but also to decide when to send a pause frame or not based on
watermark crossings.
On the receive side the user has control over whether to respond to the pause frame sent by the distant end
(SU.MACFCR.RFE bit). On the Transmit queue the user has the option of setting high and low thresholds and
corresponding interrupts. There is no automatic flow control mechanism for data received from the Serial
side waiting for transmission over the Ethernet interface during times of heavy Ethernet congestion.
8.14.2 Half Duplex Flow control
Half duplex flow control functions like Full Duplex flow control, but a jamming sequence is used to exert
backpressure on the transmitting node rather than Pause control frames. The receiving node jams the first 4 bytes
of a frame that are received from the MAC in order to cause a collision detection at the distant end. In both
100Mbps and 10Mbps MII/RMII modes, 4 bytes are jammed upon reception of a new frame. Note that the jamming
mechanism does not jam the frame that is being received during the watermark crossing, but will wait to jam the
next frame after the AR.LQW is crossed. If the queue remains above the threshold, received frames will continue
to be jammed. This jam sequence is stopped when the queue falls below the threshold in AR.LQW.
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8.15 Ethernet Interfaces
The Ethernet Interface allows for direct connection to Ethernet PHYs. The interface consists of a dual 10/100Mbps
MII/RMII interface or a single 1000Mbps GMII interface and associated Ethernet MACs. In GMII operation, the
interface contains 23 signals with a reference clock of 125MHz. In dual MII operation, each interface contains of 12
signals and uses a clock reference of 25MHz. In RMII operation, the interface contains 7 signals with a reference
clock of 50MHz. The device can be configured for GMII, MII, or RMII operation with the GL.CR1.P1SPD,
GL.CR1.P2SPD, SU.MACCR.GMIIMIIS bits and the RMII_SEL input pin. In DTE mode of operation, the TX_CLK
and RX_CLK signals are generated by the PHY and are inputs.
The data received from the MII, RMII, or GMII interface(s) is processed by internal IEEE 802.3 compliant Ethernet
MACs. The user can configure a maximum receive frame length beyond which the MAC discards the complete
frame. The maximum frame size can be configured in the SU.MPL register to any value up to 10240 bytes. Sizes
over 2048 bytes are considered “jumbo” frames. For more information on jumbo frame support requirements, see
Table 10-5. The maximum frame length (in bits) is the number specified in SU.MPL multiplied by 8.
The frame length calculation is shown below in Figure 8-8. The frame length includes only destination address,
source address, VLAN tag (2 bytes), type length field, data and CRC32. Note that the calculation used for
maximum frame size results in a different value than the 802.3 Type/Length field shown in the figure.
Figure 8-8. IEEE 802.3 Ethernet Frame
Type /
Length
Preamble
7
SFD
1
Destination Adrs
Source Address
Data
CRC32
4
6
6
2
46-1500
Max Frame Length
The distant end will normally reject the sent frames if jabber timeout, loss of carrier, excessive deferral, late
collisions, excessive collisions, under run, deferred or collision errors occur. Transmission of a frame under any of
these errors will be logged by the MAC management counters. The device provides user the option to not
automatically retransmit the frame if any of the errors have occurred through the MAC’s SU.MACCR.DRTY bit.
Frames received with errors are usually rejected by the device. More information on the Ethernet MAC functions
can be found in Section 8.19.
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Table 8-8. Configuration Recommendations for Maximum Frame Length
Maximum Frame
Length (bytes)
SU.MPL
SU.MACCR.WDD
SU.MACCR.JD
SU.MACCR.JFE
1518
2048
9018
1518
2048
9018
0
0
1
0
0
1
0
0
1 (half-duplex)
0 (full-duplex)
1 (half-duplex)
0 (full-duplex)
10240
10240
1
1
Table 8-9. Selection of MAC Interface Modes for Port 1
Function
GMII
RMII_SEL Pin
DCEDTES Pin
GMIIMIIS Bit
P1SPD Bit
0
1
0
0
0
1
Don’t Care
RMII
0 for 10Mbps
1 for 100Mbps
0 for 10Mbps
1 for 100Mbps
0 for 10Mbps
1 for 100Mbps
MII (DTE Mode)
MII (DCE Mode)
0
0
0
1
1
1
Table 8-10. Selection of MAC Interface Modes for Port 2
Function
RMII_SEL Pin
DCEDTES Pin
GMIIMIIS Bit
P1SPD Bit
RMII
1
0
1
0 for 10Mbps
1 for 100Mbps
0 for 10Mbps
1 for 100Mbps
0 for 10Mbps
1 for 100Mbps
MII (DTE Mode)
MII (DCE Mode)
0
0
0
1
1
1
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8.15.1 GMII Mode
GMII interface operates synchronously from the external 125MHz reference, and 23 signals are required. The
following figure shows the GMII architecture. Note that DCE mode is not supported for GMII mode and that GMII is
valid only for full duplex operation.
Figure 8-9. Example Configuration of GMII Interface (DTE Mode Only)
DS33X/W MAC
GMII PHY
TXD[7:0]
TX_EN1
Transmit
GTX_CLK
TX_ERR1
RXD[7:0]
RX_CRS1
RX_DV1
Receive
Control
RX_ERR1
RX_CLK1
MDC
MDIO
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8.15.2 MII Mode
The Ethernet interface can be configured for RMII operation by setting the hardware pin RMIIMIIS low. MII interface
operates synchronously from the external 25MHz reference (REF_CLK). The following figure shows the MII
architecture.
Figure 8-10. Example Configuration as DTE connected to an Ethernet PHY in MII Mode
Rx
Ethernet Phy
Rx
RXD[3:0]
RXD[3:0]
DTE
DCE
RXDV
RXDV
RX_CLK
RX_CLK
RX_ERR
RX_CRS
RX_ERR
RX_CRS
COL_DET
Arbiter
WAN
MAC
COL_DET
TXD[3:0]
TX_CLK
TXD[3:0]
Tx
TX_CLK
TX_EN
Tx
TX_EN
MDIO
MDIO
MDC
MDC
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Table 8-11. MII Mode Options
Mode/Speed
Functions
10Mbps full duplex DTE Mode with
no flow control
While in full duplex, MII DTE Mode, both the receive and transmit MII
clocks are inputs.
100Mbps full duplex, DTE Mode
with flow control
In full duplex DTE Mode the clocks are expected from the PHY. The flow
control for a full duplex operation is using control frames. If the MAC
receives a pause command the Transmitter is disabled for the time
specified in the pause command. The pause command has a multicast
address 01-80-62-00-00-01. The MAC can also initiate a pause control
frame with SU.MACFCR.FCB. The duration field in the pause control
frame is determined by settings in the MAC Flow control Register
100Mbps full duplex, DTE Mode
with no flow control
—
100Mbps full duplex DCE Mode with In full duplex DCE Mode, the clocks are provided by the device. The flow
flow control
control for a full duplex operation is using control frames. If the MAC
receives a pause command the Transmitter is disabled for the time
specified in the pause command. The pause command has a multicast
address 01-80-62-00-00-01. The MAC can also initiate a pause control
frame with SU.MACFCR.FCB. The duration field in the pause control
frame is determined by settings in the MAC Flow control Register
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8.15.3 DTE and DCE Mode
When in 10/100 mode, the Ethernet MII interface(s) can be configured for DCE or DTE Mode. When configured in
DTE Mode, direct connection can be made to Ethernet PHYs. In DCE mode, the MII interface can be connected to
MII MAC devices other than an Ethernet PHY, such as Ethernet Switch devices. The DTE/DCE connections in MII
mode are shown in the following 2 figures.
In DCE Mode, the transmitter is connected to an external receiver and receiver is connected to an external MAC
transmitter. The selection of DTE or DCE mode is done by the hardware pin DCEDTES. DCE mode is not valid for
GbE (GMII) operation.
Figure 8-11. Example Configuration as a DCE in MII Mode
DTE
Tx
DCE
Rx
TXD[3:0]
RXD[3:0]
TX_EN
RXDV
RX_CLK
TX_CLK
RX_ERR
RX_CRS
TX_ERR
RX_CRS
COL_DET
WAN
MAC
Tx
MAC
Arbiter
COL_DET
TXD[3:0]
TX_CLK
RXD[3:0]
RX_CLK
Rx
TX_EN
MDIO
RXDV
MDIO
MDC
MDC
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8.15.4 RMII Mode
The Ethernet interface can be configured for RMII operation by setting the hardware pin RMIIMIIS high. RMII
interface operates synchronously from the external 50MHz reference (REF_CLK). Only 7 signals are required. The
following figure shows the RMII architecture. Note that DCE mode is not supported for RMII mode and RMII is valid
only for full duplex operation.
Figure 8-12. RMII Interface (DTE Mode Only)
DS33X MAC - RMII
PHY RMII to MII
TX_EN
TXD[1:0]
TX_EN
TXD[3:0]
TX_ERR
TX_CLK
Transmit
MAC
CRS
CRS_DV
RXD[1:0]
REF_CLK
RX_DV
RXD[3:0]
RX_ER
RX_CLK
Receive
MAC
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8.16 Quality of Service (QoS) Features
The device contains several features designed to provide Quality of Service (QoS). These features include Virtual
LAN (VLAN) Forwarding and Priority Scheduling/Forwarding supporting both VLAN 802.1p and DSCP. The device
also includes features for Congestion Avoidance and Congestion Management. Information on Congestion
Avoidance using the integrated CIR can be found in Section 8.21. Information on Congestion Management using
Ethernet flow control can be found in Section 8.14.
VLAN Forwarding is used to separate traffic into different streams or combine traffic from multiple sources into a
single stream, while Priority Scheduling is used to prioritize traffic waiting in queue for WAN transmit bandwidth to
become available. Note that Priority Scheduling is different than Priority Forwarding. Priority Forwarding is a
technique used to separate traffic of various priority levels onto physically separate WAN connections. The use of
VLAN Forwarding, Priority Scheduling, and Priority Forwarding is determined by the Forwarding Mode of the
device. More information on the available Forwarding Modes can be found in Section 8.9.
Within the data stream for each WAN Queue group, 802.1p VLAN Priority Coding or DSCP Priority Coding can be
used to assign traffic to 4 different priority queues as discussed in the following sections.
8.16.1 VLAN Forwarding by VID (IEEE 802.1q)
The VLAN ID (VID) is a 12-bit field that is found beginning in the 15th byte of VLAN tagged Ethernet frames. The
format of the IEEE 802.1Q VLAN tagged frame is shown in Figure 8-13. The device uses a 4 kilobyte user-
configured “VLAN Table” to translate VLAN tag information into forwarding, trapping, or discarding decisions. For
more details on VLAN Table programming, see Section 8.16.2.
All frames received on the Ethernet interfaces are inspected for a VLAN ID (LAN-VLAN ID) value. The VLAN table
settings for each of the 4096 LAN-VLAN IDs are used to forward each frame to one of the four WAN groups, to
discard the frame, or to extract (trap) the frame. Only when operating in forwarding modes 3, 4, and 5 (as defined
in Section 8.9), can frames be forwarded to one of the four WAN Groups as assigned in the VLAN table. All 12-bit
LAN-VLAN IDs that are translated to the same WAN Group are considered part of the same LAN-VLAN Group.
Note that LAN-VLAN ID trapping must be assigned to an Ethernet Port with the SU.LPM.LEEPS bit, and enabled
with the SU.LPM.LEVIT bit.
All frames received on the WAN interfaces are inspected for a VLAN ID (WAN-VLAN ID) value. ). The VLAN table
settings for each of the 4096 WAN-VLAN IDs are used to forward each frame to one of the Ethernet ports, to
discard the frame, or to extract (trap) the frame. Only when operating in forwarding mode 5 (as defined in Section
8.9), can frames be forward to one of the Ethernet ports by their VLAN ID value. All 12-bit LAN-VLAN IDs that are
translated to the same Ethernet interface are considered part of the same WAN-VLAN Group. Note that WAN-
VLAN forwarding is only applicable when operating in forwarding mode 5. Also note that WAN-VLAN ID trapping
must be assigned to a specific WAN Group with the SU.WEM.WEDS bits and enabled with the SU.WEM.WEVIT
bit.
The LAN-VLAN configuration, used to specify the actions for VLAN ID values in frames received on the Ethernet
interfaces (LAN-to-WAN direction), may be unrelated to the WAN-VLAN configuration, used to specify the actions
for VLAN ID values for frames received on the WAN interface (WAN-to-LAN direction). Although there may be
VLAN tags in both data stream directions (LAN-to-WAN and WAN-to-LAN), the functionality of the device does not
require a symmetrical VLAN function. The LAN-VLAN forwarding and the WAN-VLAN forwarding may be used
independently of each other.
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8.16.2 Programming the VLAN ID Table
A 4 kilobyte user-configured “VLAN Table” is used to translate VLAN tag information from each received frame into
forwarding, trapping (frame extraction), or discarding decisions. Each address in the table corresponds to a
specific VLAN ID (VID) value from 0 to 4095, and the bit settings at each address relate to actions taken when a
frame containing the corresponding VLAN ID value is detected. The VLAN Table is configured through the
SU.VTC, SU.VTAA, SU.VTWD, and SU.VTRD registers.
Within each address location in the VLAN table, two bits of data determine the actions taken for frames received on
the WAN interfaces with VLAN IDs matching the table address value, and four bits determine actions taken on
frames received on the LAN interfaces with VLAN IDs matching the table address value. The 4K x 2 bit space used
for WAN functions is referred to as the WAN-VLAN table. The 4 K x 4 bit space used for LAN functions is referred
to as the LAN-VLAN table.
The user can also configure a default “No VLAN detected” value in the SU.LNFC register to indicate what should
be done with frames that do not have a VLAN tags. The user may indicate the same forwarding location as one of
the other VLAN Groups, or it can be used to indicate an independent process or location. For example, the user
may indicate to discard untagged frames, while VLAN tags 0 through 4094 are forwarded to the 4 WAN Groups
and VLAN tag 4095 is forwarded to the LAN Extract queue.
To Reset the VLAN Table:
1) Write SU.VTC = 05h to ensure a 0-1 transition on SU.VTC.CI and enable the VLAN Table.
2) Write SU.VTC = 07h.
3) Read SU.VTSA.VTIS until = 1.
To Program the VLAN Table:
1) Write SU.VTAA = 00h in order to begin configuration at VID 00h.
2) 4096 times, write the value of SU.VTWD for the desired action for each VID value.
To Verify the VLAN Table:
1) Write SU.VTAA = 00h in order to begin verification at VID 00h.
2) 4096 times, read the value of SU.VTRD register and verify the value.
The LAN-VLAN ID frame extraction trap must be assigned to an Ethernet Port with the SU.LPM.LEEPS bit, and
enabled with the SU.LPM.LEVIT bit.
The WAN-VLAN ID frame extraction trap must be assigned to a specific WAN Group (Decapsulator) with the
SU.WEM.WEDS bits and enabled with the SU.WEM.WEVIT bit.
In order to enable the VLAN processing functions in each port, the SU.LP1C.LP1ETF[2:1] or
SU.LP2C.LP2ETF[2:1] bits must be properly configured. When the VLAN processing functions are enabled,
incoming frames are inspected for VLAN information. The VLAN protocol ID must match the value programmed in
SU.LQTPID. Frames with alternate VLAN PIDs are processed as “untagged”. In the WAN-to-LAN direction, the
corresponding function is performed in SU.WETPID.
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8.16.3 Priority Coding with VLAN Tags (IEEE 802.1p)
The IEEE 802.1Q VLAN tagging standard allocated room for a priority code that was later defined by the IEEE
802.1p standard. IEEE 802.1p eventually became part of IEEE 802.1D.
With Priority Scheduling or Priority Forwarding enabled, the priority value is inspected as each frame arrives on the
Ethernet Interfaces. For IEEE 802.1p priority coding, the priority is located in the 15th byte of the Ethernet frame.
The format of the IEEE 802.1p VLAN tagged frame is shown in Figure 8-13. A user-programmed Priority Table is
used to translate the 3-bit 802.1p Priority value into one of four Priority Levels for each Ethernet Interface. The
received PCP value is used as the address for the Priority Table lookup operation. The Priority Levels correspond
to four separate queues. In Priority Forwarding (Forwarding Mode 1), the four queues are in separate WAN
Groups. In Priority Scheduling operation, each WAN Group contains a set of four priority queues. These queues
are collectively referred to as LAN Queues in other portions of this document.
The priority mode (802.1p, DSCP, or none) for each Ethernet port can be independently selected using the
SU.LP1C and SU.LP2C registers. See Section 8.16.6 for more information on programming the priority table.
Figure 8-13. IEEE 802.1Q and 802.1p Field Format
Ethernet Byte #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
2
3
4
5
6
7
8
9
Destination Address (DA)
Source Address (SA)
10
11
12
13
14
15
16
17
18
19+
8 (hex)
0 (hex)
3 Bit PCP Priority
1 (hex)
0 (hex)
4 bits of VLAN ID
CFI
11
8
0
7
8 bits of VLAN ID
Ethernet Type / Length (MSB)
Ethernet Type / Length (LSB)
< Data Unit >
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8.16.4 Priority Coding with Multiple (Q-in-Q) VLAN Tags
Device operation with multiple VLAN tags is similar to operation with a single VLAN tag. The Ethernet Q-in-Q
format is similar to the case outlined above, except that a second VLAN tag is inserted after the Ethernet SA field.
The format of the VLAN Q-in-Q tagged frame is shown in Figure 8-14. Both VLAN tags include a PCP (User
Priority) value and a VLAN ID. The device only makes forwarding and scheduling decisions using the “outer-most”
VLAN tag located in Ethernet bytes # 13-16, and ignores additional tags. The user can configure an alternate
WAN-VLAN Q-in-Q or VLAN Tag Protocol ID (TPID) that is used instead of the default value of 8100 in the
SU.WETPID register. The user can configure an alternate LAN-VLAN Q-in-Q or VLAN Tag Protocol ID (TPID) that
is used instead of the default value of 8100h in the SU.LQTPID register. Some additional common TPIDs are 9100,
9200 and 88A8. See Section 8.16.6 for more information on programming the priority table.
Figure 8-14. VLAN Q-in-Q Field Format
Ethernet Byte #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
2
3
Destination Address (DA)
4
5
6
7
8
9
Source Address (SA)
10
11
12
13
14
15
16
17
18
19
20
21
22
23+
8 (hex)
0 (hex)
3 Bit PCP Priority
1 (hex)
0 (hex)
4 bits of VLAN ID
CFI
CFI
11
8
0
7
7
8 bits of VLAN ID
8 (hex)
0 (hex)
3 Bit PCP Priority
1 (hex)
0 (hex)
4 bits of VLAN ID
11
8
0
8 bits of VLAN ID
Ethernet Type / Length (MSB)
Ethernet Type / Length (LSB)
< Data Unit >
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8.16.5 Priority Coding with DSCP
The IETF RFC2474 (Differentiated Services) defines a Layer-3 alternate to 802.1p priority coding, known as
Differentiated Services Code Point (DSCP). DSCP is composed of a 6-bit value located in the second byte of the IP
header. When Priority Scheduling or Priority Forwarding are enabled, the priority value is inspected as each frame
arrives on the Ethernet Interfaces. The format of the DSCP tagged frame is shown in Figure 8-15. The device
supports DSCP priority carried in IPv4 or IPv6 packets. A user-programmed Priority Table is used to translate the
6-bit DSCP Priority into one of four Priority Levels for each Ethernet Interface. The received PCP value is used as
the address for the Priority Table lookup operation. The Priority Levels correspond to four separate queues. In
Priority Forwarding (Forwarding Mode 1), the four queues are in separate WAN Groups. In Priority Scheduling
operation, each WAN Group contains a set of four priority queues. These queues are collectively referred to as
LAN Queues in other portions of this document.
The priority mode (802.1p, DSCP, or none) for each Ethernet port can be independently selected using the
SU.LP1C and SU.LP2C registers. The DSCP function is a simple enable/disable function, with all of the other
parameters (Ethernet Frame Format, and Ethernet Type) being discovered by the device. See Section 8.16.6 for
more information on programming the priority table.
Figure 8-15. Differentiated Services Code Point (DSCP) Header Information
Ethernet Byte #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
2
3
4
5
6
7
8
9
Destination Address (DA)
Source Address (SA)
10
11
12
13
14
15
16
17+
Ethernet Type / Length (MSB)
Ethernet Type / Length (LSB)
IP Version
DSCP Priority
< IP Header Continues…>
IP TYPE
ECT
CE
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8.16.6 Programming the Priority Table
The user-programmable Priority Table is accessed indirectly through the SU.PTC, SU.PTAA, SU.PTWD,
SU.PTRD, and SU.PTSA registers. The device contains a single table, with the MSB of the table address
(SU.PTAA.PTAA) used to distinguish the LAN port in multi-port devices. When a frame is received, the PCP or
DSCP value in the received frame is the address used to look up the user-programmed priority level in the Priority
Table.
The device does not require that the priority mapping be linear or monotonic. Arbitrary assignments are allowed.
Note that while the DSCP/PCP protocol definitions use a higher value to indicate a higher priority, the device uses
a lower value to indicate a higher priority. As an example, for the values PCP = 000b and DSCP = 00000b (as
defined by their protocol definitions as lowest priority) most users will choose to assign the associated priority table
address location (SU.PTAA.PTAA[6:1]=000000b) a value of 11b, indicating the lowest possible priority. Similarly
for the values PCP = 111b and DSCP = 111111b, typically the associated Priority Table address will be assigned a
value of 00b. Example Priority Table configurations for a single port are shown in the tables below.
Table 8-12. Example Priority Table Configuration for DSCP
SU.PTWD/
SU.PTWD/
SU.PTWD/
SU.PTWD/
PTAA[6:1]
PTAA[6:1]
PTAA[6:1]
PTAA[6:1]
SU.PTRD
11
SU.PTRD
10
SU.PTRD
10
SU.PTRD
01
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
11
10
10
01
11
10
10
01
10
10
10
01
10
10
10
01
10
10
10
01
10
10
10
01
10
10
10
01
10
10
10
01
10
10
10
01
10
10
10
01
10
10
10
01
10
10
10
01
10
10
10
01
10
10
10
01
10
10
10
00
* More guidance on priority mapping for legacy compatibility can be found in RFC 2474.
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Table 8-13. Example Priority Table Configuration for PCP
SU.PTWD/
PTAA[6:1]
SU.PTRD
000000
000001
000010
000011
000100
000101
000110
000111
11
11
10
10
01
01
01
00
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8.17 OAM support with Frame Trapping, Extraction, and Insertion
The device has the ability to insert and extract frames from/to the host microprocessor from both the WAN interface
and the LAN interface. There are four user-accessible FIFOs for this purpose: one for WAN insertion, one for WAN
extraction, one for LAN insertion, and one for LAN extraction. Each FIFO has the ability to issue an interrupt when
it is empty (Insertion FIFOs) or has a frame available (Extraction FIFOs). In order for frames to be extracted by the
host microprocessor, they must first be “trapped”. The device has two “traps” for capturing frames for extraction –
the LAN Trap and the WAN Trap. The maximum frame size that may be trapped or inserted is 2048 bytes.
The LAN Trap (when appropriately enabled) inspects each frame received on the Ethernet interface for its Ethernet
Destination Address (DA), VLAN tag, Q-in-Q tag, and Ethernet Type. These parameters help to determine what to
do with each frame. The LAN Trap is logically located between the Ethernet MAC and the circuitry that performs
forwarding to the WAN groups.
The WAN Trap (when appropriately enabled) inspects each frame received on the Serial interface for its Ethernet
Destination Address (DA), VLAN tag, Q-in-Q tag, Ethernet Type, or user-programmable header value. The WAN
Header Trap enables trapping on SLARP, GFP PTI/UPI, GFP CID or Shim Tag. The WAN trap is logically located
after the line decoding functions (bit/byte destuffing, descrambling), and the Decapsulator packet processing
circuitry.
Note that SPI “Burst mode” is not applicable for frame insertion or extraction, due to the indirect access of the
extract and insert queues.
There are 6 Ethernet Frame Formats supported for QoS and OAM Frame Extraction. The supported frame formats
are diagramed in Figure 8-16 and include:
•
•
•
•
•
•
DIX
VLAN tagged DIX
Q-in-Q tagged DIX
802.3 LLC/SNAP
VLAN tagged 802.3 LLC/SNAP
Q-in-Q tagged 802.3 LLC/SNAP
The user is not required to specify or configure an Ethernet frame format because it is normal for LAN traffic to
simultaneously carry multiple different Ethernet formats.
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Figure 8-16. Supported Trapped Ethernet Frame Types
VLAN Tagged
802.3
LLC/SNAP
Q-in-Q
Tagged 802.3
LLC/SNAP *
Byte
#
VLAN Tagged
DIX
Q-in-Q
Tagged DIX
802.3
LLC/SNAP
DIX
0
1
2
3
Destination
Address
Destination
Address
Destination
Address
Destination
Address
Destination
Address
Destination
Address
4
5
6
7
8
Source
Source
Source
Source
Source
Source
Address
Address
Address
Address
Address
Address
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Ethernet
Type
Length
VLAN
Tag
Q-in-Q
Tag
VLAN
Tag
Q-in-Q
Tag
LLC Header
(AA AA 03)
Ethernet
Type
Length
VLAN
Tag
VLAN
Tag
SNAP OUI
(00 00 00)
LLC Header
(AA AA 03)
Ethernet
Type
Ethernet
Type
Length
SNAP OUI
(00 00 00)
LLC Header
(AA AA 03)
Ethernet
Type
SNAP OUI
(00 00 00)
Ethernet
Type
* EtherType trapping of this format supported by the LAN trap only.
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8.17.1 Frame Trapping
Frames from the LAN interface can be trapped by VLAN ID, Ethernet Type, Broadcast Address, Management
Multicast Address (01:80:C2:xx:xx:xx), Destination Address, or a range of Destination Addresses. Frames from the
WAN interface can be trapped by VLAN ID, Ethernet Type, Broadcast Address, Management Multicast Address
(01:80:C2:xx:xx:xx), Destination Address, a range of destination addresses, or by a user-programmable header
comparison. LAN trapping is enabled in the SU.LPM register. WAN trapping is enabled in the SU.WEM register.
The LAN Trap can only be user configured to monitor one Ethernet port. The selection of LAN port to be monitored
is done with the SU.LPM.LEEP bit. The WAN Trap can only monitor for WAN Extract conditions on one (of the four
possible) Decapsulator (WAN Group) data streams. The selection of the WAN Group to monitor is done with
SU.WEM.WEDS[1:0]. The maximum frame size that may be trapped is 2Kbytes.
8.17.1.1LAN-VLAN Trapping
When trapping frames received on the LAN interface by VLAN ID, the user configures the VLAN IDs (VIDs) to be
trapped using the LAN-VLAN Table. Trapping is then enabled or disabled with the SU.LPM.LEVIT bit. See Section
8.16 for more information on VLAN configuration. Only one LAN Port can be allowed to forward frames to the LAN
Extract Queue (which of the two ports is determined by user configuration). If VLAN Forwarding is enabled, and the
4-bit value returned from the LAN-VLAN Table indicates “Extract”, but the port that the frame is associated with has
not been configured to forward to the LAN Extract queue, then the “Extract” status returned from the VLAN Table is
ignored. For more details on LAN-VLAN Table programming, see Section 8.16.2.
8.17.1.2LAN Ethernet Type Trapping
When trapping frames received on the LAN interface by Ethernet Type, the user can configure and 2-byte Ethernet
Type Field to be trapped in the SU.LEET register. Trapping is then enabled or disabled with the SU.LPM.LEETT
bit. Ethernet Type trapping enables the capture of ARP, BPDU, and other management traffic.
8.17.1.3LAN Ethernet Destination Address Trapping
When trapping frames received on the LAN interface by Unicast Destination Address, the user programs the
Destination Address for extraction into the SU.LEDAL, SU.LEDAM, and SU.LEDAH registers. By using a mask for
the lower two bytes of the DA in the SU.LEDAX register, all of the addresses within a range can be forwarded to
the LAN Extract queue. Trapping is then enabled or disabled with the SU.LPM.LEDAT bit.
When trapping frames received on the LAN interface by management multicast address (01:80:C2:xx:xx:xx), the
user simply enables extraction with the SU.LPM.LMGMTT bit. All trapped frames will be forwarded to the LAN
extract queue.
When trapping frames received on the LAN interface by broadcast address (FF:FF:FF:FF:FF:FF), the user simply
enables extraction with the SU.LPM.LBAT bit. All trapped frames will be forwarded to the LAN extract queue.
8.17.1.4WAN Ethernet Destination Address Trapping
When trapping frames received on the WAN interface by Unicast Destination Address (DA), the user programs the
Destination Address for extraction into the SU.WEDAL, SU.WEDAM, and SU.WEDAH registers. By using a mask
for the lower two bytes of the DA in the SU.WEDAX register, all of the management addresses within a range can
be forwarded to the WAN Extract queue. Trapping is then enabled or disabled with the SU.WEM.WEDAT bit.
When trapping frames received on the WAN interface by management multicast address (01:80:C2:xx:xx:xx), the
user simply enables extraction with the SU.WEM.WMGMTT bit. All trapped frames will be forwarded to the WAN
extract queue.
When trapping frames received on the WAN interface by broadcast address (FF:FF:FF:FF:FF:FF), the user simply
enables extraction with the SU.WEM.WBAT bit. All trapped frames will be forwarded to the WAN extract queue.
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8.17.1.5WAN-VLAN Trapping
When trapping frames received on the WAN interface by VLAN ID, the user configures the VLAN IDs (VIDs) to be
trapped using the WAN-VLAN Table. Trapping is then enabled or disabled with the SU.WEM.WEVIT bit. See
Section 8.16 for more information on VLAN configuration. Only one WAN Group Decapsulator can be allowed to
forward frames to the WAN Extract Queue at a time (determined by user configuration). If VLAN Trapping is
enabled, and the 4-bit value returned from the WAN-VLAN Table indicates “Extract”, but the port that the frame is
associated with has not been configured to forward to the WAN Extract queue, then the “Extract” status returned
from the WAN-VLAN Table is ignored. For more details on WAN-VLAN Table programming, see Section 8.16.2.
8.17.1.6WAN Ethernet Type Trapping
When trapping frames received on the WAN interface by Ethernet Type, the user can configure and 2-byte
Ethernet Type Field to be trapped in the SU.WEET register. Trapping is then enabled or disabled with the
SU.WEM.WEETT bit. The WAN Ethernet Type trap is valid only with frame formats in which the Ethernet Type
occurs in the first 32 bytes. Thus, the WAN Ethernet Type trap is not valid with the following frame types:
•
•
•
4-byte Encapsulation Header with Q-in-Q & std VLAN & LLC/SNAP (HDLC or GFP-Null)
8-byte Encapsulation Header with Q-in-Q & std VLAN & LLC/SNAP (HDLC or GFP-Linear)
8-byte Encapsulation Header with std VLAN & LLC/SNAP (HDLC or GFP-Linear)
8.17.1.7WAN Header Trapping
Trapping can also be performed on any two consecutive bytes within the first 8 bytes of frames received from the
WAN interface. When trapping frames received on the WAN interface by header, the user configures a 2-byte
value to be trapped in the SU.WEHT register. The offset is configured in the SU.WEHTP register. Trapping is then
enabled or disabled with the SU.WEM.WEHT bit.
8.17.2 Frame Extraction and Frame Insertion
Extraction of trapped frames through the microport is done one byte at a time, with the beginning of the frame
being read first. The device must be configured to properly trap frames as described in Section 8.17.1. The user
may enable an interrupt to alert the host processor that a frame is available for extraction via the GL.MSIER3
interrupt enable register. A latched status register (GL.MLSR3) may also be used as indication that a frame is
available for extraction. When a trapped frame is available, the user must select the correct FIFO with the
GL.MCR1 register. The user must then read the length of the frame from GL.MSR1 or GL.MSR2 in order to know
how many bytes to extract. The user then reads one byte at a time from the FIFO read access register
(GL.MFARR) to extract the entire frame. When the entire frame has been read, the user indicates that the frame
may be discarded from the FIFO with the GL.MFAWR.RD_DN bit.
Steps for Frame Extraction:
1. Read the GL.MSR3 LAN/WAN FIFO Extraction Available Status bit to verify FIFO has a frame to be read.
2. Select the corresponding FIFO via GL.MCR1.
3. Read the size of frame in bytes from GL.MSR1 or GL.MSR2.
4. Read the frame from the GL.MFARR register one byte at a time.
5. Write a 0-to-1 transition to GL.MFAWR.RD_DN.
6. Repeat step 1.
Insertion of a frame through the host microport is done one byte at a time, with the beginning of the frame written
first. The user must first configure the LAN insertion settings and enable insertion via the SU.LIM register, or
configure the WAN insertion settings and enable insertion via the AR.MQC register. The correct FIFO must then be
selected with the GL.MCR1 register. The length of the frame to be inserted must then be written into GL.MCR2 or
GL.MCR3. The user proceeds to write one byte of the frame at a time to the FIFO access register, GL.MFAWR,
beginning with the first byte of the frame. Each write to this address automatically increments the pointer of the
selected FIFO. When the entire frame has been written, the GL.MFAWR.WR_DN bit is used to indicate that the
frame is ready for transmission.
Steps for Frame Insertion:
1. Configure the LAN insertion settings in the SU.LIM register, or WAN insertion settings in AR.MQC.
2. Read the GL.MSR3 LAN/WAN Queue Empty Status bit to verify FIFO is empty.
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3. Select the appropriate FIFO for insertion via GL.MCR1.
4. Write the size of frame in bytes to GL.MCR3 for LAN insertion, GL.MCR2 for WAN insertion.
5. Write the frame to the GL.MFAWR.WPKT[0:7], one byte at a time.
6. Write a 0-to-1 transition to GL.MFAWR.WR_DN.
7. Repeat Step 1.
Frames loaded into the WAN Insertion FIFO should not include the GFP Length and cHEC fields. Inserted frames
should include all other applicable GFP/HDLC header information and a valid HECs. The header information on
inserted frames may be different than the header of normal traffic to allow for a number of management protocols
to be present on the link. The only modifications made by the device to data placed in the WAN Insertion queue are
the addition of the GFP Length/cHEC, the line coding functions of bit/byte stuffing, and X43+1 scrambling, if
enabled.
Frames loaded into the LAN Insertion FIFO should be complete and valid IEEE 802.3 or DIX Ethernet frames. If the
Ethernet MAC has been configured to add a FCS to all frames (SU.LIM.LP1CE or SU.LIM.LP2CE), the inserted
frame should not contain an Ethernet FCS. The frame loaded into the insertion FIFO should not contain a preamble
or start frame delimiter, as these will be automatically added by the MAC. Frames inserted to the LAN do not pass
through a Decapsulator.
8.17.2.1WAN Insert Forwarding
The WAN Insert Queue can be user assigned to be multiplexed with only one LAN Queue Group. The Group
Scheduler for the assigned LAN Queue Group multiplexes the WAN Insert data with the data from the LAN Queue
Group.
8.17.3 OAM by Ethernet Destination Address (DA)
The device can be configured to directly trap broadcast, management multicast (01:80:C2:xx:xx:xx), and unicast
frames by Ethernet Destination Addresses for extraction by a microprocessor. The host microprocessor can be
user-programmed for parsing, interpreting, and responding to OAM messages.
8.17.4 OAM by IP Address
When a node on the network first tries to send a management frame to the device, the transmitting node would
normally broadcast an ARP request for the unknown IP address, asking for the network to resolve the IP address
to a physical MAC address. The device is able to trap ARP request using the Broadcast address trap. The user
software should examine each ARP request, and when appropriate, insert a frame in response to the ARP request
that will associate the device's management MAC address with the desired IP address. The network then transmits
frames with the DA value of the physical MAC address in the ARP response. The device would then trap the follow-
on frames by MAC (DA) address.
8.17.5 OAM by VLAN Tag
The device can be configured to trap frames with any number of user-programmed VLAN IDs in the VLAN table.
The VLAN table is accessed indirectly through the SU.VTC, SU.VTAA, and SU.VTWD registers. The
SU.VTWD.LVDW bit is used to indicate a VLAN ID (VID) value is to be extracted if received on the LAN interface.
The SU.VTWD.WVQFW bit is used to indicate a VLAN ID (VID) value is to be extracted if received on the WAN
interface. Note that VLAN trapping must also be enabled with the SU.WEM or SU.LPM registers.
8.17.6 SNMP Support
The device can be configured to trap unicast frames for extraction by the microprocessor. The host microprocessor
can be user-programmed for parsing, interpreting, and responding to SNMP messages. Hardware counters are
provided for supporting portions of RFC2819 (RMON), and portions of RFC1213 (MIB-II). See Section 8.19.2 for
more information on the MAC Management counters used for this purpose.
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8.18 Bridging and Filtering
The Automatic Learning and Filtering functions for Ethernet Bridging are only applicable in 10/100Mbps Ethernet
applications. The static DA filtering functions available in the MAC may be used for 1000Mbps applications as
described in Section 8.19.3. The high-level features of the Automatic Learning and Filtering functions are shown
below:
•
•
•
•
•
Supports up to two 10/100 Ethernet Ports
Self-learning filtering table is “shared” between the two LAN Ports (not 2 independent tables)
Supports a continuous stream of 64-byte frames on both ports
Automatically learns up to 4096 MAC Addresses
Provides automatic Address Aging
When enabled, the Automatic Bridge Filter monitors the LAN input data stream to build a Bridge Filter Table based
on Ethernet Source Addresses (SA). A SA learning function allows the device build a table of source addresses
and their associated interface. If the SA of a received frame is not found in the table, then the current SA is stored
in the Bridge Filter Table. The Bridge Filter Table is then used to determine whether to forward or drop each frame
as it is received. If the Destination Address (DA) of a received frame from the LAN is equal to the value of an SA
that is already stored in the Bridge Filter table, the frame is discarded. If no match is found, then the frame is
forwarded to the WAN Groups.
An aging function is used to determine when a SA entry has aged to the point that it is no longer useful. The user
configures an Aging Period in SU.BFC.BFAP[1-9] that defines how long an SA will be stored in the Bridge table.
After that time period, the entry is removed so that the position may used by another SA value. The Aging Period
can be user configured to any value from 1 second to 300 seconds in 1 second steps (300 seconds is the default
setting).
On devices with two Ethernet Ports, one Bridge Filter Table is shared by the 2 LAN Ports. An SA address that is
learned on LAN Port 1 is treated as though it was also learned on LAN Port 2. This has the effect that each frame
DA received on LAN Port 1 is tested against all SAs learned on LAN Port 1 and LAN Port 2 (the same is true for
frame DAs received on LAN Port 2). If a DA matches a stored SA from either port, the frame will be discarded.
If the LAN Trap determines that a frame matches one of the LAN Extract Trap conditions, the frame is forwarded to
the LAN Extract Queue, regardless of whether the Bridge Filter indicates that frame is to be discarded.
8.18.1 Bridge Filter Table Reset
The Bridge Filter Table Reset function is used to clear all of the Bridge Table entries. This function is automatically
triggered at power-up and can be manually triggered by the user by setting SU.BFC.BFTR to 1. During the Bridge
Filter Table Reset operation, traffic will be processed as normal. The user has the option of disabling the LAN Ports
so that there is no traffic during the Bridge Filter Table Reset process or allowing traffic to continue flowing at the
same time as the Bridge Filter Table Reset process. If the user does not disable traffic, then the table may learn
some new entries before the complete table has been reset. The Bridge Filter Table Reset function takes
approximately 64 ms to complete.
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8.19 Ethernet MAC
Indirect addressing is required to access the Ethernet MAC registers. Writing to the Ethernet MAC registers
requires address and data information to be loaded into multiple registers, and the write operation initiated through
a control bit. Reading from the MAC registers requires address information to be loaded into two registers, the read
operation initiated through a control bit. After the read operation completes, data is read from four registers.
Algorithm for Indirect MAC Write Operation:
1) Read SU.MAC1RWC.MCS and verify that a read/write access is not in progress.
2) Write the address for the access into the SU.MAC1AWL and SU.MAC1AWH registers.
3) Write the data to be written into the SU.MAC1WD0-3 registers.
4) Write SU.MAC1RWC = 0x01.
5) Poll SU.MAC1RWC.MCS until the bit is clear, indicating that the write operation has completed.
Algorithm for Indirect MAC Read Operation:
1) Read SU.MAC1RWC.MCS and verify that a read/write access is not in progress.
2) Write the address for the access into the SU.MAC1RADH and SU.MAC1RADL registers.
3) Write SU.MAC1RWC = 0x03.
4) Poll SU.MAC1RWC.MCS until the bit is clear, indicating that the read operation has completed.
5) Read the data from SU.MAC1RD0-SU.MAC1RD3.
Note that only one operation can be initiated (read or write) at one time. Data cannot be written or read from the
MAC registers until the SU.MAC1RWC.MCS bit has been cleared by the device. The MAC Registers are listed in
the following table.
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Table 8-14. MAC Control Registers
INDIRECT ADDRESS
REGISTER
REGISTER DESCRIPTION
0000h
0004h
0008h
000Ch
0010h
0014h
0018h
001Ch
0040h
0044h
0048h
004Ch
0050h
0054h
0058h
005Ch
0060h
0064h
0068h
006Ch
0070h
0074h
0078h
007Ch
0080h
0084h
0088h
008Ch
0090h
0094h
0098h
009Ch
00A0h
00A4h
00A8h
00ACh
00B0h
00B4h
00B8h
00BCh
00C0h
1018h
SU.MACCR
SU.MACFFR
SU.MACHTHR
SU.MACHTLR
SU.GMIIA
MAC CONTROL REGISTER
MAC FRAME FILTER REGISTER
MAC HASH TABLE HIGH REGISTER
MAC HASH TABLE LOW REGISTER
MAC MDIO MANAGEMENT ADDRESS REGISTER
MAC MDIO MANAGEMENT DATA REGISTER
MAC FLOW CONTROL REGISTER
MAC VLAN TAG REGISTER
SU.GMIID
SU.MACFCR
SU.VLANTR
SU.ADDR0H
SU.ADDR0L
SU.ADDR1H
SU.ADDR1L
SU.ADDR2H
SU.ADDR2L
SU.ADDR3H
SU.ADDR3L
SU.ADDR4H
SU.ADDR4L
SU.ADDR5H
SU.ADDR5L
SU.ADDR6H
SU.ADDR6L
SU.ADDR7H
SU.ADDR7L
SU.ADDR8H
SU.ADDR8L
SU.ADDR9H
SU.ADDR9L
SU.ADDR10H
SU.ADDR10L
SU.ADDR11H
SU.ADDR11L
SU.ADDR12H
SU.ADDR12L
SU.ADDR13H
SU.ADDR13L
SU.ADDR14H
SU.ADDR14L
SU.ADDR15H
SU.ADDR15L
SU.PCSCR
MAC FILTER ADDRESS 0 HIGH
MAC FILTER ADDRESS 0 LOW
MAC FILTER ADDRESS 1 HIGH
MAC FILTER ADDRESS 1 LOW
MAC FILTER ADDRESS 2 HIGH
MAC FILTER ADDRESS 2 LOW
MAC FILTER ADDRESS 3 HIGH
MAC FILTER ADDRESS 3 LOW
MAC FILTER ADDRESS 4 HIGH
MAC FILTER ADDRESS 4 LOW
MAC FILTER ADDRESS 5 HIGH
MAC FILTER ADDRESS 5 LOW
MAC FILTER ADDRESS 6 HIGH
MAC FILTER ADDRESS 6 LOW
MAC FILTER ADDRESS 7 HIGH
MAC FILTER ADDRESS 7 LOW
MAC FILTER ADDRESS 8 HIGH
MAC FILTER ADDRESS 8 LOW
MAC FILTER ADDRESS 9 HIGH
MAC FILTER ADDRESS 9 LOW
MAC FILTER ADDRESS 10 HIGH
MAC FILTER ADDRESS 10 LOW
MAC FILTER ADDRESS 11 HIGH
MAC FILTER ADDRESS 11 LOW
MAC FILTER ADDRESS 12 HIGH
MAC FILTER ADDRESS 12 LOW
MAC FILTER ADDRESS 13 HIGH
MAC FILTER ADDRESS 13 LOW
MAC FILTER ADDRESS 14 HIGH
MAC FILTER ADDRESS 14 LOW
MAC FILTER ADDRESS 15 HIGH
MAC FILTER ADDRESS 15 LOW
MAC PCS (CONNECTION) CONTROL REGISTER
MAC MISCELLANEOUS CONTROL REGISTER
SU.MACMCR
Table 8-15. MAC Status Registers
INDIRECT ADDRESS
REGISTER
SU.ANSR
SU.LSR
REGISTER DESCRIPTION
MAC AUTO-NEGOTIATION STATUS REGISTER
MAC MII/RMII/GMII STATUS REGISTER
00C4h
00D8h
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Table 8-16. MAC Counter Registers
INDIRECT ADDRESS
REGISTER
REGISTER DESCRIPTION
0100h
0104h
0108h
010Ch
0110h
0114h
0118h
011Ch
0120h
0124h
0128h
012Ch
0130h
0134h
0138h
013Ch
0140h
0144h
0148h
014Ch
0150h
0154h
0158h
015Ch
0160h
0164h
0168h
016Ch
0170h
0174h
0180h
0184h
0188h
018Ch
0190h
0194h
0198h
019Ch
01A0h
01A4h
01A8h
01ACh
01B0h
01B4h
01B8h
01BCh
01C0h
01C4h
01C8h
01CCh
01D0h
01D4h
01D8h
01DCh
SU.MMCCTRL
SU.MMCRSR
SU.MMCTSR
SU.MMCRIM
SU.MMCTIM
SU.TXBC
MAC MANAGEMENT COUNTER CONTROL REGISTER
MAC MANAGEMENT COUNTER RECEIVE STATUS REGISTER
MAC MANAGEMENT COUNTER TRANSMIT STATUS REGISTER
MAC MANAGEMENT COUNTER RECEIVE INTERRUPT MASK
MAC MANAGEMENT COUNTER TRANSMIT INTERRUPT MASK
MAC MMC TRANSMIT BYTE COUNTER
SU.TXFC
MAC MMC TRANSMIT FRAME COUNTER
TRANSMIT GOOD BROADCAST FRAMES COUNTER
TRANSMIT GOOD MULTICAST FRAMES COUNTER
TRANSMIT 0-64 BYTE FRAME COUNTER
TRANSMIT 65-127 BYTE FRAMES COUNTER
TRANSMIT 128-255 BYTE FRAME COUNTER
TRANSMIT 256-511 BYTE FRAMES COUNTER
TRANSMIT 512-1023 BYTE FRAME COUNTER
TRANSMIT 1024-MAX BYTE FRAMES COUNTER
TRANSMIT UNICAST FRAME COUNTER
TRANSMIT MULTICAST FRAMES COUNTER
TRANSMIT BROADCAST FRAME COUNTER
TRANSMIT UNDERFLOW FRAMES COUNTER
TRANSMIT SINGLE COLLISION FRAME COUNTER
TRANSMIT MULTIPLE COLLISION FRAMES COUNTER
TRANSMIT DEFERRED FRAME COUNTER
TRANSMIT LATE COLLISION FRAMES COUNTER
TRANSMIT EXCESSIVE COLLISION COUNTER
TRANSMIT CARRIER ERROR COUNTER
TRANSMIT GOOD BYTE COUNTER
SU.TXGBFC
SU.TXGMFC
SU.TX0_64
SU.TX65_127
SU.TX128_255
SU.TX256_511
SU.TX512_1K
SU.TX1K_MAX
SU.TXUCAST
SU.TXMFC
SU.TXBFC
SU.TXUFE
SU.TXSNGLCL
SU.TXMLTICL
SU.TXDFRD
SU.TXLTCL
SU.TXXCSVCL
SU.TXCRERR
SU.TXGBC
SU.TXGFC
TRANSMIT GOOD FRAME COUNTER
TRANSMIT EXCESSIVE DEFERRAL COUNTER
TRANSMIT PAUSE FRAME COUNTER
TRANSMIT VLAN FRAME COUNTER
RECEIVE FRAME COUNTER
SU.TXXCSVDF
SU.TXPAUSE
SU.TXVLANF
SU.RXFC
SU.RXBC
SU.RXGBC
SU.RXGBFC
SU.RXMFC
SU.RXCRC
SU.RXALGN
SU.RXRUNT
SU.RXJBBR
SU.RXUNDRSZ
SU.RXOVRSZ
SU.RX0_64
SU.RX65_127
SU.RX128_255
SU.RX256_511
SU.RX512_1K
SU.RX1K_MAX
SU.RXUFC
SU.RXLNERR
SU.RXRANGE
SU.RXPAUSE
SU.RXOVFL
SU.RXVLAN
SU.RXWDOG
RECEIVE BYTE COUNTER
RECEIVE GOOD BYTE COUNTER
RECEIVE GOOD BROADCAST FRAME COUNTER
RECEIVE MULTICAST FRAME COUNTER
RECEIVE CRC ERROR COUNTER
RECEIVE ALIGNMENT ERROR COUNTER
RECEIVE RUNT ERROR COUNTER
RECEIVE JABBER ERROR COUNTER
RECEIVE UNDERSIZE FRAME COUNTER
RECEIVE OVERSIZE FRAME COUNTER
RECEIVE 0-64 BYTE FRAME COUNTER
RECEIVE 65-127 BYTE FRAME COUNTER
RECEIVE 128-255 BYTE FRAME COUNTER
RECEIVE 256-511 BYTE FRAME COUNTER
RECEIVE 512-1023 BYTE FRAME COUNTER
RECEIVE 1024-MAX BYTE FRAME COUNTER
RECEIVE UNICAST FRAME COUNTER
RECEIVE LENGTH ERROR COUNTER
RECEIVE OUT OF RANGE COUNTER
RECEIVE PAUSE FRAME COUNTER
RECEIVE OVERFLOW COUNTER
RECEIVE VLAN FRAME COUNTER
RECEIVE WATCHDOG ERROR COUNTER
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8.19.1 PHY MII Management Block and MDIO Interface
The MII Management Block allows for the host to control up to 32 PHYs, each with 32 registers. The MII block
communicates with the external PHY using 2-wire serial interface composed of MDC (serial clock) and MDIO for
data. The MDIO data is valid on the rising edge of the MDC clock. The Frame format for the MII Management
Interface is shown Figure 8-17. The read/write control of the MII Management is accomplished through the indirect
SU.GMIIA MII Management Address Register and data is passed through the indirect SU.GMIID Data Register.
These indirect registers are accessed through the MAC Control Registers defined in Table 8-14. The MDC clock is
internally generated and runs at 1.67MHz. Note that the device provides a single MII Management port, and all
control registers for this function are located in MAC 1.
Figure 8-17. MII Management Frame
Turn
Opco
de
Preamble
32 bits
Start
Phy Adrs
5 bits
Phy Reg
5 bits
Data
Idle
Aroun
d
2 bits
1
Bit
16
bits
2 bits
2 bits
111...111
111...111
01
01
10
01
PHYA[4:0]
PHYA[4:0]
PHYR[4:0]
PHYR[4:0]
ZZ
10
ZZZZZZZZZ
PHYD[15:0]
Z
Z
READ
WRITE
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8.19.2 Ethernet MAC Management Counters for RFC2819 RMON
RFC2819 RMON EtherStatsEntry Support
VARIABE NAME
etherStatsIndex
etherStatsDataSource
TYPE
Integer32
OBJECT
SUPPORT
User-defined by port
User-defined
IDENTIFIER
Counter32
etherStatsDropEvents
etherStatsOctets
etherStatsPkts
etherStatsBroadcastPkts
etherStatsMulticastPkts
etherStatsCRCAlignErrors
etherStatsUndersizePkts
etherStatsOversizePkts
etherStatsFragments
etherStatsJabbers
SU.RXOVFL + SU.TXUFE
SU.RXBC
SU.RXFC
SU.RXGBFC
SU.RXMFC
SU.RXCRC + SU.RXALGN
SU.RXUNDRSZ
SU.RXOVRSZ
SU.RXRUNT
SU.RXJBBR
SU.TXLTCL + (SU.TXXCSVCL*16) +
SU.TXSNGLCL + (SU.TXMLTICL*2)
SU.RX0_64
SU.RX65_127
SU.RX128_255
Counter32
Counter32
Counter32
Counter32
Counter32
Counter32
Counter32
Counter32
Counter32
Counter32
etherStatsCollisions
etherStatsPkts64Octets
Counter32
Counter32
Counter32
Counter32
Counter32
etherStatsPkts65to127Octets
etherStatsPkts128to255Octets
etherStatsPkts256to511Octets
etherStatsPkts512to1023Octets
SU.RX256_511
SU.RX512_1K
etherStatsPkts1024to1518Octets Counter32
SU.RX1K_MAX
etherStatsOwner
etherStatsStatus
OwnerString User-defined
EntryStatus User-defined
Note that implementations of the SNMP RMON MIB must also implement the system group of MIB-II and the IF-
MIB.
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8.19.3 Programmable Ethernet Destination Address Filtering
In addition to the automatic learning and filtering features described in Section 8.18, the Ethernet MAC has the
capability to filter frames by MAC Destination Address. This feature is available at all data rates. The user may
program up to 16 destination addresses that may be allowed or disallowed.
The following pseudo code is an example enabling static MAC address filter 0 to allow frames with a DA of
12:34:56:78:9A:BC to pass.
Perform an indirect write to MACCR for a basic configuration:
0x004A = 0x00 ; Point to MACCR
0x004B = 0x00
0x0046 = 0x0C
0x0047 = 0x88
0x0048 = 0x00
0x0049 = 0x00
0x004C = 0x01 ; issue write command
Configure MAC Filter #0 to a value of 12:34:56:78:9A:BC and enable it:
0x004A = 0x40 ; Point to ADDR0H
0x004B = 0x00
0x0046 = 0x9A ; Note the byte order of 9A:BC.
0x0047 = 0xBC
0x0048 = 0x00
0x0049 = 0x80
0x004C = 0x01 ; issue write command
0x004A = 0x44 ; Point to ADDR0L
0x004B = 0x00
0x0046 = 0x12 ; Note the byte order of 12:34:56:78
0x0047 = 0x34
0x0048 = 0x56
0x0049 = 0x78
0x004C = 0x01 ; issue write command
Configure the MAC Filtering in MACFCR:
0x004A = 0x04 ; Point to MACFCR
0x004B = 0x00
0x0046 = 0x00 ; 0x01 will disable filtering
0x0047 = 0x00
0x0048 = 0x00
0x0049 = 0x00 ; 0x80 will disable filtering
0x004C = 0x01 ; issue write command
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8.20 Ethernet Frame Encapsulation
The figure below depicts the Layer 1 mapping and Layer 2 protocol encapsulation options available:
IEEE 802.1D Bridge
Traffic
Mgmt
MPLS / VLAN Tagging
GFP-F LAPS cHDLC HDLC
MAC
VCAT
Synchronous Links
802.3
WAN
(PDH Interfaces)
LAN
Side
8.20.1 Transmit Packet Processor (Encapsulator)
The data from each WAN Group is processed by the Transmit Packet Processor (or Encapsulator) before being
transmitted on the Serial interfaces. The Encapsulator performs bit reordering, FCS processing, frame error
insertion, stuffing, frame abort sequence insertion, inter-frame padding, VLAN tag insertion, MPLS tag insertion,
PPP Headers, LAPS Headers, octet removal, and frame scrambling. Each WAN Group’s encapsulation settings
can be independently configured with the PP.EMCR(1-4) registers.
The Encapsulator automatically inserts the inter-frame fill and flag characters based on the selection of
HDLC/cHDLC/LAPS or GFP in PP.EMCR.EPRTSEL. A Line Header Insertion function (in PP.ELHHR and
PP.ELHLR) allows the user to insert Address, Control, and Protocol bytes for HDLC/cHDLC/X.86, or Type and
tHEC bytes for GFP. The Tag 1 Insertion function (in PP.ET1DHR and PP.ET1DLR) allows the user to insert a 4-
byte MPLS tag immediately before the Destination Address (DA). The Tag 2 Insertion function (in PP.ET2DHR and
PP.ET2DLR) allows the user to insert a 4-byte VLAN tag immediately after the Source Address (SA). Any existing
VLAN tags are “pushed” lower in the frame.
HDLC processing can be disabled. Disabling HDLC processing disables FCS processing, frame error insertion,
stuffing, frame abort sequence insertion, and inter-frame fill/padding. Only bit reordering and frame scrambling are
not disabled.
Bit reordering changes the bit order of each byte. If bit reordering is disabled, the outgoing 8-bit data stream
DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output from the Transmit FIFO with the MSB in
TFD[7] (or 15, 23, or 31) and the LSB in TFD[0] (or 8, 16, or 24) of the transmit FIFO data TFD[7:0] 15:8, 23:16, or
31:24). If bit reordering is enabled, the outgoing 8-bit data stream DT[1:8] is output from the Transmit FIFO with the
MSB in TFD[0] and the LSB in TFD[7] of the transmit FIFO data TFD[7:0]. In bit synchronous mode, DT [1] is the
first bit transmitted. Bit reordering is configured using the PP.EMCR.TBRE bit. Note that bit reordering is not
available in the A1 device revision (GL.IDR.REVn=000).
FCS processing, when enabled in PP.EMCR(1-4), appends a calculated FCS to the frame. The polynomial used
for FCS-16 is x16 + x12 + x5 + 1. The polynomial used for FCS-32 is x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 +
x7 + x5 + x4 + x2 + x + 1. The FCS is inverted after calculation. If packet processing is disabled, FCS processing is
not performed.
Frame error insertion inserts errors into the GFP PLI, data unit, or FCS bytes. A single bit is corrupted in each
errored frame. The location of the corrupted bit is user-programmable. Error insertion is controlled by the PP.EEIR
register.
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In HDLC/cHDLC/LAPS(X.86) mode, the inter-frame fill is selectable per WAN group with PP.EMCR.EIIS. If packet
processing is disabled, inter-frame padding is not performed. The frame scrambler is a x43 + 1 scrambler that
scrambles the entire frame data stream. Frame scrambling is selectable per WAN group with PP.EMCR.ECFCRD.
To optimize WAN bandwidth in point-to-point applications, the Ethernet header information may be removed from
the datagram prior to encapsulation. The Encapsulator can be configured to remove either 14 or 18 bytes from
each incoming frame using the PP.EMCR.ERE[1:0] bits. Byte removal starts with the DA field. Removing 14 bytes
will remove the DA, SA, and Length/Type fields. Removing 18 bytes will remove the DA, SA, Length/Type, and
VLAN Tag fields. Once all packet processing has been completed, the serial data stream is forwarded.
Note that some devices in the product family have less than four encapsulators. The DS33X11 contains only
Encapsulator #1. The DS33W41 and DS33X42 contain only encapsulators #1 and #3.
8.20.2 Receive Packet Processor (Decapsulator)
The Receive Packet Processor accepts data from the Receive Serial Interface performs frame descrambling, frame
delineation, inter-frame fill filtering, frame abort detection, destuffing, frame size checking, FCS error monitoring,
FCS byte extraction, and bit reordering. Frame delineation determines the frame boundary by identifying a frame
start or end flag. Receive packet processing can be disabled. Disabling packet processing disables frame
delineation, inter-frame fill filtering, frame abort detection, destuffing, frame size checking, FCS error monitoring,
and FCS byte extraction. Only frame descrambling and bit reordering are not disabled. The frame descrambler is a
self-synchronizing x43 + 1 descrambler.
Inter-frame fill filtering removes the inter-frame fill between frames. When a frame end flag is detected, all data is
discarded until a frame start flag is detected. The inter-frame fill can be flags or all 1s. The number of 1s between
flags does not need to be an integer number of bytes, and if at least seven 1s are detected in the first 16 bits after a
flag, all data after the flag is discarded until a start flag is detected.
Frame abort detection searches for a frame abort sequence between the frame start flag and a frame end flag, if an
abort sequence is detected, the frame is marked with an abort indication, the aborted frame count is incremented,
and all subsequent data is discarded until a valid frame start flag is detected.
Destuffing removes the extra data inserted to prevent data from mimicking a HDLC/cHDLC/X.86 flag or an abort
sequence. A start flag is detected, destuffing is performed until an end flag is detected. The start and end flags are
discarded. In bit synchronous mode, bit destuffing is performed. Bit destuffing consists of discarding any '0' that
directly follows five contiguous 1s. After destuffing is completed, the serial bit stream is forwarded.
Frame size validation checks each frame for a programmable maximum size. As the frame data comes in, the total
number of bytes is counted. If the frame length is below the minimum size limit, the frame is marked with an
aborted indication, and the frame size violation count is incremented. If the frame length is above the maximum
size limit, the frame is marked with an aborted indication, the frame size violation count is incremented, and all
frame data is discarded until a frame start is received. The minimum and maximum lengths include the FCS bytes,
and are determined after destuffing has occurred.
FCS error monitoring checks the FCS and aborts errored frames. If an FCS error is detected, the FCS errored
frame count is incremented and the frame is marked with an aborted indication. If an FCS error is not detected, the
receive frame count is incremented. The FCS type (16-bit or 32-bit) is programmable.
FCS byte extraction discards the FCS bytes. If FCS extraction is enabled, the FCS bytes are extracted from the
frame and discarded. If FCS extraction is disabled, the FCS bytes are stored in the receive FIFO with the frame.
Bit reordering changes the bit order of each byte. Normally, the first bit of each byte in the received data stream is
assumed to be the MSB. If bit reordering is enabled, the first bit of each byte in is assumed to be the LSB. Once all
of the packet processing has been completed, the data stream is passed to the WAN Queues. Bit reordering is
configured using the PP.DMCR.RBRE bit. Note that bit reordering is not available in the A1 device revision
(GL.IDR.REVn=000).
The Decapsulator collects 2 statistics; the number of good frames and number of errored frames due any errors.
These statistics are latched bit counters and are cleared when read by the user.
The Decapsulator must be configured to remove the 4-byte encapsulation line header information if it is present.
The 4-byte removal function is selected using the PP.DMCR.DR1E control bit. When enabled, 4 bytes are removed
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immediately after the cHEC bytes when in GFP mode or after the start flag when in HDLC mode. This bit should be
set to 1 for X.86, cHDLC and GFP transport. This bit should be equal to 0 for HDLC traffic with no headers.
The Decapsulator can be configured to remove a MPLS tag prior to forwarding to the LAN interface. The 4-byte
removal function used for this purpose is enabled using the PP.DMCR.DR2E control bit. When enabled, 4 bytes
are removed after the first remove (DR1E) function. Note that PP.DMCR.DR1E must be properly configured for this
function to operate correctly.
The Decapsulator can be configured to remove a VLAN tag prior to forwarding to the LAN interface. The 4-byte
removal function used for this purpose is enabled using the PP.DMCR.DR3E control bit. When enabled, 12 bytes
are skipped (Ethernet DA/SA) and the following 4 bytes are removed. This function is performed after the
Decapsulator Remove Function 1 and/or Decapsulator Remove Function 2 have been performed. When
Decapsulator Remove Functions 1 and 2 are disabled, 12 bytes are skipped from the beginning of the Ethernet
frame.
To optimize WAN bandwidth in point-to-point applications, Ethernet header information may be removed from the
datagram during WAN transport. The Decapsulator can be configured to replace the missing Ethernet header
information prior to forwarding to the LAN interface, by inserting a 14 or 18 byte values to each incoming frame.
This function is enabled using the PP.DMCR.DAE[1:0] control bits. When enabled, a 14-byte value from the
PP.DA1DR through PP.DA7DR registers or a 18-byte value from the PP.DA1DR through PP.DA9DR registers will
be inserted after the cHEC bytes in GFP mode, or after the HDLC header/flag when in HDLC mode. Once all
packet processing is performed by the Decapsulator, the Ethernet frames are forwarded to the MAC for
transmission on the LAN interface.
Note that some devices in the product family have less than four Decapsulators. The DS33X11 contains only
Decapsulator #1. The DS33W41 and DS33X42 contain only Decapsulators #1 and #3.
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8.20.3 GFP-F Encapsulation and Decapsulation
The GFP-F protocol provides a method for encapsulating Ethernet Frames over point-to-point serial links. The
device expects a frame or multiframe synchronization signal to provide the byte boundary. This is provided by the
RSYNC and TSYNC pins. The receive functional timing is shown Figure 11-13. The transmit functional timing is
shown in Figure 11-9.
GFP-F Encapsulation is selected with the EPRTSEL register bit. However, there are two types of GFP-F: Null and
Linear Extension Mode. The device allows the selection of GFP Linear Extension through a user-configured “GFP
CRC Mode“ bit for each Encapsulator and Decapsulator (PP.EMCR.EGCM and PP.DMCR.DGCM). For each
mode, several additional register settings are required as outlined in the following sections.
In both GFP modes, the Line Header Insertion function (in PP.ELHHR and PP.ELHLR) must be programmed by
the user to insert the required GFP Type and tHEC fields. This structure, which is also known as the GFP Payload
Header, indicates the contents of the encapsulated payload. The Type field consists of sub fields that are used to
indicate the payload type (PTI), Payload FCS Indicator (PFI) Extension Header Identifier (EXI) and User Payload
Identifier (UPI).
Table 8-17. GFP Type/tHEC Field (Payload Header) Definition
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit #
Frame Byte Number
5 & 6
7 & 8
PTI
PFI
tHEC
EXI
UPI
tHEC
15
0
The PTI field will normally be programmed to 000b for subscriber traffic. A PTI of 100b may be used for
management traffic in some applications. The PFI bit should match the user configured setting for pFCS in
PP.DMCR.DFCSAD and PP.EMCR.EFCSAD. A PFI value of 1 indicates that the payload includes a pFCS. The
EXI bits should equal 0000b for GFP Null, and 0001b for GFP Linear Extension. The UPI field should be configured
to match the type of traffic being transported. Possible UPI values are shown in the table below.
Table 8-18. GFP UPI Definitions
UPI bits <7:0>
GFP Payload Information
Frame-Mapped Ethernet
0000 0001
0000 0010
Frame-Mapped PPP
0000 1000
Frame-Mapped Multiple Access Protocol over SDH (MAPOS)
Frame-Mapped MPLS (Unicast)
Frame-Mapped MPLS (Multicast)
Frame-Mapped IS-IS
0000 1101
0000 1110
0000 1111
0001 0000
Frame-Mapped IPv4
0001 0001
Frame-Mapped IPv6
1111 0000 through 1111 1110
Reserved for proprietary use
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The final two bytes of the TYPE/tHEC field are used to perform header validation. The tHEC calculation is a CRC-
16 operation in which the two byte PLI is multiplied by X16 and divided (modulo 2) by the polynomial X16+X12+X5+1.
Another common representation for this polynomial is 0x1021. The initialization value for the operation is 0x0000.
The MSB of the PLI is bit 16, and the resulting remainder of the operation is the tHEC. To avoid requiring this
algorithm implementation in the user’s software, some common Type and the corresponding tHEC values are
provided in the table below.
Table 8-19. Example GFP Type + tHEC Values
Configuration
GFP Type (hex)
1001
tHEC (hex)
1352
Client Data, Includes pFCS, GFP Null, Ethernet
Client Data, No pFCS, GFP Null, Ethernet
Client Data, Includes pFCS, GFP Linear, Ethernet
Client Data, No pFCS, GFP Linear, Ethernet
Management Data, Includes pFCS, GFP Null, Ethernet
Management Data, No pFCS, GFP Null, Ethernet
Management Data, Includes pFCS, GFP Linear, Ethernet
Management Data, No pFCS, GFP Linear, Ethernet
0001
1021
1101
2063
0101
2310
9001
08CA
0BB9
3BFB
3888
8001
9101
8101
When receiving either GFP Null or GFP Linear Extension frames from the WAN, the PP.DMCR.DR1E bit should be
set to 1 in order to remove the incoming GFP Type and tHEC bytes from the data stream.
The ITU-T G.8040 specification requires that when using GFP over a PDH link, the VCAT byte position must not be
used for payload information. The reservation or usage of the VCAT byte position is selected via the
VCAT.TCR3.TNVCGC bit.
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8.20.3.1GFP-F NULL
When configured for GFP Null operation, no additional header information is required. The Encapsulator’s Tag 1
Insertion function (in PP.ET1DHR and PP.ET1DLR) is available to insert a 4-byte MPLS tag immediately before the
Ethernet Destination Address (DA), and the Tag 2 Insertion function (in PP.ET2DHR and PP.ET2DLR) is available
to insert a 4-byte VLAN tag immediately after the Source Address (SA). Any existing VLAN tags are “pushed” lower
in the frame. The resulting encapsulated frame format is shown below. Note that when enabled in this mode, the
pFCS calculation begins with the 9th byte of the frame.
Figure 8-18. GFP-F NULL Encapsulated Frame Format
Bytes
GFP Payload Length (PLI)
GFP cHEC
2
2
1
1
1
1st Octet of GFP Type
2nd Octet of GFP Type
1st Octet of GFP tHEC
2nd Octet of GFP tHEC
Destination Address (DA)
Source Address (SA)
1
6
6
4
VLAN TAG (optional)
Q-in-Q VLAN TAG (existing/optional)
Length / EtherType
4
2
MAC Client Data
PAD (optional)
46-1500
FCS for MAC
4
4
GFP Payload FCS (optional)
MSB
LSB
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8.20.3.2GFP-F Linear Extension
When configured for GFP Linear Extension mode, an additional header is required. The Encapsultor’s Tag 1
Insertion function (in PP.ET1DHR and PP.ET1DLR, enabled with PP.EMCR.ET1E) is used to insert the 4-byte
GFP Extension Header value. If receiving GFP Linear Extension frames from the WAN, the PP.DMCR.DR2E bit
should be set to 1 in order to remove the incoming GFP CID, Spare, and eHEC bytes from the data stream.
Table 8-20. GFP CID/Spare/eHEC (Extension Header) Field Definition
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit #
Frame Byte Number
9 & 10
CID
eHEC
SPARE
eHEC
11 & 12
15
0
The final two bytes of the Linear Extension Header field are used to perform header validation. The eHEC
calculation is a CRC-16 operation in which the two byte CID (and Spare) value is multiplied by X16 and divided
(modulo 2) by the polynomial X16+X12+X5+1. Another common representation for this polynomial is 0x1021. The
initialization value for the operation is 0x0000. The MSB of the CID is bit 16, and the resulting remainder of the
operation is the eHEC. To avoid requiring this algorithm implementation in the user’s software, several example
CID + Spare values and the corresponding eHEC values are provided in the table below.
Table 8-21. Example CID + Spare + eHEC Values
CID + Spare
(hex)
eHEC (hex)
0000
0100
0200
0400
0800
1000
2000
4000
8000
FF00
0000
3331
6662
CCC4
89A9
0373
06E6
0DCC
1B98
03FF
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The Encapsulator’s Tag 2 Insertion function (in PP.ET2DHR and PP.ET2DLR) is available to insert a 4-byte VLAN
tag immediately after the Source Address (SA). Any existing VLAN tags are “pushed” lower in the frame. The
resulting encapsulated frame format is shown below. Note that when in this mode, the pFCS calculation begins
with the 13th byte of the frame. The received eHEC value is verified by the Decapsulator. While in Linear mode, if
the eHEC verification fails, the received WAN packet is discarded.
Figure 8-19. GFP-F LINEAR EXTENSION Encapsulated Frame Format
Bytes
GFP Payload Length (PLI)
GFP cHEC
2
2
1
1
1
1st Octet of GFP Type
2nd Octet of GFP Type
1st Octet of GFP tHEC
2nd Octet of GFP tHEC
GFP CID, Spare, & eHEC
Destination Address (DA)
Source Address (SA)
1
4
6
6
4
4
VLAN TAG (optional)
Q-in-Q VLAN TAG (existing/optional)
Length / EtherType
2
MAC Client Data
PAD (optional)
46-1500
FCS for MAC
4
4
GFP Payload FCS (optional)
MSB
LSB
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8.20.4 X.86 Encoding and Decoding
X.86 protocol provides a method for encapsulating Ethernet Frame for eventual transport on a SONET or SDH
network. LAPS provides a byte-synchronous HDLC-like framing structure for encapsulation of Ethernet frames, but
is not as susceptible to dynamic bandwidth expansion as bit-stuffed HDLC. LAPS encapsulated frames can be
used to send data onto a SONET/SDH network. The device expects a byte synchronization signal to provide the
byte boundary for the X.86 receiver. This is provided by the RSYNC pin. The functional timing is shown Figure
11-13. The X.86 transmitter provides a byte boundary indicator with the signal TSYNC. The functional timing is
shown in Figure 11-9.
A Line Header Insertion function (in PP.ELHHR and PP.ELHLR) allows the user to insert Address, Control, and
SAPI bytes. The Tag 1 Insertion function (in PP.ET1DHR and PP.ET1DLR) allows the user to insert a 4-byte MPLS
tag immediately before the Destination Address (DA). The Tag 2 Insertion function (in PP.ET2DHR and
PP.ET2DLR) allows the user to insert a 4-byte VLAN tag immediately after the Source Address (SA). Any existing
VLAN tags are “pushed” lower in the frame.
Figure 8-20. LAPS / X.86 Encapsulated Frame Format
Bytes
Flag(0x7E)
Address(0x04)
1
1
1
1
Control(0x03)
1st Octet of SAPI(0xFE)
2nd Octet of SAPI(0x01)
MPLS TAG (optional)
Destination Address (DA)
Source Address (SA)
VLAN TAG (optional)
Q-in-Q VLAN TAG (existing/optional)
Length / EtherType
1
4
6
6
4
4
2
MAC Client Data
PAD (optional)
46-1500
FCS for MAC
FCS for LAPS
Flag(0x7E)
4
4
1
MSB
LSB
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The device will encode the MAC Frame with X.86 / LAPS encapsulation on a complete serial stream if configured
for X.86 mode in the register PP.EMCR. The device provides the following functions:
•
•
•
•
32 bit FCS
X43+1 Scrambling/Descrambling
Transparency Processing
Rate Adaptation Removal.
Received frames are aborted if:
•
•
•
•
•
If 7d,7E is detected. This is an abort frame sequence in X.86
Invalid FCS is detected
The received frame has less than 6 octets
Control, SAPI and address field are mismatched to the programmed value
Octet 7D and octet other than 5D,5E,7E or DD is detected
When in X.86 mode, the device encapsulates frames with a Start Flag (7Eh), Address, Control and SAPI field,
followed by the frame and a 32-bit FCS. A X43+1 scrambler scrambles the data. Between the Start and Stop flags,
data bytes matching the start/abort flag is replaced with a 2-byte escape sequence. Figure 8-20 shows a frame
Encapsulated in a LAPS Frame. Options for MPLS and VLAN and Q-in-Q information bytes are user configured. In
the receive direction, rate adaptation octets are removed. In the transmit direction, idle code fill is used, and rate
adaptation is not performed. The Encapsulator performs transparency processing or octet stuffing to ensure that
the data does not mimic flags. For transparency processing, 7Eh is translated to 7D 5Eh and 7Dh is translated to
7D 5Dh. Byte stuffing consists of detecting bytes that mimic flag and escape sequence bytes (7Eh and 7Dh), and
replacing the mimic bytes with an escape sequence (7Dh) followed by the mimic byte exclusive 'OR'ed with 20h.
Rev: 063008
95 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
8.20.5 HDLC Encoding and Decoding
The HDLC protocol provides a simple method for encapsulating Ethernet Frames over point-to-point serial links.
HDLC Encapsulation can be bit or byte synchronous. In byte synchronous mode, byte stuffing is performed. Byte
stuffing consists of detecting bytes that mimic flag and escape sequence bytes (7Eh and 7Dh), and replacing them
with an escape sequence (7Dh) followed by the byte ‘exclusive-OR’ed’ with 20h. In Bit Synchronous HDLC, 5
consecutive ones must always be followed by a 0 to avoid mimicking a start or stop flag. Note that the 5
consecutive ones can straddle any 2 consecutive bytes. HDLC frame Encapsulation of the frame is shown in
Figure 8-21.
A Line Header Insertion function (in PP.ELHHR and PP.ELHLR) allows the user to insert Address, Control, and
Protocol bytes. The Tag 1 Insertion function (in PP.ET1DHR and PP.ET1DLR) allows the user to insert a 4-byte
MPLS tag immediately before the Destination Address (DA). The Tag 2 Insertion function (in PP.ET2DHR and
PP.ET2DLR) allows the user to insert a 4-byte VLAN tag immediately after the Source Address (SA). Any existing
VLAN tags are “pushed” lower in the frame.
The device provides the following HDLC functions.
•
•
•
•
Insertion of HDLC flags
Performs HDLC bit and byte stuffing
Insertion of Payload FCS (32 bit / 16 bit)
Selectable X43+1 scrambling
•
Selectable Idle: All Ones or Flag insertion
HDLC Receive Compatibility:
•
•
•
•
•
•
•
•
•
HDLC with no line headers and encapsulated Ethernet Frames.
HDLC with LAPS Headers.
HDLC with Cisco HDLC Headers.
HDLC Encapsulated Ethernet Frames with VLAN Tags .
HDLC Encapsulated Ethernet Frames with MPLS Headers.
Bit or Byte Synchronous Stuffed HDLC
HDLC FCS lengths of 0, 16, or 32 bits.
Interframe fill can be 7Eh or all 1s.
X43+1 scrambled frame.
Rev: 063008
96 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 8-21. HDCL Encapsulated Frame Format
Bytes
Flag(0x7E)
Address (optional)
1
1
1
1
Control (optional)
1st Octet of Protocol (optional)
2nd Octet of Protocol (optional)
MPLS TAG (optional)
1
4
6
6
4
4
Destination Address (DA)
Source Address (SA)
VLAN TAG (optional)
Q-in-Q VLAN TAG (existing/optional)
Length / EtherType
2
MAC Client Data
PAD (optional)
46-1500
FCS for MAC
FCS (optional)
Flag(0x7E)
4
0 / 2 / 4
1
MSB
LSB
Rev: 063008
97 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
8.20.6 cHDLC Encoding And Decoding
The cHDLC protocol provides a simple method for encapsulating Ethernet Frames over point-to-point serial links.
A Line Header Insertion function (in PP.ELHHR and PP.ELHLR) allows the user to insert Address, Control, and
Protocol bytes. The Tag 1 Insertion function (in PP.ET1DHR and PP.ET1DLR) allows the user to insert a 4-byte
MPLS tag immediately before the Destination Address (DA). The Tag 2 Insertion function (in PP.ET2DHR and
PP.ET2DLR) allows the user to insert a 4-byte VLAN tag immediately after the Source Address (SA). Any existing
VLAN tags are “pushed” lower in the frame.
Figure 8-22. cHDLC Encapsulated Frame Format
Bytes
Flag(0x7E)
Address (0x0F)
1
1
1
1
Control (0x00)
1st Octet of Protocol
2nd Octet of Protocol
MPLS TAG (optional)
Destination Address (DA)
Source Address (SA)
VLAN TAG (optional)
Q-in-Q VLAN TAG (existing/optional)
Length / EtherType
1
4
6
6
4
4
2
MAC Client Data
PAD (optional)
46-1500
FCS for MAC
FCS (optional)
Flag(0x7E)
4
0 / 2 / 4
1
MSB
LSB
Rev: 063008
98 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
8.21 CIR/CBS Controller
The device provides a Committed Information Rate (CIR) / Committed Burst Rate (CBS) provisioning facility. The
CIR/CBS can be used to restrict the transport of received MAC data to a specific rate. The CIR will restrict the data
flow from the Receive MAC to Transmit Packet Processor. Policing parameters are user-defined in the SU.L1PP
and SU.L2PP registers. The data rate increments for CIR/CBS provision that are available to the user are based on
the operational data rate and are approximately: 64kbps from DC to 2Mbps, 2Mbps from 2Mbps to 64Mbps, and
16Mbps from 16Mbps to 416Mbps. The CIR function is based on a time-averaged value of bytes transmitted. When
the CIR is enabled, the average bytes per second of Ethernet traffic forwarded to the serial WAN interfaces is
limited to the configured CIR. The transmit CBS for all CIR settings is selectable using SU.L1PP.CBSS and
SU.L2PP.CBSS.
Some details regarding operation of the CIR are as follows:
•
•
The maximum value of CIR cannot effectively exceed the aggregate serial transmit line rate.
If the data rate received from the Ethernet interface is higher than the CIR, the device can be configured to
invoke flow control or to discard frames to reduce the forwarded traffic rate.
•
CIR function is only available for data received at the Ethernet Interface to be forwarded to WAN. There is
not a CIR function for data arriving from the WAN to be sent to the Ethernet Interface.
The user provides the following configuration parameters:
Parameter
Configured settings
Description
Off
Enables/Disables the CIR/CBS Policing function.
Enables Pause flow control when CIR is exceeded.
Policing
Policing Pause Enabled
Policing Discard Enabled Enabled Discarding of frames when CIR is exceeded.
Operating
Range
64kbps to 2Mbps
2Mbps to 64Mbps
16Mbps to 416Mbps
Low-Range CIR.
Mid-Range CIR.
High-Range CIR.
This setting allows approximate incremental steps of:
CIR Credit
Threshold
64kbps each LSB, for the 64kbps to 2Mbps operating range
2Mbps each LSB, for the 2Mbps to 64Mbps operating range
16Mbps each LSB, for the 16Mbps to 416Mbps operating range
8-bit value
Rev: 063008
99 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Table 8-22. Credit Threshold Settings with Resulting Bandwidths
Low-Range CIR
Mid-Range CIR
High-Range CIR
Credit
Threshold
243
121
80
CIR
Credit
Threshold
249
124
82
CIR
Credit
Threshold
249
124
82
CIR
Bandwidth
64.04E+3
128.07E+3
192.90E+3
256.15E+3
318.88E+3
381.10E+3
446.43E+3
504.03E+3
578.70E+3
651.04E+3
710.23E+3
781.25E+3
822.37E+3
919.12E+3
976.56E+3
1.04E+6
Bandwidth
2.00E+6
Bandwidth
16.00E+6
32.00E+6
48.19E+6
63.49E+6
80.00E+6
95.24E+6
111.11E+6
129.03E+6
142.86E+6
148.15E+6
173.91E+6
190.48E+6
210.53E+6
222.22E+6
235.29E+6
250.00E+6
266.67E+6
285.71E+6
307.69E+6
333.33E+6
363.64E+6
400.00E+6
4.00E+6
6.02E+6
60
62
7.94E+6
62
48
49
10.00E+6
11.90E+6
13.89E+6
16.13E+6
17.86E+6
18.52E+6
21.74E+6
23.81E+6
26.32E+6
27.78E+6
29.41E+6
31.25E+6
33.33E+6
35.71E+6
38.46E+6
41.67E+6
45.45E+6
50.00E+6
55.56E+6
62.50E+6
49
40
41
41
34
35
35
30
30
30
26
27
27
23
26
26
21
22
22
19
20
20
18
18
18
16
17
17
15
16
16
14
15
15
13
1.12E+6
14
14
12
1.20E+6
13
13
11
1.30E+6
12
12
10
1.42E+6
11
11
9
1.56E+6
10
10
9
1.56E+6
9
9
8
1.74E+6
8
7
1.95E+6
7
Rev: 063008
100 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
9.
Applications Information
9.1
Interfacing to Maxim T1/E1 Transceivers
The devices in the DS33X162 product family can be seamlessly connected to Maxim T1/E1 transceivers, without
the need for additional external components. The diagram below depicts the electrical connections between the
devices.
Figure 9-1. Interfacing with T1/E1 Transceivers
TSER(I)
TCHCLK(O)
TSYNC(O)
TDATA(O)
TCLK(I)
TSYNC(I)
MAXIM
T1/E1 Transceiver
DS33X162/X82/X81
/X42/X41/X11/W41
/W11
RSER(O)
RCHCLK(O)
RSYNC(O)
RDATA(I)
RCLK(I)
RSYNC(I)
Figure 9-2. Example Functional Timing: DS2155 E1 Transmit-Side Boundary Timing
TCLK
TCHCLK
FRAMING BYTE / CHANNEL 0
LSB MSB
CHANNEL 1
LSB MSB
LSB MSB
TSER
TSYNC
* Note DS2155 TCLK shown only for comparative purposes.
Rev: 063008
101 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 9-3. Example Functional Timing: DS2155 T1 Transmit-Side Boundary Timing
TCLK
TCHCLK
TIME SLOT 1
TIME SLOT 2
LSB
X
MSB
LSB MSB
LSB MSB
TSER
TSYNC
* Note DS2155 TCLK shown only for comparative purposes.
Figure 9-4. Example Functional Timing: DS2155 E1 Receive-Side Boundary Timing
RCLK
RCHCLK
CHANNEL 32
FRAMING BYTE / CHANNEL 0
CHANNEL 1
MSB
LSB
MSB
LSB
RSER
RSYNC
* Note DS2155 RCLK shown only for comparative purposes.
Figure 9-5. Example Functional Timing: DS2155 T1 Receive-Side Boundary Timing
RCLK
RCHCLK
TIME SLOT 24
TIME SLOT 1
TIME SLOT 2
MSB
LSB
MSB
LSB
F
RSER
RSYNC
* Note DS2155 RCLK shown only for comparative purposes.
When interfacing to a Maxim T1/E1 transceiver as shown, the device should be programmed to invert the RCLK
input for each serial interface (LI.RCR1.RCLKINV = 1).
Because the first gapped transmit clock input edge after the transmit sync pulse is coincident with the start of the
first byte of user data, the transmit sync setup control bits must be configured for a sync pulse that arrives zero
clock cycles early ( LI.TCR.TS_SETUP[1:0] = 00).
Rev: 063008
102 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
9.2
Interfacing to Maxim T3/E3 Transceivers
The devices in the DS33X162 product family can be seamlessly connected to Maxim T3/E3 transceivers, without
the need for additional external components. The diagram below depicts the electrical connections between the
devices.
Figure 9-6. Interfacing with T3/E3 Transceivers
TSER(I)
TGCLK(O)
TSOFO(O)
TDATA(O)
TCLK(I)
TSYNC(I)
Dallas
Semiconductor
T3/E3 Transceiver
DS33X162/X82/X81
/X42/X41/X11/W41
/W11
RDATA(I)
RCLK(I)
RSYNC(I)
RSER(O)
RGCLK(O)
RSOFO(O)
Figure 9-7. Example Functional Timing: DS3170 DS3 Transmit-Side Boundary Timing
Rev: 063008
103 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 9-8. Example Functional Timing: DS3170 DS3 Receive-Side Boundary Timing
RCLKO or
RCLKI
RSOFO
DS3 RGCLK
DS3 RSER
DS3 RDEN
X1
4
1
2
3
5
6
7
8
9
10 11 12 13 14 15
Because the third gapped transmit clock input edge after the transmit sync pulse is coincident with the start of the
first byte of user data, the transmit sync setup control bits must be configured for a sync pulse that arrives three
clock cycles early ( LI.TCR.TS_SETUP[1:0] = 11).
Rev: 063008
104 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
10. Device Registers
Eleven address bits are used address the register space. The register map is shown in Table 10-1. The
addressable range is 000h-7FFh. Register address locations are shared across the product family to preserve
software compatibility. The Serial Interface (Line) Registers are used to configure the serial port and the associated
transport protocol. The Ethernet Interface (Subscriber) registers are used to control and observe each of the
Ethernet ports. The registers associated with the MAC must be configured through indirect register write /read
access due to the architecture of the device.
When writing to a register input values for unused bits and registers (those designated with “–“) should be zero
unless specifically noted otherwise, as these bits and registers are reserved. When a register is read from, the
values of the unused bits and registers should be ignored. A latched status bit is set when an event happens and is
cleared when read.
Note that although most registers are defined as 16-bit registers, the constituent bytes are accessed through the
parallel or SPI interfaces one byte at a time. Individual address locations are defined for each byte. The register
details are provided in the following tables.
Table 10-1. Register Address Map
REGISTER
Global registers
Microport Block
MAC 1 Port
MAC 2 Port
Common VLAN Table
Transmit LAN
Receive LAN
ADDRESS RANGE
000h – 01Fh
020h – 03Fh
040h – 05Fh
060h – 07Fh
080h – 09Fh
0A0h – 0BFh
0C0h – 0FFh
100h – 1FFh
200h – 2FFh
300h – 3FFh
400h – 4FFh
500h – 5FFh
600h – 63Fh
640h – 6FFh
740h – 7FFh
Buffer Manager
Packet Processors (Encapsulators)
Packet Processors (Decapsulators)
Transmit VCAT/LCAS
Receive VCAT/LCAS
Serial Ports – Global
Serial Ports – Transmit & Voice
Serial Ports – Receive & Voice
Rev: 063008
105 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
10.1 Register Bit Maps
10.1.1 Global Register Bit Map
Table 10-2. Global Register Bit Map
ADDR Name
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
GLOBAL REGISTERS
000h
WP4
WP3
WP2
WP1
WP0
GBE
MP1
MP0
GL.IDR
001h
REV2
REV1
REV0
SPIS
VC2
-
VC1
FMC-2
-
VC0
VCAT
002h
-
-
-
-
FMC-1
FMC-0
GL.CR1
003h
-
-
P2SPD0
-
P1SPD
INTM
-
-
-
-
-
RST
-
004h
-
-
-
-
ENDEL
-
GL.CR2
005h
-
-
-
-
008h
-
BUFIS
DECIS4
BUFIE
DECIE4
-
-
TSPIS
DECIS2
TSPIE
DECIE2
-
DECIS1
ECIS4
DECIE1
ECIE4
-
ECIS1
ECIS3
ECIE1
ECIE3
-
TXLANIS RXLANIS
ECIS2 RVCATIS
TXLANIE RXLANIE
GL.ISR
009h
MICIS
DECIS3
00Ah
-
-
GL.IER
00Bh
MICIE
DECIE3
ECIE2
RVCATIE
00Ch
-
-
-
-
-
-
-
-
GL.MBSR
00Dh
-
-
DLOCK
PLOCK
MICROPORT REGISTERS
020h
-
-
-
-
-
-
FIFO1
-
FIFO0
-
GL.MCR1
021h
-
-
-
-
-
-
022h
WILEN7
WILEN6
WILEN5
WILEN4
WILEN3
WILEN2
WILEN1
WILEN0
WILEN8
LILEN0
LILEN8
GL.MCR2
023h
-
-
-
-
WILEN11 WILEN10 WILEN9
024h
LILEN7
-
LILEN6
-
LILEN5
-
LILEN4
-
LILEN3
LILEN2
LILEN1
LILEN9
GL.MCR3
025h
LILEN11
LILEN10
026h
WELEN7 WELEN6 WELEN5 WELEN4 WELEN3 WELEN2 WELEN1 WELEN0
GL.MSR1
027h
-
-
-
-
WELEN11 WELEN10 WELEN9 WELEN8
028h
LELEN7
LELEN6
LELEN5
LELEN4
LELEN3
LELEN2
LELEN1
LELEN0
LELEN8
WANIE
-
GL.MSR2
029h
-
-
-
-
LELEN11 LELEN10 LELEN9
02Ah
-
-
-
-
LANEA
LANIE
WANEA
-
GL.MSR3
02Bh
-
-
-
-
-
-
02Ch
-
-
-
-
LANEAL
-
LANIEL
-
WANEAL WANIEL
GL.MLSR3
02Dh
-
-
-
-
-
-
02Eh
-
-
-
-
LANEAIE LANIEIE WANEAIE WANIEIE
GL.MSIER3
02Fh
-
-
-
-
-
-
-
-
030h
WPKT7
WPKT6
WPKT5
WPKT4
WPKT3
WPKT2
WPKT1
RD_DN
RPKT1
-
WPKT0
WR_DN
RPKT0
-
GL.MFAWR
031h
-
-
-
-
-
-
032h
RPKT7
-
RPKT6
-
RPKT5
-
RPKT4
-
RPKT3
-
RPKT2
-
GL.MFARR
033h
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MAC 1 INTERFACE PORT
040h
041h
042h
043h
044h
045h
046h
047h
048h
049h
04Ah
04Bh
04Ch
SU.MAC1RADL
MACRA7 MACRA6 MACRA5 MACRA4 MACRA3 MACRA2 MACRA1 MACRA0
SU.MAC1RADH MACRA15 MACRA14 MACRA13 MACRA12 MACRA11 MACRA10 MACRA9 MACRA8
MACRD7 MACRD6 MACRD5 MACRD4 MACRD3 MACRD2 MACRD1 MACRD0
MACRD15 MACRD14 MACRD13 MACRD12 MACRD11 MACRD10 MACRD9 MACRD8
MACRD23 MACRD22 MACRD21 MACRD20 MACRD19 MACRD18 MACRD17 MACRD16
MACRD31 MACRD30 MACRD29 MACRD28 MACRD27 MACRD26 MACRD25 MACRD24
MACWD7 MACWD6 MACWD5 MACWD4 MACWD3 MACWD2 MACWD1 MACWD0
MACWD15 MACWD14 MACWD13 MACWD12 MACWD11 MACWD10 MACWD09 MACWD08
MACWD23 MACWD22 MACWD21 MACWD20 MACWD19 MACWD18 MACWD17 MACWD16
MACD31 MACD30 MACD29 MACD28 MACD27 MACD26 MACD25 MACD24
MACAW7 MACAW6 MACAW5 MACAW4 MACAW3 MACAW2 MACAW1 MACAW0
MACAW15 MACAW14 MACAW13 MACAW12 MACAW11 MACAW10 MACAW9 MACAW8
SU.MAC1RD0
SU.MAC1RD1
SU.MAC1RD2
SU.MAC1RD3
SU.MAC1WD0
SU.MAC1WD1
SU.MAC1WD2
SU.MAC1WD3
SU.MAC1AWL
SU.MAC1AWH
SU.MAC1RWC
-
-
-
-
-
-
MCRW
MCS
MAC 2 INTERFACE PORT
060h
061h
062h
063h
064h
065h
066h
067h
068h
069h
06Ah
06Bh
06Ch
SU.MAC2RADL
MACRA7 MACRA6 MACRA5 MACRA4 MACRA3 MACRA2 MACRA1 MACRA0
MACRA15 MACRA14 MACRA13 MACRA12 MACRA11 MACRA10 MACRA9 MACRA8
MACRD7 MACRD6 MACRD5 MACRD4 MACRD3 MACRD2 MACRD1 MACRD0
MACRD15 MACRD14 MACRD13 MACRD12 MACRD11 MACRD10 MACRD9 MACRD8
MACRD23 MACRD22 MACRD21 MACRD20 MACRD19 MACRD18 MACRD17 MACRD16
MACRD31 MACRD30 MACRD29 MACRD28 MACRD27 MACRD26 MACRD25 MACRD24
MACWD7 MACWD6 MACWD5 MACWD4 MACWD3 MACWD2 MACWD1 MACWD0
MACWD15 MACWD14 MACWD13 MACWD12 MACWD11 MACWD10 MACWD09 MACWD08
MACWD23 MACWD22 MACWD21 MACWD20 MACWD19 MACWD18 MACWD17 MACWD16
MACD31 MACD30 MACD29 MACD28 MACD27 MACD26 MACD25 MACD24
MACAW7 MACAW6 MACAW5 MACAW4 MACAW3 MACAW2 MACAW1 MACAW0
MACAW15 MACAW14 MACAW13 MACAW12 MACAW11 MACAW10 MACAW9 MACAW8
SU.MAC2RADH
SU.MAC2RD0
SU.MAC2RD1
SU.MAC2RD2
SU.MAC2RD3
SU.MAC2WD0
SU.MAC2WD1
SU.MAC2WD2
SU.MAC2WD3
SU.MAC2AWL
SU.MAC2AWH
SU.MAC2RWC
-
-
-
-
-
-
MCRW
MCS
COMMON VLAN TABLE CONTROL
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
-
-
-
-
-
CTE
-
CI
-
CAIM
-
SU.VTC
-
-
-
-
-
VTAA8
VTAA7
VTAA6
VTAA5
VTAA4
VTAA12
LVDW
-
VTAA3
VTAA11
LVEFW
-
VTAA2
VTAA10
VTAA1
VTAA9
SU.VTAA
SU.VTWD
SU.VTRD
SU.VTSA
-
-
-
-
WVQFW
-
-
-
WVEFW
LVQFW2 LVQFW1
-
-
-
-
-
-
-
WVEFR
WVQFR
-
LVDR
-
LVEFR
-
LVQFR2
-
LVQFR1
-
-
-
-
VTSA8
-
VTSA7
-
VTSA6
-
VTSA5
VTIS
VTSA4
VTSA12
VTSA3
VTSA11
VTSA2
VTSA10
VTSA1
VTSA9
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TRANSMIT LAN AND WAN EXTRACTION
0A0h
WNVDF
WEFR
WEDS2
WEDS1
WEVIT
WEETT
-
WEDAT
WEHT
WBAT
SU.WEM
0A1h
-
-
-
-
-
WMGMTT
0A2h
-
-
-
WEHTH
-
WEHTL
-
WEHTP3 WEHTP2 WEHTP1
SU.WEHTP
0A3h
-
-
-
-
-
-
0A4h
WEHT8
WEHT7
WEHT6
WEHT5
WEHT4
WEHT3
WEHT2
WEHT1
WEHT9
SU.WEHT
0A5h
WEHT16 WEHT15 WEHT14 WEHT13 WEHT12 WEHT11 WEHT10
0A6h
WEDAL8 WEDAL7 WEDAL6 WEDAL5 WEDAL4 WEDAL3 WEDAL2 WEDAL1
WEDAL16 WEDAL15 WEDAL14 WEDAL13 WEDAL12 WEDAL11 WEDAL10 WEDAL9
WEDAM8 WEDAM7 WEDAM6 WEDAM5 WEDAM4 WEDAM3 WEDAM2 WEDAM1
WEDAM16 WEDAM15 WEDAM14 WEDAM13 WEDAM12 WEDAM11 WEDAM10 WEDAM9
WEDAH8 WEDAH7 WEDAH6 WEDAH5 WEDAH4 WEDAH3 WEDAH2 WEDAH1
WEDAH16 WEDAH15 WEDAH14 WEDAH13 WEDAH12 WEDAH11 WEDAH10 WEDAH9
WEDAX8 WEDAX7 WEDAX6 WEDAX5 WEDAX4 WEDAX3 WEDAX2 WEDAX1
SU.WEDAL
0A7h
0A8h
SU.WEDAM
0A9h
0AAh
SU.WEDAH
0ABh
0ACh
SU.WEDAX
0ADh
-
-
-
-
-
-
-
-
0AEh
WEET8
WEET7
WEET6
WEET5
WEET4
WEET3
WEET2
WEET1
WEET9
WETPID1
SU.WEET
0AFh
WEET16 WEET15 WEET14 WEET13 WEET12 WEET11 WEET10
WETPID8 WETPID7 WETPID6 WETPID5 WETPID4 WETPID3 WETPID2
0B2h
SU.WETPID
0B3h
WETPID16 WETPID15 WETPID14 WETPID13 WETPID12 WETPID11 WETPID10 WETPID9
0B4h
-
-
-
-
-
-
-
-
WEOS
-
SU.WOS
0B5h
-
-
-
-
-
-
0B6h
-
-
-
LIFR
LIIP2
LP2R
-
LIIP1
LP1R
-
LIP
LIE
SU.LIM
0B7h
-
-
-
-
LP2CE
-
LP1CE
WEOM
-
0B8h
-
-
-
-
SU.WOM
0B9h
-
-
-
-
-
-
-
0BAh
-
LTCC3
LTJTO
LTCC3
LTJTO
LTCC2
LTFF
LTCC2
LTFF
LTCC1
LTCC0
LTLOC
LTCC0
LTLOC
LTEXD
LTNCP
LTEXD
LTNCP
LTUFE
LTLC
LTUFE
LTLC
LTDEF
LTEC
LTDEF
LTEC
SU.LP1XS
0BBh
LTED
-
-
0BCh
LTCC1
-
SU.LP2XS
0BDh
LTED
RECEIVE LAN REGISTERS
0C0h
-
-
-
LEEPS
-
LEVIT
-
LEETT
-
LEDAT
LMGMTT
LEDAL1
LPM
LBAT
SU.LPM
0C1h
-
-
-
0C2h
LEDAL7
LEDAL6
LEDAL5
LEDAL4
LEDAL3
LEDAL2
LEDAL0
LEDAL8
LEDAM0
LEDAM8
LEDAH0
LEDAH8
LEDAX0
-
SU.LEDAL
0C3h
LEDAL15 LEDAL14 LEDAL13 LEDAL12 LEDAL11 LEDAL10 LEDAL9
LEDAM7 LEDAM6 LEDAM5 LEDAM4 LEDAM3 LEDAM2 LEDAM1
LEDAM15 LEDAM14 LEDAM13 LEDAM12 LEDAM11 LEDAM10 LEDAM9
LEDAH7 LEDAH6 LEDAH5 LEDAH4 LEDAH3 LEDAH2 LEDAH1
LEDAH15 LEDAH14 LEDAH13 LEDAH12 LEDAH11 LEDAH10 LEDAH9
0C4h
SU.LEDAM
0C5h
0C6h
SU.LEDAH
0C7h
0C8h
LEDAX7
-
LEDAX6
-
LEDAX5
-
LEDAX4
-
LEDAX3
-
LEDAX2
-
LEDAX1
-
SU.LEDAX
0C9h
0CAh
SU.LEET
LEET7
LEET6
LEET5
LEET4
LEET3
LEET2
LEET1
LEET0
Rev: 063008
108 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
0CBh
BIT 7
LEET15
BIT 6
LEET14
BIT 5
LEET13
BIT 4
LEET12
BIT 3
LEET11
BIT 2
LEET10
BIT 1
LEET9
BIT 0
LEET8
0CCh
LP1MIM
LP1QOM
LP1FR
LP1PF2
LP1PF1
LP1ETF2 LP1ETF1
LP1E
SU.LP1C
0CDh
0CEh
0CFh
0D0h
0D1h
0D2h
0D3h
0D4h
0D5h
0D6h
0D7h
0D8h
0D9h
0DAh
0DBh
0DCh
0DDh
0DEh
0DFh
0E0h
0E1h
0E2h
0E3h
0E4h
0E5h
0E6h
0E7h
0E8h
0E9h
-
-
-
-
-
-
-
-
LP2E
-
LP2MIM
LP2QOM
LP2FR
LP2PF2
-
LP2PF1
-
LP2ETF2 LP2ETF1
SU.LP2C
SU.LNFC
SU.LQXPC
SU.LQTPID
SU.LIQOS
SU.MPL
-
-
-
-
-
-
-
LNPDF2
-
LNPDF1 LNETDF4 LNETDF3 LNETDF2 LNETDF1
-
-
-
-
-
-
-
LQXPC8
LQXPC7
LQXPC6
LQXPC5
LQXPC4
LQXPC3
LQXPC2
LQXPC1
LQXPC16 LQXPC15 LQXPC14 LQXPC13 LQXPC12 LQXPC11 LQXPC10 LQXPC9
LQTPID8 LQTPID7 LQTPID6 LQTPID5 LQTPID4 LQTPID3 LQTPID2 LQTPID1
LQTPID16 LQTPID15 LQTPID14 LQTPID13 LQTPID12 LQTPID11 LQTPID10 LQTPID9
-
-
-
-
LP2I
LP1I
LIQOS2
-
LIQOS1
-
-
-
-
-
-
-
MPL8
MPL7
MPL6
MPL5
MPL4
MPL3
MPL2
MPL10
L1PCT2
L1PCR2
L2PCT2
L2PCR2
PTE
MPL1
MPL9
L1PCT1
L1PCR1
L2PCT1
L2PCR1
PTAIM
-
-
-
MPL14
MPL13
MPL12
MPL11
L1PCT8
L1PCT7
L1PCT6
L1PCT5
L1PCT4
L1PCT3
SU.L1PP
SU.L2PP
SU.PTC
CBSS
-
-
-
L1PM2
L1PM1
L2PCT8
L2PCT7
L2PCT6
L2PCT5
L2PCT4
L2PCT3
CBSS
-
-
-
L2PM2
L2PM1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PTPAA
PTAA6
PTAA5
PTAA4
PTAA3
PTAA2
-
PTAA1
-
SU.PTAA
SU.PTWD
SU.PTRD
SU.PTSA
SU.BFC
-
-
-
-
-
-
-
-
-
-
-
-
LPQFW2 LPQFW1
-
-
-
-
-
-
-
LPQFR2
-
-
LPQFR1
-
-
-
-
-
-
-
-
-
-
-
-
-
PTIS
PTPSA
PTSA6
PTSA5
PTSA4
PTSA3
-
PTSA2
-
PTSA1
-
-
-
-
-
-
BFAP8
-
BFAP7
-
BFAP6
-
BFAP5
-
BFAP4
-
BFAP3
BFTR
BFAP2
BFE
BFAP1
BFAP9
Rev: 063008
109 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
100h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BUFFER MANAGER (ARBITER) REGISTERS
LQ1SA-8 LQ1SA-7 LQ1SA-6 LQ1SA-5 LQ1SA-4 LQ1SA-3 LQ1SA-2 LQ1SA-1
LQ1QPR LQ1SA-10 LQ1SA-9
LQ2SA-8 LQ2SA-7 LQ2SA-6 LQ2SA-5 LQ2SA-4 LQ2SA-3 LQ2SA-2 LQ2SA-1
LQ2QPR LQ2SA-10 LQ2SA-9
LQ3SA-8 LQ3SA-7 LQ3SA-6 LQ3SA-5 LQ3SA-4 LQ3SA-3 LQ3SA-2 LQ3SA-1
LQ3QPR LQ3SA-10 LQ3SA-9
LQ4SA-8 LQ4SA-7 LQ4SA-6 LQ4SA-5 LQ4SA-4 LQ4SA-3 LQ4SA-2 LQ4SA-1
LQ4QPR LQ4SA-10 LQ4SA-9
LQ5SA-8 LQ5SA-7 LQ5SA-6 LQ5SA-5 LQ5SA-4 LQ5SA-3 LQ5SA-2 LQ5SA-1
LQ5QPR LQ5SA-10 LQ5SA-9
LQ6SA-8 LQ6SA-7 LQ6SA-6 LQ6SA-5 LQ6SA-4 LQ6SA-3 LQ6SA-2 LQ6SA-1
LQ6QPR LQ6SA-10 LQ6SA-9
LQ7SA-8 LQ7SA-7 LQ7SA-6 LQ7SA-5 LQ7SA-4 LQ7SA-3 LQ7SA-2 LQ7SA-1
LQ7QPR LQ7SA-10 LQ7SA-9
LQ8SA-8 LQ8SA-7 LQ8SA-6 LQ8SA-5 LQ8SA-4 LQ8SA-3 LQ8SA-2 LQ8SA-1
LQ8QPR LQ8SA-10 LQ8SA-9
LQ9SA-8 LQ9SA-7 LQ9SA-6 LQ9SA-5 LQ9SA-4 LQ9SA-3 LQ9SA-2 LQ9SA-1
LQ9QPR LQ9SA-10 LQ9SA-9
LQ10SA-8 LQ10SA-7 LQ10SA-6 LQ10SA-5 LQ10SA-4 LQ10SA-3 LQ10SA-2 LQ10SA-1
LQ10SA-10
LQ10SA-9
AR.LQ1SA
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
121h
122h
123h
124h
125h
-
-
-
-
-
AR.LQ2SA
AR.LQ3SA
AR.LQ4SA
AR.LQ5SA
AR.LQ6SA
AR.LQ7SA
AR.LQ8SA
AR.LQ9SA
AR.LQ10SA
AR.LQ11SA
AR.LQ12SA
AR.LQ13SA
AR.LQ14SA
AR.LQ15SA
AR.LQ16SA
AR.LQ1EA
AR.LQ2EA
AR.LQ3EA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LQ10QPR
LQ11SA-8 LQ11SA-7 LQ11SA-6 LQ11SA-5 LQ11SA-4 LQ11SA-3 LQ11SA-2 LQ11SA-1
LQ11SA-10
LQ11SA-9
-
-
-
-
-
LQ11QPR
LQ12SA-8 LQ12SA-7 LQ12SA-6 LQ12SA-5 LQ12SA-4 LQ12SA-3 LQ12SA-2 LQ12SA-1
LQ12SA-10
LQ12SA-9
-
-
-
-
-
LQ12QPR
LQ13SA-8 LQ13SA-7 LQ13SA-6 LQ13SA-5 LQ13SA-4 LQ13SA-3 LQ13SA-2 LQ13SA-1
LQ13SA-10
LQ13SA-9
-
-
-
-
-
LQ13QPR
LQ14SA-8 LQ14SA-7 LQ14SA-6 LQ14SA-5 LQ14SA-4 LQ14SA-3 LQ14SA-2 LQ14SA-1
LQ14SA-10
LQ14SA-9
-
-
-
-
-
LQ14QPR
LQ15SA-8 LQ15SA-7 LQ15SA-6 LQ15SA-5 LQ15SA-4 LQ15SA-3 LQ15SA-2 LQ15SA-1
LQ15SA-10
LQ15SA-9
-
-
-
-
-
LQ15QPR
LQ16SA-8 LQ16SA-7 LQ16SA-6 LQ16SA-5 LQ16SA-4 LQ16SA-3 LQ16SA-2 LQ16SA-1
LQ16SA-10
LQ16SA-9
-
-
-
-
-
LQ16QPR
LQ1EA-8 LQ1EA-7 LQ1EA-6 LQ1EA-5 LQ1EA-4 LQ1EA-3 LQ1EA-2 LQ1EA-1
LQ1EA-10 LQ1EA-9
LQ2EA-8 LQ2EA-7 LQ2EA-6 LQ2EA-5 LQ2EA-4 LQ2EA-3 LQ2EA-2 LQ2EA-1
LQ2EA-10 LQ2EA-9
LQ3EA-8 LQ3EA-7 LQ3EA-6 LQ3EA-5 LQ3EA-4 LQ3EA-3 LQ3EA-2 LQ3EA-1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LQ3EA-10 LQ3EA-9
Rev: 063008
110 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
126h
BIT 7
LQ4EA-8 LQ4EA-7 LQ4EA-6 LQ4EA-5 LQ4EA-4 LQ4EA-3 LQ4EA-2 LQ4EA-1
LQ4EA-10 LQ4EA-9
LQ5EA-8 LQ5EA-7 LQ5EA-6 LQ5EA-5 LQ5EA-4 LQ5EA-3 LQ5EA-2 LQ5EA-1
LQ5EA-10 LQ5EA-9
LQ6EA-8 LQ6EA-7 LQ6EA-6 LQ6EA-5 LQ6EA-4 LQ6EA-3 LQ6EA-2 LQ6EA-1
LQ6EA-10 LQ6EA-9
LQ7EA-8 LQ7EA-7 LQ7EA-6 LQ7EA-5 LQ7EA-4 LQ7EA-3 LQ7EA-2 LQ7EA-1
LQ7EA-10 LQ7EA-9
LQ8EA-8 LQ8EA-7 LQ8EA-6 LQ8EA-5 LQ8EA-4 LQ8EA-3 LQ8EA-2 LQ8EA-1
LQ8EA-10 LQ8EA-9
LQ9EA-8 LQ9EA-7 LQ9EA-6 LQ9EA-5 LQ9EA-4 LQ9EA-3 LQ9EA-2 LQ9EA-1
LQ9EA-10 LQ9EA-9
LQ10EA-8 LQ10EA-7 LQ10EA-6 LQ10EA-5 LQ10EA-4 LQ10EA-3 LQ10EA-2 LQ10EA-1
LQ10EA-10
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
AR.LQ4EA
127h
128h
129h
12Ah
12Bh
12Ch
12Dh
12Eh
12Fh
130h
131h
132h
133h
134h
135h
136h
137h
138h
139h
13Ah
13Bh
13Ch
13Dh
13Eh
13Fh
140h
141h
142h
143h
144h
145h
146h
147h
148h
149h
14Ah
14Bh
14Ch
14Dh
14Eh
-
-
-
-
-
-
AR.LQ5EA
AR.LQ6EA
AR.LQ7EA
AR.LQ8EA
AR.LQ9EA
AR.LQ10EA
AR.LQ11EA
AR.LQ12EA
AR.LQ13EA
AR.LQ14EA
AR.LQ15EA
AR.LQ16EA
AR.WQ1SA
AR.WQ2SA
AR.WQ3SA
AR.WQ4SA
AR.WQ5SA
AR.WQ6SA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LQ10EA-9
LQ11EA-8 LQ11EA-7 LQ11EA-6 LQ11EA-5 LQ11EA-4 LQ11EA-3 LQ11EA-2 LQ11EA-1
LQ11EA-10
-
-
-
-
-
-
LQ11EA-9
LQ12EA-8 LQ12EA-7 LQ12EA-6 LQ12EA-5 LQ12EA-4 LQ12EA-3 LQ12EA-2 LQ12EA-1
LQ12EA-10
-
-
-
-
-
-
LQ12EA-9
LQ13EA-8 LQ13EA-7 LQ13EA-6 LQ13EA-5 LQ13EA-4 LQ13EA-3 LQ13EA-2 LQ13EA-1
LQ13EA-10
-
-
-
-
-
-
LQ13EA-9
LQ14EA-8 LQ14EA-7 LQ14EA-6 LQ14EA-5 LQ14EA-4 LQ14EA-3 LQ14EA-2 LQ14EA-1
LQ14EA-10
-
-
-
-
-
-
LQ14EA-9
LQ15EA-8 LQ15EA-7 LQ15EA-6 LQ15EA-5 LQ15EA-4 LQ15EA-3 LQ15EA-2 LQ15EA-1
LQ15EA-10
-
-
-
-
-
-
LQ15EA-9
LQ16EA-8 LQ16EA-7 LQ16EA-6 LQ16EA-5 LQ16EA-4 LQ16EA-3 LQ16EA-2 LQ16EA-1
LQ16EA-10
-
-
-
-
-
-
LQ16EA-9
WQ1SA-8 WQ1SA-7 WQ1SA-6 WQ1SA-5 WQ1SA-4 WQ1SA-3 WQ1SA-2 WQ1SA-1
WQ1SA-10
WQ2SA-8 WQ2SA-7 WQ2SA-6 WQ2SA-5 WQ2SA-4 WQ2SA-3 WQ2SA-2 WQ2SA-1
WQ2SA-10
WQ3SA-8 WQ3SA-7 WQ3SA-6 WQ3SA-5 WQ3SA-4 WQ3SA-3 WQ3SA-2 WQ3SA-1
WQ3SA-10
WQ4SA-8 WQ4SA-7 WQ4SA-6 WQ4SA-5 WQ4SA-4 WQ4SA-3 WQ4SA-2 WQ4SA-1
WQ4SA-10
WQ5SA-8 WQ5SA-7 WQ5SA-6 WQ5SA-5 WQ5SA-4 WQ5SA-3 WQ5SA-2 WQ5SA-1
WQ5SA-10
WQ6SA-8 WQ6SA-7 WQ6SA-6 WQ6SA-5 WQ6SA-4 WQ6SA-3 WQ6SA-2 WQ6SA-1
WQ6SA-10
WQ7SA-8 WQ7SA-7 WQ7SA-6 WQ7SA-5 WQ7SA-4 WQ7SA-3 WQ7SA-2 WQ7SA-1
WQ7SA-10
-
-
-
-
-
WQ1QPR
WQ1SA-9
-
-
-
-
-
WQ2QPR
WQ2SA-9
-
-
-
-
-
WQ3QPR
WQ3SA-9
-
-
-
-
-
WQ4QPR
WQ4SA-9
-
-
-
-
-
WQ5QPR
WQ5SA-9
-
-
-
-
-
WQ6QPR
WQ6SA-9
AR.WQ7SA
AR.WQ8SA
-
-
-
-
-
WQ7QPR
WQ7SA-9
WQ8SA-8 WQ8SA-7 WQ8SA-6 WQ8SA-5 WQ8SA-4 WQ8SA-3 WQ8SA-2 WQ8SA-1
Rev: 063008
111 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
14Fh
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
WQ8QPR
BIT 1
WQ8SA-10
BIT 0
WQ8SA-9
-
-
-
-
-
150h
WQ9SA-8 WQ9SA-7 WQ9SA-6 WQ9SA-5 WQ9SA-4 WQ9SA-3 WQ9SA-2 WQ9SA-1
WQ9SA-10
WQ10SA-8 WQ10SA-7 WQ10SA-6 WQ10SA-5 WQ10SA-4 WQ10SA-3 WQ10SA-2 WQ10SA-1
WQ10QPR WQ10SA-10 WQ10SA-9
WQ11SA-8 WQ11SA-7 WQ11SA-6 WQ11SA-5 WQ11SA-4 WQ11SA-3 WQ11SA-2 WQ11SA-1
WQ11QPR WQ11SA-10 WQ11SA-9
WQ12SA-8 WQ12SA-7 WQ12SA-6 WQ12SA-5 WQ12SA-4 WQ12SA-3 WQ12SA-2 WQ12SA-1
WQ12QPR WQ12SA-10 WQ12SA-9
WQ13SA-8 WQ13SA-7 WQ13SA-6 WQ13SA-5 WQ13SA-4 WQ13SA-3 WQ13SA-2 WQ13SA-1
WQ13QPR WQ13SA-10 WQ13SA-9
WQ14SA-8 WQ14SA-7 WQ14SA-6 WQ14SA-5 WQ14SA-4 WQ14SA-3 WQ14SA-2 WQ14SA-1
WQ14QPR WQ14SA-10 WQ14SA-9
WQ15SA-8 WQ15SA-7 WQ15SA-6 WQ15SA-5 WQ15SA-4 WQ15SA-3 WQ15SA-2 WQ15SA-1
WQ15QPR WQ15SA-10 WQ15SA-9
WQ16SA-8 WQ16SA-7 WQ16SA-6 WQ16SA-5 WQ16SA-4 WQ16SA-3 WQ16SA-2 WQ16SA-1
AR.WQ9SA
151h
152h
153h
154h
155h
156h
157h
158h
159h
15Ah
15Bh
15Ch
15Dh
15Eh
15Fh
160h
161h
162h
163h
164h
165h
166h
167h
168h
169h
16Ah
16Bh
16Ch
16Dh
16Eh
16Fh
170h
171h
172h
173h
174h
175h
176h
177h
-
-
-
-
-
WQ9QPR
WQ9SA-9
AR.WQ10SA
AR.WQ11SA
AR.WQ12SA
AR.WQ13SA
AR.WQ14SA
AR.WQ15SA
AR.WQ16SA
AR.WQ1EA
AR.WQ2EA
AR.WQ3EA
AR.WQ4EA
AR.WQ5EA
AR.WQ6EA
AR.WQ7EA
AR.WQ8EA
AR.WQ9EA
AR.WQ10EA
AR.WQ11EA
AR.WQ12EA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WQ16QPR WQ16SA-10 WQ16SA-9
WQ1EA-8
WQ1EA-7
WQ1EA-6
WQ1EA-5
WQ1EA-4
WQ1EA-3
WQ1EA-2
WQ1EA-10 WQ1EA-9
WQ2EA-2 WQ2EA-1
WQ2EA-10 WQ2EA-9
WQ3EA-2 WQ3EA-1
WQ3EA-10 WQ3EA-9
WQ4EA-2 WQ4EA-1
WQ4EA-10 WQ4EA-9
WQ5EA-2 WQ5EA-1
WQ5EA-10 WQ5EA-9
WQ6EA-2 WQ6EA-1
WQ6EA-10 WQ6EA-9
WQ7EA-2 WQ7EA-1
WQ7EA-10 WQ7EA-9
WQ8EA-2 WQ8EA-1
WQ8EA-10 WQ8EA-9
WQ9EA-2 WQ9EA-1
WQ9EA-10 WQ9EA-9
WQ1EA-1
-
-
-
-
-
-
WQ2EA-8
WQ2EA-7
WQ2EA-6
WQ2EA-5
WQ2EA-4
WQ2EA-3
-
-
-
-
-
-
WQ3EA-8
WQ3EA-7
WQ3EA-6
WQ3EA-5
WQ3EA-4
WQ3EA-3
-
-
-
-
-
-
WQ4EA-8
WQ4EA-7
WQ4EA-6
WQ4EA-5
WQ4EA-4
WQ4EA-3
-
-
-
-
-
-
WQ5EA-8
WQ5EA-7
WQ5EA-6
WQ5EA-5
WQ5EA-4
WQ5EA-3
-
-
-
-
-
-
WQ6EA-8
WQ6EA-7
WQ6EA-6
WQ6EA-5
WQ6EA-4
WQ6EA-3
-
-
-
-
-
-
WQ7EA-8
WQ7EA-7
WQ7EA-6
WQ7EA-5
WQ7EA-4
WQ7EA-3
-
-
-
-
-
-
WQ8EA-8
WQ8EA-7
WQ8EA-6
WQ8EA-5
WQ8EA-4
WQ8EA-3
-
-
-
-
-
-
WQ9EA-8
-
WQ9EA-7
-
WQ9EA-6
-
WQ9EA-5
-
WQ9EA-4
-
WQ9EA-3
-
WQ10EA-8 WQ10EA-7 WQ10EA-6 WQ10EA-5 WQ10EA-4 WQ10EA-3 WQ10EA-2 WQ10EA-1
WQ10EA-10 WQ10EA-9
WQ11EA-8 WQ11EA-7 WQ11EA-6 WQ11EA-5 WQ11EA-4 WQ11EA-3 WQ11EA-2 WQ11EA-1
WQ11EA-10 WQ11EA-9
WQ12EA-8 WQ12EA-7 WQ12EA-6 WQ12EA-5 WQ12EA-4 WQ12EA-3 WQ12EA-2 WQ12EA-1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WQ12EA-10 WQ12EA-9
Rev: 063008
112 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
178h
BIT 7
WQ13EA-8 WQ13EA-7 WQ13EA-6 WQ13EA-5 WQ13EA-4 WQ13EA-3 WQ13EA-2 WQ13EA-1
WQ13EA-10 WQ13EA-9
WQ14EA-8 WQ14EA-7 WQ14EA-6 WQ14EA-5 WQ14EA-4 WQ14EA-3 WQ14EA-2 WQ14EA-1
WQ14EA-10 WQ14EA-9
WQ15EA-8 WQ15EA-7 WQ15EA-6 WQ15EA-5 WQ15EA-4 WQ15EA-3 WQ15EA-2 WQ15EA-1
WQ15EA-10 WQ15EA-9
WQ16EA-8 WQ16EA-7 WQ16EA-6 WQ16EA-5 WQ16EA-4 WQ16EA-3 WQ16EA-2 WQ16EA-1
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
AR.WQ13EA
179h
17Ah
17Bh
17Ch
17Dh
17Eh
17Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
-
-
-
-
-
-
AR.WQ14EA
AR.WQ15EA
AR.WQ16EA
AR.LIQSA
AR.LIQEA
AR.LEQSA
AR.LEQEA
AR.WIQSA
AR.WIQEA
AR.WEQSA
AR.WEQEA
AR.LQW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WQ16EA-10 WQ16EA-9
LIQSA-8
LIQSA-7
LIQSA-6
LIQSA-5
LIQSA-4
LIQSA-3
LIQPR
LIQEA-3
-
LIQSA-2
LIQSA-10
LIQEA-2
LIQSA-1
LIQSA-9
LIQEA-1
LIQEA-9
LEQSA-1
LEQSA-9
LEQEA-1
LEQEA-9
WIQSA-1
WIQSA-9
WIQEA-1
WIQEA-9
WEQSA-1
-
-
-
-
-
LIQEA-8
LIQEA-7
LIQEA-6
LIQEA-5
LIQEA-4
-
-
-
-
-
LIQEA-10
LEQSA-2
LEQSA-10
LEQEA-2
LEQEA-10
WIQSA-2
WIQSA-10
WIQEA-2
WIQEA-10
WEQSA-2
LEQSA-8
LEQSA-7
LEQSA-6
LEQSA-5
LEQSA-4
LEQSA-3
LEQPR
LEQEA-3
-
-
-
-
-
-
LEQEA-8
LEQEA-7
LEQEA-6
LEQEA-5
LEQEA-4
-
-
-
-
-
WIQSA-8
WIQSA-7
WIQSA-6
WIQSA-5
WIQSA-4
WIQSA-3
WIQPR
WIQEA-3
-
-
-
-
-
-
WIQEA-8
WIQEA-7
WIQEA-6
WIQEA-5
WIQEA-4
-
-
-
-
-
WEQSA-8
WEQSA-7
WEQSA-6
WEQSA-5
WEQSA-4
WEQSA-3
WEQPR
WEQEA-3
-
-
-
-
-
WEQEA-5
-
-
WEQEA-4
-
WEQSA-10 WEQSA-9
WEQEA-2 WEQEA-1
WEQEA-10 WEQEA-9
WEQEA-8
WEQEA-7
WEQEA-6
-
-
-
LQW-8
LQW-7
LQW-6
LQW-5
LQW-13
WIENC-1
-
LQW-4
LQW-12
WISPL
-
LQW-3
LQW-11
WIENA
-
LQW-2
LQW-10
WQPD
FPEPD
LQW-1
LQW-9
-
-
-
WIRRW2
-
WIRRW1
-
WIENC2
-
ASQPR
WQODE
AR.MQC
LQ4RRW-2 LQ4RRW-1 LQ3RRW-2 LQ3RRW -1 LQ2RRW-2 LQ2RRW-1 LQ1RRW-2 LQ1RRW-1
AR.LQSC
-
-
-
-
-
-
-
LQSM
BFTOA-1
BFTOA-9
LQOS-1
BFTOA-8
-
BFTOA-7
-
BFTOA-6
-
BFTOA-5
-
BFTOA-4
-
BFTOA-3
-
BFTOA-2
BFTOA-10
LQOS-2
AR.BFTOA
AR.LQOS
LQOS-8
LQOS-16
LQOIM-8
LQOIM-16
LQNFS-8
LQOS-7
LQOS-15
LQOIM-7
LQOIM-15
LQNFS-7
LQOS-6
LQOS-14
LQOIM-6
LQOIM-14
LQNFS-6
LQOS-5
LQOS-13
LQOIM-5
LQOIM-13
LQNFS-5
LQOS-4
LQOS-12
LQOIM-4
LQOIM-12
LQNFS-4
LQOS-3
LQOS-11
LQOIM-3
LQOIM-11
LQNFS-3
LQOS-10
LQOIM-2
LQOIM-10
LQNFS-2
LQOS-9
LQOIM-1
LQOIM-9
LQNFS-1
LQNFS-9
LQNFIM-1
AR.LQOIM
AR.LQNFS
LQNFS-16 LQNFS-15 LQNFS-14 LQNFS-13 LQNFS-12 LQNFS-11 LQNFS-10
LQNFIM-8 LQNFIM-7 LQNFIM-6 LQNFIM-5 LQNFIM-4 LQNFIM-3 LQNFIM-2
AR.LQNFIM
AR.WQOS
LQNFIM-16 LQNFIM-15 LQNFIM-14 LQNFIM-13 LQNFIM-12 LQNFIM-11 LQNFIM-10 LQNFIM-9
WQOS-8
WQOS-7
WQOS-6
WQOS-5
WQOS-4
WQOS-3
WQOS-2
WQOS-1
Rev: 063008
113 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
1A1h
BIT 7
WQOS-16
BIT 6
WQOS-15
BIT 5
WQOS-14
BIT 4
WQOS-13
BIT 3
WQOS-12
BIT 2
WQOS-11
BIT 1
WQOS-10
BIT 0
WQOS-9
1A2h
WQOIM-8
WQOIM-7
WQOIM-6
WQOIM-5
WQOIM-4
WQOIM-3
WQOIM-2
WQOIM-1
AR.WQOIM
1A3h
1A4h
1A5h
1A6h
1A7h
1A8h
1A9h
1AAh
1ABh
1ACh
1ADh
WQOIM-16 WQOIM-15 WQOIM-14 WQOIM-13 WQOIM-12 WQOIM-11 WQOIM-10 WQOIM-9
WQNFS-8 WQNFS-7 WQNFS-6 WQNFS-5 WQNFS-4 WQNFS-3 WQNFS-2 WQNFS-1
AR.WQNFS
AR.WQNFIM
AR.EQOS
AR.EQOIM
AR.BMIS
WQNFS-16 WQNFS-15 WQNFS-14 WQNFS-13 WQNFS-12 WQNFS-11 WQNFS-10 WQNFS-9
WQNFIM-8 WQNFIM-7 WQNFIM-6 WQNFIM-5 WQNFIM-4 WQNFIM-3 WQNFIM-2 WQNFIM-1
WQNFIM-16 WQNFIM-15 WQNFIM-14 WQNFIM-13 WQNFIM-12 WQNFIM-11 WQNFIM-10 WQNFIM-9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WEQOS
LEQOS
-
-
-
-
-
-
-
-
WEQOIM
LEQOIM
-
EQOI
-
-
-
WQOI
-
-
LCNFI
-
-
LQOI
-
WQNFI
-
Packet Processor 1(Encapsulator 1)
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
21Eh
21Fh
220h
221h
226h
227h
EIIS
ELHDE
ET1E
ET2E
ERE1
EFCS3216S
ERE0
-
EHCBO
EBBYS
ELHD16
ELHD24
ELHD0
ELHD8
ET1D16
ET1D24
ET1D0
ET1D8
ET2D16
ET2D24
ET2D0
ET2D8
-
TBRE
EFCSB
ELHD17
ELHD25
ELHD1
ELHD9
ET1D17
ET1D25
ET1D1
ET1D9
ET2D17
ET2D25
ET2D1
ET2D9
ESEI
PP.EMCR
EGCM EPRTSEL EFCSAD ECFCRD
ELHD23
ELHD31
ELHD7
ELHD15
ET1D23
ET1D31
ET1D7
ELHD22
ELHD30
ELHD6
ELHD14
ET1D22
ET1D30
ET1D6
ELHD21
ELHD29
ELHD5
ELHD13
ET1D21
ET1D29
ET1D5
ELHD20
ELHD28
ELHD4
ELHD12
ET1D20
ET1D28
ET1D4
ELHD19
ELHD27
ELHD3
ELHD11
ET1D19
ET1D27
ET1D3
ELHD18
ELHD26
ELHD2
ELHD10
ET1D18
ET1D26
ET1D2
ET1D10
ET2D18
ET2D26
ET2D2
ET2D10
EEI0
PP.ELHHR
PP.ELHLR
PP.ET1DHR
PP.ET1DLR
PP.ET2DHR
PP.ET2DLR
PP.EEIR
ET1D15
ET2D23
ET2D31
ET2D7
ET1D14
ET2D22
ET2D30
ET2D6
ET1D13
ET2D21
ET2D29
ET2D5
ET1D12
ET2D20
ET2D28
ET2D4
ET1D11
ET2D19
ET2D27
ET2D3
ET2D15
EEI5
ET2D14
EEI4
ET2D13
EEI3
ET2D12
EEI2
ET2D11
EEI1
EPLIEIE
EFCNT7
EDEIE
EEFCSEIE EFCFEIE EBDEC1
EFCNT5 EFCNT4 EFCNT3
EBDEC0
EFCNT2
EEI7
EEI6
EFCNT6
EFCNT1
EFCNT0
EFCNT8
FE
PP.EFCLSR
PP.ESMLS
PP.ESMIE
PP.EHFL
EFCNT15 EFCNT14 EFCNT13 EFCNT12 EFCNT11 EFCNT10 EFCNT9
-
EOPLE
-
EOPSE
-
FUF
FOVF
SOPLE
FOVFIE
FLOK
SOPSE
FLOKIE
FF
-
-
COPLE
FFIE
COPSE
FEIE
-
EOPLEIE EOPSEIE
FUFIE
-
-
-
-
SOPLEIE SOPSEIE COPLEIE COPSEIE
EHFL7
-
EHFL6
-
EHFL5
-
EHFL4
-
EHFL3
-
EHFL2
-
EHFL1
-
EHFL0
-
Packet Processor 2(Encapsulator 2)
240h
241h
EIIS
ELHDE
ET1E
ET2E
ERE1
ERE0
-
TBRE
EHCBO
EBBYS
PP.EMCR
EFCS16EN
EGCM
EPRTSEL EFCSAD ECFCRD
EFCSB
Rev: 063008
114 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
242h
BIT 7
ELHD23
BIT 6
ELHD22
BIT 5
ELHD21
BIT 4
ELHD20
BIT 3
ELHD19
BIT 2
ELHD18
BIT 1
ELHD17
BIT 0
ELHD16
PP.ELHHR
243h
244h
245h
246h
247h
248h
249h
24Ah
24Bh
24Ch
24Dh
24Eh
24Fh
250h
251h
25Eh
25Fh
260h
261h
266h
267h
ELHD31
ELHD7
ELHD15
ET1D23
ET1D31
ET1D7
ELHD30
ELHD6
ELHD14
ET1D22
ET1D30
ET1D6
ELHD29
ELHD5
ELHD13
ET1D21
ET1D29
ET1D5
ELHD28
ELHD4
ELHD12
ET1D20
ET1D28
ET1D4
ELHD27
ELHD3
ELHD11
ET1D19
ET1D27
ET1D3
ELHD26
ELHD2
ELHD10
ET1D18
ET1D26
ET1D2
ELHD25
ELHD1
ELHD9
ET1D17
ET1D25
ET1D1
ET1D9
ET2D17
ET2D25
ET2D1
ET2D9
ESEI
ELHD24
ELHD0
ELHD8
ET1D16
ET1D24
ET1D0
ET1D8
ET2D16
ET2D24
ET2D0
ET2D8
-
PP.ELHLR
PP.ET1DHR
PP.ET1DLR
PP.ET2DHR
PP.ET2DLR
PP.EEIR
ET1D15
ET2D23
ET2D31
ET2D7
ET1D14
ET2D22
ET2D30
ET2D6
ET1D13
ET2D21
ET2D29
ET2D5
ET1D12
ET2D20
ET2D28
ET2D4
ET1D11
ET2D19
ET2D27
ET2D3
ET1D10
ET2D18
ET2D26
ET2D2
ET2D15
EEI5
ET2D14
EEI4
ET2D13
EEI3
ET2D12
EEI2
ET2D11
EEI1
ET2D10
EEI0
EPLIEIE
EFCNT7
EDEIE
EEFCSEIE EFCFEIE EBDEC1
EFCNT5 EFCNT4 EFCNT3
EBDEC0
EFCNT2
EEI7
EEI6
EFCNT6
EFCNT1
EFCNT0
EFCNT8
FE
PP.EFCLSR
PP.ESMLS
PP.ESMIE
PP.EHFL
EFCNT15 EFCNT14 EFCNT13 EFCNT12 EFCNT11 EFCNT10 EFCNT9
-
EOPLE
-
EOPSE
-
FUF
FOVF
SOPLE
FOVFIE
FLOK
SOPSE
FLOKIE
FF
-
-
COPLE
FFIE
COPSE
FEIE
-
EOPLEIE EOPSEIE
FUFIE
-
-
-
-
SOPLEIE SOPSEIE COPLEIE COPSEIE
EHFL7
-
EHFL6
-
EHFL5
-
EHFL4
-
EHFL3
-
EHFL2
-
EHFL1
-
EHFL0
-
Packet Processor 3 (Encapsulator 3)
ELHDE ET1E ET2E
EPRTSEL EFCSAD ECFCRD
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
EIIS
ERE1
EFCS16EN
ELHD19
ELHD27
ELHD3
ELHD11
ET1D19
ET1D27
ET1D3
ERE0
-
TBRE
EFCSB
ELHD17
ELHD25
ELHD1
ELHD9
ET1D17
ET1D25
ET1D1
ET1D9
ET2D17
ET2D25
ET2D1
ET2D9
ESEI
EHCBO
EBBYS
ELHD16
ELHD24
ELHD0
ELHD8
ET1D16
ET1D24
ET1D0
ET1D8
ET2D16
ET2D24
ET2D0
ET2D8
-
PP.EMCR
EGCM
ELHD23
ELHD31
ELHD7
ELHD15
ET1D23
ET1D31
ET1D7
ELHD22
ELHD30
ELHD6
ELHD14
ET1D22
ET1D30
ET1D6
ELHD21
ELHD29
ELHD5
ELHD13
ET1D21
ET1D29
ET1D5
ELHD20
ELHD28
ELHD4
ELHD12
ET1D20
ET1D28
ET1D4
ELHD18
ELHD26
ELHD2
ELHD10
ET1D18
ET1D26
ET1D2
ET1D10
ET2D18
ET2D26
ET2D2
ET2D10
EEI0
PP.ELHHR
PP.ELHLR
PP.ET1DHR
PP.ET1DLR
PP.ET2DHR
PP.ET2DLR
PP.EEIR
ET1D15
ET2D23
ET2D31
ET2D7
ET1D14
ET2D22
ET2D30
ET2D6
ET1D13
ET2D21
ET2D29
ET2D5
ET1D12
ET2D20
ET2D28
ET2D4
ET1D11
ET2D19
ET2D27
ET2D3
ET2D15
EEI5
ET2D14
EEI4
ET2D13
EEI3
ET2D12
EEI2
ET2D11
EEI1
EPLIEIE
EFCNT7
EDEIE
EEFCSEIE EFCFEIE EBDEC1
EFCNT5 EFCNT4 EFCNT3
EBDEC0
EFCNT2
EEI7
EEI6
EFCNT6
EFCNT1
EFCNT0
EFCNT8
PP.EFCLSR
EFCNT15 EFCNT14 EFCNT13 EFCNT12 EFCNT11 EFCNT10 EFCNT9
Rev: 063008
115 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
29Eh
BIT 7
EOPLE
BIT 6
EOPSE
BIT 5
BIT 4
FUF
BIT 3
FOVF
BIT 2
FLOK
BIT 1
BIT 0
FE
-
FF
PP.ESMLS
29Fh
2A0h
2A1h
2A6h
2A7h
-
-
-
-
SOPLE
FOVFIE
SOPSE
FLOKIE
COPLE
FFIE
COPSE
FEIE
-
EOPLEIE EOPSEIE
FUFIE
PP.ESMIE
PP.EHFL
-
-
-
-
SOPLEIE SOPSEIE COPLEIE COPSEIE
EHFL7
-
EHFL6
-
EHFL5
-
EHFL4
-
EHFL3
-
EHFL2
-
EHFL1
-
EHFL0
-
Packet Processor 4(Encapsulator 4)
2C0h
2C1h
2C2h
2C3h
2C4h
2C5h
2C6h
2C7h
2C8h
2C9h
2CAh
2CBh
2CCh
2CDh
2CEh
2CFh
2D0h
2D1h
2DEh
2DFh
2E0h
2E1h
2E6h
2E7h
EHCBO
EBBYS
ELHD16
ELHD24
ELHD0
ELHD8
ET1D16
ET1D24
ET1D0
ET1D8
ET2D16
ET2D24
ET2D0
ET2D8
-
EIIS
ELHDE
ET1E
ET2E
ERE1
EFCS16EN
ELHD19
ELHD27
ELHD3
ERE0
-
TBRE
EFCSB
ELHD17
ELHD25
ELHD1
ELHD9
ET1D17
ET1D25
ET1D1
ET1D9
ET2D17
ET2D25
ET2D1
ET2D9
ESEI
PP.EMCR
EGCM EPRTSEL EFCSAD ECFCRD
ELHD23
ELHD31
ELHD7
ELHD15
ET1D23
ET1D31
ET1D7
ELHD22
ELHD30
ELHD6
ELHD14
ET1D22
ET1D30
ET1D6
ELHD21
ELHD29
ELHD5
ELHD13
ET1D21
ET1D29
ET1D5
ELHD20
ELHD28
ELHD4
ELHD12
ET1D20
ET1D28
ET1D4
ELHD18
ELHD26
ELHD2
ELHD10
ET1D18
ET1D26
ET1D2
ET1D10
ET2D18
ET2D26
ET2D2
ET2D10
EEI0
PP.ELHHR
PP.ELHLR
PP.ET1DHR
PP.ET1DLR
PP.ET2DHR
PP.ET2DLR
PP.EEIR
ELHD11
ET1D19
ET1D27
ET1D3
ET1D15
ET2D23
ET2D31
ET2D7
ET1D14
ET2D22
ET2D30
ET2D6
ET1D13
ET2D21
ET2D29
ET2D5
ET1D12
ET2D20
ET2D28
ET2D4
ET1D11
ET2D19
ET2D27
ET2D3
ET2D15
EEI5
ET2D14
EEI4
ET2D13
EEI3
ET2D12
EEI2
ET2D11
EEI1
EPLIEIE
EFCNT7
EDEIE
EEFCSEIE EFCFEIE EBDEC1
EFCNT5 EFCNT4 EFCNT3
EBDEC0
EFCNT2
EEI7
EEI6
EFCNT6
EFCNT1
EFCNT0
EFCNT8
FE
PP.EFCLSR
PP.ESMLS
PP.ESMIE
PP.EHFL
EFCNT15 EFCNT14 EFCNT13 EFCNT12 EFCNT11 EFCNT10 EFCNT9
-
EOPLE
-
EOPSE
-
FUF
FOVF
SOPLE
FOVFIE
FLOK
SOPSE
FLOKIE
FF
-
-
COPLE
FFIE
COPSE
FEIE
-
EOPLEIE EOPSEIE
FUFIE
-
-
-
-
SOPLEIE SOPSEIE COPLEIE COPSEIE
EHFL7
-
EHFL6
-
EHFL5
-
EHFL4
-
EHFL3
-
EHFL2
-
EHFL1
-
EHFL0
-
Rev: 063008
116 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
300h
BIT 7
DR1E
BIT 6
Packet Processor 1(Decapsulator 1)
DR2E DR3E DAE1
DPRTSEL DFCSAD DCFCRD
BIT 5
BIT 4
BIT 3
BIT 2
DGSC
BIT 1
BIT 0
DAE0
DFCS16EN
D1D3D
D1D11D
D2D3D
D2D11D
D3D3D
D3D11D
D4D3D
D4D11D
D5D3D
D5D11D
D6D3D
D6D11D
D7D3D
D7D11D
D8D3D
D8D11D
D9D3D
D9D11D
-
DHRAE
DBBS
DHCBO
RBRE
PP.DMCR
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h
321h
322h
323h
DGCM
D1D7D
D1D15D
D2D7D
D2D15D
D3D7D
D3D15D
D4D7D
D4D15D
D5D7D
D5D15D
D6D7D
D6D15D
D7D7D
D7D15D
D8D7D
D8D15D
D9D7D
D9D15D
DFUR
-
D1D6D
D1D14D
D2D6D
D2D14D
D3D6D
D3D14D
D4D6D
D4D14D
D5D6D
D5D14D
D6D6D
D6D14D
D7D6D
D7D14D
D8D6D
D8D14D
D9D6D
D9D14D
DFOVF
DGSLLS
D1D5D
D1D13D
D2D5D
D2D13D
D3D5D
D3D13D
D4D5D
D4D13D
D5D5D
D5D13D
D6D5D
D6D13D
D7D5D
D7D13D
D8D5D
D8D13D
D9D5D
D9D13D
-
D1D4D
D1D12D
D2D4D
D2D12D
D3D4D
D3D12D
D4D4D
D4D12D
D5D4D
D5D12D
D6D4D
D6D12D
D7D4D
D7D12D
D8D4D
D8D12D
D9D4D
D9D12D
-
D1D2D
D1D10D
D2D2D
D2D10D
D3D2D
D3D10D
D4D2D
D4D10D
D5D2D
D5D10D
D6D2D
D6D10D
D7D2D
D7D10D
D8D2D
D8D10D
D9D2D
D9D10D
-
D1D1D
D1D9D
D2D1D
D2D9D
D3D1D
D3D9D
D4D1D
D4D9D
D5D1D
D5D9D
D6D1D
D6D9D
D7D1D
D7D9D
D8D1D
D8D9D
D9D1D
D9D9D
-
D1D0D
D1D8D
D2D0D
D2D8D
D3D0D
D3D8D
D4D0D
D4D8D
D5D0D
D5D8D
D6D0D
D6D8D
D7D0D
D7D8D
D8D0D
D8D8D
D9D0D
D9D8D
-
PP.DA1DR
PP.DA2DR
PP.DA3DR
PP.DA4DR
PP.DA5DR
PP.DA6DR
PP.DA7DR
PP.DA8DR
PP.DA9DR
PP.DMLSR
PP.DMLSIE
PP.DGPLC
PP.DGBLC
PP.DSSR
DTCHECFLS
DCHECFLS
-
DGSLS
DGLCLS DGLCSLS
DFFLS
-
-
DFURIE DFOVFIE
-
-
-
-
DCHECFIE DTCHECFIE
DGSIE
DGSLIE
DGPLC6
DGLCIE DGLCSIE
DGPLC5 DGPLC4
DFFIE
-
DGPLC7
DGPLC3
DGPLC2
DGPLC1
DGPLC0
DGPLC8
DBPLC0
DBPLC8
DGPLC15 DGPLC14 DGPLC13 DGPLC12 DGPLC11 DGPLC10 DGPLC9
DBPLC7 DBPLC6 DBPLC5 DBPLC4 DBPLC3 DBPLC2 DBPLC1
DBPLC15 DBPLC14 DBPLC13 DBPLC12 DBPLC11 DBPLC10 DBPLC9
-
-
-
-
-
DGSYNC DGPSYNC DGHUNT
-
-
-
-
-
-
-
-
DHSR23
DHSR31
DHSR7
DHSR15
-
DHSR22
DHSR30
DHSR6
DHSR14
-
DHSR21
DHSR29
DHSR5
DHSR13
-
DHSR20
DHSR28
DHSR4
DHSR12
DHSR19
DHSR27
DHSR3
DHSR11
DEM
DHSR18
DHSR26
DHSR2
DHSR10
DSMRE
-
DHSR17
DHSR25
DHSR1
DHSR9
DHSR16
DHSR24
DHSR0
DHSR8
PP.DHHSR
PP.DHLSR
PP.DFSCR
DEPRE DFSRPWC
-
-
-
-
-
-
-
Rev: 063008
117 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
340h
BIT 7
DR1E
BIT 6
Packet Processor 2 (Decapsulator 2)
DR2E DR3E DAE1
DPRTSEL DFCSAD DCFCRD
BIT 5
BIT 4
BIT 3
BIT 2
DGSC
BIT 1
BIT 0
DAE0
DFCS16EN
D1D3D
D1D11D
D2D3D
D2D11D
D3D3D
D3D11D
D4D3D
D4D11D
D5D3D
D5D11D
D6D3D
D6D11D
D7D3D
D7D11D
D8D3D
D8D11D
D9D3D
D9D11D
-
DHRAE
DBBS
DHCBO
RBRE
PP.DMCR
341h
342h
343h
344h
345h
346h
347h
348h
349h
34Ah
34Bh
34Ch
34Dh
34Eh
34Fh
350h
351h
352h
353h
354h
355h
356h
DGCM
D1D7D
D1D15D
D2D7D
D2D15D
D3D7D
D3D15D
D4D7D
D4D15D
D5D7D
D5D15D
D6D7D
D6D15D
D7D7D
D7D15D
D8D7D
D8D15D
D9D7D
D9D15D
DFUR
-
D1D6D
D1D14D
D2D6D
D2D14D
D3D6D
D3D14D
D4D6D
D4D14D
D5D6D
D5D14D
D6D6D
D6D14D
D7D6D
D7D14D
D8D6D
D8D14D
D9D6D
D9D14D
DFOVF
DGSLLS
D1D5D
D1D13D
D2D5D
D2D13D
D3D5D
D3D13D
D4D5D
D4D13D
D5D5D
D5D13D
D6D5D
D6D13D
D7D5D
D7D13D
D8D5D
D8D13D
D9D5D
D9D13D
-
D1D4D
D1D12D
D2D4D
D2D12D
D3D4D
D3D12D
D4D4D
D4D12D
D5D4D
D5D12D
D6D4D
D6D12D
D7D4D
D7D12D
D8D4D
D8D12D
D9D4D
D9D12D
-
D1D2D
D1D10D
D2D2D
D2D10D
D3D2D
D3D10D
D4D2D
D4D10D
D5D2D
D5D10D
D6D2D
D6D10D
D7D2D
D7D10D
D8D2D
D8D10D
D9D2D
D9D10D
-
D1D1D
D1D9D
D2D1D
D2D9D
D3D1D
D3D9D
D4D1D
D4D9D
D5D1D
D5D9D
D6D1D
D6D9D
D7D1D
D7D9D
D8D1D
D8D9D
D9D1D
D9D9D
-
D1D0D
D1D8D
D2D0D
D2D8D
D3D0D
D3D8D
D4D0D
D4D8D
D5D0D
D5D8D
D6D0D
D6D8D
D7D0D
D7D8D
D8D0D
D8D8D
D9D0D
D9D8D
-
PP.DA1DR
PP.DA2DR
PP.DA3DR
PP.DA4DR
PP.DA5DR
PP.DA6DR
PP.DA7DR
PP.DA8DR
PP.DA9DR
PP.DMLSR
DTCHECFLS
DCHECFLS
DGSLS
DGLCLS DGLCSLS
DFFLS
-
-
DFURIE DFOVFIE
DGSIE DGSLIE
-
-
-
-
-
PP.DMLSIE
DCHECFI
E
357h
DTCHECFIE
DGLCIE DGLCSIE
DFFIE
-
358h
359h
35Ah
35Bh
35Ch
35Dh
35Eh
35Fh
360h
361h
362h
363h
DGPLC7 DGPLC6 DGPLC5 DGPLC4 DGPLC3 DGPLC2 DGPLC1 DGPLC0
DGPLC15 DGPLC14 DGPLC13 DGPLC12 DGPLC11 DGPLC10 DGPLC9 DGPLC8
DBPLC7 DBPLC6 DBPLC5 DBPLC4 DBPLC3 DBPLC2 DBPLC1 DBPLC0
DBPLC15 DBPLC14 DBPLC13 DBPLC12 DBPLC11 DBPLC10 DBPLC9 DBPLC8
PP.DGPLC
PP.DGBLC
PP.DSSR
-
-
-
-
-
DGSYNC DGPSYNC DGHUNT
-
-
-
-
-
-
-
-
DHSR23
DHSR31
DHSR7
DHSR15
-
DHSR22
DHSR30
DHSR6
DHSR14
-
DHSR21
DHSR29
DHSR5
DHSR13
-
DHSR20
DHSR28
DHSR4
DHSR12
-
DHSR19
DHSR27
DHSR3
DHSR11
DEM
DHSR18
DHSR26
DHSR2
DHSR10
DSMRE
-
DHSR17
DHSR25
DHSR1
DHSR9
DHSR16
DHSR24
DHSR0
DHSR8
PP.DHHSR
PP.DHLSR
PP.DFSCR
DEPRE DFSRPWC
-
-
-
-
-
-
-
Rev: 063008
118 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
380h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Packet Processor 3(Decapsulator 3)
DR1E
DR2E
DPRTSEL
D1D6D
DR3E
DAE1
DAE0
DFCS16EN
D1D3D
D1D11D
D2D3D
D2D11D
D3D3D
D3D11D
D4D3D
D4D11D
D5D3D
D5D11D
D6D3D
D6D11D
D7D3D
D7D11D
D8D3D
D8D11D
D9D3D
D9D11D
-
DGSC
-
DHRAE DHCBO
PP.DMCR
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
DGCM
D1D7D
D1D15D
D2D7D
D2D15D
D3D7D
D3D15D
D4D7D
D4D15D
D5D7D
D5D15D
D6D7D
D6D15D
D7D7D
D7D15D
D8D7D
D8D15D
D9D7D
D9D15D
DFUR
DFCSAD DCFCRD
DBBS
D1D1D
D1D9D
D2D1D
D2D9D
D3D1D
D3D9D
D4D1D
D4D9D
D5D1D
D5D9D
D6D1D
D6D9D
D7D1D
D7D9D
D8D1D
D8D9D
D9D1D
D9D9D
-
RBRE
D1D0D
D1D8D
D2D0D
D2D8D
D3D0D
D3D8D
D4D0D
D4D8D
D5D0D
D5D8D
D6D0D
D6D8D
D7D0D
D7D8D
D8D0D
D8D8D
D9D0D
D9D8D
-
D1D5D
D1D13D
D2D5D
D2D13D
D3D5D
D3D13D
D4D5D
D4D13D
D5D5D
D5D13D
D6D5D
D6D13D
D7D5D
D7D13D
D8D5D
D8D13D
D9D5D
D9D13D
-
D1D4D
D1D12D
D2D4D
D2D12D
D3D4D
D3D12D
D4D4D
D4D12D
D5D4D
D5D12D
D6D4D
D6D12D
D7D4D
D7D12D
D8D4D
D8D12D
D9D4D
D9D12D
-
D1D2D
D1D10D
D2D2D
D2D10D
D3D2D
D3D10D
D4D2D
D4D10D
D5D2D
D5D10D
D6D2D
D6D10D
D7D2D
D7D10D
D8D2D
D8D10D
D9D2D
D9D10D
-
PP.DA1DR
PP.DA2DR
PP.DA3DR
PP.DA4DR
PP.DA5DR
PP.DA6DR
PP.DA7DR
PP.DA8DR
PP.DA9DR
PP.DMLSR
D1D14D
D2D6D
D2D14D
D3D6D
D3D14D
D4D6D
D4D14D
D5D6D
D5D14D
D6D6D
D6D14D
D7D6D
D7D14D
D8D6D
D8D14D
D9D6D
D9D14D
DFOVF
DGSLLS
DTCHECFLS
DCHECFLS
DGSLS
DGLCLS DGLCSLS
DFFLS
-
-
DFURIE DFOVFIE
DGSIE DGSLIE
-
-
-
-
-
PP.DMLSIE
DCHECFI
E
397h
DTCHECFIE
DGLCIE DGLCSIE
DFFIE
-
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
3A1h
3A2h
3A3h
DGPLC7 DGPLC6 DGPLC5 DGPLC4 DGPLC3 DGPLC2 DGPLC1 DGPLC0
DGPLC15 DGPLC14 DGPLC13 DGPLC12 DGPLC11 DGPLC10 DGPLC9 DGPLC8
DBPLC7 DBPLC6 DBPLC5 DBPLC4 DBPLC3 DBPLC2 DBPLC1 DBPLC0
DBPLC15 DBPLC14 DBPLC13 DBPLC12 DBPLC11 DBPLC10 DBPLC9 DBPLC8
PP.DGPLC
PP.DGBLC
PP.DSSR
-
-
-
-
-
DGSYNC DGPSYNC DGHUNT
-
-
-
-
-
-
-
-
DHSR23
DHSR31
DHSR7
DHSR15
-
DHSR22
DHSR30
DHSR6
DHSR14
-
DHSR21
DHSR29
DHSR5
DHSR13
-
DHSR20
DHSR28
DHSR4
DHSR12
-
DHSR19
DHSR27
DHSR3
DHSR11
DEM
DHSR18
DHSR26
DHSR2
DHSR10
DSMRE
-
DHSR17
DHSR25
DHSR1
DHSR9
DHSR16
DHSR24
DHSR0
DHSR8
PP.DHHSR
PP.DHLSR
PP.DFSCR
DEPRE DFSRPWC
-
-
-
-
-
-
-
Rev: 063008
119 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
3C0h
BIT 7
DR1E
BIT 6
Packet Processor 4(Decapsulator 4)
DR2E DR3E DAE1
DPRTSEL DFCSAD DCFCRD
BIT 5
BIT 4
BIT 3
BIT 2
DGSC
BIT 1
BIT 0
DAE0
DFCS16EN
D1D3D
D1D11D
D2D3D
D2D11D
D3D3D
D3D11D
D4D3D
D4D11D
D5D3D
D5D11D
D6D3D
D6D11D
D7D3D
D7D11D
D8D3D
D8D11D
D9D3D
D9D11D
-
DHRAE
DBBS
DHCBO
RBRE
PP.DMCR
3C1h
3C2h
3C3h
3C4h
3C5h
3C6h
3C7h
3C8h
3C9h
3CAh
3CBh
3CCh
3CDh
3CEh
3CFh
3D0h
3D1h
3D2h
3D3h
3D4h
3D5h
3D6h
DGCM
D1D7D
D1D15D
D2D7D
D2D15D
D3D7D
D3D15D
D4D7D
D4D15D
D5D7D
D5D15D
D6D7D
D6D15D
D7D7D
D7D15D
D8D7D
D8D15D
D9D7D
D9D15D
DFUR
-
D1D6D
D1D14D
D2D6D
D2D14D
D3D6D
D3D14D
D4D6D
D4D14D
D5D6D
D5D14D
D6D6D
D6D14D
D7D6D
D7D14D
D8D6D
D8D14D
D9D6D
D9D14D
DFOVF
DGSLLS
D1D5D
D1D13D
D2D5D
D2D13D
D3D5D
D3D13D
D4D5D
D4D13D
D5D5D
D5D13D
D6D5D
D6D13D
D7D5D
D7D13D
D8D5D
D8D13D
D9D5D
D9D13D
-
D1D4D
D1D12D
D2D4D
D2D12D
D3D4D
D3D12D
D4D4D
D4D12D
D5D4D
D5D12D
D6D4D
D6D12D
D7D4D
D7D12D
D8D4D
D8D12D
D9D4D
D9D12D
-
D1D2D
D1D10D
D2D2D
D2D10D
D3D2D
D3D10D
D4D2D
D4D10D
D5D2D
D5D10D
D6D2D
D6D10D
D7D2D
D7D10D
D8D2D
D8D10D
D9D2D
D9D10D
-
D1D1D
D1D9D
D2D1D
D2D9D
D3D1D
D3D9D
D4D1D
D4D9D
D5D1D
D5D9D
D6D1D
D6D9D
D7D1D
D7D9D
D8D1D
D8D9D
D9D1D
D9D9D
-
D1D0D
D1D8D
D2D0D
D2D8D
D3D0D
D3D8D
D4D0D
D4D8D
D5D0D
D5D8D
D6D0D
D6D8D
D7D0D
D7D8D
D8D0D
D8D8D
D9D0D
D9D8D
-
PP.DA1DR
PP.DA2DR
PP.DA3DR
PP.DA4DR
PP.DA5DR
PP.DA6DR
PP.DA7DR
PP.DA8DR
PP.DA9DR
PP.DMLSR
DTCHECFLS
DCHECFLS
DGSLS
DFURIE DFOVFIE
DGLCLS DGLCSLS
DFFLS
-
-
-
-
-
-
-
PP.DMLSIE
DCHECFI
E
DTCHECFIE
DGSIE
DGSLIE
DGLCIE DGLCSIE
DGPLC5 DGPLC4
DFFIE
-
3D7h
3D8h
3D9h
3DAh
3DBh
3DCh
3DDh
3DEh
3DFh
3E0h
3E1h
3E2h
3E3h
DGPLC7
DGPLC6
DGPLC3
DGPLC2
DGPLC1
DGPLC0
DGPLC8
PP.DGPLC
PP.DGBLC
PP.DSSR
DGPLC15 DGPLC14 DGPLC13 DGPLC12 DGPLC11 DGPLC10 DGPLC9
DBPLC7 DBPLC6 DBPLC5 DBPLC4 DBPLC3 DBPLC2 DBPLC1
DBPLC15 DBPLC14 DBPLC13 DBPLC12 DBPLC11 DBPLC10 DBPLC9
DBPLC0
DBPLC8
-
-
-
-
-
DGSYNC DGPSYNC DGHUNT
-
-
-
-
-
-
-
-
DHSR23
DHSR31
DHSR7
DHSR15
-
DHSR22
DHSR30
DHSR6
DHSR14
-
DHSR21
DHSR29
DHSR5
DHSR13
-
DHSR20
DHSR28
DHSR4
DHSR12
-
DHSR19
DHSR27
DHSR3
DHSR11
DEM
DHSR18
DHSR26
DHSR2
DHSR10
DSMRE
-
DHSR17
DHSR25
DHSR1
DHSR9
DHSR16
DHSR24
DHSR0
DHSR8
PP.DHHSR
PP.DHLSR
PP.DFSCR
DEPRE DFSRPWC
-
-
-
-
-
-
-
Rev: 063008
120 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
400h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
VCAT / LCAS TRANSMIT REGISTERS
V4FM1
V4FM0
V3FM1
V3FM0
V2FM1
TGIDBC
TV1MC3
TV3MC3
RSACK4
-
V2FM0
TGIDM
TV1MC2
TV3MC2
RSACK3
-
V1FM1
TLOAD
TV1MC1
TV3MC1
RSACK2
-
V1FM0
TVBLKEN
TV1MC0
TV3MC0
RSACK1
-
VCAT.TCR1
401h
402h
403h
406h
407h
408h
409h
40Ah
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
420h
421h
422h
423h
424h
425h
426h
427h
428h
429h
42Ah
42Bh
42Ch
42Dh
42Eh
42Fh
430h
431h
432h
433h
-
-
-
-
TV2MC3
TV2MC2
TV2MC1
TV2MC0
VCAT.TCR2
TV4MC3
TV4MC2
TV4MC1
TV4MC0
-
-
-
-
VCAT.TLCR1
VCAT.TLCR2
VCAT.TLCR3
VCAT.TLCR4
VCAT.TLCR5
VCAT.TLCR6
VCAT.TCR3(1)
VCAT.TCR3(2)
VCAT.TCR3(3)
VCAT.TCR3(4)
VCAT.TCR3(5)
VCAT.TCR3(6)
VCAT.TCR3(7)
VCAT.TCR3(8)
VCAT.TCR3(9)
VCAT.TCR3(10)
-
-
-
-
-
-
-
-
ATMSTD4 ATMSTD3 ATMSTD2 ATMSTD1
-
-
-
-
-
-
-
-
V1MST7
V1MST6
V1MST5
V1MST4
V1MST3
V1MST2
V1MST1
V1MST0
V1MST8
V2MST0
V2MST8
V3MST0
V3MST8
V4MST0
V4MST8
TPA
V1MST15 V1MST14 V1MST13 V1MST12 V1MST11 V1MST10 V1MST9
V2MST7 V2MST6 V2MST5 V2MST4 V2MST3 V2MST2 V2MST1
V2MST15 V2MST14 V2MST13 V2MST12 V2MST11 V2MST10 V2MST9
V3MST7 V3MST6 V3MST5 V3MST4 V3MST3 V3MST2 V3MST1
V3MST15 V3MST14 V3MST13 V3MST12 V3MST11 V3MST10 V3MST9
V4MST7 V4MST6 V4MST5 V4MST4 V4MST3 V4MST2 V4MST1
V4MST15 V4MST14 V4MST13 V4MST12 V4MST11 V4MST10 V4MST9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TNVCGC
TVGS2
TVSQ3
TVGS2
TVSQ3
TVGS2
TVSQ3
TVGS2
TVSQ3
TVGS2
TVSQ3
TVGS2
TVSQ3
TVGS2
TVSQ3
TVGS2
TVSQ3
TVGS2
TVSQ3
TVGS2
TVSQ3
TVGS1
TVSQ2
TVGS1
TVSQ2
TVGS1
TVSQ2
TVGS1
TVSQ2
TVGS1
TVSQ2
TVGS1
TVSQ2
TVGS1
TVSQ2
TVGS1
TVSQ2
TVGS1
TVSQ2
TVGS1
TVSQ2
TVGS0
TVSQ1
TVGS0
TVSQ1
TVGS0
TVSQ1
TVGS0
TVSQ1
TVGS0
TVSQ1
TVGS0
TVSQ1
TVGS0
TVSQ1
TVGS0
TVSQ1
TVGS0
TVSQ1
TVGS0
TVSQ1
-
TVSQ0
TPA
TNVCGC
-
TVSQ0
TPA
TNVCGC
-
TVSQ0
TPA
TNVCGC
-
TVSQ0
TPA
TNVCGC
-
TVSQ0
TPA
TNVCGC
-
TVSQ0
TPA
TNVCGC
-
TVSQ0
TPA
TNVCGC
-
TVSQ0
TPA
TNVCGC
-
TVSQ0
TPA
TNVCGC
-
TVSQ0
Rev: 063008
121 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
434h
BIT 7
BIT 6
BIT 5
BIT 4
TNVCGC
BIT 3
TVGS2
BIT 2
TVGS1
BIT 1
TVGS0
BIT 0
TPA
-
-
-
VCAT.TCR3(11)
435h
436h
437h
438h
439h
43Ah
43Bh
43Ch
43Dh
43Eh
43Fh
440h
441h
442h
443h
444h
445h
446h
447h
448h
449h
44Ah
44Bh
44Ch
44Dh
44Eh
44Fh
450h
451h
452h
453h
454h
455h
456h
457h
458h
459h
45Ah
45Bh
45Ch
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TVSQ3
TVGS2
TVSQ3
TVGS2
TVSQ3
TVGS2
TVSQ3
TVGS2
TVSQ3
TVGS2
TVSQ3
CTRL3
-
TVSQ2
TVGS1
TVSQ2
TVGS1
TVSQ2
TVGS1
TVSQ2
TVGS1
TVSQ2
TVGS1
TVSQ2
CTRL2
-
TVSQ1
TVGS0
TVSQ1
TVGS0
TVSQ1
TVGS0
TVSQ1
TVGS0
TVSQ1
TVGS0
TVSQ1
CTRL1
-
TVSQ0
TPA
TVSQ0
TPA
TVSQ0
TPA
TVSQ0
TPA
TVSQ0
TPA
TVSQ0
CTRL0
-
TNVCGC
VCAT.TCR3(12)
VCAT.TCR3(13)
VCAT.TCR3(14)
VCAT.TCR3(15)
VCAT.TCR3(16)
VCAT.TLCR8(1)
VCAT.TLCR8(2)
VCAT.TLCR8(3)
VCAT.TLCR8(4)
VCAT.TLCR8(5)
VCAT.TLCR8(6)
VCAT.TLCR8(7)
VCAT.TLCR8(8)
VCAT.TLCR8(9)
VCAT.TLCR8(10)
VCAT.TLCR8(11)
VCAT.TLCR8(12)
VCAT.TLCR8(13)
-
TNVCGC
-
TNVCGC
-
TNVCGC
-
TNVCGC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CTRL3
-
CTRL2
-
CTRL1
-
CTRL0
-
CTRL3
-
CTRL2
-
CTRL1
-
CTRL0
-
CTRL3
-
CTRL2
-
CTRL1
-
CTRL0
-
CTRL3
-
CTRL2
-
CTRL1
-
CTRL0
-
CTRL3
-
CTRL2
-
CTRL1
-
CTRL0
-
CTRL3
-
CTRL2
-
CTRL1
-
CTRL0
-
CTRL3
-
CTRL2
-
CTRL1
-
CTRL0
-
CTRL3
-
CTRL2
-
CTRL1
-
CTRL0
-
CTRL3
-
CTRL2
-
CTRL1
-
CTRL0
-
CTRL3
-
CTRL2
-
CTRL1
-
CTRL0
-
CTRL3
-
CTRL2
-
CTRL1
-
CTRL0
-
CTRL3
-
CTRL2
-
CTRL1
-
CTRL0
-
CTRL3
-
CTRL2
-
CTRL1
-
CTRL0
-
VCAT.TLCR8(14)
VCAT.TLCR8(15)
CTRL3
CTRL2
CTRL1
CTRL0
Rev: 063008
122 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
45Dh
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
-
-
-
-
-
-
-
-
45Eh
-
-
-
-
-
-
-
-
CTRL3
-
CTRL2
-
CTRL1
-
CTRL0
-
VCAT.TLCR8(16)
45Fh
480h
481h
482h
483h
484h
485h
486h
487h
TGID7
TGID6
TGID5
TGID4
TGID3
TGID11
TGID3
TGID11
TGID3
TGID11
TGID3
TGID11
TGID2
TGID10
TGID2
TGID10
TGID2
TGID10
TGID2
TGID10
TGID1
TGID9
TGID1
TGID9
TGID1
TGID9
TGID1
TGID9
TGID0
TGID8
TGID0
TGID8
TGID0
TGID8
TGID0
TGID8
VCAT.TCR4(1)
VCAT.TCR4(2)
VCAT.TCR4(3)
VCAT.TCR4(4)
TGID15
TGID7
TGID14
TGID6
TGID13
TGID5
TGID12
TGID4
TGID15
TGID7
TGID14
TGID6
TGID13
TGID5
TGID12
TGID4
TGID15
TGID7
TGID14
TGID6
TGID13
TGID5
TGID12
TGID4
TGID15
TGID14
TGID13
TGID12
VCAT / LCAS RECEIVE REGISTERS
500h
501h
502h
503h
504h
505h
508h
509h
50Ah
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
530h
531h
532h
533h
534h
535h
536h
537h
538h
-
-
SVINTD T3T1WG4 T3T1WG3 T3T1WG2 T3T1WG1 RVBLKEN
VCAT.RCR1
VCAT.RCR2
VCAT.RCR3
VCAT.RISR
-
LE4
-
-
LE3
-
-
LE2
-
RVEN4
RGIDBC
RVEN3
RVEN2
RVEN1
LE1
-
REALIGN4 REALIGN3 REALIGN2 REALIGN1
-
-
-
-
RV2MC3 RV2MC2 RV2MC1 RV2MC0 RV1MC3 RV1MC2 RV1MC1 RV1MC0
RV4MC3 RV4MC2 RV4MC1 RV4MC0 RV3MC3 RV3MC2 RV3MC1 RV3MC0
PISR8
PISR16
V1MST7
PISR7
PISR15
V1MST6
PISR6
PISR14
V1MST5
PISR5
PISR13
V1MST4
PISR4
PISR12
V1MST3
PISR3
PISR11
V1MST2
PISR2
PISR10
V1MST1
PISR1
PISR9
V1MST0
V1MST8
V2MST0
V2MST8
V3MST0
V3MST8
V4MST0
V4MST8
REALIGNL1
VCAT.RLSR1
VCAT.RLSR2
VCAT.RLSR3
VCAT.RLSR4
VCAT.RRLSR
VCAT.RRSIE
VCAT.RCR4(1)
VCAT.RCR4(2)
VCAT.RCR4(3)
V1MST15 V1MST14 V1MST13 V1MST12 V1MST11 V1MST10 V1MST9
V2MST7 V2MST6 V2MST5 V2MST4 V2MST3 V2MST2 V2MST1
V2MST15 V2MST14 V2MST13 V2MST12 V2MST11 V2MST10 V2MST9
V3MST7 V3MST6 V3MST5 V3MST4 V3MST3 V3MST2 V3MST1
V3MST15 V3MST14 V3MST13 V3MST12 V3MST11 V3MST10 V3MST9
V4MST7 V4MST6 V4MST5 V4MST4 V4MST3 V4MST2 V4MST1
V4MST15 V4MST14 V4MST13 V4MST12 V4MST11 V4MST10 V4MST9
REALIGNL4
REALIGNL3
REALIGNL2
DDE4
-
DDE3
-
DDE2
-
DDE1
-
VMSTC4 VMSTC3 VMSTC2 VMSTC1
REALIGNIE4 REALIGNIE3 REALIGNIE2 REALIGNIE1
VDDEIE4 VDDEIE3 VDDEIE2 VDDEIE1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VMSTCIE4 VMSTCIE3 VMSTCIE2 VMSTCIE1
RFM
RNVCGC
RVGS2
RVGS1
RVGS0
RPA
RFRST
RFM
-
-
-
-
-
RPA
-
RNVCGC
RVGS2
RVGS1
RVGS0
RFRST
RFM
-
-
-
-
RNVCGC
RVGS2
-
RVGS1
-
RVGS0
-
RPA
-
RFRST
RFM
-
RNVCGC
-
RVGS2
-
RVGS1
-
RVGS0
-
RPA
-
VCAT.RCR4(4)
VCAT.RCR4(5)
RFRST
RFM
RNVCGC
RVGS2
RVGS1
RVGS0
RPA
Rev: 063008
123 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
539h
BIT 7
RFRST
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
-
-
-
-
-
-
-
53Ah
RFM
RFRST
RFM
RFRST
RFM
RFRST
RFM
RFRST
RFM
RFRST
RFM
RFRST
RFM
RFRST
RFM
RFRST
RFM
RFRST
RFM
RFRST
RFM
RFRST
-
-
-
RNVCGC
-
RVGS2
RVGS1
RVGS0
RPA
VCAT.RCR4(6)
53Bh
53Ch
53Dh
53Eh
53Fh
540h
541h
542h
543h
544h
545h
546h
547h
548h
549h
54Ah
54Bh
54Ch
54Dh
54Eh
54Fh
550h
551h
552h
553h
554h
555h
556h
557h
558h
559h
55Ah
55Bh
55Ch
55Dh
55Eh
55Fh
560h
561h
-
-
-
-
-
-
RPA
-
-
-
RNVCGC
-
RVGS2
RVGS1
RVGS0
VCAT.RCR4(7)
VCAT.RCR4(8)
VCAT.RCR4(9)
VCAT.RCR4(10)
VCAT.RCR4(11)
VCAT.RCR4(12)
VCAT.RCR4(13)
VCAT.RCR4(14)
VCAT.RCR4(15)
VCAT.RCR4(16)
VCAT.RSR1(1)
VCAT.RSR1(2)
VCAT.RSR1(3)
VCAT.RSR1(4)
VCAT.RSR1(5)
VCAT.RSR1(6)
VCAT.RSR1(7)
VCAT.RSR1(8)
VCAT.RSR1(9)
-
-
-
-
-
-
-
RNVCGC
-
RVGS2
RVGS1
RVGS0
RPA
-
-
-
-
-
-
-
-
RNVCGC
-
RVGS2
RVGS1
RVGS0
RPA
-
-
-
-
-
-
-
-
RNVCGC
-
RVGS2
RVGS1
RVGS0
RPA
-
-
-
-
-
-
-
-
RNVCGC
-
RVGS2
RVGS1
RVGS0
RPA
-
-
-
-
-
-
-
-
RNVCGC
-
RVGS2
RVGS1
RVGS0
RPA
-
-
-
-
-
-
-
-
RNVCGC
-
RVGS2
RVGS1
RVGS0
RPA
-
-
-
-
-
-
-
-
RNVCGC
-
RVGS2
RVGS1
RVGS0
RPA
-
-
-
-
-
-
-
-
RNVCGC
-
RVGS2
RVGS1
RVGS0
RPA
-
-
-
-
-
-
-
-
RNVCGC
-
RVGS2
RVGS1
RVGS0
RPA
-
-
-
-
-
-
-
-
RSACK
RVSQ0
RSACK
RVSQ0
RSACK
RVSQ0
RSACK
RVSQ0
RSACK
RVSQ0
RSACK
RVSQ0
RSACK
RVSQ0
RSACK
RVSQ0
RSACK
RVSQ0
-
-
-
LOM
CTRL0
LOM
CTRL0
LOM
CTRL0
LOM
CTRL0
LOM
CTRL0
LOM
CTRL0
LOM
CTRL0
LOM
CTRL0
LOM
CTRL0
RVSQ3
-
RVSQ2
RVSQ1
CTRL3
CTRL2
CTRL1
-
-
-
-
-
RVSQ3
-
RVSQ2
RVSQ1
CTRL3
CTRL2
CTRL1
-
-
-
-
-
RVSQ3
-
RVSQ2
RVSQ1
CTRL3
CTRL2
CTRL1
-
-
-
-
-
RVSQ3
-
RVSQ2
RVSQ1
CTRL3
CTRL2
CTRL1
-
-
-
-
-
RVSQ3
-
RVSQ2
RVSQ1
CTRL3
CTRL2
CTRL1
-
-
-
-
-
RVSQ3
-
RVSQ2
RVSQ1
CTRL3
CTRL2
CTRL1
-
-
-
-
-
RVSQ3
-
RVSQ2
-
RVSQ1
-
CTRL3
-
CTRL2
-
CTRL1
-
RVSQ3
-
RVSQ2
-
RVSQ1
-
CTRL3
-
CTRL2
-
CTRL1
-
RVSQ3
RVSQ2
RVSQ1
CTRL3
CTRL2
CTRL1
Rev: 063008
124 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
562h
BIT 7
BIT 6
BIT 5
BIT 4
RSACK
BIT 3
BIT 2
BIT 1
BIT 0
LOM
-
-
-
-
-
-
VCAT.RSR1(10)
563h
564h
565h
566h
567h
568h
569h
56Ah
56Bh
56Ch
56Dh
56Eh
56Fh
570h
571h
572h
573h
574h
575h
576h
577h
578h
579h
57Ah
57Bh
57Ch
57Dh
57Eh
57Fh
580h
581h
582h
583h
584h
585h
586h
587h
588h
589h
58Ah
RVSQ3
RVSQ2
RVSQ1
RVSQ0
CTRL3
CTRL2
CTRL1
CTRL0
LOM
CTRL0
LOM
CTRL0
LOM
CTRL0
LOM
CTRL0
LOM
CTRL0
LOM
CTRL0
EMF
-
-
-
-
RSACK
-
-
-
VCAT.RSR1(11)
VCAT.RSR1(12)
VCAT.RSR1(13)
VCAT.RSR1(14)
VCAT.RSR1(15)
VCAT.RSR1(16)
VCAT.RSR2(1)
VCAT.RSR2(2)
VCAT.RSR2(3)
VCAT.RSR2(4)
VCAT.RSR2(5)
VCAT.RSR2(6)
VCAT.RSR2(7)
VCAT.RSR2(8)
VCAT.RSR2(9)
VCAT.RSR2(10)
VCAT.RSR2(11)
VCAT.RSR2(12)
RVSQ3
RVSQ2
RVSQ1
RVSQ0
CTRL3
CTRL2
CTRL1
-
-
-
RSACK
-
-
-
RVSQ3
RVSQ2
RVSQ1
RVSQ0
CTRL3
CTRL2
CTRL1
-
-
-
RSACK
-
-
-
RVSQ3
RVSQ2
RVSQ1
RVSQ0
CTRL3
CTRL2
CTRL1
-
-
-
RSACK
-
-
-
RVSQ3
RVSQ2
RVSQ1
RVSQ0
CTRL3
CTRL2
CTRL1
-
-
-
RSACK
-
-
-
RVSQ3
RVSQ2
RVSQ1
RVSQ0
CTRL3
CTRL2
CTRL1
-
-
-
RSACK
-
-
-
RVSQ3
RVSQ2
RVSQ1
RVSQ0
CTRL3
CTRL2
CTRL1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CRCE
GID
SEMF
-
-
-
CRCE
GID
SEMF
EMF
-
-
-
-
CRCE
GID
SEMF
EMF
-
-
-
GID
-
-
CRCE
SEMF
EMF
-
-
-
CRCE
GID
-
SEMF
EMF
-
-
-
CRCE
GID
-
SEMF
EMF
-
-
-
CRCE
GID
-
SEMF
EMF
-
-
-
CRCE
GID
-
SEMF
EMF
-
-
-
CRCE
GID
-
SEMF
EMF
-
-
-
CRCE
GID
-
SEMF
EMF
-
-
-
CRCE
GID
-
SEMF
EMF
-
-
-
CRCE
-
GID
-
SEMF
-
EMF
-
CRCE
-
GID
-
SEMF
-
EMF
-
VCAT.RSR2(13)
VCAT.RSR2(14)
CRCE
GID
SEMF
EMF
Rev: 063008
125 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
58Bh
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
-
-
-
-
-
-
-
-
58Ch
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CRCE
GID
SEMF
EMF
VCAT.RSR2(15)
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
5A1h
5A2h
5A3h
5A4h
5A5h
5A6h
5A7h
5A8h
5A9h
5AAh
5ABh
5ACh
5ADh
5AEh
5AFh
5B0h
5B1h
5B2h
5B3h
-
-
-
-
-
-
CRCE
GID
SEMF
EMF
VCAT.RSR2(16)
VCAT.RSLSR(1)
VCAT.RSLSR(2)
VCAT.RSLSR(3)
VCAT.RSLSR(4)
VCAT.RSLSR(5)
VCAT.RSLSR(6)
VCAT.RSLSR(7)
VCAT.RSLSR(8)
VCAT.RSLSR(9)
VCAT.RSLSR(10)
VCAT.RSLSR(11)
VCAT.RSLSR(12)
VCAT.RSLSR(13)
VCAT.RSLSR(14)
VCAT.RSLSR(15)
VCAT.RSLSR(16)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RSACKL
SQL
CTRL
LOML
-
-
-
-
RSACKL
SQL
CTRL
LOML
-
-
-
-
RSACKL
SQL
CTRL
LOML
-
-
-
-
RSACKL
SQL
CTRL
LOML
-
-
-
-
RSACKL
SQL
CTRL
LOML
-
-
-
-
RSACKL
SQL
CTRL
LOML
-
-
-
-
RSACKL
SQL
CTRL
LOML
-
-
-
-
RSACKL
SQL
CTRL
LOML
-
-
-
-
RSACKL
SQL
CTRL
LOML
-
-
-
-
RSACKL
SQL
CTRL
LOML
-
-
-
-
RSACKL
SQL
CTRL
LOML
-
-
-
-
RSACKL
SQL
CTRL
LOML
-
-
-
-
RSACKL
SQL
CTRL
LOML
-
-
-
-
RSACKL
SQL
CTRL
LOML
-
-
-
-
RSACKL
SQL
CTRL
LOML
-
-
-
-
RSACKL
SQL
CTRL
LOML
-
-
-
-
RSACKIE
SQIE
CTRIE
LOMIE
VCAT.RSIE(1)
VCAT.RSIE(2)
-
-
SQIE
-
-
-
RSACKIE
-
CTRIE
-
LOMIE
-
Rev: 063008
126 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
5B4h
BIT 7
BIT 6
BIT 5
BIT 4
RSACKIE
BIT 3
SQIE
BIT 2
CTRIE
BIT 1
BIT 0
LOMIE
-
-
-
-
VCAT.RSIE(3)
5B5h
5B6h
5B7h
5B8h
5B9h
5BAh
5BBh
5BCh
5BDh
5BEh
5BFh
5C0h
5C1h
5C2h
5C3h
5C4h
5C5h
5C6h
5C7h
5C8h
5C9h
5CAh
5CBh
5CCh
5CDh
5CEh
5CFh
5D0h
5D1h
5D2h
5D3h
5D4h
5D5h
5D6h
5D7h
5D8h
5D9h
5DAh
5DBh
5DCh
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SQIE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RSACKIE
-
CTRIE
-
LOMIE
-
VCAT.RSIE(4)
VCAT.RSIE(5)
VCAT.RSIE(6)
VCAT.RSIE(7)
VCAT.RSIE(8)
VCAT.RSIE(9)
VCAT.RSIE(10)
VCAT.RSIE(11)
VCAT.RSIE(12)
VCAT.RSIE(13)
VCAT.RSIE(14)
VCAT.RSIE(15)
VCAT.RSIE(16)
VCAT.RSR3(1)
VCAT.RSR3(2)
VCAT.RSR3(3)
VCAT.RSR3(4)
VCAT.RSR3(5)
RSACKIE
-
SQIE
-
CTRIE
-
LOMIE
-
RSACKIE
-
SQIE
-
CTRIE
-
LOMIE
-
RSACKIE
-
SQIE
-
CTRIE
-
LOMIE
-
RSACKIE
-
SQIE
-
CTRIE
-
LOMIE
-
RSACKIE
-
SQIE
-
CTRIE
-
LOMIE
-
RSACKIE
-
SQIE
-
CTRIE
-
LOMIE
-
RSACKIE
-
SQIE
-
CTRIE
-
LOMIE
-
RSACKIE
-
SQIE
-
CTRIE
-
LOMIE
-
RSACKIE
-
SQIE
-
CTRIE
-
LOMIE
-
RSACKIE
-
SQIE
-
CTRIE
-
LOMIE
-
RSACKIE
-
SQIE
-
CTRIE
-
LOMIE
-
RSACKIE
-
SQIE
-
CTRIE
-
LOMIE
-
RGID7
RGID6
RGID5
RGID4
RGID12
RGID4
RGID12
RGID4
RGID12
RGID4
RGID12
RGID4
RGID12
RGID4
RGID12
RGID4
RGID3
RGID11
RGID3
RGID11
RGID3
RGID11
RGID3
RGID11
RGID3
RGID11
RGID3
RGID11
RGID3
RGID2
RGID10
RGID2
RGID10
RGID2
RGID10
RGID2
RGID10
RGID2
RGID10
RGID2
RGID10
RGID2
RGID1
RGID0
RGID8
RGID0
RGID8
RGID0
RGID8
RGID0
RGID8
RGID0
RGID8
RGID0
RGID8
RGID0
RGID15
RGID7
RGID15
RGID7
RGID15
RGID7
RGID15
RGID7
RGID15
RGID7
RGID15
RGID7
RGID14
RGID6
RGID14
RGID6
RGID14
RGID6
RGID14
RGID6
RGID14
RGID6
RGID14
RGID6
RGID13
RGID5
RGID13
RGID5
RGID13
RGID5
RGID13
RGID5
RGID13
RGID5
RGID13
RGID5
RGID9
RGID1
RGID9
RGID1
RGID9
RGID1
RGID9
RGID1
RGID9
RGID1
RGID9
RGID1
VCAT.RSR3(6)
VCAT.RSR3(7)
Rev: 063008
127 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
5DDh
BIT 7
RGID15
BIT 6
RGID14
BIT 5
RGID13
BIT 4
RGID12
BIT 3
RGID11
BIT 2
RGID10
BIT 1
RGID9
BIT 0
RGID8
5DEh
RGID7
RGID15
RGID7
RGID15
RGID7
RGID15
RGID7
RGID15
RGID7
RGID15
RGID7
RGID15
RGID7
RGID15
RGID7
RGID15
RGID7
RGID15
RGID6
RGID14
RGID6
RGID14
RGID6
RGID14
RGID6
RGID14
RGID6
RGID14
RGID6
RGID14
RGID6
RGID14
RGID6
RGID14
RGID6
RGID14
RGID5
RGID13
RGID5
RGID13
RGID5
RGID13
RGID5
RGID13
RGID5
RGID13
RGID5
RGID13
RGID5
RGID13
RGID5
RGID13
RGID5
RGID13
RGID4
RGID12
RGID4
RGID12
RGID4
RGID12
RGID4
RGID12
RGID4
RGID12
RGID4
RGID12
RGID4
RGID12
RGID4
RGID12
RGID4
RGID12
RGID3
RGID11
RGID3
RGID11
RGID3
RGID11
RGID3
RGID11
RGID3
RGID11
RGID3
RGID11
RGID3
RGID11
RGID3
RGID11
RGID3
RGID11
RGID2
RGID10
RGID2
RGID10
RGID2
RGID10
RGID2
RGID10
RGID2
RGID10
RGID2
RGID10
RGID2
RGID10
RGID2
RGID10
RGID2
RGID10
RGID1
RGID9
RGID1
RGID9
RGID1
RGID9
RGID1
RGID9
RGID1
RGID9
RGID1
RGID9
RGID1
RGID9
RGID1
RGID9
RGID1
RGID9
RGID0
RGID8
RGID0
RGID8
RGID0
RGID8
RGID0
RGID8
RGID0
RGID8
RGID0
RGID8
RGID0
RGID8
RGID0
RGID8
RGID0
RGID8
VCAT.RSR3(8)
5DFh
5E0h
5E1h
5E2h
5E3h
5E4h
5E5h
5E6h
5E7h
5E8h
5E9h
5EAh
5EBh
5ECh
5EDh
5EEh
5EFh
VCAT.RSR3(9)
VCAT.RSR3(10)
VCAT.RSR3(11)
VCAT.RSR3(12)
VCAT.RSR3(13)
VCAT.RSR3(14)
VCAT.RSR3(15)
VCAT.RSR3(16)
SERIAL INTERFACE GLOBAL
600h
601h
602h
603h
604h
605h
606h
607h
608h
609h
60Ah
60Bh
LLB8
LLB16
TLB8
TLB16
TCLKA8
-
LLB7
LLB15
TLB7
TLB15
TCLKA7
-
LLB6
LLB14
TLB6
TLB14
TCLKA6
-
LLB5
LLB13
TLB5
LLB4
LLB12
TLB4
TLB12
TCLKA4
-
LLB3
LLB11
TLB3
TLB11
TCLKA3
-
LLB2
LLB10
TLB2
TLB10
TCLKA2
-
LLB1
LLB9
LI.LCR1
LI.LCR2
LI.TCSR
LI.TVCSR
LI.RCSR
LI.RVCSR
TLB1
TLB13
TCLKA5
TMCLKA4
-
TLB9
TCLKA1
TMCLKA3
TVCLKA1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RCLKA8
RCLKA7
RCLKA6
RCLKA5
RCLKA4
RCLKA3
RCLKA2
RCLKA1
RCLKA16 RCLKA15 RCLKA14 RCLKA13 RCLKA12 RCLKA11 RCLKA10 RCLKA9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RVCLKA1
-
TRANSMIT SERIAL PER-PORT
TS_SETUP1 TS_SETUP0
640h
641h
648h
649h
650h
651h
658h
659h
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TCLKINV
-
-
-
-
-
-
-
-
TD_SEL
LI.TCR(1)
LI.TCR(2)
LI.TCR(3)
LI.TCR(4)
-
-
-
-
TS_SETUP1 TS_SETUP0
TCLKINV
TD_SEL
-
-
-
-
TS_SETUP1 TS_SETUP0
TCLKINV
TD_SEL
-
-
-
-
TS_SETUP1 TS_SETUP0
TCLKINV
-
TD_SEL
-
-
-
Rev: 063008
128 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
660h
BIT 7
BIT 6
BIT 5
BIT 4
TCLKINV
BIT 3
BIT 2
BIT 1
BIT 0
TD_SEL
TS_SETUP1 TS_SETUP0
-
-
-
-
LI.TCR(5)
661h
668h
669h
670h
671h
678h
679h
680h
681h
688h
689h
690h
691h
698h
699h
6A0h
6A1h
6A8h
6A9h
6B0h
6B1h
6B8h
6B9h
6C0h
6C1h
6C2h
6C3h
6C4h
6C5h
6C6h
6C7h
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TS_SETUP1 TS_SETUP0
-
-
-
TCLKINV
TD_SEL
LI.TCR(6)
LI.TCR(7)
LI.TCR(8)
LI.TCR(9)
LI.TCR(10)
LI.TCR(11)
LI.TCR(12)
LI.TCR(13)
LI.TCR(14)
LI.TCR(15)
LI.TCR(16)
LI.TVPCR
LI.TVFSR
LI.TVFLSR
LI.TVFSRIE
-
-
-
-
-
-
-
TS_SETUP1 TS_SETUP0
-
-
-
TCLKINV
TD_SEL
-
-
-
-
-
-
-
TS_SETUP1 TS_SETUP0
-
-
-
TCLKINV
TD_SEL
-
-
-
-
-
-
-
TS_SETUP1 TS_SETUP0
-
-
-
TCLKINV
-
-
-
-
-
-
-
-
TS_SETUP1 TS_SETUP0
-
-
-
TCLKINV
-
-
-
-
-
-
-
-
TS_SETUP1 TS_SETUP0
-
-
-
TCLKINV
-
-
-
-
-
-
-
-
TS_SETUP1 TS_SETUP0
-
-
-
TCLKINV
-
-
-
-
-
-
-
-
TS_SETUP1 TS_SETUP0
-
-
-
TCLKINV
-
-
-
-
-
-
-
-
TS_SETUP1 TS_SETUP0
-
-
-
TCLKINV
-
-
-
-
-
-
-
-
TS_SETUP1 TS_SETUP0
-
-
-
TCLKINV
-
-
-
-
-
-
-
-
TS_SETUP1 TS_SETUP0
-
-
-
TCLKINV
-
-
-
-
-
-
-
PC
-
TPE
TVCLKI
TVFO
-
TVOPF4
TVOPF3
TVOPF2
TVOPF1
TVOPF0 TSYNCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TVFRST
TVFU
-
TVFUL
-
TVFOL
-
TVFULIE TVFOLIE
-
-
Rev: 063008
129 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR Name
740h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RECEIVE SERIAL PER-PORT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RCLKINV
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RFRST
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LI.RCR1(1)
741h
748h
749h
750h
751h
758h
759h
760h
761h
768h
769h
770h
771h
778h
779h
780h
781h
788h
789h
790h
791h
798h
799h
7A0h
7A1h
7A8h
7A9h
7B0h
7B1h
7B8h
7B9h
7C0h
7C1h
-
-
RCLKINV
RFRST
LI.RCR1(2)
LI.RCR1(3)
LI.RCR1(4)
LI.RCR1(5)
LI.RCR1(6)
LI.RCR1(7)
LI.RCR1(8)
LI.RCR1(9)
LI.RCR1(10)
LI.RCR1(11)
LI.RCR1(12)
LI.RCR1(13)
LI.RCR1(14)
LI.RCR1(15)
LI.RCR1(16)
LI.RVPCR
-
-
RCLKINV
RFRST
-
-
RCLKINV
RFRST
-
-
RCLKINV
RFRST
-
-
RCLKINV
RFRST
-
-
RCLKINV
RFRST
-
-
RCLKINV
RFRST
-
-
RCLKINV
RFRST
-
-
RCLKINV
RFRST
-
-
RCLKINV
RFRST
-
-
RCLKINV
RFRST
-
-
RCLKINV
RFRST
-
-
RCLKINV
RFRST
-
-
RCLKINV
RFRST
-
-
RFRST
-
RCLKINV
-
RVOPF4 RVOPF3 RVOPF2 RVOPF1 RVOPF0 RSYNCC
PC
RPE
-
-
-
-
-
-
RVFRST
RVCLKI
Rev: 063008
130 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
10.1.2 MAC Indirect Register Bit Map
Table 10-3. MAC Indirect Register Bit Map
ADDR
NAME
SU.MACCR
31:24
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0000h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
23:16
15:8
7:0
WDD
GMIIMIIS
ACST
JD
EM
FBE
DRO
JFE
LM
DC
Reserved Reserved Reserved Reserved
DM
TE
Reserved
RE
DRTY
Reserved Reserved
APST
BOLMT1 BOLMT0
SU.MACFFR
31:24
0004h
0008h
000Ch
0010h
0014h
0018h
001Ch
RAF
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
23:16
15:8
7:0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PCF
Reserved
DBF
PAM
INVF
HFUF
HFMF
PM
SU.MACHTHR
31:24
HTH[31] HTH[30] HTH[29] HTH[28] HTH[27] HTH[26] HTH[25] HTH[24]
23:16
15:8
7:0
HTH[23] HTH[22] HTH[21] HTH[20] HTH[19] HTH[18] HTH[17] HTH[16]
HTH[15] HTH[14] HTH[13] HTH[12] HTH[11] HTH[10]
HTH[7] HTH[6] HTH[5] HTH[4] HTH[3] HTH[2]
HTH[9]
HTH[1]
HTH[8]
HTH[0]
SU.MACHTLR
31:24
HTL[31] HTL[30] HTL[29] HTL[28] HTL[27] HTL[26] HTL[25] HTL[24]
23:16
15:8
7:0
SU.GMIIA
31:24
23:16
15:8
7:0
SU.GMIID
31:24
HTL[23] HTL[22] HTL[21] HTL[20] HTL[19] HTL[18] HTL[17] HTL[16]
HTL[15] HTL[14] HTL[13] HTL[12] HTL[11] HTL[10]
HTL[7] HTL[6] HTL[5] HTL[4] HTL[3] HTL[2]
HTL[9]
HTL[1]
HTL[8]
HTL[0]
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PPA[4]
GM[1]
PPA[3]
GM[0]
PPA[2]
Reserved Reserved
PPA[1]
PPA[0]
CR[1]
GM[4]
CR[0]
GM[3]
GW
GM[2]
GB
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
23:16
15:8
7:0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
GD[15]
GD[7]
GD[14]
GD[6]
GD[13]
GD[5]
GD[12]
GD[4]
GD[11]
GD[3]
GD[10]
GD[2]
GD[9]
GD[1]
GD[8]
GD[0]
SU.MACFCR
31:24
PT[15]
PT[14]
PT[13]
PT[12]
PT[11]
PT[10]
PT[9]
PT[8]
23:16
15:8
7:0
PT[7]
PT[6]
PT[5]
PT[4]
PT[3]
PT[2]
PT[1]
PT[0]
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved
PLT
UP
RFE
TFE
FCB
SU.VLANTR
31:24
-
-
-
-
-
-
-
-
23:16
15:8
7:0
-
-
-
-
-
-
-
-
VLTID[15]
VLTID[7]
VLTID[14]
VLTID[6]
VLTID[13]
VLTID[5]
VLTID[12]
VLTID[4]
VLTID[11]
VLTID[3]
VLTID[10]
VLTID[2]
VLTID[9]
VLTID[1]
VLTID[8]
VLTID[0]
SU.ADDR0H
31:24
MADDR0AE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0040h
0044h
23:16
15:8
7:0
MADDR0[47] MADDR0[46] MADDR0[45] MADDR0[44] MADDR0[43] MADDR0[42] MADDR0[41] MADDR0[40]
MADDR0[39] MADDR0[38] MADDR0[37] MADDR0[36] MADDR0[35] MADDR0[34] MADDR0[33] MADDR0[32]
SU.ADDR0L
31:24
MADDR0[31] MADDR0[30] MADDR0[29] MADDR0[28] MADDR0[27] MADDR0[26] MADDR0[25] MADDR0[24]
MADDR0[23] MADDR0[22] MADDR0[21] MADDR0[20] MADDR0[19] MADDR0[18] MADDR0[17] MADDR0[16]
23:16
15:8
7:0
MADDR0[15] MADDR0[14] MADDR0[13] MADDR0[12] MADDR0[11] MADDR0[10]
MADDR0[7] MADDR0[6] MADDR0[5] MADDR0[4] MADDR0[3] MADDR0[2]
MADDR0[9]
MADDR0[1]
MADDR0[8]
MADDR0[0]
Rev: 063008
131 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR
NAME
SU.ADDR1H
31:24
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MADDR1AE
-
-
-
-
-
-
-
0048h
23:16
15:8
7:0
-
-
-
-
-
-
-
-
MADDR1[47] MADDR1[46] MADDR1[45] MADDR1[44] MADDR1[43] MADDR1[42] MADDR1[41] MADDR1[40]
MADDR1[39] MADDR1[38] MADDR1[37] MADDR1[36] MADDR1[35] MADDR1[34] MADDR1[33] MADDR1[32]
SU.ADDR1L
31:24
MADDR1[31] MADDR1[30] MADDR1[29] MADDR1[28] MADDR1[27] MADDR1[26] MADDR1[25] MADDR1[24]
MADDR1[23] MADDR1[22] MADDR1[21] MADDR1[20] MADDR1[19] MADDR1[18] MADDR1[17] MADDR1[16]
004Ch
0050h
0054h
0058h
005Ch
0060h
0064h
0068h
006Ch
0070h
23:16
15:8
7:0
MADDR1[15] MADDR1[14] MADDR1[13] MADDR1[12] MADDR1[11] MADDR1[10]
MADDR1[9]
MADDR1[1]
MADDR1[8]
MADDR1[0]
MADDR1[7]
MADDR2AE
-
MADDR1[6]
MADDR1[5]
MADDR1[4]
MADDR1[3]
MADDR1[2]
SU.ADDR2H
31:24
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23:16
15:8
7:0
MADDR2[47] MADDR2[46] MADDR2[45] MADDR2[44] MADDR2[43] MADDR2[42] MADDR2[41] MADDR2[40]
MADDR2[39] MADDR2[38] MADDR2[37] MADDR2[36] MADDR2[35] MADDR2[34] MADDR2[33] MADDR2[32]
SU.ADDR2L
31:24
MADDR2[31] MADDR2[30] MADDR2[29] MADDR2[28] MADDR2[27] MADDR2[26] MADDR2[25] MADDR2[24]
MADDR2[23] MADDR2[22] MADDR2[21] MADDR2[20] MADDR2[19] MADDR2[18] MADDR2[17] MADDR2[16]
23:16
15:8
7:0
MADDR2[15] MADDR2[14] MADDR2[13] MADDR2[12] MADDR2[11] MADDR2[10]
MADDR2[9]
MADDR2[1]
MADDR2[8]
MADDR2[0]
MADDR2[7]
MADDR3AE
-
MADDR2[6]
MADDR2[5]
MADDR2[4]
MADDR2[3]
MADDR2[2]
SU.ADDR3H
31:24
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23:16
15:8
7:0
MADDR3[47] MADDR3[46] MADDR3[45] MADDR3[44] MADDR3[43] MADDR3[42] MADDR3[41] MADDR3[40]
MADDR3[39] MADDR3[38] MADDR3[37] MADDR3[36] MADDR3[35] MADDR3[34] MADDR3[33] MADDR3[32]
SU.ADDR3L
31:24
MADDR3[31] MADDR3[30] MADDR3[29] MADDR3[28] MADDR3[27] MADDR3[26] MADDR3[25] MADDR3[24]
MADDR3[23] MADDR3[22] MADDR3[21] MADDR3[20] MADDR3[19] MADDR3[18] MADDR3[17] MADDR3[16]
23:16
15:8
7:0
MADDR3[15] MADDR3[14] MADDR3[13] MADDR3[12] MADDR3[11] MADDR3[10]
MADDR3[9]
MADDR3[1]
MADDR3[8]
MADDR3[0]
MADDR3[7]
MADDR4AE
-
MADDR3[6]
MADDR3[5]
MADDR3[4]
MADDR3[3]
MADDR3[2]
SU.ADDR4H
31:24
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23:16
15:8
7:0
MADDR4[47] MADDR4[46] MADDR4[45] MADDR4[44] MADDR4[43] MADDR4[42] MADDR4[41] MADDR4[40]
MADDR4[39] MADDR4[38] MADDR4[37] MADDR4[36] MADDR4[35] MADDR4[34] MADDR4[33] MADDR4[32]
SU.ADDR4L
31:24
MADDR4[31] MADDR4[30] MADDR4[29] MADDR4[28] MADDR4[27] MADDR4[26] MADDR4[25] MADDR4[24]
MADDR4[23] MADDR4[22] MADDR4[21] MADDR4[20] MADDR4[19] MADDR4[18] MADDR4[17] MADDR4[16]
23:16
15:8
7:0
MADDR4[15] MADDR4[14] MADDR4[13] MADDR4[12] MADDR4[11] MADDR4[10]
MADDR4[9]
MADDR4[1]
MADDR4[8]
MADDR4[0]
MADDR4[7]
MADDR5AE
-
MADDR4[6]
MADDR4[5]
MADDR4[4]
MADDR4[3]
MADDR4[2]
SU.ADDR5H
31:24
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23:16
15:8
7:0
MADDR5[47] MADDR5[46] MADDR5[45] MADDR5[44] MADDR5[43] MADDR5[42] MADDR5[41] MADDR5[40]
MADDR5[39] MADDR5[38] MADDR5[37] MADDR5[36] MADDR5[35] MADDR5[34] MADDR5[33] MADDR5[32]
SU.ADDR5L
31:24
MADDR5[31] MADDR5[30] MADDR5[29] MADDR5[28] MADDR5[27] MADDR5[26] MADDR5[25] MADDR5[24]
MADDR5[23] MADDR5[22] MADDR5[21] MADDR5[20] MADDR5[19] MADDR5[18] MADDR5[17] MADDR5[16]
23:16
15:8
7:0
MADDR5[15] MADDR5[14] MADDR5[13] MADDR5[12] MADDR5[11] MADDR5[10]
MADDR5[9]
MADDR5[1]
MADDR5[8]
MADDR5[0]
MADDR5[7]
MADDR6AE
MADDR5[6]
-
MADDR5[5]
-
MADDR5[4]
-
MADDR5[3]
-
MADDR5[2]
-
SU.ADDR6H
31:24
-
-
Rev: 063008
132 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR
NAME
23:16
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
-
-
-
-
-
-
-
-
15:8
7:0
MADDR6[47] MADDR6[46] MADDR6[45] MADDR6[44] MADDR6[43] MADDR6[42] MADDR6[41] MADDR6[40]
MADDR6[39] MADDR6[38] MADDR6[37] MADDR6[36] MADDR6[35] MADDR6[34] MADDR6[33] MADDR6[32]
SU.ADDR6L
31:24
MADDR6[31] MADDR6[30] MADDR6[29] MADDR6[28] MADDR6[27] MADDR6[26] MADDR6[25] MADDR6[24]
MADDR6[23] MADDR6[22] MADDR6[21] MADDR6[20] MADDR6[19] MADDR6[18] MADDR6[17] MADDR6[16]
0074h
23:16
15:8
7:0
MADDR6[15] MADDR6[14] MADDR6[13] MADDR6[12] MADDR6[11] MADDR6[10]
MADDR6[9]
MADDR6[1]
MADDR6[8]
MADDR6[0]
MADDR6[7]
MADDR7AE
-
MADDR6[6]
MADDR6[5]
MADDR6[4]
MADDR6[3]
MADDR6[2]
SU.ADDR7H
31:24
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0078h
007Ch
0080h
0084h
0088h
008Ch
0090h
0094h
0098h
23:16
15:8
7:0
MADDR7[47] MADDR7[46] MADDR7[45] MADDR7[44] MADDR7[43] MADDR7[42] MADDR7[41] MADDR7[40]
MADDR7[39] MADDR7[38] MADDR7[37] MADDR7[36] MADDR7[35] MADDR7[34] MADDR7[33] MADDR7[32]
SU.ADDR7L
31:24
MADDR7[31] MADDR7[30] MADDR7[29] MADDR7[28] MADDR7[27] MADDR7[26] MADDR7[25] MADDR7[24]
MADDR7[23] MADDR7[22] MADDR7[21] MADDR7[20] MADDR7[19] MADDR7[18] MADDR7[17] MADDR7[16]
23:16
15:8
7:0
MADDR7[15] MADDR7[14] MADDR7[13] MADDR7[12] MADDR7[11] MADDR7[10]
MADDR7[9]
MADDR7[1]
MADDR7[8]
MADDR7[0]
MADDR7[7]
MADDR8AE
-
MADDR7[6]
MADDR7[5]
MADDR7[4]
MADDR7[3]
MADDR7[2]
SU.ADDR8H
31:24
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23:16
15:8
7:0
MADDR8[47] MADDR8[46] MADDR8[45] MADDR8[44] MADDR8[43] MADDR8[42] MADDR8[41] MADDR8[40]
MADDR8[39] MADDR8[38] MADDR8[37] MADDR8[36] MADDR8[35] MADDR8[34] MADDR8[33] MADDR8[32]
SU.ADDR8L
31:24
MADDR8[31] MADDR8[30] MADDR8[29] MADDR8[28] MADDR8[27] MADDR8[26] MADDR8[25] MADDR8[24]
MADDR8[23] MADDR8[22] MADDR8[21] MADDR8[20] MADDR8[19] MADDR8[18] MADDR8[17] MADDR8[16]
23:16
15:8
7:0
MADDR8[15] MADDR8[14] MADDR8[13] MADDR8[12] MADDR8[11] MADDR8[10]
MADDR8[9]
MADDR8[1]
MADDR8[8]
MADDR8[0]
MADDR8[7]
MADDR9AE
-
MADDR8[6]
MADDR8[5]
MADDR8[4]
MADDR8[3]
MADDR8[2]
SU.ADDR9H
31:24
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23:16
15:8
7:0
MADDR9[47] MADDR9[46] MADDR9[45] MADDR9[44] MADDR9[43] MADDR9[42] MADDR9[41] MADDR9[40]
MADDR9[39] MADDR9[38] MADDR9[37] MADDR9[36] MADDR9[35] MADDR9[34] MADDR9[33] MADDR9[32]
SU.ADDR9L
31:24
MADDR9[31] MADDR9[30] MADDR9[29] MADDR9[28] MADDR9[27] MADDR9[26] MADDR9[25] MADDR9[24]
MADDR9[23] MADDR9[22] MADDR9[21] MADDR9[20] MADDR9[19] MADDR9[18] MADDR9[17] MADDR9[16]
23:16
15:8
7:0
MADDR9[15] MADDR9[14] MADDR9[13] MADDR9[12] MADDR9[11] MADDR9[10]
MADDR9[9]
MADDR9[1]
MADDR9[8]
MADDR9[0]
MADDR9[7]
MADDR10AE
-
MADDR9[6]
MADDR9[5]
MADDR9[4]
MADDR9[3]
MADDR9[2]
SU.ADDR10H
31:24
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23:16
15:8
7:0
MADDR10[47] MADDR10[46] MADDR10[45] MADDR10[44] MADDR10[43] MADDR10[42] MADDR10[41] MADDR10[40]
MADDR10[39] MADDR10[38] MADDR10[37] MADDR10[36] MADDR10[35] MADDR10[34] MADDR10[33] MADDR10[32]
SU.ADDR10L
31:24
MADDR10[31] MADDR10[30] MADDR10[29] MADDR10[28] MADDR10[27] MADDR10[26] MADDR10[25] MADDR10[24]
23:16
15:8
7:0
MADDR10[23] MADDR10[22] MADDR10[21] MADDR10[20] MADDR10[19] MADDR10[18] MADDR10[17] MADDR10[16]
MADDR10[15] MADDR10[14] MADDR10[13] MADDR10[12] MADDR10[11] MADDR10[10] MADDR10[9] MADDR10[8]
MADDR10[7] MADDR10[6] MADDR10[5] MADDR10[4] MADDR10[3] MADDR10[2] MADDR10[1] MADDR10[0]
SU.ADDR11H
31:24
MADDR11AE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23:16
-
Rev: 063008
133 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR
NAME
15:8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MADDR11[47] MADDR11[46] MADDR11[45] MADDR11[44] MADDR11[43] MADDR11[42] MADDR11[41] MADDR11[40]
7:0
MADDR11[39] MADDR11[38] MADDR11[37] MADDR11[36] MADDR11[35] MADDR11[34] MADDR11[33] MADDR11[32]
SU.ADDR11L
31:24
MADDR11[31] MADDR11[30] MADDR11[29] MADDR11[28] MADDR11[27] MADDR11[26] MADDR11[25] MADDR11[24]
009Ch
23:16
15:8
7:0
MADDR11[23] MADDR11[22] MADDR11[21] MADDR11[20] MADDR11[19] MADDR11[18] MADDR11[17] MADDR11[16]
MADDR11[15] MADDR11[14] MADDR11[13] MADDR11[12] MADDR11[11] MADDR11[10] MADDR11[9] MADDR11[8]
MADDR11[7] MADDR11[6] MADDR11[5] MADDR11[4] MADDR11[3] MADDR11[2] MADDR11[1] MADDR11[0]
SU.ADDR12H
31:24
MADDR12AE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
00A0h
00A4h
00A8h
00ACh
00B0h
00B4h
00B8h
00BCh
00C0h
23:16
15:8
7:0
MADDR12[47] MADDR12[46] MADDR12[45] MADDR12[44] MADDR12[43] MADDR12[42] MADDR12[41] MADDR12[40]
MADDR12[39] MADDR12[38] MADDR12[37] MADDR12[36] MADDR12[35] MADDR12[34] MADDR12[33] MADDR12[32]
SU.ADDR12L
31:24
MADDR12[31] MADDR12[30] MADDR12[29] MADDR12[28] MADDR12[27] MADDR12[26] MADDR12[25] MADDR12[24]
23:16
15:8
7:0
MADDR12[23] MADDR12[22] MADDR12[21] MADDR12[20] MADDR12[19] MADDR12[18] MADDR12[17] MADDR12[16]
MADDR12[15] MADDR12[14] MADDR12[13] MADDR12[12] MADDR12[11] MADDR12[10] MADDR12[9] MADDR12[8]
MADDR12[7] MADDR12[6] MADDR12[5] MADDR12[4] MADDR12[3] MADDR12[2] MADDR12[1] MADDR12[0]
SU.ADDR13H
31:24
MADDR13AE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23:16
15:8
7:0
MADDR13[47] MADDR13[46] MADDR13[45] MADDR13[44] MADDR13[43] MADDR13[42] MADDR13[41] MADDR13[40]
MADDR13[39] MADDR13[38] MADDR13[37] MADDR13[36] MADDR13[35] MADDR13[34] MADDR13[33] MADDR13[32]
SU.ADDR13L
31:24
MADDR13[31] MADDR13[30] MADDR13[29] MADDR13[28] MADDR13[27] MADDR13[26] MADDR13[25] MADDR13[24]
23:16
15:8
7:0
MADDR13[23] MADDR13[22] MADDR13[21] MADDR13[20] MADDR13[19] MADDR13[18] MADDR13[17] MADDR13[16]
MADDR13[15] MADDR13[14] MADDR13[13] MADDR13[12] MADDR13[11] MADDR13[10] MADDR13[9] MADDR13[8]
MADDR13[7] MADDR13[6] MADDR13[5] MADDR13[4] MADDR13[3] MADDR13[2] MADDR13[1] MADDR13[0]
SU.ADDR14H
31:24
MADDR14AE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23:16
15:8
7:0
MADDR14[47] MADDR14[46] MADDR14[45] MADDR14[44] MADDR14[43] MADDR14[42] MADDR14[41] MADDR14[40]
MADDR14[39] MADDR14[38] MADDR14[37] MADDR14[36] MADDR14[35] MADDR14[34] MADDR14[33] MADDR14[32]
SU.ADDR14L
31:24
MADDR14[31] MADDR14[30] MADDR14[29] MADDR14[28] MADDR14[27] MADDR14[26] MADDR14[25] MADDR14[24]
23:16
15:8
7:0
MADDR14[23] MADDR14[22] MADDR14[21] MADDR14[20] MADDR14[19] MADDR14[18] MADDR14[17] MADDR14[16]
MADDR14[15] MADDR14[14] MADDR14[13] MADDR14[12] MADDR14[11] MADDR14[10] MADDR14[9] MADDR14[8]
MADDR14[7] MADDR14[6] MADDR14[5] MADDR14[4] MADDR14[3] MADDR14[2] MADDR14[1] MADDR14[0]
SU.ADDR15H
31:24
MADDR15AE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23:16
15:8
7:0
MADDR15[47] MADDR15[46] MADDR15[45] MADDR15[44] MADDR15[43] MADDR15[42] MADDR15[41] MADDR15[40]
MADDR15[39] MADDR15[38] MADDR15[37] MADDR15[36] MADDR15[35] MADDR15[34] MADDR15[33] MADDR15[32]
SU.ADDR15L
31:24
MADDR15[31] MADDR15[30] MADDR15[29] MADDR15[28] MADDR15[27] MADDR15[26] MADDR15[25] MADDR15[24]
23:16
15:8
7:0
MADDR15[23] MADDR15[22] MADDR15[21] MADDR15[20] MADDR15[19] MADDR15[18] MADDR15[17] MADDR15[16]
MADDR15[15] MADDR15[14] MADDR15[13] MADDR15[12] MADDR15[11] MADDR15[10] MADDR15[9] MADDR15[8]
MADDR15[7] MADDR15[6] MADDR15[5] MADDR15[4] MADDR15[3] MADDR15[2] MADDR15[1] MADDR15[0]
SU.PCSCR
31:24
-
-
-
-
-
-
-
-
23:16
-
-
-
-
-
-
-
-
-
-
LR
ECD
-
15:8
ELE
ANE
RAN
Rev: 063008
134 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR
NAME
7:0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
-
-
-
-
-
-
-
-
SU.ANSR
31:24
-
-
-
-
-
-
-
-
00C4h
23:16
15:8
7:0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ES
-
ANC
ANA
LS
SU.LSR
31:24
23:16
15:8
7:0
-
-
-
-
-
-
-
-
00D8h
0100h
0104h
0108h
010Ch
0110h
0114h
0118h
011Ch
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LINKUP
LNKSPD[1] LNKSPD[0]
LINKM
SU.MMCCTRL
31:24
-
-
-
-
-
-
-
-
23:16
15:8
7:0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ROR
CSR
CRST
SU.MMCRSR
31:24
-
-
-
-
-
-
-
-
23:16
15:8
7:0
RXWDOG
RXVLAN
RXOVFL
RXPAUSE RXRANGE RXLNERR RXUCAST RX1K_MAX
RX512_1K RX256_511 RX128_255 RX65_127
RX0_64
RXOVRSZ RXUNRSZ
RXJBBR
RXFC
RXRUNT
-
RXALGN
-
RXCRC
-
RXMFC
-
RXGBFC
RXBCG
-
RXBCGB
-
SU.MMCTSR
31:24
-
TXVLAN
TXDFRD
23:16
15:8
7:0
TXPAUSE TXXCSVDF
TXMLTICL TXSNGLCL
TXFCNT
TXUFE
TXBCNT
TXBFC
TX0_64
TXCERR
TXMFC
TXXCSVCL
TXLTCL
TXUCAST TX1K_MAX TX512_1K
TX256_511 TX128_255 TX65_127
TXGMFC
TXGBFC
-
TXFC
-
TXBC
-
SU.MMCRIM
31:24
-
-
-
-
-
23:16
15:8
7:0
RXWDOG
RXVLAN
RXOVFL
RXPAUSE RXRANGE RXLNERR RXUCAST RX1K_MAX
RX512_1K RX256_511 RX128_255 RX65_127
RX0_64
RXOVRSZ RXUNRSZ
RXJBBR
RXFC
RXRUNT
-
RXALGN
-
RXCRC
-
RXMFC
-
RXGBFC
RXBCG
-
RXBCGB
-
SU.MMCTIM
31:24
-
TXVLAN
TXDFRD
23:16
15:8
7:0
TXPAUSE TXXCSVDF
TXMLTICL TXSNGLCL
TXFCNT
TXUFE
TXBCNT
TXBFC
TX0_64
TXCERR
TXMFC
TXXCSVCL
TXLTCL
TXUCAST TX1K_MAX TX512_1K
TX256_511 TX128_255 TX65_127
TXGMFC
TXGBFC
TXBC[26]
TXFC
TXBC
SU.TXBC
31:24
23:16
15:8
7:0
TXBC[31]
TXBC[30]
TXBC[29]
TXBC[28]
TXBC[27]
TXBC[25]
TXBC[24]
TXBC[23]
TXBC[15]
TXBC[7]
TXBC[22]
TXBC[14]
TXBC[6]
TXBC[21]
TXBC[13]
TXBC[5]
TXBC[20]
TXBC[12]
TXBC[4]
TXBC[19]
TXBC[11]
TXBC[3]
TXBC[18]
TXBC[10]
TXBC[2]
TXBC[17]
TXBC[9]
TXBC[1]
TXBC[16]
TXBC[8]
TXBC[0]
SU.TXFC
31:24
23:16
15:8
7:0
TXFC[31]
TXFC[30]
TXFC[29]
TXFC[28]
TXFC[27]
TXFC[26]
TXFC[25]
TXFC[24]
TXFC[23]
TXFC[15]
TXFC[7]
TXFC[22]
TXFC[14]
TXFC[6]
TXFC[21]
TXFC[13]
TXFC[5]
TXFC[20]
TXFC[12]
TXFC[4]
TXFC[19]
TXFC[11]
TXFC[3]
TXFC[18]
TXFC[10]
TXFC[2]
TXFC[17]
TXFC[9]
TXFC[1]
TXFC[16]
TXFC[8]
TXFC[0]
SU.TXGBFC
31:24
TXGBFC[31] TXGBFC[30] TXGBFC[29] TXGBFC[28] TXGBFC[27] TXGBFC[26] TXGBFC[25] TXGBFC[24]
TXGBFC[23] TXGBFC[22] TXGBFC[21] TXGBFC[20] TXGBFC[19] TXGBFC[18] TXGBFC[17] TXGBFC[16]
23:16
Rev: 063008
135 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR
NAME
15:8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TXGBFC[15] TXGBFC[14] TXGBFC[13] TXGBFC[12] TXGBFC[11] TXGBFC[10] TXGBFC[9] TXGBFC[8]
7:0
TXGBFC[7] TXGBFC[6] TXGBFC[5] TXGBFC[4] TXGBFC[3] TXGBFC[2] TXGBFC[1] TXGBFC[0]
SU.TXGMFC
31:24
TXGMFC[31] TXGMFC[30] TXGMFC[29] TXGMFC[28] TXGMFC[27] TXGMFC[26] TXGMFC[25] TXGMFC[24]
TXGMFC[23] TXGMFC[22] TXGMFC[21] TXGMFC[20] TXGMFC[19] TXGMFC[18] TXGMFC[17] TXGMFC[16]
0120h
23:16
15:8
7:0
TXGMFC[15] TXGMFC[14] TXGMFC[13] TXGMFC[12] TXGMFC[11] TXGMFC[10]
TXGMFC[9]
TXGMFC[8]
TXGMFC[7] TXGMFC[6] TXGMFC[5] TXGMFC[4] TXGMFC[3] TXGMFC[2] TXGMFC[1] TXGMFC[0]
TX0_64[31] TX0_64[30] TX0_64[29] TX0_64[28] TX0_64[27] TX0_64[26] TX0_64[25] TX0_64[24]
TX0_64[23] TX0_64[22] TX0_64[21] TX0_64[20] TX0_64[19] TX0_64[18] TX0_64[17] TX0_64[16]
SU.TX0_64
31:24
23:16
15:8
7:0
0124h
0128h
TX0_64[15] TX0_64[14] TX0_64[13] TX0_64[12] TX0_64[11] TX0_64[10] TX0_64[9]
TX0_64[7] TX0_64[6] TX0_64[5] TX0_64[4] TX0_64[3] TX0_64[2] TX0_64[1]
TX0_64[8]
TX0_64[0]
SU.TX65_127
31:24
TX65_127[31] TX65_127[30] TX65_127[29] TX65_127[28] TX65_127[27] TX65_127[26] TX65_127[25] TX65_127[24]
23:16
15:8
7:0
TX65_127[23] TX65_127[22] TX65_127[21] TX65_127[20] TX65_127[19] TX65_127[18] TX65_127[17] TX65_127[16]
TX65_127[15] TX65_127[14] TX65_127[13] TX65_127[12] TX65_127[11] TX65_127[10] TX65_127[9] TX65_127[8]
TX65_127[7] TX65_127[6] TX65_127[5] TX65_127[4] TX65_127[3] TX65_127[2] TX65_127[1] TX65_127[0]
SU.TX128_255
31:24
TX128_255[31]
TX128_255[30]
TX128_255[29]
TX128_255[28]
TX128_255[27]
TX128_255[26]
TX128_255[25]
TX128_255[24]
012Ch
0130h
0134h
0138h
013Ch
23:16
15:8
7:0
TX128_255[23]
TX128_255[15]
TX128_255[7]
TX128_255[22]
TX128_255[14]
TX128_255[6]
TX128_255[21]
TX128_255[13]
TX128_255[5]
TX128_255[20]
TX128_255[12]
TX128_255[4]
TX128_255[19]
TX128_255[11]
TX128_255[3]
TX128_255[18]
TX128_255[10]
TX128_255[2]
TX128_255[17]
TX128_255[9]
TX128_255[1]
TX128_255[16]
TX128_255[8]
TX128_255[0]
SU.TX256_511
31:24
TX256_511[31]
TX256_511[30]
TX256_511[29]
TX256_511[28]
TX256_511[27]
TX256_511[26]
TX256_511[25]
TX256_511[24]
23:16
15:8
7:0
TX256_511[23]
TX256_511[15]
TX256_511[7]
TX256_511[22]
TX256_511[14]
TX256_511[6]
TX256_511[21]
TX256_511[13]
TX256_511[5]
TX256_511[20]
TX256_511[12]
TX256_511[4]
TX256_511[19]
TX256_511[11]
TX256_511[3]
TX256_511[18]
TX256_511[10]
TX256_511[2]
TX256_511[17]
TX256_511[9]
TX256_511[1]
TX256_511[16]
TX256_511[8]
TX256_511[0]
SU.TX512_1K
31:24
TX512_1K[31]
TX512_1K[30]
TX512_1K[29]
TX512_1K[28]
TX512_1K[27]
TX512_1K[26]
TX512_1K[25]
TX512_1K[24]
23:16
15:8
7:0
TX512_1K[23]
TX512_1K[15]
TX512_1K[7]
TX512_1K[22]
TX512_1K[14]
TX512_1K[6]
TX512_1K[21]
TX512_1K[13]
TX512_1K[5]
TX512_1K[20]
TX512_1K[12]
TX512_1K[4]
TX512_1K[19]
TX512_1K[11]
TX512_1K[3]
TX512_1K[18]
TX512_1K[10]
TX512_1K[2]
TX512_1K[17]
TX512_1K[9]
TX512_1K[1]
TX512_1K[16]
TX512_1K[8]
TX512_1K[0]
SU.TX1K_MAX
31:24
TX1K_MAX[31] TX1K_MAX[30] TX1K_MAX[29] TX1K_MAX[28] TX1K_MAX[27] TX1K_MAX[26] TX1K_MAX[25] TX1K_MAX[24]
TX1K_MAX[23] TX1K_MAX[22] TX1K_MAX[21] TX1K_MAX[20] TX1K_MAX[19] TX1K_MAX[18] TX1K_MAX[17] TX1K_MAX[16]
23:16
15:8
7:0
TX1K_MAX[15] TX1K_MAX[14] TX1K_MAX[13] TX1K_MAX[12] TX1K_MAX[11] TX1K_MAX[10]
TX1K_MAX[7] TX1K_MAX[6] TX1K_MAX[5] TX1K_MAX[4] TX1K_MAX[3] TX1K_MAX[2]
TX1K_MAX[9]
TX1K_MAX[1]
TX1K_MAX[8]
TX1K_MAX[0]
SU.TXUCAST
31:24
TXUCAST[31] TXUCAST[30] TXUCAST[29] TXUCAST[28] TXUCAST[27] TXUCAST[26] TXUCAST[25] TXUCAST[24]
23:16
15:8
7:0
TXUCAST[23] TXUCAST[22] TXUCAST[21] TXUCAST[20] TXUCAST[19] TXUCAST[18] TXUCAST[17] TXUCAST[16]
TXUCAST[15] TXUCAST[14] TXUCAST[13] TXUCAST[12] TXUCAST[11] TXUCAST[10] TXUCAST[9] TXUCAST[8]
TXUCAST[7] TXUCAST[6] TXUCAST[5] TXUCAST[4] TXUCAST[3] TXUCAST[2] TXUCAST[1] TXUCAST[0]
SU.TXMFC
31:24
23:16
15:8
7:0
TXMFC[31]
TXMFC[30]
TXMFC[29]
TXMFC[28]
TXMFC[27]
TXMFC[26]
TXMFC[25]
TXMFC[24]
0140h
0144h
TXMFC[23]
TXMFC[15]
TXMFC[7]
TXMFC[22]
TXMFC[14]
TXMFC[6]
TXMFC[21]
TXMFC[13]
TXMFC[5]
TXMFC[20]
TXMFC[12]
TXMFC[4]
TXMFC[19]
TXMFC[11]
TXMFC[3]
TXMFC[18]
TXMFC[10]
TXMFC[2]
TXMFC[17]
TXMFC[9]
TXMFC[1]
TXMFC[16]
TXMFC[8]
TXMFC[0]
SU.TXBFC
31:24
TXBFC[31]
TXBFC[30]
TXBFC[29]
TXBFC[28]
TXBFC[27]
TXBFC[26]
TXBFC[25]
TXBFC[24]
23:16
15:8
7:0
TXBFC[23]
TXBFC[15]
TXBFC[7]
TXBFC[22]
TXBFC[14]
TXBFC[6]
TXBFC[21]
TXBFC[13]
TXBFC[5]
TXBFC[20]
TXBFC[12]
TXBFC[4]
TXBFC[19]
TXBFC[11]
TXBFC[3]
TXBFC[18]
TXBFC[10]
TXBFC[2]
TXBFC[17]
TXBFC[9]
TXBFC[1]
TXBFC[16]
TXBFC[8]
TXBFC[0]
Rev: 063008
136 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR
NAME
SU.TXUFE
31:24
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TXUFE[31]
TXUFE[30]
TXUFE[29]
TXUFE[28]
TXUFE[27]
TXUFE[26]
TXUFE[25]
TXUFE[24]
0148h
23:16
15:8
7:0
TXUFE[23]
TXUFE[15]
TXUFE[7]
TXUFE[22]
TXUFE[14]
TXUFE[6]
TXUFE[21]
TXUFE[13]
TXUFE[5]
TXUFE[20]
TXUFE[12]
TXUFE[4]
TXUFE[19]
TXUFE[11]
TXUFE[3]
TXUFE[18]
TXUFE[10]
TXUFE[2]
TXUFE[17]
TXUFE[9]
TXUFE[1]
TXUFE[16]
TXUFE[8]
TXUFE[0]
SU.TXSNGLCL
31:24
TXSNGLCL[31] TXSNGLCL[30] TXSNGLCL[29] TXSNGLCL[28] TXSNGLCL[27] TXSNGLCL[26] TXSNGLCL[25] TXSNGLCL[24]
TXSNGLCL[23] TXSNGLCL[22] TXSNGLCL[21] TXSNGLCL[20] TXSNGLCL[19] TXSNGLCL[18] TXSNGLCL[17] TXSNGLCL[16]
014Ch
0150h
0154h
23:16
15:8
7:0
TXSNGLCL[15] TXSNGLCL[14] TXSNGLCL[13] TXSNGLCL[12] TXSNGLCL[11] TXSNGLCL[10]
TXSNGLCL[9]
TXSNGLCL[1]
TXSNGLCL[8]
TXSNGLCL[0]
TXSNGLCL[7]
TXMLTICL[31]
TXSNGLCL[6]
TXMLTICL[30]
TXSNGLCL[5]
TXMLTICL[29]
TXSNGLCL[4]
TXMLTICL[28]
TXSNGLCL[3]
TXMLTICL[27]
TXSNGLCL[2]
TXMLTICL[26]
SU.TXMLTICL
31:24
TXMLTICL[25]
TXMLTICL[24]
23:16
15:8
7:0
TXMLTICL[23]
TXMLTICL[15]
TXMLTICL[7]
TXMLTICL[22]
TXMLTICL[14]
TXMLTICL[6]
TXMLTICL[21]
TXMLTICL[13]
TXMLTICL[5]
TXMLTICL[20]
TXMLTICL[12]
TXMLTICL[4]
TXMLTICL[19]
TXMLTICL[11]
TXMLTICL[3]
TXMLTICL[18]
TXMLTICL[10]
TXMLTICL[2]
TXMLTICL[17]
TXMLTICL[9]
TXMLTICL[1]
TXMLTICL[16]
TXMLTICL[8]
TXMLTICL[0]
SU.TXDFRD
31:24
TXDFRD[31] TXDFRD[30] TXDFRD[29] TXDFRD[28] TXDFRD[27] TXDFRD[26] TXDFRD[25] TXDFRD[24]
TXDFRD[23] TXDFRD[22] TXDFRD[21] TXDFRD[20] TXDFRD[19] TXDFRD[18] TXDFRD[17] TXDFRD[16]
23:16
15:8
7:0
TXDFRD[15] TXDFRD[14] TXDFRD[13] TXDFRD[12] TXDFRD[11] TXDFRD[10]
TXDFRD[9]
TXDFRD[1]
TXDFRD[8]
TXDFRD[0]
TXDFRD[7]
TXLTCL[31]
TXDFRD[6]
TXLTCL[30]
TXDFRD[5]
TXLTCL[29]
TXDFRD[4]
TXLTCL[28]
TXDFRD[3]
TXLTCL[27]
TXDFRD[2]
TXLTCL[26]
SU.TXLTCL
31:24
TXLTCL[25]
TXLTCL[24]
0158h
23:16
15:8
7:0
TXLTCL[23]
TXLTCL[15]
TXLTCL[7]
TXLTCL[22]
TXLTCL[14]
TXLTCL[6]
TXLTCL[21]
TXLTCL[13]
TXLTCL[5]
TXLTCL[20]
TXLTCL[12]
TXLTCL[4]
TXLTCL[19]
TXLTCL[11]
TXLTCL[3]
TXLTCL[18]
TXLTCL[10]
TXLTCL[2]
TXLTCL[17]
TXLTCL[9]
TXLTCL[1]
TXLTCL[16]
TXLTCL[8]
TXLTCL[0]
SU.TXXCSVCL
31:24
TXXCSVCL[31] TXXCSVCL[30] TXXCSVCL[29] TXXCSVCL[28] TXXCSVCL[27] TXXCSVCL[26] TXXCSVCL[25] TXXCSVCL[24]
TXXCSVCL[23] TXXCSVCL[22] TXXCSVCL[21] TXXCSVCL[20] TXXCSVCL[19] TXXCSVCL[18] TXXCSVCL[17] TXXCSVCL[16]
015Ch
0160h
23:16
15:8
7:0
TXXCSVCL[15] TXXCSVCL[14] TXXCSVCL[13] TXXCSVCL[12] TXXCSVCL[11] TXXCSVCL[10]
TXXCSVCL[7] TXXCSVCL[6] TXXCSVCL[5] TXXCSVCL[4] TXXCSVCL[3] TXXCSVCL[2]
TXXCSVCL[9]
TXXCSVCL[1]
TXXCSVCL[8]
TXXCSVCL[0]
SU.TXCRERR
31:24
TXCRERR[31] TXCRERR[30] TXCRERR[29] TXCRERR[28] TXCRERR[27] TXCRERR[26] TXCRERR[25] TXCRERR[24]
23:16
15:8
7:0
TXCRERR[23] TXCRERR[22] TXCRERR[21] TXCRERR[20] TXCRERR[19] TXCRERR[18] TXCRERR[17] TXCRERR[16]
TXCRERR[15] TXCRERR[14] TXCRERR[13] TXCRERR[12] TXCRERR[11] TXCRERR[10] TXCRERR[9] TXCRERR[8]
TXCRERR[7] TXCRERR[6] TXCRERR[5] TXCRERR[4] TXCRERR[3] TXCRERR[2] TXCRERR[1] TXCRERR[0]
SU.TXGBC
31:24
23:16
15:8
7:0
TXGBC[31]
TXGBC[30]
TXGBC[29]
TXGBC[28]
TXGBC[27]
TXGBC[26]
TXGBC[25]
TXGBC[24]
0164h
0168h
TXGBC[23]
TXGBC[15]
TXGBC[7]
TXGBC[22]
TXGBC[14]
TXGBC[6]
TXGBC[21]
TXGBC[13]
TXGBC[5]
TXGBC[20]
TXGBC[12]
TXGBC[4]
TXGBC[19]
TXGBC[11]
TXGBC[3]
TXGBC[18]
TXGBC[10]
TXGBC[2]
TXGBC[17]
TXGBC[9]
TXGBC[1]
TXGBC[16]
TXGBC[8]
TXGBC[0]
SU.TXGFC
31:24
TXGFC[31]
TXGFC[30]
TXGFC[29]
TXGFC[28]
TXGFC[27]
TXGFC[26]
TXGFC[25]
TXGFC[24]
23:16
15:8
7:0
TXGFC[23]
TXGFC[15]
TXGFC[7]
TXGFC[22]
TXGFC[14]
TXGFC[6]
TXGFC[21]
TXGFC[13]
TXGFC[5]
TXGFC[20]
TXGFC[12]
TXGFC[4]
TXGFC[19]
TXGFC[11]
TXGFC[3]
TXGFC[18]
TXGFC[10]
TXGFC[2]
TXGFC[17]
TXGFC[9]
TXGFC[1]
TXGFC[16]
TXGFC[8]
TXGFC[0]
SU.TXXCSVDF
31:24
TXXCSVDF[31] TXXCSVDF[30] TXXCSVDF[29] TXXCSVDF[28] TXXCSVDF[27] TXXCSVDF[26] TXXCSVDF[25] TXXCSVDF[24]
TXXCSVDF[23] TXXCSVDF[22] TXXCSVDF[21] TXXCSVDF[20] TXXCSVDF[19] TXXCSVDF[18] TXXCSVDF[17] TXXCSVDF[16]
016Ch
0170h
23:16
15:8
7:0
TXXCSVDF[15] TXXCSVDF[14] TXXCSVDF[13] TXXCSVDF[12] TXXCSVDF[11] TXXCSVDF[10]
TXXCSVDF[7] TXXCSVDF[6] TXXCSVDF[5] TXXCSVDF[4] TXXCSVDF[3] TXXCSVDF[2]
TXXCSVDF[9]
TXXCSVDF[1]
TXXCSVDF[8]
TXXCSVDF[0]
SU.TXPAUSE
31:24
TXPAUSE[31] TXPAUSE[30] TXPAUSE[29] TXPAUSE[28] TXPAUSE[27] TXPAUSE[26] TXPAUSE[25] TXPAUSE[24]
TXPAUSE[23] TXPAUSE[22] TXPAUSE[21] TXPAUSE[20] TXPAUSE[19] TXPAUSE[18] TXPAUSE[17] TXPAUSE[16]
23:16
Rev: 063008
137 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR
NAME
15:8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TXPAUSE[15] TXPAUSE[14] TXPAUSE[13] TXPAUSE[12] TXPAUSE[11] TXPAUSE[10] TXPAUSE[9] TXPAUSE[8]
7:0
TXPAUSE[7] TXPAUSE[6] TXPAUSE[5] TXPAUSE[4] TXPAUSE[3] TXPAUSE[2] TXPAUSE[1] TXPAUSE[0]
SU.TXVLANF
31:24
TXVLANF[31] TXVLANF[30] TXVLANF[29] TXVLANF[28] TXVLANF[27] TXVLANF[26] TXVLANF[25] TXVLANF[24]
TXVLANF[23] TXVLANF[22] TXVLANF[21] TXVLANF[20] TXVLANF[19] TXVLANF[18] TXVLANF[17] TXVLANF[16]
0174h
23:16
15:8
7:0
TXVLANF[15] TXVLANF[14] TXVLANF[13] TXVLANF[12] TXVLANF[11] TXVLANF[10] TXVLANF[9]
TXVLANF[8]
TXVLANF[0]
TXVLANF[7]
-
TXVLANF[6]
-
TXVLANF[5]
-
TXVLANF[4]
-
TXVLANF[3]
-
TXVLANF[2]
-
TXVLANF[1]
-
RESERVED
31:24
-
0178h
017Ch
0180h
0184h
0188h
23:16
15:8
7:0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESERVED
31:24
-
-
-
-
-
-
-
-
23:16
15:8
7:0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SU.RXFC
31:24
23:16
15:8
7:0
RXFC[31]
RXFC[30]
RXFC[29]
RXFC[28]
RXFC[27]
RXFC[26]
RXFC[25]
RXFC[24]
RXFC[23]
RXFC[15]
RXFC[7]
RXFC[22]
RXFC[14]
RXFC[6]
RXFC[21]
RXFC[13]
RXFC[5]
RXFC[20]
RXFC[12]
RXFC[4]
RXFC[19]
RXFC[11]
RXFC[3]
RXFC[18]
RXFC[10]
RXFC[2]
RXFC[17]
RXFC[9]
RXFC[1]
RXFC[16]
RXFC[8]
RXFC[0]
SU.RXBC
31:24
23:16
15:8
7:0
RXBC[31]
RXBC[30]
RXBC[29]
RXBC[28]
RXBC[27]
RXBC[26]
RXBC[25]
RXBC[24]
RXBC[23]
RXBC[15]
RXBC[7]
RXBC[22]
RXBC[14]
RXBC[6]
RXBC[21]
RXBC[13]
RXBC[5]
RXBC[20]
RXBC[12]
RXBC[4]
RXBC[19]
RXBC[11]
RXBC[3]
RXBC[18]
RXBC[10]
RXBC[2]
RXBC[17]
RXBC[9]
RXBC[1]
RXBC[16]
RXBC[8]
RXBC[0]
SU.RXGBC
31:24
23:16
15:8
7:0
RXGBC[31] RXGBC[30] RXGBC[29] RXGBC[28] RXGBC[27] RXGBC[26] RXGBC[25] RXGBC[24]
RXGBC[23] RXGBC[22] RXGBC[21] RXGBC[20] RXGBC[19] RXGBC[18] RXGBC[17] RXGBC[16]
RXGBC[15] RXGBC[14] RXGBC[13] RXGBC[12] RXGBC[11] RXGBC[10] RXGBC[9]
RXGBC[7] RXGBC[6] RXGBC[5] RXGBC[4] RXGBC[3] RXGBC[2] RXGBC[1]
RXGBC[8]
RXGBC[0]
SU.RXGBFC
31:24
RXGBFC[31] RXGBFC[30] RXGBFC[29] RXGBFC[28] RXGBFC[27] RXGBFC[26] RXGBFC[25] RXGBFC[24]
RXGBFC[23] RXGBFC[22] RXGBFC[21] RXGBFC[20] RXGBFC[19] RXGBFC[18] RXGBFC[17] RXGBFC[16]
018Ch
0190h
23:16
15:8
7:0
RXGBFC[15] RXGBFC[14] RXGBFC[13] RXGBFC[12] RXGBFC[11] RXGBFC[10]
RXGBFC[9]
RXGBFC[8]
RXGBFC[7] RXGBFC[6] RXGBFC[5] RXGBFC[4] RXGBFC[3] RXGBFC[2] RXGBFC[1] RXGBFC[0]
RXMFC[31] RXMFC[30] RXMFC[29] RXMFC[28] RXMFC[27] RXMFC[26] RXMFC[25] RXMFC[24]
RXMFC[23] RXMFC[22] RXMFC[21] RXMFC[20] RXMFC[19] RXMFC[18] RXMFC[17] RXMFC[16]
SU.RXMFC
31:24
23:16
15:8
7:0
RXMFC[15] RXMFC[14] RXMFC[13] RXMFC[12] RXMFC[11] RXMFC[10] RXMFC[9]
RXMFC[7] RXMFC[6] RXMFC[5] RXMFC[4] RXMFC[3] RXMFC[2] RXMFC[1]
RXMFC[8]
RXMFC[0]
SU.RXCRC
31:24
23:16
15:8
7:0
RXCRC[31] RXCRC[30] RXCRC[29] RXCRC[28] RXCRC[27] RXCRC[26] RXCRC[25] RXCRC[24]
RXCRC[23] RXCRC[22] RXCRC[21] RXCRC[20] RXCRC[19] RXCRC[18] RXCRC[17] RXCRC[16]
0194h
0198h
RXCRC[15] RXCRC[14] RXCRC[13] RXCRC[12] RXCRC[11] RXCRC[10] RXCRC[9]
RXCRC[7] RXCRC[6] RXCRC[5] RXCRC[4] RXCRC[3] RXCRC[2] RXCRC[1]
RXCRC[8]
RXCRC[0]
SU.RXALGN
31:24
RXALGN[31] RXALGN[30] RXALGN[29] RXALGN[28] RXALGN[27] RXALGN[26] RXALGN[25] RXALGN[24]
Rev: 063008
138 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR
NAME
23:16
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RXALGN[23] RXALGN[22] RXALGN[21] RXALGN[20] RXALGN[19] RXALGN[18] RXALGN[17] RXALGN[16]
RXALGN[15] RXALGN[14] RXALGN[13] RXALGN[12] RXALGN[11] RXALGN[10] RXALGN[9] RXALGN[8]
RXALGN[7] RXALGN[6] RXALGN[5] RXALGN[4] RXALGN[3] RXALGN[2] RXALGN[1] RXALGN[0]
RXRUNT[31 RXRUNT[30 RXRUNT[29 RXRUNT[28 RXRUNT[27 RXRUNT[26 RXRUNT[25 RXRUNT[24
15:8
7:0
SU.RXRUNT
31:24
019Ch
]
]
]
]
]
]
]
]
23:16
15:8
7:0
RXRUNT[23 RXRUNT[22 RXRUNT[21 RXRUNT[20 RXRUNT[19 RXRUNT[18 RXRUNT[17 RXRUNT[16
]
]
]
]
]
]
]
]
RXRUNT[15 RXRUNT[14 RXRUNT[13 RXRUNT[12 RXRUNT[11 RXRUNT[10
RXRUNT[9] RXRUNT[8]
]
]
]
]
]
]
RXRUNT[7] RXRUNT[6] RXRUNT[5] RXRUNT[4] RXRUNT[3] RXRUNT[2] RXRUNT[1] RXRUNT[0]
RXJBBR[31] RXJBBR[30] RXJBBR[29] RXJBBR[28] RXJBBR[27] RXJBBR[26] RXJBBR[25] RXJBBR[24]
SU.RXJBBR
31:24
01A0h
23:16
15:8
7:0
RXJBBR[23] RXJBBR[22] RXJBBR[21] RXJBBR[20] RXJBBR[19] RXJBBR[18] RXJBBR[17] RXJBBR[16]
RXJBBR[15] RXJBBR[14] RXJBBR[13] RXJBBR[12] RXJBBR[11] RXJBBR[10] RXJBBR[9] RXJBBR[8]
RXJBBR[7] RXJBBR[6] RXJBBR[5] RXJBBR[4] RXJBBR[3] RXJBBR[2] RXJBBR[1] RXJBBR[0]
RXUNDRSZ[31] RXUNDRSZ[30] RXUNDRSZ[29] RXUNDRSZ[28] RXUNDRSZ[27] RXUNDRSZ[26] RXUNDRSZ[25] RXUNDRSZ[24]
RXUNDRSZ[23] RXUNDRSZ[22] RXUNDRSZ[21] RXUNDRSZ[20] RXUNDRSZ[19] RXUNDRSZ[18] RXUNDRSZ[17] RXUNDRSZ[16]
SU.RXUNDRSZ
31:24
01A4h
01A8h
23:16
15:8
7:0
RXUNDRSZ[15] RXUNDRSZ[14] RXUNDRSZ[13] RXUNDRSZ[12] RXUNDRSZ[11] RXUNDRSZ[10] RXUNDRSZ[9]
RXUNDRSZ[7] RXUNDRSZ[6] RXUNDRSZ[5] RXUNDRSZ[4] RXUNDRSZ[3] RXUNDRSZ[2] RXUNDRSZ[1]
RXUNDRSZ[8]
RXUNDRSZ[0]
SU.RXOVRSZ
31:24
RXOVRSZ[31] RXOVRSZ[30] RXOVRSZ[29] RXOVRSZ[28] RXOVRSZ[27] RXOVRSZ[26] RXOVRSZ[25] RXOVRSZ[24]
23:16
15:8
7:0
RXOVRSZ[23] RXOVRSZ[22] RXOVRSZ[21] RXOVRSZ[20] RXOVRSZ[19] RXOVRSZ[18] RXOVRSZ[17] RXOVRSZ[16]
RXOVRSZ[15] RXOVRSZ[14] RXOVRSZ[13] RXOVRSZ[12] RXOVRSZ[11] RXOVRSZ[10] RXOVRSZ[9] RXOVRSZ[8]
RXOVRSZ[7] RXOVRSZ[6] RXOVRSZ[5] RXOVRSZ[4] RXOVRSZ[3] RXOVRSZ[2] RXOVRSZ[1] RXOVRSZ[0]
SU.RX0_64
31:24
23:16
15:8
7:0
RX0_64[31]
RX0_64[30]
RX0_64[29]
RX0_64[28]
RX0_64[27]
RX0_64[26]
RX0_64[25]
RX0_64[24]
01ACh
01B0h
RX0_64[23]
RX0_64[15]
RX0_64[7]
RX0_64[22]
RX0_64[14]
RX0_64[6]
RX0_64[21]
RX0_64[13]
RX0_64[5]
RX0_64[20]
RX0_64[12]
RX0_64[4]
RX0_64[19]
RX0_64[11]
RX0_64[3]
RX0_64[18]
RX0_64[10]
RX0_64[2]
RX0_64[17]
RX0_64[9]
RX0_64[1]
RX0_64[16]
RX0_64[8]
RX0_64[0]
SU.RX65_127
31:24
RX65_127[31] RX65_127[30] RX65_127[29] RX65_127[28] RX65_127[27] RX65_127[26] RX65_127[25] RX65_127[24]
23:16
15:8
7:0
RX65_127[23] RX65_127[22] RX65_127[21] RX65_127[20] RX65_127[19] RX65_127[18] RX65_127[17] RX65_127[16]
RX65_127[15] RX65_127[14] RX65_127[13] RX65_127[12] RX65_127[11] RX65_127[10] RX65_127[9] RX65_127[8]
RX65_127[7] RX65_127[6] RX65_127[5] RX65_127[4] RX65_127[3] RX65_127[2] RX65_127[1] RX65_127[0]
SU.RX128_255
31:24
RX128_255[31] RX128_255[30] RX128_255[29] RX128_255[28] RX128_255[27] RX128_255[26] RX128_255[25] RX128_255[24]
RX128_255[23] RX128_255[22] RX128_255[21] RX128_255[20] RX128_255[19] RX128_255[18] RX128_255[17] RX128_255[16]
01B4h
01B8h
01BCh
01C0h
23:16
15:8
7:0
RX128_255[15] RX128_255[14] RX128_255[13] RX128_255[12] RX128_255[11] RX128_255[10]
RX128_255[7] RX128_255[6] RX128_255[5] RX128_255[4] RX128_255[3] RX128_255[2]
RX128_255[9]
RX128_255[1]
RX128_255[8]
RX128_255[0]
SU.RX256_511
31:24
RX256_511[31] RX256_511[30] RX256_511[29] RX256_511[28] RX256_511[27] RX256_511[26] RX256_511[25] RX256_511[24]
RX256_511[23] RX256_511[22] RX256_511[21] RX256_511[20] RX256_511[19] RX256_511[18] RX256_511[17] RX256_511[16]
23:16
15:8
7:0
RX256_511[15] RX256_511[14] RX256_511[13] RX256_511[12] RX256_511[11] RX256_511[10]
RX256_511[9]
RX256_511[1]
RX256_511[8]
RX256_511[0]
RX256_511[7]
RX512_1K[31]
RX256_511[6]
RX512_1K[30]
RX256_511[5]
RX512_1K[29]
RX256_511[4]
RX512_1K[28]
RX256_511[3]
RX512_1K[27]
RX256_511[2]
RX512_1K[26]
SU.RX512_1K
31:24
RX512_1K[25]
RX512_1K[24]
23:16
15:8
7:0
RX512_1K[23]
RX512_1K[15]
RX512_1K[7]
RX512_1K[22]
RX512_1K[14]
RX512_1K[6]
RX512_1K[21]
RX512_1K[13]
RX512_1K[5]
RX512_1K[20]
RX512_1K[12]
RX512_1K[4]
RX512_1K[19]
RX512_1K[11]
RX512_1K[3]
RX512_1K[18]
RX512_1K[10]
RX512_1K[2]
RX512_1K[17]
RX512_1K[9]
RX512_1K[1]
RX512_1K[16]
RX512_1K[8]
RX512_1K[0]
SU.RX1K_MAX
31:24
RX1K_MAX[31] RX1K_MAX[30] RX1K_MAX[29] RX1K_MAX[28] RX1K_MAX[27] RX1K_MAX[26] RX1K_MAX[25] RX1K_MAX[24]
Rev: 063008
139 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ADDR
NAME
23:16
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RX1K_MAX[23] RX1K_MAX[22] RX1K_MAX[21] RX1K_MAX[20] RX1K_MAX[19] RX1K_MAX[18] RX1K_MAX[17] RX1K_MAX[16]
15:8
7:0
RX1K_MAX[15] RX1K_MAX[14] RX1K_MAX[13] RX1K_MAX[12] RX1K_MAX[11] RX1K_MAX[10]
RX1K_MAX[9]
RX1K_MAX[1]
RX1K_MAX[8]
RX1K_MAX[0]
RX1K_MAX[7]
RXUFC[31]
RX1K_MAX[6]
RXUFC[30]
RX1K_MAX[5]
RXUFC[29]
RX1K_MAX[4]
RXUFC[28]
RX1K_MAX[3]
RXUFC[27]
RX1K_MAX[2]
RXUFC[26]
SU.RXUFC
31:24
RXUFC[25]
RXUFC[24]
01C4h
23:16
15:8
7:0
RXUFC[23]
RXUFC[15]
RXUFC[7]
RXUFC[22]
RXUFC[14]
RXUFC[6]
RXUFC[21]
RXUFC[13]
RXUFC[5]
RXUFC[20]
RXUFC[12]
RXUFC[4]
RXUFC[19]
RXUFC[11]
RXUFC[3]
RXUFC[18]
RXUFC[10]
RXUFC[2]
RXUFC[17]
RXUFC[9]
RXUFC[1]
RXUFC[16]
RXUFC[8]
RXUFC[0]
SU.RXLNERR
31:24
RXLNERR[31] RXLNERR[30] RXLNERR[29] RXLNERR[28] RXLNERR[27] RXLNERR[26] RXLNERR[25] RXLNERR[24]
01C8h
01CCh
01D0h
01D4h
01D8h
01DCh
1018h
23:16
15:8
7:0
RXLNERR[23] RXLNERR[22] RXLNERR[21] RXLNERR[20] RXLNERR[19] RXLNERR[18] RXLNERR[17] RXLNERR[16]
RXLNERR[15] RXLNERR[14] RXLNERR[13] RXLNERR[12] RXLNERR[11] RXLNERR[10] RXLNERR[9] RXLNERR[8]
RXLNERR[7] RXLNERR[6] RXLNERR[5] RXLNERR[4] RXLNERR[3] RXLNERR[2] RXLNERR[1] RXLNERR[0]
SU.RXRANGE
31:24
RXRANGE[31] RXRANGE[30] RXRANGE[29] RXRANGE[28] RXRANGE[27] RXRANGE[26] RXRANGE[25] RXRANGE[24]
23:16
15:8
7:0
RXRANGE[23] RXRANGE[22] RXRANGE[21] RXRANGE[20] RXRANGE[19] RXRANGE[18] RXRANGE[17] RXRANGE[16]
RXRANGE[15] RXRANGE[14] RXRANGE[13] RXRANGE[12] RXRANGE[11] RXRANGE[10] RXRANGE[9] RXRANGE[8]
RXRANGE[7] RXRANGE[6] RXRANGE[5] RXRANGE[4] RXRANGE[3] RXRANGE[2] RXRANGE[1] RXRANGE[0]
SU.RXPAUSE
31:24
RXPAUSE[31] RXPAUSE[30] RXPAUSE[29] RXPAUSE[28] RXPAUSE[27] RXPAUSE[26] RXPAUSE[25] RXPAUSE[24]
23:16
15:8
7:0
RXPAUSE[23] RXPAUSE[22] RXPAUSE[21] RXPAUSE[20] RXPAUSE[19] RXPAUSE[18] RXPAUSE[17] RXPAUSE[16]
RXPAUSE[15] RXPAUSE[14] RXPAUSE[13] RXPAUSE[12] RXPAUSE[11] RXPAUSE[10] RXPAUSE[9] RXPAUSE[8]
RXPAUSE[7] RXPAUSE[6] RXPAUSE[5] RXPAUSE[4] RXPAUSE[3] RXPAUSE[2] RXPAUSE[1] RXPAUSE[0]
SU.RXOVFL
31:24
RXOVFL[31] RXOVFL[30]
RXOVFL[29] RXOVFL[28]
RXOVFL[27] RXOVFL[26]
RXOVFL[25] RXOVFL[24]
RXOVFL[17] RXOVFL[16]
23:16
15:8
7:0
RXOVFL[23] RXOVFL[22]
RXOVFL[15] RXOVFL[14]
RXOVFL[21] RXOVFL[20]
RXOVFL[13] RXOVFL[12]
RXOVFL[19] RXOVFL[18]
RXOVFL[11] RXOVFL[10]
RXOVFL[9]
RXOVFL[1]
RXOVFL[8]
RXOVFL[0]
RXOVFL[7]
RXOVFL[6]
RXOVFL[5]
RXOVFL[4]
RXOVFL[3]
RXOVFL[2]
SU.RXVLAN
31:24
RXVLAN[31] RXVLAN[30]
RXVLAN[29] RXVLAN[28]
RXVLAN[27] RXVLAN[26]
RXVLAN[25] RXVLAN[24]
RXVLAN[17] RXVLAN[16]
23:16
15:8
7:0
RXVLAN[23] RXVLAN[22]
RXVLAN[15] RXVLAN[14]
RXVLAN[21] RXVLAN[20]
RXVLAN[13] RXVLAN[12]
RXVLAN[19] RXVLAN[18]
RXVLAN[11] RXVLAN[10]
RXVLAN[9]
RXVLAN[1]
RXVLAN[8]
RXVLAN[0]
RXVLAN[7]
RXVLAN[6]
RXVLAN[5]
RXVLAN[4]
RXVLAN[3]
RXVLAN[2]
SU.RXWDOG
31:24
RXWDOG[31] RXWDOG[30] RXWDOG[29] RXWDOG[28] RXWDOG[27] RXWDOG[26] RXWDOG[25] RXWDOG[24]
23:16
15:8
7:0
RXWDOG[23] RXWDOG[22] RXWDOG[21] RXWDOG[20] RXWDOG[19] RXWDOG[18] RXWDOG[17] RXWDOG[16]
RXWDOG[15] RXWDOG[14] RXWDOG[13] RXWDOG[12] RXWDOG[11] RXWDOG[10] RXWDOG[9] RXWDOG[8]
RXWDOG[7] RXWDOG[6] RXWDOG[5] RXWDOG[4] RXWDOG[3] RXWDOG[2] RXWDOG[1] RXWDOG[0]
SU.MACMCR
31:24
-
-
-
-
-
-
-
-
23:16
15:8
7:0
-
-
-
-
-
-
-
-
-
FTF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Note that the addresses in the table above are the indirect addresses that must be provided to the SU.MAC1AWH and SU.MAC1AWL. All
unused and reserved locations must be initialized to zero for proper operation unless specifically noted otherwise.
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
10.2 Global Register Definitions
Note that although most registers are defined as 16-bit registers, the constituent bytes are accessed
through the parallel or SPI interfaces one byte at a time. Individual address locations are defined for each
byte.
Register Name:
GL.IDR
Register Description:
Register Address:
Global ID Register
000h
Bit 15
REV2
0
Bit 14
REV1
-
Bit 13
REV0
-
Bit 12
SPIS
Bit 11
VC2
-
Bit 10
VC1
-
Bit 9
VC0
0
Bit 8
VCAT
0
001h:
Default
-
Bit 7
WP4
-
Bit 6
WP3
-
Bit 5
WP2
-
Bit 4
WP1
-
Bit 3
WP0
-
Bit 2
GBE
0
Bit 1
MP1
-
Bit 0
MP0
-
000h:
Default
Bits 13-15: Revision Number (REV[2:0]) Contains a sequential number that is related to, but not equal to, the
device revision on the top brand. Silicon revision numbering begins at 000.
Bit 12: SPI Slave (SPIS) If this bit is set to 1, the device only supports a SPI Slave microprocessor port.
Bits 9-11: Voice Channels (VC[2:0]) This contains the number of voice channels supported.
Bit 8: VCAT (VCAT) If this bit is set to 1, the device has VCAT functionality.
Bits 3-7: Serial WAN Ports (WP[4:0]) These bits contain the number of WAN ports in the device.
Bit 3: Gigabit Ethernet Support (GBE) If this bit is set, the device support GbE.
Bits 0-1: Ethernet LAN Ports (MP[1:0]) These bits contain the number of MAC ports in the device.
Table 10-4. Default GL.IDR Values
Device
SPIS
VC[2:0]
000
000
000
000
000
000
001
000
001
VCAT
WP[4:0]
10000
10000
01000
01000
00100
00100
00100
00001
00001
GBE
MP[1:0]
10
DS33X162
DS33X161
DS33X82
DS33X81
DS33X42
DS33X41
DS33W41
DS33X11
DS33W11
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
01
1
10
1
01
1
10
1
01
1
01
1*
1*
01
01
*Note, the single-port DS33X11 and DS33W11 devices support reservation of the VCAT overhead byte position as
required by ITU-T G.8040, not the actual concatenation of WAN links.
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
GL.CR1
Register Description:
Register Address:
Global Control Register 1
002h
Bit 15
Bit 14
Bit 13
P2SPD
0
Bit 12
-
0
Bit 11
P1SPD
0
Bit 10
-
0
Bit 9
-
0
Bit 8
-
0
-
0
-
0
003h:
Default
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
FMC-2
0
Bit 1
FMC-1
0
Bit 0
FMC-0
0
002h:
Default
Bit 13: LAN Port 2 Speed Selection (P2SPD)
0 = 10Mbps operation
1 = 100Mbps
Bit 11: LAN Port 1 Speed Selection (P1SPD)
0 = 10Mbps operation
1 = 100Mbps operation
This bit setting is only applicable to MII and RMII modes.
Bits 0-2: Forwarding Mode Control (FMC[2:0])
000 = Reserved
001 = Forwarding mode 1. Single Ethernet Port with Priority Forwarding. In this mode, Ethernet frames
are segregated into up to four priority levels and forwarded to separate WAN data streams.
010 = Forwarding mode 2. Per-Ethernet-Port Forwarding with Priority Scheduling. In this mode, frames
from each Ethernet port are forwarded to their own group of four priority queues, generating two
separate WAN data streams with priority scheduled traffic.
011 = Forwarding mode 3. Single Ethernet Port with VLAN Forwarding and Priority Scheduling. In this
mode, Ethernet frames are forwarded by VLAN tag (VID) into up to four groups of four priority
queues (WAN Groups) each. Each WAN Group forms a separate WAN data stream with priority
scheduled traffic.
100 = Forwarding mode 4. Per-Ethernet-Port Forwarding, with VLAN Forwarding and Priority
Scheduling within each VLAN group. In this mode, Ethernet frames from each Ethernet port are
forwarded separately, by VLAN tag, into two sets of four priority queues (WAN Groups) each. The
two WAN Groups form separate WAN data streams with priority scheduled traffic.
101 = Forwarding mode 5. Full VLAN Forwarding in both the LAN-to-WAN and WAN-to-LAN
directions. In this mode, Ethernet frames from both ports can be forwarded by VLAN tag to two
shared WAN groups. Within each WAN group, there are two sets of four priority queues. The two
sets of priority queues are serviced with a round-robin algorithm. Frames received from the WAN
side can be forwarded by VLAN tag to either Ethernet port. The LAN-to-WAN and WAN-to-LAN
mappings are independent and can be configured separately.
110 = Reserved.
111 = Reserved.
In all forwarding modes, VCAT/LCAS can be used to aggregate multiple physical serial ports for each WAN
Group’s data stream, except on devices that do not support VCAT/LCAS.
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Register Name:
GL.CR2
Register Description:
Register Address:
Global Control Register 2
004h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
005h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
INTM
0
Bit 2
ENDEL
0
Bit 1
-
0
Bit 0
RST
0
004h:
Default
Bit 3: Interrupt Mode (INTM) When this bit is set to 1, the inactive state of the INT pin will be high-impedance.
When this bit is equal to 0, the inactive state of the INT pin will be a driven logic high.
Bit 2: Encap/Decap Loopback (ENDEL) When this bit is set to 1, the WAN-side output data from Encapsulator #1
is looped back to the WAN input of Decapsulator #1.
Bit 0: Global Reset (RST) When this bit is set, all of the internal data path, status, and control registers (except the
RST bit), on all ports, will be reset to the default state. This bit must remain set to 1 for a minimum of 100ns to
initiate the reset operation. The bit should be cleared to 0 for normal operation to resume. Note that setting this bit
does not tri-state output pins. When using a revision A1 (GL.IDR.REVn=000) device in SPI mode, the individual
block reset bits or the hardware reset pin should be used instead of this bit.
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Register Name:
GL.ISR
Register Description:
Register Address:
Global Interrupt Status Register
008h
Bit 15
MICIS
Bit 14
DECIS4
0
Bit 13
DECIS3
0
Bit 12
DECIS2
0
Bit 11
ECIS4
0
Bit 10
ECIS3
0
Bit 9
ECIS2
0
Bit 8
RVCATIS
0
009h:
Default
0
Bit 7
-
0
Bit 6
BUFIS
0
Bit 5
-
0
Bit 4
TSPIS
0
Bit 3
DECIS1
0
Bit 2
ECIS1
0
Bit 1
TXLANIS
0
Bit 0
RXLANIS
0
008h:
Default
Bit 15: Microprocessor Interrupt Status (MICIS) This bit is set if the Microport has an active, enabled interrupt
condition. Normally, this condition is caused by the presence of a trapped frame for extraction and processing.
Bit 14: Decapsulation Interrupt Status 4 (DECIS4) This bit is set if Decapsulator 4 has an active, enabled
interrupt condition.
Bit 13: Decapsulation Interrupt Status 3 (DECIS3) This bit is set if Decapsulator 3 has an active, enabled
interrupt condition.
Bit 12: Decapsulation Interrupt Status 2 (DECIS2) This bit is set if Decapsulator 2 has an active, enabled
interrupt condition.
Bit 11: Encapsulation Interrupt Status 4 (ECIS4) This bit is set if Encapsulator 4 has an active, enabled interrupt
condition.
Bit 10: Encapsulation Interrupt Status 3 (ECIS3) This bit is set if Encapsulator 3 has an active, enabled interrupt
condition.
Bit 9: Encapsulation Interrupt Status 2 (ECIS2) This bit is set if Encapsulator 2 has an active, enabled interrupt
condition.
Bit 8: Receive VCAT Interrupt Status (RVCATIS) This bit is set if the receive VCAT has an active, enabled
interrupt condition.
Bit 6: Buffer Manager (Arbiter) Interrupt Status (BUFIS) This bit is set if the buffer manager has an active,
enabled interrupt condition.
Bit 4: Transmit WAN Serial Port Interrupt Status (TSPIS) This bit is set if the transmit serial WAN port has an
active, enabled interrupt condition.
Bit 3: Decapsulation Interrupt Status 1 (DECIS1) This bit is set if Decapsulator 1 has an active, enabled interrupt
condition.
Bit 2: Encapsulation Interrupt Status 1 (ECIS1) This bit is set if Encapsulator 1 has an active, enabled interrupt
condition.
Bit 1: Transmit LAN Interrupt Status (TXLANIS) This bit is set if a transmit Ethernet LAN port has an active,
enabled interrupt condition.
Bit 0: Receive LAN and Bridge Filter Interrupt Status (RXLANIS) This bit is set if either of the receive Ethernet
LAN MAC(s) or the LAN Queue Overflows have an active, enabled interrupt condition.
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Register Name:
GL.IER
Register Description:
Register Address:
Global Interrupt Enable Register
00Ah
Bit 15
MICIE
Bit 14
DECIE4
0
Bit 13
DECIE3
0
Bit 12
DECIE2
0
Bit 11
ECIE4
0
Bit 10
ECIE3
0
Bit 9
ECIE2
0
Bit 8
RVCATIE
0
00Bh:
Default
0
Bit 7
-
0
Bit 6
BUFIE
0
Bit 5
-
0
Bit 4
TSPIE
0
Bit 3
DECIE1
0
Bit 2
ECIE1
0
Bit 1
TXLANIE
0
Bit 0
RXLANIE
0
00Ah:
Default
Bit 15: Microport Interrupt Enable (MICIE) When this bit is set to 1, MICIS will generate an interrupt.
Bit 14: Decapsulation Interrupt Enable 4 (DECIE4) When this bit is set to 1, DECIS4 will generate an interrupt.
Bit 13: Decapsulation Interrupt Enable 3 (DECIE3) When this bit is set to 1, DECIS3 will generate an interrupt.
Bit 12: Decapsulation Interrupt Enable 2 (DECIE2) When this bit is set to 1, DECIS2 will generate an interrupt.
Bit 11: Encapsulation Interrupt Enable 4 (ECIE4) When this bit is set to 1, ECIS4 will generate an interrupt.
Bit 10: Encapsulation Interrupt Enable 3 (ECIE3) When this bit is set to 1, ECIS3 will generate an interrupt.
Bit 9: Encapsulation Interrupt Enable 2 (ECIE2) When this bit is set to 1, ECIS2 will generate an interrupt.
Bit 8: Receive VCAT Interrupt Enable (RVCATIE) When this bit is set to 1, RVCATIS will generate an interrupt.
Bit 6: Buffer Manager (Arbiter) Interrupt Enable (BUFIE) When this bit is set to 1, BUFIS will generate an
interrupt.
Bit 4: Transmit WAN Serial Port Interrupt Enable (TSPIE) When this bit is set to 1, TSPIS will generate an
interrupt.
Bit 3: Decapsulation Interrupt Enable 1 (DECIE1) When this bit is set to 1, DECIS1 will generate an interrupt.
Bit 2: Encapsulation Interrupt Enable 1 (ECIE1) When this bit is set to 1, ECIS1 will generate an interrupt.
Bit 1: Transmit LAN Interrupt Enable (TXLANIE) When this bit is set to 1, TXLANIS will generate an interrupt.
Bit 0: Receive LAN and Bridge Filter Interrupt Enable (RXLANIE) When this bit is set to 1, RXLANIS will
generate an interrupt.
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
GL.MBSR
Register Description:
Register Address:
Global PLL Status Register
00Ch
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
DLOCK
0
Bit 10
PLOCK
0
Bit 9
-
0
Bit 8
-
0
-
0
-
0
-
0
00Dh:
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
00Ch:
Default
0
0
0
0
0
0
0
0
Bit 11: DPLL Lock (DLOCK) This bit is set to 1 if the DPLL has achieved lock.
Bit 10: PLL Lock (PLOCK) This bit is set to 1 if PLL has achieved lock.
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
10.2.1 Microport Registers
Register Name:
GL.MCR1
Register Description:
Register Address:
Microport Control Register 1
020h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
021h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
-
0
Bit 1
FIFO1
0
Bit 0
FIFO0
0
020h:
Default
Bits 0-1: FIFO[1:0] FIFO Selection These bits select which FIFO will be accessed for reading or writing.
00 = WAN Insertion FIFO
01 = WAN Extraction FIFO
10 = LAN Insertion FIFO
11 = LAN Extraction FIFO
Register Name:
GL.MCR2
Register Description:
Register Address:
Microport Control Register 2
022h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
WILEN11
0
Bit 10
WILEN10
0
Bit 9
WILEN9
0
Bit 8
WILEN8
0
-
0
-
0
-
0
023h:
Default
Bit 7
WILEN7
0
Bit 6
WILEN6
0
Bit 5
WILEN5
0
Bit 4
WILEN4
0
Bit 3
WILEN3
0
Bit 2
WILEN2
0
Bit 1
WILEN1
0
Bit 0
WILEN0
0
022h:
Default
Bits 0-11: WAN Insertion Frame Length (WILEN[11:0]) These bits determine the number of bytes of the frame to
be written to FIFO selected (Insertion FIFOs only). Maximum size frame is 2048 bytes.
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Register Name:
GL.MCR3
Register Description:
Register Address:
Microport Control Register 3
024h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
LILEN11
0
Bit 10
LILEN10
0
Bit 9
LILEN9
0
Bit 8
LILEN8
0
-
0
-
0
-
0
025h:
Default
Bit 7
LILEN7
0
Bit 6
LILEN6
0
Bit 5
LILEN5
0
Bit 4
LILEN4
0
Bit 3
LILEN3
0
Bit 2
LILEN2
0
Bit 1
LILEN1
0
Bit 0
LILEN0
0
024h:
Default
Bits 0-11: LAN Insertion Frame Length (LILEN[11:0])These bits determine the number of bytes of the frame to
be written to FIFO selected (Insertion FIFOs only). Maximum size frame is 2048 bytes.
Register Name:
GL.MSR1
Register Description:
Register Address:
Microport Status Register 1
026h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
WELEN11
0
Bit 10
WELEN10
0
Bit 9
WELEN9
0
Bit 8
WELEN8
0
-
0
-
0
-
0
027h:
Default
Bit 7
WELEN7
0
Bit 6
WELEN6
0
Bit 5
WELEN5
0
Bit 4
WELEN4
0
Bit 3
WELEN3
0
Bit 2
WELEN2
0
Bit 1
WELEN1
0
Bit 0
WELEN0
0
026h:
Default
Bits 0-11: WAN Extraction Frame Length (WELEN[11:0]) These bits report the size of the frame in bytes
available in the WAN Extraction FIFO. Maximum size frame is 2048 bytes. This value is updated when a complete
frame is received in the WAN Extraction FIFO.
Register Name:
GL.MSR2
Register Description:
Register Address:
Microport Status Register 2
028h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
LILEN11
0
Bit 10
LELEN10
0
Bit 9
LELEN9
0
Bit 8
LELEN8
0
-
0
-
0
-
0
029h:
Default
Bit 7
LELEN7
0
Bit 6
LELEN6
0
Bit 5
LELEN5
0
Bit 4
LELEN4
0
Bit 3
LELEN3
0
Bit 2
LELEN2
0
Bit 1
LELEN1
0
Bit 0
LELEN0
0
028h:
Default
Bits 0-11: LAN Extraction Frame Length (LELEN[11:0]) These bits report the size of the frame in bytes available
in the LAN Extraction FIFO. Maximum size frame is 2048 bytes. This value is updated when a complete frame is
received in the LAN Extraction FIFO.
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
GL.MSR3
Register Description:
Register Address:
Microport Status Register 3
02Ah
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
02Bh:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
LANEA
0
Bit 2
LANIE
0
Bit 1
WANEA
0
Bit 0
WANIE
0
02Ah:
Default
Bit 3: LAN Extraction Available (LANEA) Set when the LAN Extraction FIFO has a frame available to read.
Clears when the first byte is read from the FIFO.
Bit 2: LAN Insertion Queue Empty (LANIE) Set when the LAN Insertion FIFO is empty.
Bit 1: WAN Extraction Available (WANEA) Set when the WAN Extraction FIFO has a frame available to read.
Clears when the first byte is read from the FIFO
Bit 0: WAN Insertion Queue Empty (WANIE) Set when the WAN Insertion FIFO is empty.
Register Name:
GL.MLSR3
Register Description:
Register Address:
Microport Latched Status Register 3
02Ch
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
02Dh:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
LANEAL
0
Bit 2
LANIEL
0
Bit 1
WANEAL
0
Bit 0
WANIEL
0
02Ch:
Default
Bit 3: LAN Extraction Available - Latched (LANEAL) Set when the LAN Extraction FIFO has a frame available to
read. Clears when the first byte is read from the FIFO.
Bit 2: LAN Insertion Empty - Latched (LANIEL) Set when the LAN Insertion FIFO is empty.
Bit 1: WAN Extraction Available - Latched (WANEAL) Set when the WAN Extraction FIFO has a frame available
to read. Clears when the first byte is read from the FIFO.
Bit 0: WAN Insertion Empty - Latched (WANIEL) Set when the WAN Insertion FIFO is empty.
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Register Name:
GL.MSIER3
Register Description:
Register Address:
Microport Status Interrupt Enable Register 3
02Eh
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
02Fh:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
LANEAIE
0
Bit 2
LANIEIE
0
Bit 1
WANEAIE
0
Bit 0
WANIEIE
0
02Eh:
Default
Bit 3: LAN Extraction Available Interrupt Enable (LANEAIE) This bit enables LANEAL to cause an interrupt.
0 = interrupt disabled
1 = interrupt enabled
Bit 2: LAN Insertion Empty Interrupt Enable (LANIEIE) This bit enables an interrupt if the LANIEL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 1: WAN Extraction Available Interrupt Enable (WANEAIE) This bit enables WANEAL to cause an interrupt.
0 = interrupt disabled
1 = interrupt enabled
Bit 0: WAN Insertion Empty Interrupt Enable (WANIEIE) This bit enables an interrupt if the WANIEL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Register Name:
GL.MFAWR
Register Description:
Register Address:
Microport FIFO Access Write Register
030h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
-
0
Bit 10
-
0
Bit 9
RD_DN
0
Bit 8
WR_DN
0
-
0
-
0
-
0
031h:
Default
Bit 7
WPKT7
0
Bit 6
WPKT6
0
Bit 5
WPKT5
0
Bit 4
WPKT4
0
Bit 3
WPKT3
0
Bit 2
WPKT2
0
Bit 1
WPKT1
0
Bit 0
WPKT0
0
030h:
Default
Bit 9: Read Byte (RD_DN) A zero-to-one transition is required after the last byte of the frame has been read from
the MFAWR Register. This signals the associated FIFO (WAN Extract or LAN Extract) to reset its pointers.
Bit 8: Write Byte (WR_DN) A zero-to-one transition is required after the last byte of the frame has been written to
MFAWR Register. This transition signals that the frame is ready to be transferred.
Bits 0-7: Packet Write Byte (WPKT[7:0]) If an Insertion FIFO is selected, this register inserts a byte of frame data
into the FIFO selected by MCR2. The beginning of the frame to be transmitted is written first. Each write
automatically increments the FIFO pointer. If an Extraction FIFO is selected, this register reports a byte of frame
data from the FIFO selected by MCR2. The beginning of the frame to be transmitted is read first. Each read
automatically increments the FIFO pointer.
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Register Name:
GL.MFARR
Register Description:
Register Address:
Microport FIFO Access Read Register
032h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
033h:
Default
0
0
0
0
0
0
0
0
Bit 7
RPKT7
0
Bit 6
RPKT6
0
Bit 5
RPKT5
0
Bit 4
RPKT4
0
Bit 3
RPKT3
0
Bit 2
RPKT2
0
Bit 1
RPKT1
0
Bit 0
RPKT0
0
032h:
Default
Bits 0-7: Packet Read Byte (RPKT[7:0]) If an Extraction FIFO is selected, this register reports a byte of frame
data from the FIFO selected by MCR1. The beginning of the frame to be transmitted is read first. Each read
automatically increments the FIFO pointer.
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
10.2.2 MAC 1 Interface Access Registers
Register Name:
SU.MAC1RADL
Register Description:
Register Address:
MAC 1 Read Address Low Register
040h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
040h:
MACRA7
MACRA6
MACRA5
MACRA4
MACRA3
MACRA2
MACRA1
MACRA0
Default
0
0
0
0
0
0
0
0
Bits 0 – 7: MAC Read Address (MACRA0-7) - Low byte of the MAC address. Used only for read operations.
Register Name:
SU.MAC1RADH
Register Description:
Register Address:
MAC 1 Read Address High Register
041h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
041h:
MACRA15 MACRA14 MACRA13 MACRA12 MACRA11 MACRA10 MACRA9
MACRA8
Default
0
0
0
0
0
0
0
0
Bits 0 – 7: MAC Read Address (MACRA8-15) - High byte of the MAC address. Used only for read operations.
Register Name:
Register Description:
Register Address:
SU.MAC1RD0
MAC 1 Read Data Byte 0
042h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
042h:
MACRD7
MACRD6
MACRD5
MACRD4
MACRD3
MACRD2
MACRD1
MACRD0
Default
0
0
0
0
0
0
0
0
Bits 0 – 7: MAC Read Data 0 (MACRD0-7): One of four bytes of data read from the MAC. Valid after a read
command has been issued and the SU.MAC1RWC.MCS bit is zero.
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Register Name:
Register Description:
Register Address:
SU.MAC1RD1
MAC 1 Read Data Byte 1
043h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
043h:
MACRD15 MACRD14 MACRD13 MACRD12 MACRD11 MACRD10 MACRD9
MACRD8
Default
0
0
0
0
0
0
0
0
Bits 0 - 7: MAC Read Data 1 (MACRD8-15) - One of four bytes of data read from the MAC. Valid after a read
command has been issued and the SU.MAC1RWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
SU.MAC1RD2
MAC 1 Read Data Byte 2
044h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
044h:
MACRD23 MACRD22 MACRD21 MACRD20 MACRD19 MACRD18 MACRD17 MACRD16
Default
0
0
0
0
0
0
0
0
Bits 0 – 7: MAC Read Data 2 (MACRD16-23) - One of four bytes of data read from the MAC. Valid after a read
command has been issued and the SU.MAC1RWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
SU.MAC1RD3
MAC 1 Read Data Byte 3
045h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
045h:
MACRD31 MACRD30 MACRD29 MACRD28 MACRD27 MACRD26 MACRD25 MACRD24
Default
0
0
0
0
0
0
0
0
Bits 0 – 7: MAC Read Data 3 (MACRD24-31) - One of four bytes of data read from the MAC. Valid after a read
command has been issued and the SU.MAC1RWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
SU.MAC1WD0
MAC 1 Write Data Byte 0
046h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
046h:
MACWD7 MACWD6 MACWD5 MACWD4 MACWD3 MACWD2 MACWD1 MACWD0
Default
0
0
0
0
0
0
0
0
Bits 0 – 7: MAC Write Data 0 (MACWD0-7) - One of four bytes of data to be written to the MAC. Data has been
written after a write command has been issued and the SU.MAC1RWC.MCS bit is zero.
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Register Name:
Register Description:
Register Address:
SU.MAC1WD1
MAC 1 Write Data Byte 1
047h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
047h:
MACWD15 MACWD14 MACWD13 MACWD12 MACWD11 MACWD10 MACWD09 MACWD08
Default
0
0
0
0
0
0
0
0
Bits 0 – 7: MAC Write Data 1 (MACWD8-15) - One of four bytes of data to be written to the MAC. Data has been
written after a write command has been issued and the SU.MAC1RWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
SU.MAC1WD2
MAC 1 Write Data Byte 2
048h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
048h:
MACWD23 MACWD22 MACWD21 MACWD20 MACWD19 MACWD18 MACWD17 MACWD16
Default
0
0
0
0
0
0
0
0
Bits 0 - 7: MAC Write Data 2 (MACWD16-23) - One of four bytes of data to be written to the MAC. Data has been
written after a write command has been issued and the SU.MAC1RWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
SU.MAC1WD3
MAC 1 Write Data Byte 3
049h
Bit 7
MACD31
0
Bit 6
MACD30
0
Bit 5
MACD29
0
Bit 4
MACD28
0
Bit 3
MACD27
0
Bit 2
MACD26
0
Bit 1
MACD25
0
Bit 0
MACD24
0
049h:
Default
Bits 0 – 7: MAC Write Data 3 (MACD24-31) - One of four bytes of data to be written to the MAC. Data has been
written after a write command has been issued and the SU.MAC1RWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
SU.MAC1AWL
MAC 1 Address Write Low
04Ah
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
04Ah:
MACAW7 MACAW6 MACAW5 MACAW4 MACAW3 MACAW2 MACAW1 MACAW0
Default
0
0
0
0
0
0
0
0
Bits 0 -7: MAC Write Address (MACAW0-7) - Low byte of the MAC address. Used only for write operations.
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Register Name:
Register Description:
Register Address:
SU.MAC1AWH
MAC 1 Address Write High
04Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
04Bh:
MACAW15 MACAW14 MACAW13 MACAW12 MACAW11 MACAW10 MACAW9 MACAW8
Default
0
0
0
0
0
0
0
0
Bits 0 – 7: MAC Write Address (MACAW8-15) - High byte of the MAC address. Used only for write operations.
Register Name:
SU.MAC1RWC
Register Description:
Register Address:
MAC 1 Read Write Command Status
04Ch
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
MCRW
Bit 0
MCS
04Ch:
Default
0
0
0
0
0
0
0
0
Bit 1: MAC Command RW – If this bit is written to 1, a read is performed from the MAC. If this bit is written to 0, a
write operation is performed. Address information for write operations must be located in SU.MAC1AWH and
SU.MAC1AWL. Address information for read operations must be located in SU.MAC1RADH and SU.MAC1RADL.
The user must also write a 1 to the MCS bit, and the device will clear MCS when the operation is complete.
Bit 0: MAC Command Status – Setting MCS in conjunction with MCRW will initiate a read or write to the MAC
registers. Upon completion of the read or write this bit is cleared. Once a read or write command has been initiated
the host must poll this bit to see when the operation is complete.
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10.2.3 MAC 2 Interface Access Registers
Register Name:
SU.MAC2RADL
Register Description:
Register Address:
MAC 2 Read Address Low Register
060h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
060h:
MACRA7
MACRA6
MACRA5
MACRA4
MACRA3
MACRA2
MACRA1
MACRA0
Default
0
0
0
0
0
0
0
0
Bits 0 – 7: MAC Read Address (MACRA0-7) - Low byte of the MAC address. Used only for read operations.
Register Name:
SU.MAC2RADH
Register Description:
Register Address:
MAC 2 Read Address High Register
061h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
061h:
MACRA15 MACRA14 MACRA13 MACRA12 MACRA11 MACRA10 MACRA9
MACRA8
Default
0
0
0
0
0
0
0
0
Bits 0 – 7: MAC Read Address (MACRA8-15) - High byte of the MAC address. Used only for read operations.
Register Name:
Register Description:
Register Address:
SU.MAC2RD0
MAC 2 Read Data Byte 0
062h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
062h:
MACRD7
MACRD6
MACRD5
MACRD4
MACRD3
MACRD2
MACRD1
MACRD0
Default
0
0
0
0
0
0
0
0
Bits 0 – 7: MAC Read Data 0 (MACRD0-7): One of four bytes of data read from the MAC. Valid after a read
command has been issued and the SU.MAC1RWC.MCS bit is zero.
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Register Name:
Register Description:
Register Address:
SU.MAC2RD1
MAC 2 Read Data Byte 1
063h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
063h:
MACRD15 MACRD14 MACRD13 MACRD12 MACRD11 MACRD10 MACRD9
MACRD8
Default
0
0
0
0
0
0
0
0
Bits 0 - 7: MAC Read Data 1 (MACRD8-15) - One of four bytes of data read from the MAC. Valid after a read
command has been issued and the SU.MAC1RWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
SU.MAC2RD2
MAC 2 Read Data Byte 2
064h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
064h:
MACRD23 MACRD22 MACRD21 MACRD20 MACRD19 MACRD18 MACRD17 MACRD16
Default
0
0
0
0
0
0
0
0
Bits 0 – 7: MAC Read Data 2 (MACRD16-23) - One of four bytes of data read from the MAC. Valid after a read
command has been issued and the SU.MAC1RWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
SU.MAC2RD3
MAC 2 Read Data Byte 3
065h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
065h:
MACRD31 MACRD30 MACRD29 MACRD28 MACRD27 MACRD26 MACRD25 MACRD24
Default
0
0
0
0
0
0
0
0
Bits 0 – 7: MAC Read Data 3 (MACRD24-31) - One of four bytes of data read from the MAC. Valid after a read
command has been issued and the SU.MAC1RWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
SU.MAC2WD0
MAC 2 Write Data Byte 0
066h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
066h:
MACWD7 MACWD6 MACWD5 MACWD4 MACWD3 MACWD2 MACWD1 MACWD0
Default
0
0
0
0
0
0
0
0
Bits 0 – 7: MAC Write Data 0 (MACWD0-7) - One of four bytes of data to be written to the MAC. Data has been
written after a write command has been issued and the SU.MAC1RWC.MCS bit is zero.
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Register Name:
Register Description:
Register Address:
SU.MAC2WD1
MAC 2 Write Data Byte 1
067h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
067h:
MACWD15 MACWD14 MACWD13 MACWD12 MACWD11 MACWD10 MACWD09 MACWD08
Default
0
0
0
0
0
0
0
0
Bits 0 – 7: MAC Write Data 1 (MACWD8-15) - One of four bytes of data to be written to the MAC. Data has been
written after a write command has been issued and the SU.MAC1RWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
SU.MAC2WD2
MAC 2 Write Data Byte 2
068h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
068h:
MACWD23 MACWD22 MACWD21 MACWD20 MACWD19 MACWD18 MACWD17 MACWD16
Default
0
0
0
0
0
0
0
0
Bits 0 - 7: MAC Write Data 2 (MACWD16-23) - One of four bytes of data to be written to the MAC. Data has been
written after a write command has been issued and the SU.MAC1RWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
SU.MAC2WD3
MAC 2 Write Data Byte 3
069h
Bit 7
MACD31
0
Bit 6
MACD30
0
Bit 5
MACD29
0
Bit 4
MACD28
0
Bit 3
MACD27
0
Bit 2
MACD26
0
Bit 1
MACD25
0
Bit 0
MACD24
0
069h:
Default
Bits 0 – 7: MAC Write Data 3 (MACD24-31) - One of four bytes of data to be written to the MAC. Data has been
written after a write command has been issued and the SU.MAC1RWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
SU.MAC2AWL
MAC 2 Address Write Low
06Ah
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
06Ah:
MACAW7 MACAW6 MACAW5 MACAW4 MACAW3 MACAW2 MACAW1 MACAW0
Default
0
0
0
0
0
0
0
0
Bits 0 -7: MAC Write Address (MACAW0-7) - Low byte of the MAC address. Used only for write operations.
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Register Name:
Register Description:
Register Address:
SU.MAC2AWH
MAC 2 Address Write High
06Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
06Bh:
MACAW15 MACAW14 MACAW13 MACAW12 MACAW11 MACAW10 MACAW9 MACAW8
Default
0
0
0
0
0
0
0
0
Bits 0 – 7: MAC Write Address (MACAW8-15) - High byte of the MAC address. Used only for write operations.
Register Name:
SU.MAC2RWC
Register Description:
Register Address:
MAC 2 Read Write Command Status
06Ch
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
MCRW
Bit 0
MCS
06Ch:
Default
0
0
0
0
0
0
0
0
Bit 1: MAC Command RW – If this bit is written to 1, a read is performed from the MAC. If this bit is written to 0, a
write operation is performed. Address information for write operations must be located in SU.MAC1AWH and
SU.MAC1AWL. Address information for read operations must be located in SU.MAC1RADH and SU.MAC1RADL.
The user must also write a 1 to the MCS bit, and the device will clear MCS when the operation is complete.
Bit 0: MAC Command Status – Setting MCS in conjunction with MCRW will initiate a read or write to the MAC
registers. Upon completion of the read or write this bit is cleared. Once a read or write command has been initiated
the host must poll this bit to see when the operation is complete.
Rev: 063008
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10.2.4 VLAN Control Registers
Register Name:
SU.VTC
Register Description:
Register Address:
VLAN Table Control
080h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
081h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
CTE
0
Bit 1
CI
0
Bit 0
CAIM
0
080h:
Default
This register is used to control the VLAN Table. The Initialization function resets all of the 4096 entries in the VLAN
Table to their default value.
Bit 2: Control Table Enable (CTE) When equal to zero, the VLAN Table is fully enabled. When set to 1, the VLAN
Table is only enabled as required by the LAN Extract (LAN-VLAN Trap), WAN Extract (WAN-VLAN Trap), or
microprocessor operations.
Bit 1: Control Initialization (CI). A transition from zero to one starts the VLAN Table initialization by resetting all
VLAN table addresses to their default values. A device reset will also trigger a VLAN Table initialization.
Bit 0: Control Auto Increment Mode (CAIM). When set to 1, the VLAN Table Address in SU.VTAA is
automatically incremented with each read or write of the SU.VTWD or SU.VTRD registers.
Register Name:
SU.VTAA
Register Description:
Register Address:
VLAN Table Access Address
082h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
VTAA12
0
Bit 10
VTAA11
0
Bit 9
VTAA10
0
Bit 8
VTAA9
0
-
0
-
0
-
0
083h:
Default
Bit 7
VTAA8
0
Bit 6
VTAA7
0
Bit 5
VTAA6
0
Bit 4
VTAA5
0
Bit 3
VTAA4
0
Bit 2
VTAA3
0
Bit 1
VTAA2
0
Bit 0
VTAA1
0
082h:
Default
The data that is stored at the specified VLAN Table address is automatically loaded into the read register for this
configuration register address. This is true whether the user is performing a read or write function. The user may
choose to read the data (for the read operation) or disregard the data (for the write operation).
Bits 0-11: VLAN Table Access Address (VTAA [12:1]). This register provides the VLAN Table Address for a uP
Read or Write operation.
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Register Name:
SU.VTWD
Register Description:
Register Address:
VLAN Table Write Data
084h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
085h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
WVEFW
0
Bit 4
WVQFW
0
Bit 3
LVDW
0
Bit 2
LVEFW
0
Bit 1
LVQFW2
0
Bit 0
LVQFW1
0
084h:
Default
Whenever a write is performed to this configuration register address the data is stored in the VLAN Table at the
address specified by the SU.VTAA register (i.e. the VTAA value must be provided in advance of the VTWD data).
VLAN Forwarding, Extracting (Trapping), or Discarding. Each address (SU.VTAA) in the VLAN table
corresponds to a specific VLAN ID (VID) value from 0 to 4095, and the bit settings at each address relate to
actions taken when a frame containing the corresponding VLAN ID value is detected. These values are used to
translate VLAN tag information from each received frame into forwarding, trapping (frame extraction), or discarding
decisions. The user may configure any or all of the 4096 VLAN IDs values in the VLAN table. The data written to
this register is stored in the VLAN Table at the specified VLAN Table Address.
Bit 5: WAN-VLAN Extract Forwarding (WAN-VLAN Trap) (WVEFW)
0 = Do nothing.
1 = Trap frames received from the WAN with this VID and place them in the WAN Extract Queue.
Bit 4: WAN-VLAN Queue Forwarding (WVQFW; Only valid in Forwarding Mode 5)
0 = Forward frames received from the WAN with this VID value to Ethernet Port 1
1 = Forward frames received from the WAN with this VID value to Ethernet Port 2
Bit 3: LAN-VLAN Discard (LVDW)
0 = Do nothing.
1 = Discard frames received from the LAN with this VID
Bit 2: LAN-VLAN Extract Forwarding (LAN-VLAN Trap) (LVEFW)
0 = Do not forward this frame to the LAN Extract Queue
1 = Forward this frame to the LAN Extract Queue
Bits 0-1: LAN-VLAN Queue Forwarding (LVQFW [2:1])
00 = Forward frames with a VID value equal to this table address to LAN Queue Group 1
01 = Forward frames with a VID value equal to this table address to LAN Queue Group 2
10 = Forward frames with a VID value equal to this table address to LAN Queue Group 3
11 = Forward frames with a VID value equal to this table address to LAN Queue Group 4
NOTE:
LAN Extract forwarding takes precedence over LAN Queue forwarding.
LAN Discard takes precedence over LAN Extract forwarding (trapping).
WAN Extract forwarding (trapping) takes precedence over WAN Queue forwarding.
Rev: 063008
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Register Name:
SU.VTRD
Register Description:
Register Address:
VLAN Table Read Data
086h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
087h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
WVEFR
0
Bit 4
WVQFR
0
Bit 3
LVDR
0
Bit 2
LVEFR
0
Bit 1
LVQFR2
0
Bit 0
LVQFR1
0
086h:
Default
Whenever a read operation is performed on this configuration register, the data stored in the VLAN Table at the
address specified by the SU.VTAA register is read. The VTAA value must be initialized prior to the read operation.
VLAN Forwarding. These values determine whether to forward a frame to an extract or forwarding queue or (in
the LAN to WAN direction) whether to discard the frame, There are 4096 VLAN IDs. The user may configure any
number of these 4096 VLAN IDs. The data in this register provides the read data that was retrieved from a VLAN
Table Read operation.
Bit 5: WAN-VLAN Extract Forwarding (WAN-VLAN Trap) (WVEFR)
0 = Do nothing.
1 = Trap frames received from the WAN with this VID and place them in the WAN Extract Queue.
Bit 4: WAN-VLAN Queue Forwarding (WVQFR; Only valid in Forwarding Mode 5)
0 = Forward frames received from the WAN with this VID value to Ethernet Port 1
1 = Forward frames received from the WAN with this VID value to Ethernet Port 2
Bit 3: LAN-VLAN Discard (LVDR)
0 = Do nothing.
1 = Discard frames received from the LAN with this VID
Bit 2: LAN-VLAN Extract Forwarding (LAN-VLAN Trap) (LVEFR)
0 = Do not forward this frame to the LAN Extract Queue
1 = Forward this frame to the LAN Extract Queue
Bits 0-1: LAN-VLAN Queue Forwarding (LVQFR[2:1])
00 = Forward frames with a VID value equal to this table address to LAN Queue Group 1
01 = Forward frames with a VID value equal to this table address to LAN Queue Group 2
10 = Forward frames with a VID value equal to this table address to LAN Queue Group 3
11 = Forward frames with a VID value equal to this table address to LAN Queue Group 4
NOTE:
LAN Extract forwarding takes precedence over LAN Queue forwarding.
LAN Discard takes precedence over LAN Extract forwarding (trapping).
WAN Extract forwarding (trapping) takes precedence over WAN Queue forwarding.
Rev: 063008
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Register Name:
SU.VTSA
Register Description:
Register Address:
VLAN Table Shadow Address
088h
Bit 15
Bit 14
Bit 13
Bit 12
VTIS
0
Bit 11
VTSA12
0
Bit 10
VTSA11
0
Bit 9
VTSA10
0
Bit 8
VTSA9
0
-
0
-
0
-
0
089h:
Default
Bit 7
VTSA8
0
Bit 6
VTSA7
0
Bit 5
VTSA6
0
Bit 4
VTSA5
0
Bit 3
VTSA4
0
Bit 2
VTSA3
0
Bit 1
VTSA2
0
Bit 0
VTSA1
0
088h:
Default
Bit 12: VLAN Table Initialization Status (VTIS): This bit is set to 1 when the VLAN Table initialization has been
completed. Occurs upon reset.
Bits 0-11: VLAN Table Shadow Address (VTSA [12:1]) This register interfaces directly to the VLAN Table
memory block to provide the selected VLAN Table Address that is to be used for each VLAN Table operation (LAN
Trap, WAN Trap or uP Read/Write). When SU.VTC.CAIM = 1, the Shadow Address automatically increments for
each Read and/or Write VLAN Table Access.
Rev: 063008
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10.3 Ethernet Interface Registers
The Ethernet Interface registers are used to configure GMII/MII/RMII bus operation and establish the MAC
parameters as required by the user. The MAC Registers cannot be addressed directly from the Processor port. The
registers below are used to perform indirect read or write operations to the MAC registers. The MAC Status
Registers are shown in Table 10-3. Accessing the MAC Registers is described in Section 8.19.
10.3.1 WAN Extraction and Transmit LAN registers
Register Name:
SU.WEM
Register Description:
Register Address:
WAN Extract Modes and Ethernet Tag Settings
0A0h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
-
0
Bit 10
-
0
Bit 9
WMGMTT
0
Bit 8
WBAT
0
-
0
-
0
-
0
0A1h:
Default
Bit 7
WNVDF
0
Bit 6
WEFR
0
Bit 5
WEDS2
0
Bit 4
WEDS1
0
Bit 3
WEVIT
0
Bit 2
WEETT
0
Bit 1
WEDAT
0
Bit 0
WEHT
0
0A0h:
Default
WAN Extract Modes. This register determines which set of WAN Trap modes have been enabled. The WAN Trap
modes can be unrelated to the LAN Trap modes in the opposite direction. Any combination of these Traps can be
enabled. If any enabled Trap Modes overlap so that the WAN Trap indicates that a frame should be forwarded to
an Ethernet Port and to the WAN Extract, the frame is to be only forwarded to the WAN Extract (e.g. the user might
have configured the WAN Trap to forward the frame’s VLAN ID to Ethernet Port 1, but the frame’s DA might also
indicate that the frame is to be sent to the WAN Extract). WAN VLAN/Q-in-Q Forwarding is enabled through the
Forwarding Mode (not through these registers). The default setting is all Modes disabled.
Bit 9: WAN Extract Management Address Trap (WMGMTT)
0 = WAN Extract Management Address Trap is disabled.
1 = WAN Extract Management Address Trap is enabled. All Ethernet frames with an Ethernet Destination
Address (DA) = 01:80:C2:xx:xx:xx, where “x” is “don’t care,” are forwarded to the WAN extract queue.
Bit 8: WAN Extract Broadcast Address Trap (WBAT)
0 = WAN Extract Broadcast Address Trap is disabled.
1 = WAN Extract Broadcast Address Trap is enabled. All Ethernet frames with an Ethernet Destination
Address (DA) = FF:FF:FF:FF:FF:FF are forwarded to the WAN extract queue.
Bit 7: WAN “No VLAN/Q-in-Q” Detected Forwarding (WNVDF).
0 = When the 13th and 14th bytes in the frame do not equate to the value in WETPID, then the frame is to be
forwarded to Ethernet Interface 1.
1 = When the 13th and 14th bytes in the frame do not equate to the value in WETPID, then the frame is to be
forwarded to Ethernet Interface 2.
To configure the X162 for VLAN or Q-in-Q, WAN to LAN forwarding, the Forwarding Mode must be set to 5, and
the WETPID register must be configured (or use the configuration register default values).
Bit 6: WAN Extract FIFO Reset (WEFR)
0 = Normal – no reset.
1 = One-time, momentary reset of the WAN Extract FIFO.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Bits 4-5: WAN Extract Decap Source (WEDS[2:1])
00 = WAN Extract is to be performed on the data stream from Decapsulator 1 (WAN Group 1).
01 = WAN Extract is to be performed on the data stream from Decapsulator 2 (WAN Group 2).
10 = WAN Extract is to be performed on the data stream from Decapsulator 3 (WAN Group 3).
11 = WAN Extract is to be performed on the data stream from Decapsulator 4 (WAN Group 4).
Note that not all decapsulators are available in all Forwarding Modes. The user should consult the forwarding
diagrams in Section 8.9.1 for the available decapsulators for the configured Forwarding Mode.
Bit 3: WAN Extract VLAN ID Trap (WEVIT)
0 = WAN Extract VLAN ID Trap is disabled.
1 = WAN Extract VLAN ID Trap is enabled. (See Section 8.16.2 for VLAN table programming details.)
Note: Invalid if the WAN Extract Decapsulator (selected by WEDS) has been configured to add an Ethernet Header
(in PP.DMCR.DAE[1:0]). Adding an Ethernet header implies that there is no VLAN ID to Trap.
Bit 2: WAN Extract Ethernet Type Trap (WEETT)
0 = WAN Extract Ethernet Type Trap is disabled.
1 = WAN Extract Ethernet Type Trap is enabled.
Note: Invalid if the WAN Extract Decapsulator (selected by WEDS) has been configured to add an Ethernet Header
(in PP.DMCR.DAE[1:0]). Adding an Ethernet header implies that there is no Ethernet Type field to Trap. Note that
WAN Extract Ethernet Type trapping is not available for frame formats in which the Ethernet Type field is more than
32 bytes into the frame. Thus, Ethernet Type trapping is not applicable on WAN frames in the LLC/SNAP frame
format with 4/8 byte frame headers plus dual VLAN Tags.
Bit 1: WAN Extract Destination Address Trap (WEDAT)
0 = WAN Extract Destination Address Trap is disabled.
1 = WAN Extract Destination Address Trap is enabled.
Note: Invalid if the WAN Extract Decapsulator (selected by WEDS) has been configured to add an Ethernet Header
(in PP.DMCR.DAE[1:0]). Adding an Ethernet header implies that there is no Ethernet DA to Trap.
Bit 0: WAN Extract Header Trap (WEHT)
0 = WAN Extract Header Trap is disabled.
1 = WAN Extract Header Trap is enabled.
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.WEHTP
Register Description:
Register Address:
WAN Extract Header Trap Position
0A2h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
0A3h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
WEHTH
0
Bit 3
WEHTL
0
Bit 2
WEHTP3
0
Bit 1
WEHTP2
0
Bit 0
WEHTP1
0
0A2h:
Default
Bit 4: WAN Extract Header Trap High Byte (WEHTH). This value indicates whether the most significant byte of
the WEHT is to be used when performing the WAN Extract Header Trap
0 = Most significant byte is masked.
1 = Most significant byte is tested (not masked).
Bit 3: WAN Extract Header Trap Low Byte (WEHTL). This value indicates whether the least significant byte of
the WEHT is to be used when performing the WAN Extract Header Trap
0 = Least significant byte is masked.
1 = Least significant byte is tested (not masked).
Bits 0-2: WAN Header Extract Trap Position (WEHTP[3:1]) This value indicates the beginning byte position
within the WAN frame, for where the WAN Header Extract Trap is to be tested. Only binary values 0-6 are valid. A
value “0” indicates that the test is to begin on the first byte of the frame. The WAN Header Trap enables trapping
on SLARP, GFP PTI/UPI, GFP CID or Shim Tag.
Example SU.WEHTP Settings
Bytes
tested
WEHTH
1
WEHTL
0
WEHTP-3 WEHTP-2 WEHTP-1
WEHT
GFP – PTI
100x
xxxxb
xxh
1
0
0
0
Management
GFP Linear -CID
cHDLC SLARP
GFP Null
1
2
1
1
0
1
1
0
0
1
0
0
80 35h
Extension with
Tag-1 (Shim;
MPLS-like)
2
1
1
1
0
0
xx xxh
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.WEHT
Register Description:
Register Address:
WAN Extract Header Trap
0A4h
Bit 15
WEHT16
Bit 14
WEHT15
0
Bit 13
WEHT14
0
Bit 12
WEHT13
0
Bit 11
WEHT12
0
Bit 10
WEHT11
0
Bit 9
WEHT10
0
Bit 8
WEHT9
0
0A5h:
Default
0
Bit 7
WEHT8
0
Bit 6
WEHT7
0
Bit 5
WEHT6
0
Bit 4
WEHT5
0
Bit 3
WEHT4
0
Bit 2
WEHT3
0
Bit 1
WEHT2
0
Bit 0
WEHT1
0
0A4h:
Default
Bits 0-15: WAN Header Trap (WEHT [16:1]) This value provides the first and second bytes of the WAN
Header Extract Trap (least significant bytes of the Trap Header). Any binary value is possible. The least significant
of these two bytes is in bit positions 0 – 7.
Register Name:
SU.WEDAL
Register Description:
Register Address:
WAN Extract Destination Address Low
0A6h
Bit 15
WEDAL16
Bit 14
WEDAL15
0
Bit 13
WEDAL14
0
Bit 12
WEDAL13
0
Bit 11
WEDAL12
0
Bit 10
WEDAL11
0
Bit 9
WEDAL10
0
Bit 8
WEDAL9
0
0A7h:
Default
0
Bit 7
WEDAL8
0
Bit 6
WEDAL7
0
Bit 5
WEDAL6
0
Bit 4
WEDAL5
0
Bit 3
WEDAL4
0
Bit 2
WEDAL3
0
Bit 1
WEDAL2
0
Bit 0
WEDAL1
0
0A6h:
Default
Bits 0-15: WAN Extract Destination Address Low (WEDAL [16:1]) This value provides the first and second
bytes of the WAN Extract Destination Address (least significant bytes of the address). This value in combination
with WEDAM and WEDAH make up the WAN Extract Destination Address. Any binary value is possible. The least
significant of these two bytes is in bit positions 0 – 7. The byte position of the DA within the WAN frame is derived
from the Decap, which knows whether 0, 4 or 8 WAN Header bytes will be removed.
Register Name:
SU.WEDAM
Register Description:
Register Address:
WAN Extract Destination Address Middle
0A8h
Bit 15
WEDAM16
Bit 14
WEDAM15
0
Bit 13
WEDAM14
0
Bit 12
WEDAM13
0
Bit 11
WEDAM12
0
Bit 10
WEDAM11
0
Bit 9
WEDAM10
0
Bit 8
WEDAM9
0
0A9h:
Default
0
Bit 7
WEDAM8
0
Bit 6
WEDAM7
0
Bit 5
WEDAM6
0
Bit 4
WEDAM5
0
Bit 3
WEDAM4
0
Bit 2
WEDAM3
0
Bit 1
WEDAM2
0
Bit 0
WEDAM1
0
0A8h:
Default
Bits 0-15: WAN Extract Destination Address Mid (WEDAM [16:1]) This value provides the third and fourth
bytes of the WAN Extract Destination Address. This value in combination with WEDAL and WEDAH make up the
WAN Extract Destination Address. Any binary value is possible. The least significant of these two bytes is in bit
positions 0 – 7.
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.WEDAH
Register Description:
Register Address:
WAN Extract Destination Address High
0AAh
Bit 15
WEDAH16
Bit 14
WEDAH15
0
Bit 13
WEDAH14
0
Bit 12
WEDAH13
0
Bit 11
WEDAH12
0
Bit 10
WEDAH11
0
Bit 9
WEDAH10
0
Bit 8
WEDAH9
0
0ABh:
Default
0
Bit 7
WEDAH8
0
Bit 6
WEDAH7
0
Bit 5
WEDAH6
0
Bit 4
WEDAH5
0
Bit 3
WEDAH4
0
Bit 2
WEDAH3
0
Bit 1
WEDAH2
0
Bit 0
WEDAH1
0
0AAh:
Default
Bits 0-15: WAN Extract Destination Address High (WEDAH [16:1]) This value provides the fifth and sixth
bytes of the WAN Extract Destination Address. This value in combination with WEDAL and WEDAM make up the
WAN Extract Destination Address. Any binary value is possible. The least significant of these two bytes is in bit
positions 0 – 7.
Register Name:
SU.WEDAX
Register Description:
Register Address:
WAN Extract Destination Address Mask
0ACh
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
0ADh:
Default
0
0
0
0
0
0
0
0
Bit 7
WEDAX8
0
Bit 6
WEDAX7
0
Bit 5
WEDAX6
0
Bit 4
WEDAX5
0
Bit 3
WEDAX4
0
Bit 2
WEDAX3
0
Bit 1
WEDAX2
0
Bit 0
WEDAX1
0
0ACh:
Default
Bits 0-7: WAN Extract Destination Address Mask (WEDAX [8:1]) This value provides a Mask for the Least
Significant byte of the WAN Extract Destination Address (bits 0 - 7 of WEDA0). This mask allows the device to Trap
on multiple DAs (e.g. Bridge Group Address 01-80-C2-00-00-00, Slow Protocols 01-80-C2-00-00-01 and Bridge
Management 01-80-C2-00-00-10). The default setting is all bit positions = 0.
0 = bit mask disabled.
1 = bit mask enabled (this bit of the WAN Extract Destination Address is “don’t care”).
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.WEET
Register Description:
Register Address:
WAN Extract Ethernet Type
0AEh
Bit 15
WEET16
Bit 14
WEET15
0
Bit 13
WEET14
0
Bit 12
WEET13
0
Bit 11
WEET12
0
Bit 10
WEET11
0
Bit 9
WEET10
0
Bit 8
WEET9
0
0AFh:
Default
0
Bit 7
WEET8
0
Bit 6
WEET7
0
Bit 5
WEET6
0
Bit 4
WEET5
0
Bit 3
WEET4
0
Bit 2
WEET3
0
Bit 1
WEET2
0
Bit 0
WEET1
0
0AEh:
Default
Bits 0-15: WAN Extract Ethernet Type (WEET [16:1]). This value defines the 2-byte Ethernet Protocol Type
that the WAN Trap is to monitor for. Bits 0 to 7 are used to define the least significant byte. One example setting is
08-06 (hex) for Ethernet Type = ARP. Note that WAN Extract Ethernet Type trapping is not available for frame
formats in which the Ethernet Type field is more than 32 bytes into the frame. Thus, Ethernet Type trapping is not
applicable on WAN frames in the LLC/SNAP frame format with 4/8 byte frame headers plus dual VLAN Tags.
Register Name:
SU.WETPID
Register Description:
Register Address:
WAN Ethernet Tag Protocol ID
0B2h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
WETPID9
1
WETPID16 WETPID15 WETPID14 WETPID13 WETPID12 WETPID11 WETPID10
0B3h:
Default
1
0
0
0
0
0
0
Bit 7
WETPID8
0
Bit 6
WETPID7
0
Bit 5
WETPID6
0
Bit 4
WETPID5
0
Bit 3
WETPID4
0
Bit 2
WETPID3
0
Bit 1
WETPID2
0
Bit 0
WETPID1
0
0B2h:
Default
WAN Ethernet Tag Protocol ID (WETPID [16:1]). This register specifies the Ethernet Tag Protocol ID that is used
to denote WAN-VLAN frames. Four example settings are 8100 (standard), 9100 and 9200 (Juniper and Foundry)
and 88A8 (Extreme). Only applicable in Forwarding Mode 5.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.WOS
Register Description:
Register Address:
WAN Overflow Status
0B4h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
0B5h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
-
0
Bit 1
-
0
Bit 0
WEOS
0
0B4h:
Default
Bit 0: WAN Extract Overflow Status
0 = no overflow events have occurred since the last read.
1 = 1 or more overflow events have occurred since the last read.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.LIM
Register Description:
Register Address:
LAN Interface Mode
0B6h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
LP2R
0
Bit 10
LP1R
0
Bit 9
LP2CE
0
Bit 8
LP1CE
0
-
0
-
0
-
0
0B7h:
Default
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
LIFR
0
Bit 3
LIIP2
0
Bit 2
LIIP1
0
Bit 1
LIP
0
Bit 0
LIE
0
0B6h:
Default
Bit 11: LAN Port #2 - SRAM Queue Reset (LP2R)
0 = Normal operation.
1 = One-time, momentary reset of all SRAM Queue pointers associated with LAN Transmit Port 2.
Bit 10: LAN Port #1 - SRAM Queue Reset (LP1R)
0 = Normal operation.
1 = One-time, momentary reset of all SRAM Queue pointers associated with LAN Transmit Port 1.
To insure proper reset function, the associated MAC Transmit must be disabled before a reset. This must be done
to ensure that the Transmit MAC is not in the middle of transmitting a frame when the queue is reset. Activating
LP1R does not affect traffic on Port 2 and activating LP2R does not affect traffic on Port 1.
Bit 9: LAN Port 2 CRC Enable (LP2CE)
0 = The transmit MAC will not add an Ethernet FCS (CRC) to frames before transmission.
1 = The transmit MAC adds an Ethernet FCS (CRC) to all frames before transmission.
Bit 8: LAN Port 1 CRC Enable (LP1CE)
0 = The transmit MAC will not add an Ethernet FCS (CRC) to frames before transmission.
1 = The transmit MAC adds an Ethernet FCS (CRC) to all frames before transmission.
Bit 4: LAN Insert FIFO Reset (LIFR)
0 = Normal – no reset.
1 = One-time, momentary reset of the LAN Insert FIFO.
Bit 2-3: LAN Insert Insertion Point (LIIP[2:1])
00 = LAN Insert data is multiplexed with data from Decapsulator #1.
01 = LAN Insert data is multiplexed with data from Decapsulator #2.
10 = LAN Insert data is multiplexed with data from Decapsulator #3.
11 = LAN Insert data is multiplexed with data from Decapsulator #4.
If the LAN Insert is assigned to a Decapsulator that is not enabled (because of the Forwarding mode setting or
because there are no enabled WAN ports associated with that Decapsulator) then the LAN Insert has exclusive
use of that LAN Transmit Queue. For MPL > 2048, if the LAN Insert is enabled (LIE = 1), LIIP must equal 00. In
Forwarding Modes 2 and 5, only LIIP = 00 and 10 are valid. In all other cases, the recommended value is LIIP = 01
for insertion to LAN Port 1, or LIIP = 10 for insertion to LAN Port 2.
Bit 1: LAN Insert Priority (LIP)
0 = LAN Insert frames are lower priority than frames from the associated Decapsulator.
1 = LAN Insert frames are higher priority than frames from the associated Decapsulator.
Bit 0: LAN Insert Enable (LIE)
0 = LAN Insertion is disabled.
1 = LAN Insertion is enabled.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.WOM
Register Description:
Register Address:
WAN Overflow Mask
0B8h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
0B9h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
-
0
Bit 1
-
0
Bit 0
WEOM
0
0B8h:
Default
Bit 0: WAN Extract Overflow Interrupt Mask
0 = WEOS will cause interrupts.
1 = WEOS will not cause interrupts.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.LP1XS
Register Description:
Register Address:
LAN Port 1 Transmit Status
0BAh
Bit 15
LTED
Bit 14
LTJTO
0
Bit 13
LTFF
0
Bit 12
-
0
Bit 11
LTLOC
0
Bit 10
LTNCP
0
Bit 9
LTLC
0
Bit 8
LTEC
0
0BBh:
Default
0
Bit 7
-
0
Bit 6
LTCC3
0
Bit 5
LTCC2
0
Bit 4
LTCC1
0
Bit 3
LTCC0
0
Bit 2
LTEXD
0
Bit 1
LTUFE
0
Bit 0
LTDEF
0
0BAh:
Default
NOTE: This is a real-time status register. Usefulness is limited to single frame transmissions for system
debugging. Most applications will be better served by monitoring the MAC Management Counter (MMC)
registers rather than polling these bits.
Bit 15: LAN Transmit Error Detected (LTED) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission attempt. Indicates Jaber Timeout, Frame Flushed, Loss of Carrier, No
Carrier, Late Collision, Excessive Collisions, or Excessive Deferral.
Bit 14: LAN Transmit Jabber Timeout (LTJTO) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to Jaber Timeout.
Bit 13: LAN Transmit Frame Flushed (LTFF) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to the frame being flushed by a software reset.
Bit 11: LAN Transmit Loss of Carrier (LTLOC) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to Loss of Carrier.
Bit 10: LAN Transmit No Carrier Present (LTNCP) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to the lack of a Carrier.
Bit 9: LAN Transmit Late Collision (LTLC) This real-time status bit is set to 1 when the transmit MAC encounters
an error during a transmission due to a Late Collision.
Bit 8: LAN Transmit Excessive Collisions (LTEC) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to Excessive (>16) Collisions.
Bits 3-6: LAN Transmit Collision Count (LTCC[3:0]) These real-time status bits indicate the number collisions
encountered while attempting to transmit the current frame.
Bit 2: LAN Transmit Excessive Deferral (LTEXD) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to Excessive Deferral.
Bit 1: LAN Transmit Underflow Error (LTUFE) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to data underflow.
Bit 0: LAN Transmit Deferred (LTDEF) This real-time status bit is set to 1 when the transmit MAC is deferring
transmission due to carrier availability. Only valid in half-duplex mode.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.LP2XS
Register Description:
Register Address:
LAN Port 2 Transmit Status
0BCh
Bit 15
LTED
Bit 14
LTJTO
0
Bit 13
LTFF
0
Bit 12
-
0
Bit 11
LTLOC
0
Bit 10
LTNCP
0
Bit 9
LTLC
0
Bit 8
LTEC
0
0BDh:
Default
0
Bit 7
-
0
Bit 6
LTCC3
0
Bit 5
LTCC2
0
Bit 4
LTCC1
0
Bit 3
LTCC0
0
Bit 2
LTEXD
0
Bit 1
LTUFE
0
Bit 0
LTDEF
0
0BCh:
Default
NOTE: This is a real-time status register. Usefulness is limited to single frame transmissions for system
debugging. Most applications will be better served by monitoring the MAC Management Counter (MMC)
registers rather than polling these bits.
Bit 15: LAN Transmit Error Detected (LTED) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission attempt. Indicates Jaber Timeout, Frame Flushed, Loss of Carrier, No
Carrier, Late Collision, Excessive Collisions, or Excessive Deferral.
Bit 14: LAN Transmit Jabber Timeout (LTJTO) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to Jaber Timeout.
Bit 13: LAN Transmit Frame Flushed (LTFF) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to the frame being flushed by a software reset.
Bit 11: LAN Transmit Loss of Carrier (LTLOC) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to Loss of Carrier.
Bit 10: LAN Transmit No Carrier Present (LTNCP) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to the lack of a Carrier.
Bit 9: LAN Transmit Late Collision (LTLC) This real-time status bit is set to 1 when the transmit MAC encounters
an error during a transmission due to a Late Collision.
Bit 8: LAN Transmit Excessive Collisions (LTEC) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to Excessive (>16) Collisions.
Bits 3-6: LAN Transmit Collision Count (LTCC[3:0]) These real-time status bits indicate the number collisions
encountered while attempting to transmit the current frame.
Bit 2: LAN Transmit Excessive Deferral (LTEXD) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to Excessive Deferral.
Bit 1: LAN Transmit Underflow Error (LTUFE) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to data underflow.
Bit 0: LAN Transmit Deferred (LTDEF) This real-time status bit is set to 1 when the transmit MAC is deferring
transmission due to carrier availability. Only valid in half-duplex mode.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
10.3.2 Receive LAN Register Definitions
Register Name:
SU.LPM
Register Description:
Register Address:
LAN Port Modes
0C0h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
-
0
Bit 10
-
0
Bit 9
LMGMTT
0
Bit 8
LBAT
0
-
0
-
0
-
0
0C1h:
Default
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
LEEPS
0
Bit 3
LEVIT
0
Bit 2
LEETT
0
Bit 1
LEDAT
0
Bit 0
LPM
0
0C0h:
Default
This register determines which set of LAN Trap modes have been enabled and whether the device is being used in
a single or dual LAN Port application. The LAN Trap modes can be unrelated to the WAN Trap modes in the
opposite direction. Any combination of these Traps can be enabled. If any enabled Trap Modes overlap so that the
LAN Trap indicates that a frame should be forwarded to a LAN Queue and to the LAN Extract, the frame is to be
only forwarded to the LAN Extract (e.g. the user might have configured the LAN Trap to forward the frame’s VLAN
ID to LAN Queue 1, but the frame’s DA might also indicate that the frame is to be sent to the LAN Extract). LAN
VLAN/Q-in-Q Forwarding is enabled through the device’s Forwarding Mode (Common Control Registers; not
through these registers).
Bit 9: LAN Extract Management Address Trap (LMGMTT)
0 = LAN Extract Management Address Trap is disabled
1 = LAN Extract Management Address Trap is enabled. All Ethernet frames with an Ethernet Destination
Address (DA) = 01:80:C2:xx:xx:xx, where “x” is “don’t care”, are forwarded to the LAN extract queue.
Bit 8: LAN Extract Broadcast Address Trap (LBAT)
0 = LAN Extract Broadcast Address Trap is disabled
1 = LAN Extract Broadcast Address Trap is enabled. All Ethernet frames with an Ethernet Destination
Address (DA) = FF:FF:FF:FF:FF:FF are forwarded to the LAN extract queue.
Bit 4: LAN Extract LAN Port Source (LEEPS)
0 = LAN Extract is to be performed on the data stream from LAN Port 1.
1 = LAN Extract is to be performed on the data stream from LAN Port 2. This option is only valid on
devices that contain two Ethernet Ports, in Forwarding Modes 2, 4, and 5.
Bit 3: LAN Extract VLAN ID Trap (LEVIT)
0 = LAN Extract VLAN ID Trap is disabled
1 = LAN Extract VLAN ID Trap is enabled (See Section 8.16.2 for VLAN table programming details.)
Bit 2: LAN Extract Ethernet Type Trap (LEETT)
0 = LAN Extract Ethernet Type Trap is disabled
1 = LAN Extract Ethernet Type Trap is enabled
Bit 1: LAN Extract Destination Address Trap (LEDAT)
0 = LAN Extract Destination Address Trap is disabled
1 = LAN Extract Destination Address Trap is enabled
Bit 0: LAN Port Mode (LPM).
0 = Single Port Applications using Port 1 (required for GbE applications)
1 = Dual Port Applications (GbE GMII operation not allowed)
Rev: 063008
175 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.LEDAL
Register Description:
Register Address:
LAN Extract Destination Address Low
0C2h
Bit 15
LEDAL15
Bit 14
LEDAL14
0
Bit 13
LEDAL13
0
Bit 12
LEDAL12
0
Bit 11
LEDAL11
0
Bit 10
LEDAL10
0
Bit 9
LEDAL9
0
Bit 8
LEDAL8
0
0C3h:
Default
0
Bit 7
LEDAL7
0
Bit 6
LEDAL6
0
Bit 5
LEDAL5
0
Bit 4
LEDAL4
0
Bit 3
LEDAL3
0
Bit 2
LEDAL2
0
Bit 1
LEDAL1
0
Bit 0
LEDAL0
0
0C2h:
Default
Bits 0-15: LAN Extract Destination Address Low (LEDAL[16:1]). This value provides the first and second
bytes of the LAN Extract Destination Address (least significant bytes of the address). This value in combination with
LEDAM and LEDAH make up the LAN Extract Destination Address. Any binary value is possible. The least
significant of these two bytes is in bit positions 0-7.
Register Name:
SU.LEDAM
Register Description:
Register Address:
LAN Extract Destination Address Middle
0C4h
Bit 15
LEDAM15
Bit 14
LEDAM14
0
Bit 13
LEDAM13
0
Bit 12
LEDAM12
0
Bit 11
LEDAM11
0
Bit 10
LEDAM10
0
Bit 9
LEDAM9
0
Bit 8
LEDAM8
0
0C5h:
Default
0
Bit 7
LEDAM7
0
Bit 6
LEDAM6
0
Bit 5
LEDAM5
0
Bit 4
LEDAM4
0
Bit 3
LEDAM3
0
Bit 2
LEDAM2
0
Bit 1
LEDAM1
0
Bit 0
LEDAM0
0
0C4h:
Default
Bits 0-15: LAN Extract Destination Address Middle (LEDAM[16:1]). This value provides the third and fourth
bytes of the LAN Extract Destination Address. This value in combination with LEDAL and LEDAH make up the LAN
Extract Destination Address. Any binary value is possible. The least significant of these two bytes is in bit positions
0-7.
Rev: 063008
176 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.LEDAH
Register Description:
Register Address:
LAN Extract Destination Address High
0C6h
Bit 15
LEDAH15
Bit 14
LEDAH14
0
Bit 13
LEDAH13
0
Bit 12
LEDAH12
0
Bit 11
LEDAH11
0
Bit 10
LEDAH10
0
Bit 9
LEDAH9
0
Bit 8
LEDAH8
0
0C7h:
Default
0
Bit 7
LEDAH7
0
Bit 6
LEDAH6
0
Bit 5
LEDAH5
0
Bit 4
LEDAH4
0
Bit 3
LEDAH3
0
Bit 2
LEDAH2
0
Bit 1
LEDAH1
0
Bit 0
LEDAH0
0
0C6h:
Default
Bits 0-15: LAN Extract Destination Address High (LEDAH[16:1]) This value provides the fifth and sixth
bytes of the LAN Extract Destination Address. This value in combination with LEDAL and LEDAM make up the
LAN Extract Destination Address. Any binary value is possible. The least significant of these two bytes is in bit
positions 0-7.
Register Name:
SU.LEDAX
Register Description:
Register Address:
LAN Extract Destination Address Mask
0C8h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
0C9h:
Default
0
0
0
0
0
0
0
0
Bit 7
LEDAX7
0
Bit 6
LEDAX6
0
Bit 5
LEDAX5
0
Bit 4
LEDAX4
0
Bit 3
LEDAX3
0
Bit 2
LEDAX2
0
Bit 1
LEDAX1
0
Bit 0
LEDAX0
0
0C8h:
Default
Bits 0-7: LAN Extract Destination Address Mask (LEDAX [8:1]). This value provides a Mask for the Least
Significant byte of the LAN Extract Destination Address (bits 0 - 7 of LEDA0). This mask allows the device to Trap
on multiple DAs (e.g. Bridge Group Address 01-80-C2-00-00-00, Slow Protocols 01-80-C2-00-00-01 and Bridge
Management 01-80-C2-00-00-10).
0 = bit mask disabled
1 = bit mask enabled (this bit of the LAN Extract Destination Address is “does not care”)
Rev: 063008
177 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.LEET
Register Description:
Register Address:
LAN Extract Ethernet Type
0CAh
Bit 15
LEET15
Bit 14
LEET14
0
Bit 13
LEET13
0
Bit 12
LEET12
0
Bit 11
LEET11
0
Bit 10
LEET10
0
Bit 9
LEET9
0
Bit 8
LEET8
0
0CBh:
Default
0
Bit 7
LEET7
0
Bit 6
LEET6
0
Bit 5
LEET5
0
Bit 4
LEET4
0
Bit 3
LEET3
0
Bit 2
LEET2
0
Bit 1
LEET1
0
Bit 0
LEET0
0
0CAh:
Default
Bits 0-15: LAN Extract Ethernet Type (LEET[16:1]). This value defines the 2-byte Ethernet Protocol Type
that the LAN Trap is to monitor for. Bits 0 to 7 are used to define the least significant byte. One example setting is
08-06 (hex) for Ethernet Type = ARP.
Register Name:
SU.LP1C
Register Description:
Register Address:
LAN Port 1 Control
0CCh
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
0CDh:
Default
0
0
0
0
0
0
0
0
Bit 7
LP1MIM
0
Bit 6
LP1QOM
0
Bit 5
LP1FR
0
Bit 4
LP1PF2
0
Bit 3
LP1PF1
0
Bit 2
LP1ETF2
0
Bit 1
LP1ETF1
0
Bit 0
LP1E
0
0CCh:
Default
Bit 7: LAN Port 1 MAC Interrupt Mask control (LP1MIM)
0 = Interrupt is disabled so that LAN Port 1 MAC cannot generate an interrupt.
1 = Interrupt is enabled so that LAN Port 1 MAC can generate an interrupt.
Bit 6: LAN Port 1 Queue Overflow Mask (LP1QOM)
0 = SU.LIQOS.LIQOS1 will not generate an interrupt.
1 = SU.LIQOS.LIQOS1 will generate an interrupt.
Bit 5: LAN Port 1 FIFO Reset (LP1FR)
0 = Normal operation.
1 = Reset the LAN 1 receive FIFO. The MAC Receiver should be disabled during FIFO reset.
Bits 3-4: LAN Port 1 Priority Forwarding (LP1PF[2:1])
00 = Priority Forwarding/Scheduling Disabled
01 = DSCP (DiffServ) Priority Forwarding/Scheduling Enabled
10 = 802.1Q (VLAN Tag PCP) Priority Forwarding/Scheduling Enabled
11 = Reserved
Bit 1-2: LAN Port 1 Ethernet VLAN Tag Function Enable(LP1ETF[2:1]). The Ethernet VLAN Tag functions
are not required to be enabled for Priority Scheduling (LP1PF = 01/10).
00 = LAN Ethernet VLAN Tag Functions Disabled
01 = LAN Ethernet VLAN Tag Extract, Forwarding/Scheduling, Discarding Functions Enabled
10 = Reserved
11 = Reserved
Bit 0: LAN Port 1 Enable (LP1E)
0 = Disabled
1 = Enabled
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.LP2C
Register Description:
Register Address:
LAN Port 2 Control
0CEh
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
0CFh:
Default
0
0
0
0
0
0
0
0
Bit 7
LP2MIM
0
Bit 6
LP2QOM
0
Bit 5
LP2FR
0
Bit 4
LP2PF2
0
Bit 3
LP2PF1
0
Bit 2
LP2ETF2
0
Bit 1
LP2ETF1
0
Bit 0
LP2E
0
0CEh:
Default
Bit 7: LAN Port 2 MAC Interrupt Mask control (LP2MIM)
0 = Interrupt is disabled so that LAN Port 2 MAC cannot generate an interrupt.
1 = Interrupt is enabled so that LAN Port 2 MAC can generate an interrupt.
Bit 6: LAN Port 2 Queue Overflow Mask (LP2QOM)
0 = SU.LIQOS.LIQOS2 will not generate an interrupt.
1 = SU.LIQOS.LIQOS2 will generate an interrupt.
Bit 5: LAN Port 2 FIFO Reset (LP2FR)
0 = Normal operation.
1 = Reset the LAN 2 receive FIFO. The MAC Receiver should be disabled during FIFO reset.
Bit 4-3: LAN Port 2 Priority Forwarding/Scheduling (LP2PF[2:1]).
00 = Priority Forwarding/Scheduling Disabled
01 = DSCP (DiffServ) Priority Forwarding/Scheduling Enabled
10 = 802.1Q (VLAN Tag PCP) Priority Forwarding/Scheduling Enabled
11 = Reserved
Bit 2-1: LAN Port 2 Ethernet VLAN Tag Function Enable (LP2ETF[2:1]). The Ethernet VLAN Tag functions
are not required to be enabled for Priority Scheduling (LP1PF = 01/10).
00 = LAN Ethernet VLAN Tag Functions Disabled
01 = LAN Ethernet VLAN Tag Extract, Forwarding/Scheduling, Discarding Functions Enabled
10 = Reserved
11 = Reserved
Bit 0: LAN Port 2 Enable (LP2E).
0 = Disabled
1 = Enabled
The L2PE = 1 (Enabled) is only valid when LPM = 1 (Dual Port) and when in Forwarding Modes 2, 4, or 5.
Otherwise, the device should be configured to L2PE =0 (Disabled).
When LAN Port 2 Priority Forwarding or Priority Scheduling has been enabled, the user must also configure the
Priority Table and No Priority Detected registers.
When LAN Port 2 Ethernet Tag Forwarding has been enabled, the user must also configure the Ethernet Tag Table
and No Ethernet Tag Detected registers.
Rev: 063008
179 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.LNFC
Register Description:
Register Address:
LAN No-Match Forwarding Control
0D0h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
0D1h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
LNPDF2
0
Bit 4
LNPDF1
0
Bit 3
LNETDF4
0
Bit 2
LNETDF3
0
Bit 1
LNETDF2
0
Bit 0
LNETDF1
0
0D0h:
Default
Bit 4-5: LAN No Priority Tag Detected Forwarding (LNPDF[2:1]). Enabled for each port with SU.LP1C.LP1PF
or SU.LP2C.LP2PF. Controls how frames are handled when the received frame does not contain DSCP, does not
contain a VLAN Tag, or the 13th and 14th bytes of the frame do not match the value in SU.LQTPID. The same
action is applied to both Ethernet ports.
00 = Forward to LAN Priority Queue 1
01 = Forward to LAN Priority Queue 2
10 = Forward to LAN Priority Queue 3
11 = Forward to LAN Priority Queue 4
Bit 0-3: LAN No VLAN Tag Detected Forwarding (LNVDF[4:1]). Enabled for each port with SU.LP1C.LP1ETF or
SU.LP2C.LP2ETF. Controls how frames are handled when the received frame does not contain a VLAN tag or the
13th and 14th bytes of the frame do no match the value in SU.LQTPID. The same action is applied to both Ethernet
ports.
0000 = Forward to WAN Group 1
0001 = Forward to WAN Group 2
0010 = Forward to WAN Group 3
0011 = Forward to WAN Group 4
01xx = Forward this frame to the LAN Extract Queue
1xxx = Discard this frame
Register Name:
SU.LQXPC
Register Description:
Register Address:
LAN Queue Watermark Transmit Pause Control
0D2h
Bit 15
LQXPC16
Bit 14
LQXPC15
0
Bit 13
LQXPC14
0
Bit 12
LQXPC13
0
Bit 11
LQXPC12
0
Bit 10
LQXPC11
0
Bit 9
LQXPC10
0
Bit 8
LQXPC9
0
0D3h:
Default
0
Bit 7
LQXPC8
0
Bit 6
LQXPC7
0
Bit 5
LQXPC6
0
Bit 4
LQXPC5
0
Bit 3
LQXPC4
0
Bit 2
LQXPC3
0
Bit 1
LQXPC2
0
Bit 0
LQXPC1
0
0D2h:
Default
Bits 0-15: LAN Queue Watermark Xmt Pause Control (LQXPC [16-1]) One bit is provided for each of the 16
LAN Queues. When set to one, a pause frame will be transmitted when the associated queue has exceeded the
watermark defined in AR.LQW.
0 = LAN Queue Watermark Xmt Pause Control Disabled
1 = LAN Queue Watermark Xmt Pause Control Enabled
Rev: 063008
180 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.LQTPID
Register Description:
Register Address:
LAN Q-in-Q and VLAN Tag Protocol ID
0D4h
Bit 15
LQTPID16
Bit 14
LQTPID15
0
Bit 13
LQTPID14
0
Bit 12
LQTPID13
0
Bit 11
LQTPID12
0
Bit 10
LQTPID11
0
Bit 9
LQTPID10
0
Bit 8
LQTPID9
0
0D5h:
Default
0
Bit 7
LQTPID8
0
Bit 6
LQTPID7
0
Bit 5
LQTPID6
0
Bit 4
LQTPID5
0
Bit 3
LQTPID4
0
Bit 2
LQTPID3
0
Bit 1
LQTPID2
0
Bit 0
LQTPID1
0
0D4h:
Default
Bits 0-15: LAN Q-in-Q Tag Protocol ID (LQTPID [16:1]) This register specifies the Ethernet Tag Protocol ID that
is used to denote LAN-VLAN and Q-in-Q frames. Four example settings are 8100 (standard), 9100 and 9200
(Juniper and Foundry) and 88A8 (Extreme). The default setting is for 8100.
Register Name:
SU.LIQOS
Register Description:
Register Address:
LAN Port and LAN Queue Overflow Status
0D6h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
0D7h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
LP2I
0
Bit 2
LP1I
0
Bit 1
LIQOS2
0
Bit 0
LIQOS1
0
0D6h:
Default
Bit 3: LAN Port 2 Interrupt Status (LP2I):
0 = No active interrupt condition on LAN Port 2.
1 = Active interrupt condition on LAN Port 2. Reset following a read of this register.
Bit 2: LAN Port 1 Interrupt Status (LP1I):
0 = No active interrupt condition on LAN Port 1.
1 = Active interrupt condition on LAN Port 1. Reset following a read of this register.
Bit 1: LAN Input Queue Overflow Status - LAN Port 2 (LIQOS2):
0 = no overflow events have occurred since the last read
1 = 1 or more overflow events have occurred since the last read
Bit 0: LAN Input Queue Overflow Status - LAN Port 1 (LIQOS1):
0 = no overflow events have occurred since the last read
1 = 1 or more overflow events have occurred since the last read
The LAN Queue Overflow Status register bits are set when a frame has been discarded due to Transmit LAN
Queue overflow and are reset following a read of this register.
Rev: 063008
181 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.MPL
Register Description:
Register Address:
LAN Maximum Packet Length
0D8h
Bit 15
Bit 14
Bit 13
MPL14
0
Bit 12
MPL13
0
Bit 11
MPL12
0
Bit 10
MPL11
1
Bit 9
MPL10
0
Bit 8
MPL9
1
-
0
-
0
0D9h:
Default
Bit 7
MPL8
1
Bit 6
MPL7
1
Bit 5
MPL6
1
Bit 4
MPL5
1
Bit 3
MPL4
1
Bit 2
MPL3
1
Bit 1
MPL2
1
Bit 0
MPL1
1
0D8h:
Default
Bits 0-13: Maximum Packet Length (MPL [14:1]) Maximum frame length, in bytes. The receive MAC discards
Ethernet frame received from the LAN interface that have a frame length greater than the user configured MPL
value. This value is applied to both Ethernet ports. If the device has been configured to discard the Ethernet FCS
then the byte count up to the FCS is used. If the FCS is retained, then the count includes 4 bytes for the FCS. The
maximum valid value for this register is 10240 bytes. Note that frames between 9018 and 10240 bytes may be
counted as “giant frames” by the MAC.
Table 10-5. Valid Conditions for MPL > 2048
Jumbo Frames
Description
Register / Bit
Comments
Supported When
Forwarding Mode GL.CR1.FMC
= 001
Forwarding mode 2 only.
Priority
Only no priority or strict priority scheduling
supported.
For dual port devices, Single Port Mode
must be used.
For dual port devices, port 2 must be
disabled.
AR.LQSC.LQSM
Scheduling
= 0
= 0
= 0
LAN Port Mode
SU.LPM.LPM
LAN Port 2
Enable
SU.LP2C.LP2E
Port 1 Policing
SU.L1PP.L1PM[2:1]
= 00
= 0
Port policing must be disabled.
Bridge filter must be disabled.
If LAN Insert is enabled.
Bridge Filter
LAN Insert
SU.BFC.BFE
SU.LIM.LIIP[2:1]
= 00
= 0
LAN Extract
SU.LPM.LEEPS
If LAN Extract is enabled (LPM enables).
Rev: 063008
182 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.L1PP
Register Description:
Register Address:
LAN 1 Policing Parameters
0DAh
Bit 15
CBSS
Bit 14
Bit 13
Bit 12
-
0
Bit 11
L1PM2
0
Bit 10
L1PM1
0
Bit 9
L1PCR2
0
Bit 8
L1PCR1
0
-
0
-
0
0DBh:
Default
0
Bit 7
L1PCT8
0
Bit 6
L1PCT7
0
Bit 5
L1PCT6
0
Bit 4
L1PCT5
0
Bit 3
L1PCT4
0
Bit 2
L1PCT3
0
Bit 1
L1PCT2
0
Bit 0
L1PCT1
0
0DAh:
Default
LAN 1 Policing Parameters . This register determines the Policing function setting for Ethernet port 1. The
Policing function is used to control the rate at which frames are forwarded to Serial Interfaces. The Policing function
can be configured to send Explicit Back Pressure Flow Control to the Ethernet Sending equipment (Ethernet Pause
Control) or can be used to enable a frame discarding mechanism that restrict the rate at which frame are accepted.
Bit 15: Committed Burst Size Selection (CBSS) This bit function is not available in device revision A1
(GL.IDR.REVn = 000).
0 = Default condition. CBS is 4096 bytes.
1 = CBS is 12288 bytes. Only valid in Policing Discard mode.
Bits 10-11: LAN 1 Policing Mode (L1PM[2:1])
00 = Policing Disabled
01 = Policing Pause Enabled
10 = Policing Discard Enabled
11 = Reserved
Bits 8-9: LAN 1 Policing Credit Range (L1PCR[2:1])
00 = Low Credit Range for CIR = 64kbps to 2Mbps
01 = Mid Credit Range for CIR = 2Mbps to 16Mbps
10 = High Credit Range for CIR = 16Mbps to 416Mbps
11 = Reserved
Bits 0-7: LAN 1 Policing Credit Threshold (L1PCT[8:1]). This register specifies the Credit Threshold setting of
the Policing function. Only values between 8 to 255 are supported.
Rev: 063008
183 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.L2PP
Register Description:
Register Address:
LAN 2 Policing Parameters
0DCh
Bit 15
CBSS
Bit 14
Bit 13
Bit 12
-
0
Bit 11
L2PM2
0
Bit 10
L2PM1
0
Bit 9
L2PCR2
0
Bit 8
L2PCR1
0
-
0
-
0
0DDh:
Default
0
Bit 7
L2PCT8
0
Bit 6
L2PCT7
0
Bit 5
L2PCT6
0
Bit 4
L2PCT5
0
Bit 3
L2PCT4
0
Bit 2
L2PCT3
0
Bit 1
L2PCT2
0
Bit 0
L2PCT1
0
0DCh:
Default
LAN 2 Policing Parameters. This register determines the Policing function setting for Ethernet port 2. The Policing
function is used to control the rate at which frames are forwarded to Serial Interfaces. The Policing function can be
configured to send Explicit Back Pressure Flow Control to the Ethernet Sending equipment (Ethernet Pause
Control) or can be used to enable a frame discarding mechanism that restrict the rate at which frame are accepted.
Bit 15: Committed Burst Size Selection (CBSS) This bit function is not available in device revision A1
(GL.IDR.REVn=000).
0 = Default condition. CBS is 4096 bytes.
1 = CBS is 12288 bytes. Only valid in Policing Discard mode.
Bits 10-11: LAN 2 Policing Mode (L2PM[2:1])
00 = Policing Disabled
01 = Policing Pause Enabled
10 = Policing Discard Enabled
11 = Reserved
Bits 8-9: LAN 2 Policing Credit Range (L2PCR[2:1])
00 = Low Credit Range for CIR = 64kbps to 2Mbps
01 = Mid Credit Range for CIR = 2Mbps to 16Mbps
10 = High Credit Range for CIR = 16Mbps to 416Mbps
11 = Reserved
Bits 0-7: LAN 2 Policing Credit Threshold (L2PCT[8:1]). This register specifies the Credit Threshold setting of
the Policing function. Only values between 8 to 255 are supported.
Rev: 063008
184 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.PTC
Register Description:
Register Address:
Priority Table Control
0DEh
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
0DFh:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
-
0
Bit 1
PTE
0
Bit 0
PTAIM
0
0DEh:
Default
Priority Table Control This register is used to initialize and specify the operating mode of the Priority Table. The
Initialization function causes each entry of the Priority Table to be populated with the Priority Table Write Data
default value. The configuration of this table is similar to that of the VLAN Table. However, although this table
provides an automated self-init at power-up, it does not allow the user to request a new initialization ”at will”.
Bit 1: Priority Table Enable (PTE) When equal to zero, the Priority Table is enabled. When set to 1, the Priority
Table does not affect the forwarding of frames.
Bit 0: Priority Table Auto Increment Mode (PTAIM) When set, the Priority Table Address in SU.PTAA is
automatically with each read or write of the SU.PTWD or SU.PTRD registers.
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Register Name:
SU.PTAA
Register Description:
Register Address:
Priority Table Access Address
0E0h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
0E1h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
PTPAA
0
Bit 5
PTAA6
0
Bit 4
PTAA5
0
Bit 3
PTAA4
0
Bit 2
PTAA3
0
Bit 1
PTAA2
0
Bit 0
PTAA1
0
0E0h:
Default
Bit 6: Priority Table Port Access Address (PTPAA). This bit is an extension of the PTAA[6:1] bits, but is used to
divide between Priority lookups for Ethernet (LAN) Port 1 (PTPAA = 0) and Ethernet (LAN) Port 2 (PTPAA = 1). Not
valid for devices with only one Ethernet port.
Bits 0-5: Priority Table Access Address (PTAA [6:1]). These bits provide the Priority Table Address for a uP
Read or Write operation. The address into the priority table is used to resolve VLAN 802.1p PCP and DSCP to the
four priority levels. When using PCP priority mode, only addresses PTAA[3:1] are used. The priority mode for each
Ethernet port can be independently selected using the SU.LP1C and SU.LP2C registers.
Register Name:
SU.PTWD
Register Description:
Register Address:
Priority Table Write Data
0E2h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
0E3h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
-
0
Bit 1
LPQFW2
0
Bit 0
LPQFW1
0
0E2h:
Default
Bits 0-1: LAN Priority Queue Forwarding (LPQFW[2:1])
00 = Map the value of this table entry’s address (PCP or DSCP) to Priority Level 1
01 = Map the value of this table entry’s address (PCP or DSCP) to Priority Level 2
10 = Map the value of this table entry’s address (PCP or DSCP) to Priority Level 3
11 = Map the value of this table entry’s address (PCP or DSCP) to Priority Level 4
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Register Name:
SU.PTRD
Register Description:
Register Address:
Priority Table Read Data
0E4h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
0E5h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
-
0
Bit 1
LPQFR2
0
Bit 0
LPQFR1
0
0E4h:
Default
Bits 0-1: LAN Priority Queue Forwarding (LPQFR[2:1])
00 = The value of this table entry’s address (PCP or DSCP) is mapped to Priority Level 1
01 = The value of this table entry’s address (PCP or DSCP) is mapped to Priority Level 2
10 = The value of this table entry’s address (PCP or DSCP) is mapped to Priority Level 3
11 = The value of this table entry’s address (PCP or DSCP) is mapped to Priority Level 4
Note that LAN-VLAN Discarding and LAN Extraction takes precedence over Priority Forwarding.
Register Name:
SU.PTSA
Register Description:
Register Address:
Priority Table Shadow Address
0E6h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
0E7h:
Default
0
0
0
0
0
0
0
0
Bit 7
PTIS
0
Bit 6
PTPSA
0
Bit 5
PTSA6
0
Bit 4
PTSA5
0
Bit 3
PTSA4
0
Bit 2
PTSA3
0
Bit 1
PTSA2
0
Bit 0
PTSA1
0
0E6h:
Default
Bit 7: Priority Table Initialization Status (PTIS): This bit is set when the Priority Table initialization has been
completed.
Bit 6: Priority Table Port Shadow Address (PTSAA). This bit is an extension of the PTSA [6:1] bits, but is used
to divide between Priority lookups for LAN Port 1 (PTSAA = 0) and LAN Port 2 (PTSAA = 1).
Bits 0-5: Priority Table Shadow Address (PTSA [6:1]). This register interfaces directly to the Priority Table
memory block to provide the selected Priority Table Address that is to be used for each Priority Table operation
(LAN Trap, WAN Trap or uP Read/Write). When PTAIM = 1, the Shadow Address automatically increments for
each updated Read and/or Write Priority Table Access Address.
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10.3.3 Bridge Filter Registers
Register Name:
SU.BFC
Register Description:
Register Address:
Bridge Filter Control
0E8h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
BFTR
Bit 9
BFE
Bit 8
BFAP9
0E9h:
-
-
-
-
-
Default
0
0
0
0
0
0
0
1
Bit 7
BFAP8
0
Bit 6
BFAP7
0
Bit 5
BFAP6
1
Bit 4
BFAP5
0
Bit 3
BFAP4
1
Bit 2
BFAP3
Bit 1
BFAP2
Bit 0
BFAP1
0
0E8h:
Default
1
0
Bit 10: Bridge Filter Table Reset (BFTR). When the user configures this bit to BFTR = 1, the Bridge Filter
automatically steps through each of the 4096 Bridge Filter Table addresses, aging all Table entries so that the table
is reset (one-time event each time the user writes BFTR = 1).
0 = No Bridge Filter Table Reset
1 = One-time Bridge Filter Table Reset
Bit 9: Automatic Bridge Filter Enable (BFE)
0 = Automatic Bridging and Filtering disabled for all Ethernet ports.
1 = Automatic Bridging and Filtering enabled for all Ethernet ports.
Bits 8-0: Bridge Filter Aging Period (BFAP[1-9]). These bits provide the binary coded value for the Aging Period.
The valid equivalent decimal values for this variable are 1 to 300. Values larger than 300 will not increase the aging
period above 300 seconds. The default is set to 300 sec.
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10.4 Arbiter Registers
The Arbiter manages the transport between the Ethernet port and the Serial Interface. It is responsible for queuing
and dequeuing data to an external SDRAM. The arbiter handles requests from the HDLC and MAC to transfer data
to/from the SDRAM.
10.4.1 Arbiter Register Bit Descriptions
Register Name:
AR.LQ1SA
Register Description:
Register Address:
LAN Queue 1 Start Address
100h
Bit 15
-
0
Bit 14
-
0
Bit 13
-
0
Bit 12
-
0
Bit 11
-
0
Bit 10
LQ1QPR
0
Bit 9
LQ1SA-10
0
Bit 8
LQ1SA-9
0
101h:
Default
Bit 7
LQ1SA-8
0
Bit 6
LQ1SA-7
0
Bit 5
LQ1SA-6
0
Bit 4
LQ1SA-5
0
Bit 3
LQ1SA-4
0
Bit 2
LQ1SA-3
0
Bit 1
LQ1SA-2
0
Bit 0
LQ1SA-1
0
100h:
Default
Bit 10: LAN Queue 1 Queue Pointer Reset
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Queue 1 Start Address [10-1] This register specifies the Start Address for the LAN Queue 1. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.LQ2SA
Register Description:
Register Address:
LAN Queue 2 Start Address
102h
Bit 15
-
0
Bit 14
-
0
Bit 13
-
0
Bit 12
-
0
Bit 11
-
0
Bit 10
LQ2QPR
0
Bit 9
LQ2SA-10
0
Bit 8
LQ2SA-9
0
103h:
Default
Bit 7
LQ2SA-8
0
Bit 6
LQ2SA-7
0
Bit 5
LQ2SA-6
0
Bit 4
LQ2SA-5
0
Bit 3
LQ2SA-4
0
Bit 2
LQ2SA-3
0
Bit 1
LQ2SA-2
0
Bit 0
LQ2SA-1
0
102h:
Default
Bit 10: LAN Queue 2 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Queue 2 Start Address [10-1] This register specifies the Start Address for the LAN Queue 2. The
value specifies the most significant 10 bits of the SDRAM absolute address.
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Register Name:
AR.LQ3SA
Register Description:
Register Address:
LAN Queue 3 Start Address
104h
Bit 15
-
0
Bit 14
-
0
Bit 13
-
0
Bit 12
-
0
Bit 11
-
0
Bit 10
LQ3QPR
0
Bit 9
LQ3SA-10
0
Bit 8
LQ3SA-9
0
105h:
Default
Bit 7
LQ3SA-8
0
Bit 6
LQ3SA-7
0
Bit 5
LQ3SA-6
0
Bit 4
LQ3SA-5
0
Bit 3
LQ3SA-4
0
Bit 2
LQ3SA-3
0
Bit 1
LQ3SA-2
0
Bit 0
LQ3SA-1
0
104h:
Default
Bit 10: LAN Queue 3 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Queue 3 Start Address [10-1] This register specifies the Start Address for the LAN Queue 3. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.LQ4SA
Register Description:
Register Address:
LAN Queue 4 Start Address
106h
Bit 15
-
0
Bit 14
-
0
Bit 13
-
0
Bit 12
-
0
Bit 11
-
0
Bit 10
LQ4QPR
0
Bit 9
LQ4SA-10
0
Bit 8
LQ4SA-9
0
107h:
Default
Bit 7
LQ4SA-8
0
Bit 6
LQ4SA-7
0
Bit 5
LQ4SA-6
0
Bit 4
LQ4SA-5
0
Bit 3
LQ4SA-4
0
Bit 2
LQ4SA-3
0
Bit 1
LQ4SA-2
0
Bit 0
LQ4SA-1
0
106h:
Default
Bit 10: LAN Queue 4 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Queue 4 Start Address [10-1] This register specifies the Start Address for the LAN Queue 4. The
value specifies the most significant 10 bits of the SDRAM absolute address.
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Register Name:
AR.LQ5SA
Register Description:
Register Address:
LAN Queue 5 Start Address
108h
Bit 15
-
0
Bit 14
-
0
Bit 13
-
0
Bit 12
-
0
Bit 11
-
0
Bit 10
LQ5QPR
0
Bit 9
LQ5SA-10
0
Bit 8
LQ5SA-9
0
109h:
Default
Bit 7
LQ5SA-8
0
Bit 6
LQ5SA-7
0
Bit 5
LQ5SA-6
0
Bit 4
LQ5SA-5
0
Bit 3
LQ5SA-4
0
Bit 2
LQ5SA-3
0
Bit 1
LQ5SA-2
0
Bit 0
LQ5SA-1
0
108h:
Default
Bit 10: LAN Queue 5 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Queue 5 Start Address [10-1] This register specifies the Start Address for the LAN Queue 5. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.LQ6SA
Register Description:
Register Address:
LAN Queue 6 Start Address
10Ah
Bit 15
-
0
Bit 14
-
0
Bit 13
-
0
Bit 12
-
0
Bit 11
-
0
Bit 10
LQ6QPR
0
Bit 9
LQ6SA-10
0
Bit 8
LQ6SA-9
0
10Bh:
Default
Bit 7
LQ6SA-8
0
Bit 6
LQ6SA-7
0
Bit 5
LQ6SA-6
0
Bit 4
LQ6SA-5
0
Bit 3
LQ6SA-4
0
Bit 2
LQ6SA-3
0
Bit 1
LQ6SA-2
0
Bit 0
LQ6SA-1
0
10Ah:
Default
Bit 10: LAN Queue 6 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Queue 6 Start Address [10-1] This register specifies the Start Address for the LAN Queue 6. The
value specifies the most significant 10 bits of the SDRAM absolute address.
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.LQ7SA
Register Description:
Register Address:
LAN Queue 7 Start Address
10Ch
Bit 15
-
0
Bit 14
-
0
Bit 13
-
0
Bit 12
-
0
Bit 11
-
0
Bit 10
LQ7QPR
0
Bit 9
LQ7SA-10
0
Bit 8
LQ7SA-9
0
10Dh:
Default
Bit 7
LQ7SA-8
0
Bit 6
LQ7SA-7
0
Bit 5
LQ7SA-6
0
Bit 4
LQ7SA-5
0
Bit 3
LQ7SA-4
0
Bit 2
LQ7SA-3
0
Bit 1
LQ7SA-2
0
Bit 0
LQ7SA-1
0
10Ch:
Default
Bit 10: LAN Queue 7 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Queue 7 Start Address [10-1] This register specifies the Start Address for the LAN Queue 7. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.LQ8SA
Register Description:
Register Address:
LAN Queue 8 Start Address
10Eh
Bit 15
-
0
Bit 14
-
0
Bit 13
-
0
Bit 12
-
0
Bit 11
-
0
Bit 10
LQ8QPR
0
Bit 9
LQ8SA-10
0
Bit 8
LQ8SA-9
0
10Fh:
Default
Bit 7
LQ8SA-8
0
Bit 6
LQ8SA-7
0
Bit 5
LQ8SA-6
0
Bit 4
LQ8SA-5
0
Bit 3
LQ8SA-4
0
Bit 2
LQ8SA-3
0
Bit 1
LQ8SA-2
0
Bit 0
LQ8SA-1
0
10Eh:
Default
Bit 10: LAN Queue 8 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Queue 8 Start Address [10-1]. This register specifies the Start Address for the LAN Queue 8. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.LQ9SA
Register Description:
Register Address:
LAN Queue 9 Start Address
110h
Bit 15
-
0
Bit 14
-
0
Bit 13
-
0
Bit 12
-
0
Bit 11
-
0
Bit 10
LQ9QPR
0
Bit 9
LQ9SA-10
0
Bit 8
LQ9SA-9
0
111h:
Default
Bit 7
Bit 7
0
Bit 6
Bit 6
0
Bit 5
Bit 5
0
Bit 4
Bit 4
0
Bit 3
Bit 3
0
Bit 2
Bit 2
0
Bit 1
Bit 1
0
Bit 0
Bit 0
0
110h:
Default
Bit 10: LAN Queue 9 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Queue 9 Start Address [10-1]. This register specifies the Start Address for the LAN Queue 9. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.LQ10SA
Register Description:
Register Address:
LAN Queue 10 Start Address
112h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
113h:
-
-
-
-
-
LQ10QPR LQ10SA-10 LQ10SA-9
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
112h:
LQ10SA-8 LQ10SA-7 LQ10SA-6 LQ10SA-5 LQ10SA-4 LQ10SA-3 LQ10SA-2 LQ10SA-1
Default
0
0
0
0
0
0
0
0
Bit 10: LAN Queue 10 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Queue 10 Start Address [10-1] This register specifies the Start Address for the LAN Queue 10.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.LQ11SA
Register Description:
Register Address:
LAN Queue 11 Start Address
114h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
115h:
-
-
-
-
-
LQ11QPR LQ11SA-10 LQ11SA-9
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
114h:
LQ11SA-8 LQ11SA-7 LQ11SA-6 LQ11SA-5 LQ11SA-4 LQ11SA-3 LQ11SA-2 LQ11SA-1
Default
0
0
0
0
0
0
0
0
Bit 10: LAN Queue 11 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Queue 11 Start Address [10-1]. This register specifies the Start Address for the LAN Queue 11.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.LQ12SA
Register Description:
Register Address:
LAN Queue 12 Start Address
116h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
117h:
-
-
-
-
-
LQ12QPR LQ12SA-10 LQ12SA-9
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
116h:
LQ12SA-8 LQ12SA-7 LQ12SA-6 LQ12SA-5 LQ12SA-4 LQ12SA-3 LQ12SA-2 LQ12SA-1
Default
0
0
0
0
0
0
0
0
Bit 10: LAN Queue 12 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Queue 12 Start Address [10-1] This register specifies the Start Address for the LAN Queue 12.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.LQ13SA
Register Description:
Register Address:
LAN Queue 13 Start Address
118h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
119h:
-
-
-
-
-
LQ13QPR LQ13SA-10 LQ13SA-9
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
118h:
LQ13SA-8 LQ13SA-7 LQ13SA-6 LQ13SA-5 LQ13SA-4 LQ13SA-3 LQ13SA-2 LQ13SA-1
Default
0
0
0
0
0
0
0
0
Bit 10: LAN Queue 13 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Queue 13 Start Address [10-1] This register specifies the Start Address for the LAN Queue 13.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.LQ14SA
Register Description:
Register Address:
LAN Queue 14 Start Address
11Ah
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
11Bh:
-
-
-
-
-
LQ14QPR LQ14SA-10 LQ14SA-9
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
11Ah:
LQ14SA-8 LQ14SA-7 LQ14SA-6 LQ14SA-5 LQ14SA-4 LQ14SA-3 LQ14SA-2 LQ14SA-1
Default
0
0
0
0
0
0
0
0
Bit 10: LAN Queue 14 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Queue 14 Start Address [10-1] This register specifies the Start Address for the LAN Queue 14.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.LQ15SA
Register Description:
Register Address:
LAN Queue 15 Start Address
11Ch
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
11Dh:
-
-
-
-
-
LQ15QPR LQ15SA-10 LQ15SA-9
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
11Ch:
LQ15SA-8 LQ15SA-7 LQ15SA-6 LQ15SA-5 LQ15SA-4 LQ15SA-3 LQ15SA-2 LQ15SA-1
Default
0
0
0
0
0
0
0
0
Bit 10: LAN Queue 15 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Queue 15 Start Address [10-1]. This register specifies the Start Address for the LAN Queue 15.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.LQ16SA
Register Description:
Register Address:
LAN Queue 16 Start Address
11Eh
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
11Fh:
-
-
-
-
-
LQ16QPR LQ16SA-10 LQ16SA-9
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
11Eh:
LQ16SA-8 LQ16SA-7 LQ16SA-6 LQ16SA-5 LQ16SA-4 LQ16SA-3 LQ16SA-2 LQ16SA-1
Default
0
0
0
0
0
0
0
0
Bit 10: LAN Queue 16 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Queue 16 Start Address [10-1]. This register specifies the Start Address for the LAN Queue 16.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
196 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.LQ1EA
Register Description:
Register Address:
LAN Queue 1 End Address
120h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
LQ1EA-10
0
Bit 8
LQ1EA-9
0
121h:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
LQ1EA-8
0
Bit 6
LQ1EA-7
0
Bit 5
LQ1EA-6
0
Bit 4
LQ1EA-5
0
Bit 3
LQ1EA-4
0
Bit 2
LQ1EA-3
0
Bit 1
LQ1EA-2
0
Bit 0
LQ1EA-1
0
120h:
Default
Bits 0-9: LAN Queue 1 End Address [10-1] This register specifies the End Address for the LAN Queue 1. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.LQ2EA
Register Description:
Register Address:
LAN Queue 2 End Address
122h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
LQ2EA-10
0
Bit 8
LQ2EA-9
0
123h:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
LQ2EA-8
0
Bit 6
LQ2EA-7
0
Bit 5
LQ2EA-6
0
Bit 4
LQ2EA-5
0
Bit 3
LQ2EA-4
0
Bit 2
LQ2EA-3
0
Bit 1
LQ2EA-2
0
Bit 0
LQ2EA-1
0
122h:
Default
Bits 0-9: LAN Queue 2 End Address [10-1] This register specifies the End Address for the LAN Queue 2. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.LQ3EA
Register Description:
Register Address:
LAN Queue 3 End Address
124h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
LQ3EA-10
0
Bit 8
LQ3EA-9
0
125h:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
LQ3EA-8
0
Bit 6
LQ3EA-7
0
Bit 5
LQ3EA-6
0
Bit 4
LQ3EA-5
0
Bit 3
LQ3EA-4
0
Bit 2
LQ3EA-3
0
Bit 1
LQ3EA-2
0
Bit 0
LQ3EA-1
0
124h:
Default
Bits 0-9: LAN Queue 3 End Address [10-1]. This register specifies the End Address for the LAN Queue 3. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.LQ4EA
Register Description:
Register Address:
LAN Queue 4 End Address
126h
Rev: 063008
197 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
LQ4EA-10
0
Bit 8
LQ4EA-9
0
127h:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
LQ4EA-8
0
Bit 6
LQ4EA-7
0
Bit 5
LQ4EA-6
0
Bit 4
LQ4EA-5
0
Bit 3
LQ4EA-4
0
Bit 2
LQ4EA-3
0
Bit 1
LQ4EA-2
0
Bit 0
LQ4EA-1
0
126h:
Default
Bits 0-9: LAN Queue 4 End Address [10-1] This register specifies the End Address for the LAN Queue 4. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.LQ5EA
Register Description:
Register Address:
LAN Queue 5 End Address
128h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
LQ5EA-10
0
Bit 8
LQ5EA-9
0
129h:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
LQ5EA-8
0
Bit 6
LQ5EA-7
0
Bit 5
LQ5EA-6
0
Bit 4
LQ5EA-5
0
Bit 3
LQ5EA-4
0
Bit 2
LQ5EA-3
0
Bit 1
LQ5EA-2
0
Bit 0
LQ5EA-1
0
128h:
Default
Bits 0-9: LAN Queue 5 End Address [10-1] This register specifies the End Address for the LAN Queue 5. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.LQ6EA
Register Description:
Register Address:
LAN Queue 6 End Address
12Ah
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
LQ6EA-10
0
Bit 8
LQ6EA-9
0
12Bh:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
LQ6EA-8
0
Bit 6
LQ6EA-7
0
Bit 5
LQ6EA-6
0
Bit 4
LQ6EA-5
0
Bit 3
LQ6EA-4
0
Bit 2
LQ6EA-3
0
Bit 1
LQ6EA-2
0
Bit 0
LQ6EA-1
0
12Ah:
Default
Bits 0-9: LAN Queue 6 End Address [10-1] This register specifies the End Address for the LAN Queue 6. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Rev: 063008
198 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.LQ7EA
Register Description:
Register Address:
LAN Queue 7 End Address
12Ch
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
LQ7EA-10
0
Bit 8
LQ7EA-9
0
12Dh:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
LQ7EA-8
0
Bit 6
LQ7EA-7
0
Bit 5
LQ7EA-6
0
Bit 4
LQ7EA-5
0
Bit 3
LQ7EA-4
0
Bit 2
LQ7EA-3
0
Bit 1
LQ7EA-2
0
Bit 0
LQ7EA-1
0
12Ch:
Default
Bits 0-9: LAN Queue 7 End Address [10-1] This register specifies the End Address for the LAN Queue 7. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.LQ8EA
Register Description:
Register Address:
LAN Queue 8 End Address
12Eh
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
LQ8EA-10
0
Bit 8
LQ8EA-9
0
12Fh:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
LQ8EA-8
0
Bit 6
LQ8EA-7
0
Bit 5
LQ8EA-6
0
Bit 4
LQ8EA-5
0
Bit 3
LQ8EA-4
0
Bit 2
LQ8EA-3
0
Bit 1
LQ8EA-2
0
Bit 0
LQ8EA-1
0
12Eh:
Default
Bits 0-9: LAN Queue 8 End Address [10-1] This register specifies the End Address for the LAN Queue 8. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.LQ9EA
Register Description:
Register Address:
LAN Queue 9 End Address
130h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
LQ9EA-10
0
Bit 8
LQ9EA-9
0
131h:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
LQ9EA-8
0
Bit 6
LQ9EA-7
0
Bit 5
LQ9EA-6
0
Bit 4
LQ9EA-5
0
Bit 3
LQ9EA-4
0
Bit 2
LQ9EA-3
0
Bit 1
LQ9EA-2
0
Bit 0
LQ9EA-1
0
130h:
Default
Bits 0-9: LAN Queue 9 End Address [10-1] This register specifies the End Address for the LAN Queue 9. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Rev: 063008
199 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.LQ10EA
Register Description:
Register Address:
LAN Queue 10 End Address
132h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
133h:
-
-
-
-
-
-
LQ10EA-10 LQ10EA-9
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
132h:
LQ10EA-8 LQ10EA-7 LQ10EA-6 LQ10EA-5 LQ10EA-4 LQ10EA-3 LQ10EA-2 LQ10EA-1
Default
0
0
0
0
0
0
0
0
Bits 0-9: LAN Queue 10 End Address [10-1]. This register specifies the End Address for the LAN Queue 10. The
value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.LQ11EA
Register Description:
Register Address:
LAN Queue 11 End Address
134h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
135h:
-
-
-
-
-
-
LQ11EA-10 LQ11EA-9
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
134h:
LQ11EA-8 LQ11EA-7 LQ11EA-6 LQ11EA-5 LQ11EA-4 LQ11EA-3 LQ11EA-2 LQ11EA-1
Default
0
0
0
0
0
0
0
0
Bits 0-9: LAN Queue 11 End Address [10-1] This register specifies the End Address for the LAN Queue 11. The
value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.LQ12EA
Register Description:
Register Address:
LAN Queue 12 End Address
136h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
137h:
-
-
-
-
-
-
LQ12EA-10 LQ12EA-9
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
136h:
LQ12EA-8 LQ12EA-7 LQ12EA-6 LQ12EA-5 LQ12EA-4 LQ12EA-3 LQ12EA-2 LQ12EA-1
Default
0
0
0
0
0
0
0
0
Bits 0-9: LAN Queue 12 End Address [10-1] This register specifies the End Address for the LAN Queue 12. The
value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
200 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.LQ13EA
Register Description:
Register Address:
LAN Queue 13 End Address
138h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
139h:
-
-
-
-
-
-
LQ13EA-10 LQ13EA-9
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
138h:
LQ13EA-8 LQ13EA-7 LQ13EA-6 LQ13EA-5 LQ13EA-4 LQ13EA-3 LQ13EA-2 LQ13EA-1
Default
0
0
0
0
0
0
0
0
Bits 0-9: LAN Queue 13 End Address [10-1] This register specifies the End Address for the LAN Queue 13. The
value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.LQ14EA
Register Description:
Register Address:
LAN Queue 14 End Address
13Ah
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
13Bh:
-
-
-
-
-
-
LQ14EA-10 LQ14EA-9
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
13Ah:
LQ14EA-8 LQ14EA-7 LQ14EA-6 LQ14EA-5 LQ14EA-4 LQ14EA-3 LQ14EA-2 LQ14EA-1
Default
0
0
0
0
0
0
0
0
Bits 0-9: LAN Queue 14 End Address [10-1] This register specifies the End Address for the LAN Queue 14. The
value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.LQ15EA
Register Description:
Register Address:
LAN Queue 15 End Address
13Ch
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
13Dh:
-
-
-
-
-
-
LQ15EA-10 LQ15EA-9
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
13Ch:
LQ15EA-8 LQ15EA-7 LQ15EA-6 LQ15EA-5 LQ15EA-4 LQ15EA-3 LQ15EA-2 LQ15EA-1
Default
0
0
0
0
0
0
0
0
Bits 0-9: LAN Queue 15 End Address [10-1] This register specifies the End Address for the LAN Queue 15. The
value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
201 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.LQ16EA
Register Description:
Register Address:
LAN Queue 16 End Address
13Eh
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
13Fh:
-
-
-
-
-
-
LQ16EA-10 LQ16EA-9
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
13Eh:
LQ16EA-8 LQ16EA-7 LQ16EA-6 LQ16EA-5 LQ16EA-4 LQ16EA-3 LQ16EA-2 LQ16EA-1
Default
0
0
0
0
0
0
0
0
Bits 0-9: LAN Queue 16 End Address [10-1]. This register specifies the End Address for the LAN Queue 16. The
value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.WQ1SA
Register Description:
Register Address:
WAN Queue 1 Start Address
140h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
WQ1QPR
0
Bit 9
WQ1SA-10
0
Bit 8
WQ1SA-9
0
141h:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
140h:
WQ1SA-8 WQ1SA-7 WQ1SA-6 WQ1SA-5 WQ1SA-4 WQ1SA-3 WQ1SA-2 WQ1SA-1
Default
0
0
0
0
0
0
0
0
Bit 10: WAN Queue 1 Queue Pointer Reset
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Queue 1 Start Address [10-1] This register specifies the Start Address for the WAN Queue 1.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
202 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WQ2SA
Register Description:
Register Address:
WAN Queue 2 Start Address
142h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
WQ2QPR
0
Bit 9
WQ2SA-10
0
Bit 8
WQ2SA-9
0
143h:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
142h:
WQ2SA-8 WQ2SA-7 WQ2SA-6 WQ2SA-5 WQ2SA-4 WQ2SA-3 WQ2SA-2 WQ2SA-1
Default
0
0
0
0
0
0
0
0
Bit 10: WAN Queue 2 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Queue 2 Start Address [10-1] This register specifies the Start Address for the WAN Queue 2.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.WQ3SA
Register Description:
Register Address:
WAN Queue 3 Start Address
144h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
WQ3QPR
0
Bit 9
WQ3SA-10
0
Bit 8
WQ3SA-9
0
145h:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
144h:
WQ3SA-8 WQ3SA-7 WQ3SA-6 WQ3SA-5 WQ3SA-4 WQ3SA-3 WQ3SA-2 WQ3SA-1
Default
0
0
0
0
0
0
0
0
Bit 10: WAN Queue 3 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Queue 3 Start Address [10-1]. This register specifies the Start Address for the WAN Queue 3.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
203 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WQ4SA
Register Description:
Register Address:
WAN Queue 4 Start Address
146h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
WQ4QPR
0
Bit 9
WQ4SA-10
0
Bit 8
WQ4SA-9
0
147h:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
146h:
WQ4SA-8 WQ4SA-7 WQ4SA-6 WQ4SA-5 WQ4SA-4 WQ4SA-3 WQ4SA-2 WQ4SA-1
Default
0
0
0
0
0
0
0
0
Bit 10: WAN Queue 4 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Queue 4 Start Address [10-1] This register specifies the Start Address for the WAN Queue 4.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.WQ5SA
Register Description:
Register Address:
WAN Queue 5 Start Address
148h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
WQ5QPR
0
Bit 9
WQ5SA-10
0
Bit 8
WQ5SA-9
0
149h:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
148h:
WQ5SA-8 WQ5SA-7 WQ5SA-6 WQ5SA-5 WQ5SA-4 WQ5SA-3 WQ5SA-2 WQ5SA-1
Default
0
0
0
0
0
0
0
0
Bit 10: WAN Queue 5 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Queue 5 Start Address [10-1] This register specifies the Start Address for the WAN Queue 5.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
204 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WQ6SA
Register Description:
Register Address:
WAN Queue 6 Start Address
14Ah
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
WQ6QPR
0
Bit 9
WQ6SA-10
0
Bit 8
WQ6SA-9
0
14Bh:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
14Ah:
WQ6SA-8 WQ6SA-7 WQ6SA-6 WQ6SA-5 WQ6SA-4 WQ6SA-3 WQ6SA-2 WQ6SA-1
Default
0
0
0
0
0
0
0
0
Bit 10: WAN Queue 6 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Queue 6 Start Address [10-1] This register specifies the Start Address for the WAN Queue 6.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.WQ7SA
Register Description:
Register Address:
WAN Queue 7 Start Address
14Ch
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
WQ7QPR
0
Bit 9
WQ7SA-10
0
Bit 8
WQ7SA-9
0
14Dh:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
14Ch:
WQ7SA-8 WQ7SA-7 WQ7SA-6 WQ7SA-5 WQ7SA-4 WQ7SA-3 WQ7SA-2 WQ7SA-1
Default
0
0
0
0
0
0
0
0
Bit 10: WAN Queue 7 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Queue 7 Start Address [10-1] This register specifies the Start Address for the WAN Queue 7.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
205 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WQ8SA
Register Description:
Register Address:
WAN Queue 8 Start Address
14Eh
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
WQ8QPR
0
Bit 9
WQ8SA-10
0
Bit 8
WQ8SA-9
0
14Fh:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
14Eh:
WQ8SA-8 WQ8SA-7 WQ8SA-6 WQ8SA-5 WQ8SA-4 WQ8SA-3 WQ8SA-2 WQ8SA-1
Default
0
0
0
0
0
0
0
0
Bit 10: WAN Queue 8 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Queue 8 Start Address [10-1]. This register specifies the Start Address for the WAN Queue 8.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.WQ9SA
Register Description:
Register Address:
WAN Queue 9 Start Address
150h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
WQ9QPR
0
Bit 9
WQ9SA-10
0
Bit 8
WQ9SA-9
0
151h:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
150h:
WQ9SA-8 WQ9SA-7 WQ9SA-6 WQ9SA-5 WQ9SA-4 WQ9SA-3 WQ9SA-2 WQ9SA-1
Default
0
0
0
0
0
0
0
0
Bit 10: WAN Queue 9 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Queue 9 Start Address [10-1] This register specifies the Start Address for the WAN Queue 9.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
206 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WQ10SA
Register Description:
Register Address:
WAN Queue 10 Start Address
152h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
WQ10QPR
0
Bit 9
WQ10SA-10
0
Bit 8
WQ10SA-9
0
-
0
-
0
-
0
-
0
-
0
153h:
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WQ10SA-8 WQ10SA-7 WQ10SA-6 WQ10SA-5 WQ10SA-4 WQ10SA-3 WQ10SA-2 WQ10SA-1
152h:
Default
0
0
0
0
0
0
0
0
Bit 10: WAN Queue 10 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Queue 10 Start Address [10-1]. This register specifies the Start Address for the WAN Queue 10.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.WQ11SA
Register Description:
Register Address:
WAN Queue 1 1Start Address
154h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
WQ11QPR
0
Bit 9
WQ11SA-10
0
Bit 8
WQ11SA-9
0
-
0
-
0
-
0
-
0
-
0
155h:
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WQ11SA-8 WQ11SA-7 WQ11SA-6 WQ11SA-5 WQ11SA-4 WQ11SA-3 WQ11SA-2 WQ11SA-1
154h:
Default
0
0
0
0
0
0
0
0
Bit 10: WAN Queue 11 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Queue 11 Start Address [10-1] This register specifies the Start Address for the WAN Queue 11.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
207 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WQ12SA
Register Description:
Register Address:
WAN Queue 12 Start Address
156h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
WQ12QPR
0
Bit 9
WQ12SA-10
0
Bit 8
WQ12SA-9
0
-
0
-
0
-
0
-
0
-
0
157h:
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WQ12SA-8 WQ12SA-7 WQ12SA-6 WQ12SA-5 WQ12SA-4 WQ12SA-3 WQ12SA-2 WQ12SA-1
156h:
Default
0
0
0
0
0
0
0
0
Bit 10: WAN Queue 12 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Queue 12 Start Address [10-1]. This register specifies the Start Address for the WAN Queue 12.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.WQ13SA
Register Description:
Register Address:
WAN Queue 13 Start Address
158h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
WQ13QPR
0
Bit 9
WQ13SA-10
0
Bit 8
WQ13SA-9
0
-
0
-
0
-
0
-
0
-
0
159h:
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WQ13SA-8 WQ13SA-7 WQ13SA-6 WQ13SA-5 WQ13SA-4 WQ13SA-3 WQ13SA-2 WQ13SA-1
158h:
Default
0
0
0
0
0
0
0
0
Bit 10: WAN Queue 13 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Queue 13 Start Address [10-1] This register specifies the Start Address for the WAN Queue 13.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
208 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WQ14SA
Register Description:
Register Address:
WAN Queue 14 Start Address
15Ah
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
WQ14QPR
0
Bit 9
WQ14SA-10
0
Bit 8
WQ14SA-9
0
-
0
-
0
-
0
-
0
-
0
15Bh:
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WQ14SA-8 WQ14SA-7 WQ14SA-6 WQ14SA-5 WQ14SA-4 WQ14SA-3 WQ14SA-2 WQ14SA-1
15Ah:
Default
0
0
0
0
0
0
0
0
Bit 10: WAN Queue 14 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Queue 14 Start Address [10-1] This register specifies the Start Address for the WAN Queue 14.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.WQ15SA
Register Description:
Register Address:
WAN Queue 15 Start Address
15Ch
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
WQ15QPR
0
Bit 9
WQ15SA-10
0
Bit 8
WQ15SA-9
0
-
0
-
0
-
0
-
0
-
0
15Dh:
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WQ15SA-8 WQ15SA-7 WQ15SA-6 WQ15SA-5 WQ15SA-4 WQ15SA-3 WQ15SA-2 WQ15SA-1
15Ch:
Default
0
0
0
0
0
0
0
0
Bit 10: WAN Queue 15 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Queue 15 Start Address [10-1] This register specifies the Start Address for the WAN Queue 15.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
209 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WQ16SA
Register Description:
Register Address:
WAN Queue 16 Start Address
15Eh
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
WQ16QPR
0
Bit 9
WQ16SA-10
0
Bit 8
WQ16SA-9
0
-
0
-
0
-
0
-
0
-
0
15Fh:
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WQ16SA-8 WQ16SA-7 WQ16SA-6 WQ16SA-5 WQ16SA-4 WQ16SA-3 WQ16SA-2 WQ16SA-1
15Eh:
Default
0
0
0
0
0
0
0
0
Bit 10: WAN Queue 16 Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Queue 16 Start Address [10-1] This register specifies the Start Address for the WAN Queue 16.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.WQ1EA
Register Description:
Register Address:
WAN Queue 1 End Address
160h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
Bit 10
Bit 9
WQ1EA-10
0
Bit 8
WQ1EA-9
0
161h:
Default
-
0
-
0
-
0
-
0
-
0
Bit 7
WQ1EA-8
0
Bit 6
WQ1EA-7
0
Bit 5
WQ1EA-6
0
Bit 4
WQ1EA-5
0
Bit 3
WQ1EA-4
0
Bit 2
WQ1EA-3
0
Bit 1
WQ1EA-2
0
Bit 0
WQ1EA-1
0
160h:
Default
Bits 0-9: WAN Queue 1 End Address [10-1] This register specifies the End Address for the WAN Queue 1. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.WQ2EA
Register Description:
Register Address:
WAN Queue 2 End Address
162h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
WQ2EA-10
0
Bit 8
WQ2EA-9
0
-
0
-
0
-
0
-
0
-
0
163h:
Default
Bit 7
WQ2EA-8
0
Bit 6
WQ2EA-7
0
Bit 5
WQ2EA-6
Bit 4
WQ2EA-5
Bit 3
WQ2EA-4
Bit 2
WQ2EA-3
Bit 1
WQ2EA-2
0
Bit 0
WQ2EA-1
0
162h:
Default
0
0
0
0
Bits 0-9: WAN Queue 2 End Address [10-1] This register specifies the End Address for the WAN Queue 2. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Rev: 063008
210 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WQ3EA
Register Description:
Register Address:
WAN Queue 3 End Address
164h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
WQ3EA-10
0
Bit 8
WQ3EA-9
0
-
0
-
0
-
0
-
0
-
0
165h:
Default
Bit 7
WQ3EA-8
0
Bit 6
WQ3EA-7
0
Bit 5
WQ3EA-6
Bit 4
WQ3EA-5
Bit 3
WQ3EA-4
Bit 2
WQ3EA-3
Bit 1
WQ3EA-2
0
Bit 0
WQ3EA-1
0
164h:
Default
0
0
0
0
Bits 0-9: WAN Queue 3 End Address [10-1] This register specifies the End Address for the WAN Queue 3. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.WQ4EA
Register Description:
Register Address:
WAN Queue 4 End Address
166h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
WQ4EA-10
0
Bit 8
WQ4EA-9
0
-
0
-
0
-
0
-
0
-
0
167h:
Default
Bit 7
WQ4EA-8
0
Bit 6
WQ4EA-7
0
Bit 5
WQ4EA-6
Bit 4
WQ4EA-5
Bit 3
WQ4EA-4
Bit 2
WQ4EA-3
Bit 1
WQ4EA-2
0
Bit 0
WQ4EA-1
0
166h:
Default
0
0
0
0
Bits 0-9: WAN Queue 4 End Address [10-1] This register specifies the End Address for the WAN Queue 4. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.WQ5EA
Register Description:
Register Address:
WAN Queue 5 End Address
168h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
WQ5EA-10
0
Bit 8
WQ5EA-9
0
-
0
-
0
-
0
-
0
-
0
169h:
Default
Bit 7
WQ5EA-8
0
Bit 6
WQ5EA-7
0
Bit 5
WQ5EA-6
Bit 4
WQ5EA-5
Bit 3
WQ5EA-4
Bit 2
WQ5EA-3
Bit 1
WQ5EA-2
0
Bit 0
WQ5EA-1
0
168h:
Default
0
0
0
0
Bits 0-9: WAN Queue 5 End Address [10-1] This register specifies the End Address for the WAN Queue 5. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Rev: 063008
211 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WQ6EA
Register Description:
Register Address:
WAN Queue 6 End Address
16Ah
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
WQ6EA-10
0
Bit 8
WQ6EA-9
0
-
0
-
0
-
0
-
0
-
0
16Bh:
Default
Bit 7
WQ6EA-8
0
Bit 6
WQ6EA-7
0
Bit 5
WQ6EA-6
Bit 4
WQ6EA-5
Bit 3
WQ6EA-4
Bit 2
WQ6EA-3
Bit 1
WQ6EA-2
0
Bit 0
WQ6EA-1
0
16Ah:
Default
0
0
0
0
Bits 0-9: WAN Queue 6 End Address [10-1] This register specifies the End Address for the WAN Queue 6. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.WQ7EA
Register Description:
Register Address:
WAN Queue 7 End Address
16Ch
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
WQ7EA-10
0
Bit 8
WQ7EA-9
0
-
0
-
0
-
0
-
0
-
0
16Dh:
Default
Bit 7
WQ7EA-8
0
Bit 6
WQ7EA-7
0
Bit 5
WQ7EA-6
Bit 4
WQ7EA-5
Bit 3
WQ7EA-4
Bit 2
WQ7EA-3
Bit 1
WQ7EA-2
0
Bit 0
WQ7EA-1
0
16Ch:
Default
0
0
0
0
Bits 0-9: WAN Queue 7 End Address [10-1] This register specifies the End Address for the WAN Queue 7. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.WQ8EA
Register Description:
Register Address:
WAN Queue 8 End Address
16Eh
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
WQ8EA-10
0
Bit 8
WQ8EA-9
0
-
0
-
0
-
0
-
0
-
0
16Fh:
Default
Bit 7
WQ8EA-8
0
Bit 6
WQ8EA-7
0
Bit 5
WQ8EA-6
Bit 4
WQ8EA-5
Bit 3
WQ8EA-4
Bit 2
WQ8EA-3
Bit 1
WQ8EA-2
0
Bit 0
WQ8EA-1
0
16Eh:
Default
0
0
0
0
Bits 0-9: WAN Queue 8 End Address [10-1] This register specifies the End Address for the WAN Queue 8. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Rev: 063008
212 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WQ9EA
Register Description:
Register Address:
WAN Queue 9 End Address
170h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
WQ9EA-10
0
Bit 8
WQ9EA-9
0
-
0
-
0
-
0
-
0
-
0
171h:
Default
Bit 7
WQ9EA-8
0
Bit 6
WQ9EA-7
0
Bit 5
WQ9EA-6
Bit 4
WQ9EA-5
Bit 3
WQ9EA-4
Bit 2
WQ9EA-3
Bit 1
WQ9EA-2
0
Bit 0
WQ9EA-1
0
170h:
Default
0
0
0
0
Bits 0-9: WAN Queue 9 End Address [10-1] This register specifies the End Address for the WAN Queue 9. The
value specifies the most significant 10 bits of the SDRAM absolute address.
Register Name:
AR.WQ10EA
Register Description:
Register Address:
WAN Queue 10 End Address
172h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
WQ10EA-10
0
Bit 8
WQ10EA-9
0
-
0
-
0
-
0
-
0
-
0
173h:
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WQ10EA-8 WQ10EA-7 WQ10EA-6 WQ10EA-5 WQ10EA-4 WQ10EA-3 WQ10EA-2 WQ10EA-1
172h:
Default
0
0
0
0
0
0
0
0
Bits 0-9: WAN Queue 10 End Address [10-1] This register specifies the End Address for the WAN Queue 10.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.WQ11EA
Register Description:
Register Address:
WAN Queue 11 End Address
174h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
WQ11EA-10
0
Bit 8
WQ11EA-9
0
-
0
-
0
-
0
-
0
-
0
175h:
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WQ11EA-8 WQ11EA-7 WQ11EA-6 WQ11EA-5 WQ11EA-4 WQ11EA-3 WQ11EA-2 WQ11EA-1
174h:
Default
0
0
0
0
0
0
0
0
Bits 0-9: WAN Queue 11 End Address [10-1] This register specifies the End Address for the WAN Queue 11.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
213 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WQ12EA
Register Description:
Register Address:
WAN Queue 12 End Address
176h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
WQ12EA-10
0
Bit 8
WQ12EA-9
0
-
0
-
0
-
0
-
0
-
0
177h:
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WQ12EA-8 WQ12EA-7 WQ12EA-6 WQ12EA-5 WQ12EA-4 WQ12EA-3 WQ12EA-2 WQ12EA-1
176h:
Default
0
0
0
0
0
0
0
0
Bits 0-9: WAN Queue 12 End Address [10-1]. This register specifies the End Address for the WAN Queue 12.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.WQ13EA
Register Description:
Register Address:
WAN Queue 13 End Address
178h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
WQ13EA-10
0
Bit 8
WQ13EA-9
0
-
0
-
0
-
0
-
0
-
0
179h:
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WQ13EA-8 WQ13EA-7 WQ13EA-6 WQ13EA-5 WQ13EA-4 WQ13EA-3 WQ13EA-2 WQ13EA-1
178h:
Default
0
0
0
0
0
0
0
0
Bits 0-9: WAN Queue 13 End Address [10-1] This register specifies the End Address for the WAN Queue 13.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.WQ14EA
Register Description:
Register Address:
WAN Queue 14 End Address
17Ah
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
WQ14EA-10
0
Bit 8
WQ14EA-9
0
-
0
-
0
-
0
-
0
-
0
17Bh:
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WQ14EA-8 WQ14EA-7 WQ14EA-6 WQ14EA-5 WQ14EA-4 WQ14EA-3 WQ14EA-2 WQ14EA-1
17Ah:
Default
0
0
0
0
0
0
0
0
Bits 0-9: WAN Queue 14 End Address [10-1] This register specifies the End Address for the WAN Queue 14.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
214 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WQ15EA
Register Description:
Register Address:
WAN Queue 15 End Address
17Ch
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
WQ15EA-10
0
Bit 8
WQ15EA-9
0
-
0
-
0
-
0
-
0
-
0
17Dh:
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WQ15EA-8 WQ15EA-7 WQ15EA-6 WQ15EA-5 WQ15EA-4 WQ15EA-3 WQ15EA-2 WQ15EA-1
17Ch:
Default
0
0
0
0
0
0
0
0
Bits 0-9: WAN Queue 15 End Address [10-1] This register specifies the End Address for the WAN Queue 15.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Register Name:
AR.WQ16EA
Register Description:
Register Address:
WAN Queue 16 End Address
17Eh
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
-
0
Bit 9
WQ16EA-10
0
Bit 8
WQ16EA-9
0
-
0
-
0
-
0
-
0
-
0
17Fh:
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WQ16EA-8 WQ16EA-7 WQ16EA-6 WQ16EA-5 WQ16EA-4 WQ16EA-3 WQ16EA-2 WQ16EA-1
17Eh:
Default
0
0
0
0
0
0
0
0
Bits 0-9: WAN Queue 16 End Address [10-1] This register specifies the End Address for the WAN Queue 16.
The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity of 32,768
bytes per LSB.
Rev: 063008
215 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.LIQSA
Register Description:
Register Address:
LAN Insert Queue Start Address
180h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
Bit 10
LIQPR
0
Bit 9
LIQSA-10
0
Bit 8
LIQSA-9
0
-
0
-
0
-
0
-
0
181h:
Default
Bit 7
LIQSA-8
0
Bit 6
LIQSA-7
0
Bit 5
LIQSA-6
0
Bit 4
LIQSA-5
0
Bit 3
LIQSA-4
0
Bit 2
LIQSA-3
0
Bit 1
LIQSA-2
0
Bit 0
LIQSA-1
0
180h:
Default
Bit 10: LAN Insert Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Insert Queue Start Address [10-1] This register specifies the Start Address for the LAN Insert
Queue. The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity
of 32,768 bytes per LSB.
Register Name:
AR.LIQEA
Register Description:
Register Address:
LAN Insert Queue End Address
182h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
LIQEA-10
0
Bit 8
LIQEA-9
0
-
0
-
0
-
0
-
0
-
0
-
0
183h:
Default
Bit 7
LIQEA-8
0
Bit 6
LIQEA-7
0
Bit 5
LIQEA-6
0
Bit 4
LIQEA-5
0
Bit 3
LIQEA-4
0
Bit 2
LIQEA-3
0
Bit 1
LIQEA-2
0
Bit 0
LIQEA-1
0
182h:
Default
Bits 0-9: LAN Insert Queue End Address [10-1] This register specifies the End Address for the LAN Insert
Queue. The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity
of 32,768 bytes per LSB.
Rev: 063008
216 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.LEQSA
Register Description:
Register Address:
LAN Extract Queue Start Address
184h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
Bit 10
LEQPR
0
Bit 9
LEQSA-10
0
Bit 8
LEQSA-9
0
-
0
-
0
-
0
-
0
185h:
Default
Bit 7
LEQSA-8
0
Bit 6
LEQSA-7
0
Bit 5
LEQSA-6
0
Bit 4
LEQSA-5
0
Bit 3
LEQSA-4
0
Bit 2
LEQSA-3
0
Bit 1
LEQSA-2
0
Bit 0
LEQSA-1
0
184h:
Default
Bit 10: LAN Extract Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: LAN Extract Queue Start Address [10-1] This register specifies the Start Address for the LAN Extract
Queue. The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity
of 32,768 bytes per LSB.
Register Name:
AR.LEQEA
Register Description:
Register Address:
LAN Extract Queue End Address
186h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
LEQEA-10
0
Bit 8
LEQEA-9
0
-
0
-
0
-
0
-
0
-
0
-
0
187h:
Default
Bit 7
LEQEA-8
0
Bit 6
LEQEA-7
0
Bit 5
LEQEA-6
0
Bit 4
LEQEA-5
0
Bit 3
LEQEA-4
0
Bit 2
LEQEA-3
0
Bit 1
LEQEA-2
0
Bit 0
LEQEA-1
0
186h:
Default
Bits 0-9: LAN Extract Queue End Address [10-1]. This register specifies the End Address for the LAN Extract
Queue. The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity
of 32,768 bytes per LSB.
Rev: 063008
217 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WIQSA
Register Description:
Register Address:
WAN Insert Queue Start Address
188h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
Bit 10
WIQPR
0
Bit 9
WIQSA-10
0
Bit 8
WIQSA-9
0
-
0
-
0
-
0
-
0
189h:
Default
Bit 7
WIQSA-8
0
Bit 6
WIQSA-7
0
Bit 5
WIQSA-6
0
Bit 4
WIQSA-5
0
Bit 3
WIQSA-4
0
Bit 2
WIQSA-3
0
Bit 1
WIQSA-2
0
Bit 0
WIQSA-1
0
188h:
Default
Bit 10: WAN Insert Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 0-9: WAN Insert Queue Start Address [10-1] This register specifies the Start Address for the WAN Insert
Queue. The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity
of 32,768 bytes per LSB.
Register Name:
AR.WIQEA
Register Description:
Register Address:
WAN Insert Queue End Address
18Ah
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
WIQEA-10
0
Bit 8
WIQEA-9
0
-
0
-
0
-
0
-
0
-
0
-
0
18Bh:
Default
Bit 7
WIQEA-8
0
Bit 6
WIQEA-7
0
Bit 5
WIQEA-6
0
Bit 4
WIQEA-5
0
Bit 3
WIQEA-4
0
Bit 2
WIQEA-3
0
Bit 1
WIQEA-2
0
Bit 0
WIQEA-1
0
18Ah:
Default
Bits 0-9: WAN Insert Queue End Address [10-1] This register specifies the End Address for the WAN Insert
Queue. The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity
of 32,768 bytes per LSB.
Rev: 063008
218 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WEQSA
Register Description:
Register Address:
WAN Extract Queue Start Address
18Ch
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
Bit 10
WEQPR
0
Bit 9
WEQSA-10
0
Bit 8
WEQSA-9
0
-
0
-
0
-
0
-
0
18Dh:
Default
Bit 7
WEQSA-8
0
Bit 6
WEQSA-7
0
Bit 5
WEQSA-6
0
Bit 4
WEQSA-5
0
Bit 3
WEQSA-4
0
Bit 2
WEQSA-3
0
Bit 1
WEQSA-2
0
Bit 0
WEQSA-1
0
18Ch:
Default
Bit 10: WAN Extract Queue Pointer Reset.
0 = No reset of the Queue Pointers (the user may be re-configuring to the same value)
1 = Momentary Reset of Queue Pointers (user is not required to change value to “0” to conclude reset)
Bits 9-0: WAN Extract Queue Start Address [10-1] This register specifies the Start Address for the WAN Extract
Queue. The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity
of 32,768 bytes per LSB.
Register Name:
AR.WEQEA
Register Description:
Register Address:
WAN Extract Queue End Address
18Eh
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
WEQEA-10
0
Bit 8
WEQEA-9
0
-
0
-
0
-
0
-
0
-
0
-
0
18Fh:
Default
Bit 7
WEQEA-8
0
Bit 6
WEQEA-7
0
Bit 5
WEQEA-6
0
Bit 4
WEQEA-5
0
Bit 3
WEQEA-4
0
Bit 2
WEQEA-3
0
Bit 1
WEQEA-2
0
Bit 0
WEQEA-1
0
18Eh:
Default
Bits 0-9: WAN Extract Queue End Address [10-1] This register specifies the End Address for the WAN Extract
Queue. The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a granularity
of 32,768 bytes per LSB.
Rev: 063008
219 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.LQW
Register Description:
Register Address:
LAN Queue Watermark
190h
Bit 15
Bit 14
Bit 13
Bit 12
LQW-13
0
Bit 11
LQW-12
0
Bit 10
LQW-11
0
Bit 9
LQW-10
0
Bit 8
LQW-9
0
-
0
-
0
-
0
191h:
Default
Bit 7
LQW-8
0
Bit 6
LQW-7
0
Bit 5
LQW-6
0
Bit 4
LQW-5
0
Bit 3
LQW-4
0
Bit 2
LQW-3
0
Bit 1
LQW-2
0
Bit 0
LQW-1
0
190h:
Default
Bits 0-12: LAN Queue Watermark [LQW 13-1] This register specifies the Watermark Threshold that is used to
trigger a LAN Pause control frame. One value is used for all 16 queues (each queue is independently enabled and
tested). The value from this register is multiplied by 64 to determine the minimum number of bytes available in each
DDR SDRAM LAN Queue after Flow Control (or LAN Queue Watermark Interrupt) is triggered. The maximum valid
value is decimal 8191, which designates that a minimum of 8191 x 64 bytes = 524,224 bytes can be stored after
the watermark is reached. The lowest valid setting is decimal 3, or a minimum of 192 bytes available when flow
control is triggered.
The purpose of the LQW setting is to prevent data loss due to queue overflow. The LQW setting is independent of
the CIR Policing function that monitors the rate at which data is received irrespective of the fill level of the queue.
For applications with maximum packet Length < 2049 and with a short Ethernet PHY transmission distance (< 25
meters) it is recommended that the LQW be set to a minimum value of 57.
For applications that include a long Ethernet PHY transmission distance the LQW setting can be increased. For
GbE applications the LQW value can be increased by 1 for each additional 88 meters (up to LQW = 8191 or
715km). For 100Mbps each incremental step will support 880 meters (at 100Mbps there is less/slower data on the
transmission line). For 10Mbps each incremental step will support 8,800 meters. It is recommended that the user
verify the LQW setting in long Ethernet transmission line applications.
Rev: 063008
220 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.MQC
Register Description:
Register Address:
Miscellaneous Queue Control
192h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
Bit 10
Bit 9
FPEPD
0
Bit 8
WQODE
0
-
0
-
0
-
0
-
0
-
0
193h:
Default
Bit 7
WIRRW2
0
Bit 6
WIRRW1
0
Bit 5
WIENC2
Bit 4
WIENC1
Bit 3
WISPL
Bit 2
WIENA
Bit 1
WQPD
Bit 0
ASQPR
192h:
Default
0
0
0
0
0
0
Bit 9: Fractional Packet Error Purge Disable (FPEPD)
0 = Fractional Frame Error Purge Enabled.
1 = Fractional Frame Error Purge Disabled.
Bit 8: WAN Queue Overflow Discard Enable (WQODE) Setting used for all 16 WAN Queues.
0 = Overflow Discard Enabled.
1 = Overflow Discard Disabled.
This setting is used for all 16 WAN Queues. When WQODE = 0 and an overflow condition occurs on a WAN
queue, that entire queue is discarded. This bit setting is independent of the Preemptive Discard (WQPD).
Bits 6-7: WAN Insert Round Robin Weight (WIRRW[2:1])
00: Round Robin Weight = 1.
01: Round Robin Weight = 2.
10: Round Robin Weight = 4.
11: Round Robin Weight = 8.
Only valid in Forwarding Mode 2, when LQSM = 1 (Weighted Round Robin Scheduling).
Bits 4-5: WAN Insert Encapsulator (WIENC[2:1])
00 = multiplexed with data from Encapsulator #1 (WAN Group1).
01 = multiplexed with data from Encapsulator #2 (WAN Group 2).
10 = multiplexed with data from Encapsulator #3 (WAN Group 3).
11 = multiplexed with data from Encapsulator #4 (WAN Group 4).
Bit 3: WAN Insert Strict Priority Level (WISPL])
For LQSM = 0 (Strict Priority Scheduling; the LQSM bit is defined in the LQSC register below)
0: WAN Insert using priority level 1.5; Inserted frames scheduled ahead of levels 2, 3, 4.
1: WAN Insert using priority level 3.5; Inserted frames scheduled ahead of level 4.
Note: Only valid when using Strict Priority Scheduling (LQSM = 0).
Bit 2: WAN Insert Enable (WIENA).
0 = WAN Insertion is disabled.
1 = WAN Insertion is enabled.
Bit 1: WAN Queue Preemptive Discard (WQPD).
0 = Disabled.
1 = Enabled. Frames are discarded when the WAN queue high threshold is exceeded.
Bit 0: All SDRAM Queue Pointer Reset. (ASQPR)
0 = Normal operation.
1 = Momentary Reset of all WAN, LAN, Insert and Extract Queue Pointers.
Rev: 063008
221 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.LQSC
Register Description:
Register Address:
LAN Queue Scheduling Control
194h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
-
0
Bit 10
-
0
Bit 9
-
0
Bit 8
LQSM
0
-
0
-
0
-
0
195h:
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LQ4RRW-2 LQ4RRW-1 LQ3RRW-2 LQ3RRW -1 LQ2RRW-2 LQ2RRW-1 LQ1RRW-2 LQ1RRW-1
194h:
Default
0
0
0
0
0
0
0
0
Bit 8: LAN Queue Scheduling Mode (LQSM)
0 = Strict Priority scheduling between LAN Queues within the same LAN Queue Group (enabled for all 4
LAN Queue Groups) and the WAN Insert Channel
1 = Weighted Round Robin (WRR) Scheduling between LAN Queues within LAN Queue Group #1
and with the WAN Insert Channel. When LQSM = 1, the other 3 LAN Queue Groups (12 LAN Queues)
are not allowed. WRR Scheduling mode is only available in Forwarding Mode 2, with a single LAN
Port enabled.
Bit 6-7: LAN Queue 4 Round Robin Weighting (LQ4RRW [2:1])
00: Round Robin Weight = 1
01: Round Robin Weight = 2
10: Round Robin Weight = 4
11: Round Robin Weight = 8
Bit 4-5: LAN Queue 3 Round Robin Weighting (LQ3RRW [2:1])
00: Round Robin Weight = 1
01: Round Robin Weight = 2
10: Round Robin Weight = 4
11: Round Robin Weight = 8
Bit 2-3: LAN Queue 2 Round Robin Weighting (LQ2RRW [2:1])
00: Round Robin Weight = 1
01: Round Robin Weight = 2
10: Round Robin Weight = 4
11: Round Robin Weight = 8
Bit 0-1: LAN Queue 1 Round Robin Weighting (LQ1RRW [2:1])
00: Round Robin Weight = 1
01: Round Robin Weight = 2
10: Round Robin Weight = 4
11: Round Robin Weight = 8
Rev: 063008
222 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.BFTOA
Register Description:
Register Address:
Bridge Filter Table Offset Address
196h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
-
0
Bit 10
-
0
Bit 9
BFTOA-10
0
Bit 8
BFTOA-9
0
-
0
-
0
-
0
197h:
Default
Bit 7
BFTOA-8
0
Bit 6
BFTOA-7
0
Bit 5
BFTOA-6
0
Bit 4
BFTOA-5
0
Bit 3
BFTOA-4
0
Bit 2
BFTOA-3
0
Bit 1
BFTOA-2
0
Bit 0
BFTOA-1
0
196h:
Default
Bits 0-9: Bridge Filter Table Offset Address (BFTOA[10-1]) This register specifies the Offset Address for the
Bridge Table. The value specifies the most significant 10 bits of the SDRAM absolute address, resulting in a
granularity of 32,768 bytes per LSB.
Register Name:
AR.LQOS
Register Description:
Register Address:
LAN Queue Overflow Status
198h
Bit 15
LQOS-16
Bit 14
LQOS-15
0
Bit 13
LQOS-14
0
Bit 12
LQOS-13
0
Bit 11
LQOS-12
0
Bit 10
LQOS-11
0
Bit 9
LQOS-10
0
Bit 8
LQOS-9
0
199h:
Default
0
Bit 7
LQOS-8
0
Bit 6
LQOS-7
0
Bit 5
LQOS-6
0
Bit 4
LQOS-5
0
Bit 3
LQOS-4
0
Bit 2
LQOS-3
0
Bit 1
LQOS-2
0
Bit 0
LQOS-1
0
198h:
Default
Bits 0-15: LAN Queue Overflow Status (LQOS[16-1]) This register indicates whether an overflow condition has
occurred on any of the LAN Queues since the last read of this register (one status bit per LAN Queue). This
register is reset each time it is read.
0 = No overflow condition detected
1 = At least one overflow condition detected since last read
Rev: 063008
223 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.LQOIM
Register Description:
Register Address:
LAN Queue Overflow Interrupt Mask
19Ah
Bit 15
LQOIM-16
Bit 14
LQOIM-15
0
Bit 13
LQOIM-14
0
Bit 12
LQOIM-13
0
Bit 11
LQOIM-12
0
Bit 10
LQOIM-11
0
Bit 9
LQOIM-10
0
Bit 8
LQOIM-9
0
19Bh:
Default
0
Bit 7
LQOIM-8
0
Bit 6
LQOIM-7
0
Bit 5
LQOIM-6
0
Bit 4
LQOIM-5
0
Bit 3
LQOIM-4
0
Bit 2
LQOIM-3
0
Bit 1
LQOIM-2
0
Bit 0
LQOIM-1
0
19Ah:
Default
Bits 0-15: LAN Queue Overflow Interrupt Mask (LQOIM[16-1]) This register provides an interrupt bit mask to
filter out unwanted interrupts.
0 = Bit mask disabled
1 = Bit mask enabled
Register Name:
AR.LQNFS
Register Description:
Register Address:
LAN Queue Near Full Status
19Ch
Bit 15
LQNFS-16
Bit 14
LQNFS-15
0
Bit 13
LQNFS-14
0
Bit 12
LQNFS-13
0
Bit 11
LQNFS-12
0
Bit 10
LQNFS-11
0
Bit 9
LQNFS-10
0
Bit 8
LQNFS-9
0
19Dh:
Default
0
Bit 7
LQNFS-8
0
Bit 6
LQNFS-7
0
Bit 5
LQNFS-6
0
Bit 4
LQNFS-5
0
Bit 3
LQNFS-4
0
Bit 2
LQNFS-3
0
Bit 1
LQNFS-2
0
Bit 0
LQNFS-1
0
19Ch:
Default
Bits 0-15: LAN Queue Near Full Status (LQNFS[16-1]) This register indicates whether any of the LAN Queues
have exceeded the LAN Queue Watermark defined in AR.LQW since the last read of this register (one status bit
per LAN Queue). This register is reset each time it is read.
0 = No Near Full condition detected
1 = At least one Near Full condition detected since last read
Rev: 063008
224 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.LQNFIM
Register Description:
Register Address:
LAN Queue Near Full Interrupt Mask
19Eh
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
LQNFIM-9
0
LQNFIM-16 LQNFIM-15 LQNFIM-14 LQNFIM-13 LQNFIM-12 LQNFIM-11 LQNFIM-10
19Fh:
Default
0
0
0
0
0
0
0
Bit 7
LQNFIM-8
0
Bit 6
LQNFIM-7
0
Bit 5
LQNFIM-6
0
Bit 4
LQNFIM-5
0
Bit 3
LQNFIM-4
0
Bit 2
LQNFIM-3
0
Bit 1
LQNFIM-2
0
Bit 0
LQNFIM-1
0
19Eh:
Default
Bits 0-15: LAN Queue Near Full Interrupt Mask (LQNFIM[16-1]) This register provides an interrupt bit mask to
filter out unwanted interrupts.
0 = Bit mask disabled
1 = Bit mask enabled
Register Name:
AR.WQOS
Register Description:
Register Address:
WAN Queue Overflow Status
1A0h
Bit 15
WQOS-16
Bit 14
WQOS-15
0
Bit 13
WQOS-14
0
Bit 12
WQOS-13
0
Bit 11
WQOS-12
0
Bit 10
WQOS-11
0
Bit 9
WQOS-10
0
Bit 8
WQOS-9
0
1A1h:
Default
0
Bit 7
WQOS-8
0
Bit 6
WQOS-7
0
Bit 5
WQOS-6
0
Bit 4
WQOS-5
0
Bit 3
WQOS-4
0
Bit 2
WQOS-3
0
Bit 1
WQOS-2
0
Bit 0
WQOS-1
0
1A0h:
Default
Bits 0-15: WAN Queue Overflow Status (WQOS[16-1]) This register indicates whether an overflow condition has
occurred on any of the WAN Queues since the last read of this register (one status bit per WAN Queue). This
register is reset each time it is read.
0 = No overflow condition detected
1 = At least one overflow condition detected since last read
Rev: 063008
225 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WQOIM
Register Description:
Register Address:
WAN Queue Overflow Interrupt Mask
1A2h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
WQOIM-9
0
WQOIM-16 WQOIM-15 WQOIM-14 WQOIM-13 WQOIM-12 WQOIM-11 WQOIM-10
1A3h:
Default
0
0
0
0
0
0
0
Bit 7
WQOIM-8
0
Bit 6
WQOIM-7
0
Bit 5
WQOIM-6
0
Bit 4
WQOIM-5
0
Bit 3
WQOIM-4
0
Bit 2
WQOIM-3
0
Bit 1
WQOIM-2
0
Bit 0
WQOIM-1
0
1A2h:
Default
Bits 0-15: WAN Queue Overflow Interrupt Mask (WQOIM[16-1]) This register provides an interrupt bit mask to
filter out unwanted interrupts.
0 = Bit mask disabled
1 = Bit mask enabled
Register Name:
AR.WQNFS
Register Description:
Register Address:
WAN Queue Near Full Status
1A4h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
WQNFS-9
0
WQNFS-16 WQNFS-15 WQNFS-14 WQNFS-13 WQNFS-12 WQNFS-11 WQNFS-10
1A5h:
Default
0
0
0
0
0
0
0
Bit 7
WQNFS-8
0
Bit 6
WQNFS-7
0
Bit 5
WQNFS-6
0
Bit 4
WQNFS-5
0
Bit 3
WQNFS-4
0
Bit 2
WQNFS-3
0
Bit 1
WQNFS-2
0
Bit 0
WQNFS-1
0
1A4h:
Default
Bits 0-15: WAN Queue Near Full Status (WQNFS[16-1]) This register indicates whether an impending overflow
condition has occurred on a WAN Queue, and the device initiated the discarding of incoming frames on a WAN
interface. This condition can occur if the transmit LAN interface is disabled, if the MAC has received excessive
pause flow control frames and completely filled the buffers for the transmit LAN while responding to the pause
requests, or if operating in half duplex mode with heavy LAN network congestion. This register is cleared each time
it is read.
0 = Normal operation
1 = At least one “Near Full” condition detected since last read, frames may have been discarded.
Rev: 063008
226 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.WQNFIM
Register Description:
Register Address:
WAN Queue Near Full Interrupt Mask
1A6h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
WQNFIM-16 WQNFIM-15 WQNFIM-14 WQNFIM-13 WQNFIM-12 WQNFIM-11 WQNFIM-10 WQNFIM-9
1A7h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WQNFIM-8 WQNFIM-7 WQNFIM-6 WQNFIM-5 WQNFIM-4 WQNFIM-3 WQNFIM-2 WQNFIM-1
1A6h:
Default
0
0
0
0
0
0
0
0
Bits 0-15: WAN Queue Near Full Interrupt Mask (WQNFIM[16-1]) This register provides an interrupt bit mask to
filter interrupts based on the status conditions in the AR.WQNFS register.
0 = Bit mask disabled
1 = Bit mask enabled
Register Name:
AR.EQOS
Register Description:
Register Address:
Extract Queue Overflow Status
1A8h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
1A9h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
-
0
Bit 1
WEQOS
0
Bit 0
LEQOS
0
1A8h:
Default
Bit 1: WAN Extract Queue Overflow Status [WEQOS] This bit indicates whether an overflow condition has
occurred on the LAN Extract Queue since the last read of this register. This register is reset each time it is read.
0 = No Overflow condition detected
1 = At least one Overflow condition detected since last read
Bit 0: LAN Extract Queue Overflow Status [LEQOS] This bit indicates whether an overflow condition has
occurred on the LAN Extract Queue since the last read of this register. This register is reset each time it is read.
0 = No Overflow condition detected
1 = At least one Overflow condition detected since last read
Rev: 063008
227 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.EQOIM
Register Description:
Register Address:
Extract Queue Overflow Interrupt Mask
1AAh
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
1ABh:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
-
0
Bit 1
WEQOIM
0
Bit 0
LEQOIM
0
1AAh:
Default
Bit 1: WAN Extract Queue Overflow Interrupt Mask [WEQOIM] This bit provides an interrupt bit mask to filter
out unwanted interrupts.
0 = Bit mask disabled
1 = Bit mask enabled
Bit 0: LAN Extract Queue Overflow Interrupt Mask [LEQOIM] This bit provides an interrupt bit mask to filter
out unwanted interrupts.
0 = Bit mask disabled
1 = Bit mask enabled
Rev: 063008
228 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
AR.BMIS
Register Description:
Register Address:
Buffer Manager(Arbiter) Interrupt Status
1ACh
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
1ADh:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
EQOI
0
Bit 3
WQNFI
0
Bit 2
WQOI
0
Bit 1
LCNFI
0
Bit 0
LQOI
0
1ACh:
Default
Bit 4: Extract Queue Overflow Interrupt [EQOI] This bit provides an indication of whether this is an active
interrupt. This bit should not be latched, but should provide a logical OR of the Extract Queue Overflow Status
register bits (any “1” generates an interrupt).
0 = No active Interrupt
1 = Active Interrupt
Bit 3: WAN Queue Near Full Interrupt [WQNFI] This bit provides an indication of whether this is an active
interrupt. This bit should not be latched, but should provide a logical OR of the WAN Queue Near Full Status
register bits (any “1” generates an interrupt).
0 = No active Interrupt
1 = Active Interrupt
Bit 2: WAN Queue Overflow Interrupt [WQOI] This bit provides an indication of whether this is an active
interrupt. This bit should not be latched, but should provide a logical OR of the WAN Queue Overflow Status
register bits (any “1” generates an interrupt).
0 = No active Interrupt
1 = Active Interrupt
Bit 1: LAN Queue Near Full Interrupt [LQNFI] This bit provides an indication of whether this is an active
interrupt. This bit should not be latched, but should provide a logical OR of the LAN Queue Near Full Status
register bits (any “1” generates an interrupt).
0 = No active Interrupt
1 = Active Interrupt
Bit 0: LAN Queue Overflow Interrupt [LQOI] This bit provides an indication of whether this is an active
interrupt. This bit should not be latched, but should provide a logical OR of the LAN Queue Overflow Status register
bits (any “1” generates an interrupt).
0 = No active Interrupt
1 = Active Interrupt
Rev: 063008
229 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
10.5 Packet Processor (Encapsulator) Registers
Note that some devices in the product family have less than four encapsulators. The DS33X11 contains only
Encapsulator #1. The DS33W41 and DS33X42 devices contain only encapsulators #1 and #3.
Register Name:
PP.EMCR
Register Description:
Register Address:
Encapsulator Master Control Register
200h (+ 040h x (n-1), WAN Group Encapsulator n=1 to 4)
Bit 15
EGCM
0
Bit 14
EPRTSEL EFCSAD
Bit 13
Bit 12
ECFCRD
0
Bit 11
EFCS16EN
Bit 10
Bit 9
EFCSB
0
Bit 8
EBBYS
0
201h:
Default
-
0
0
0
0
Bit 7
EIIS
0
Bit 6
ELHDE
0
Bit 5
ET1E
0
Bit 4
ET2E
0
Bit 3
ERE1
0
Bit 2
ERE0
0
Bit 1
TBRE
0
Bit 0
EHCBO
0
200h:
Default
Bit 15: Encapsulator GFP CRC Mode(EGCM)
0= GFP Null. Encapsulator pFCS calculation begins with the 9th byte after the start of the frame.
1= GFP Linear. Encapsulator pFCS calculation begins with the 13th byte after the start of the frame.
Bit 14: Encapsulator Protocol Selection (EPRTSEL)
0= GFP
1= HDLC/cHDLC/LAPS(X.86)
Bit 13: Encapsulator Frame Check Sequence Append Disable (EFCSAD) When set to 1, frames will not have a
HDLC/GFP FCS appended prior to transmission. When equal to 0, the encapsulation FCS will be appended.
Bit 12: Encapsulator Scrambler Disable (ECFCRD) When set to 1, encapsulation X43+1 scrambling is disabled.
Bit 11: Encapsulator 16-bit FCS Enable (EFCS16EN) – When set to 1, the HDLC Encapsulation uses a 16-bit
FCS. When equal to 0, a 32 bit FCS is appended. This bit only applies when EFCSAD = 0.
Bit 9: Encapsulator Ethernet FCS Bypass (EFCSB) When set to 1, the Ethernet FCS is forwarded exactly as
received. When equal to 0, the Ethernet FCS is removed prior to encapsulation.
Bit 8: Encapsulator Bit Byte Synchronous (EBBYS) When set to 1, the Encapsulator performs Byte Stuffing.
When equal to 0, the Encapsulator performs Bit Stuffing. When in GFP mode (EPRTSEL = 0), this bit should be set
to 1. Bit-stuffed HDLC is not valid for multi-member VCGs.
Bit 7: Encapsulator Interframe Idle Selection (EIIS) When set to 1, the Encapsulator Idle sequence is 0xFF.
When equal to 0, the Encapsulator Idle sequence is 0x7E. This bit only applies when EPRTSEL = 1.
Bit 6: Encapsulator Line Header Enable (ELHDE) When set to 1, the Encapsulator will insert the values in
PP.ELHHR and PP.ELHLR as a 4-byte Line Header. The header is appended after the PLI+CHEC field in GFP
mode, and after the start flag in HDLC mode.
Bit 5: Encapsulator Tag 1 Enable (ET1E) When set to 1, the Encapsulator will insert the values in PP.ET1DHR
and PP.ET1DLR as a 4-byte tag immediately before the DA field.
Bit 4: Encapsulator Tag 2 Enable (ET2E) When set to 1, the Encapsulator will insert the values in PP.ET2DHR
and PP.ET2DLR as a 4-byte tag immediately after the SA field.
Bits 2-3: Encapsulator Remove Enable (ERE[1:0])
00 = Normal operation.
01 = 18 bytes are removed from the frame prior to encapsulation, starting with the DA field.
10 = 14 bytes are removed from the frame prior to encapsulation, starting with the DA field.
11 = Reserved.
Bit 1: Transmit Bit Reorder (TBRE) Controls the endian order of HDLC transmission. This bit function is not
available in device revision A1 (GL.IDR.REVn=000).
Rev: 063008
230 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
0 = HDLC payload will be transmitted MSB-first. Default operation.
1 = HDLC payload will be transmitted LSB-first.
Bit 0: Encapsulator HDLC CRC Bit Reorder (EHCBO) Controls the endian order of the HDLC CRC calculation.
This bit function is not available in device revision A1 (GL.IDR.REVn=000).
0 = HDLC CRC will be calculated MSB-first. Default operation.
1 = HDLC CRC will be calculated LSB-first.
Register Name:
PP.ELHHR
Register Description:
Register Address:
Encapsulator Line Header High Data Register
202h (+ 040h x (n-1), WAN Group Encapsulator n=1 to 4)
Bit 15
ELHD31
Bit 14
ELHD30
0
Bit 13
ELHD29
0
Bit 12
ELHD28
0
Bit 11
ELHD27
0
Bit 10
ELHD26
0
Bit 9
ELHD25
0
Bit 8
ELHD24
0
203h:
Default
0
Bit 7
ELHD23
0
Bit 6
ELHD22
0
Bit 5
ELHD21
0
Bit 4
ELHD20
0
Bit 3
ELHD19
0
Bit 2
ELHD18
0
Bit 1
ELHD17
0
Bit 0
ELHD16
0
202h:
Default
Bits 0-15: Encapsulator Line Header Data (ELHD[31:16]) These 2 bytes provide the most significant bytes of the
Line Header, when enabled with ELHDE. ELDH[31:25] is inserted first, followed by ELHD[23:16].
Register Name:
PP.ELHLR
Register Description:
Register Address:
Encapsulator Line Header Low Data Register
204h (+ 040h x (n-1), WAN Group Encapsulator n=1 to 4)
Bit 15
ELHD15
Bit 14
ELHD14
0
Bit 13
ELHD13
0
Bit 12
ELHD12
0
Bit 11
ELHD11
0
Bit 10
ELHD10
0
Bit 9
ELHD9
0
Bit 8
ELHD8
0
205h:
Default
0
Bit 7
ELHD7
0
Bit 6
ELHD6
0
Bit 5
ELHD5
0
Bit 4
ELHD4
0
Bit 3
ELHD3
0
Bit 2
ELHD2
0
Bit 1
ELHD1
0
Bit 0
ELHD0
0
204h:
Default
Bits 0-15: Encapsulator Line Header Data (ELHD[15:0]) These 2 bytes provide the least significant bytes of the
Line Header, when enabled with ELHDE. ELDH[15:8] is inserted first, followed by ELHD[7:0].
Rev: 063008
231 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
PP.ET1DHR
Register Description:
Register Address:
Encapsulator Tag 1 Data High Register
206h (+ 040h x (n-1), WAN Group Encapsulator n=1 to 4)
Bit 15
ET1D31
Bit 14
ET1D30
0
Bit 13
ET1D29
0
Bit 12
ET1D28
0
Bit 11
ET1D27
0
Bit 10
ET1D26
0
Bit 9
ET1D25
0
Bit 8
ET1D24
0
207h:
Default
0
Bit 7
ET1D23
0
Bit 6
ET1D22
0
Bit 5
ET1D21
0
Bit 4
ET1D20
0
Bit 3
ET1D19
0
Bit 2
ET1D18
0
Bit 1
ET1D17
0
Bit 0
ET1D16
0
206h:
Default
Bits 0-15: Encapsulator Tag 1 Data (ET1D[31:16]) These 2 bytes provide the most significant bytes of Tag 1,
when enabled with ET1E. ET1D[31:25] is inserted first, followed by ET1D[23:16].
Register Name:
PP.ET1DLR
Register Description:
Register Address:
Encapsulator Tag 1 Data Low Register
208h (+ 040h x (n-1), WAN Group Encapsulator n=1 to 4)
Bit 15
ET1D15
Bit 14
ET1D14
0
Bit 13
ET1D13
0
Bit 12
ET1D12
0
Bit 11
ET1D11
0
Bit 10
ET1D10
0
Bit 9
ET1D9
0
Bit 8
ET1D8
0
209h:
Default
0
Bit 7
ET1D7
0
Bit 6
ET1D6
0
Bit 5
ET1D5
0
Bit 4
ET1D4
0
Bit 3
ET1D3
0
Bit 2
ET1D2
0
Bit 1
ET1D1
0
Bit 0
ET1D0
0
208h:
Default
Bits 0-15: Encapsulator Tag 1 Data (ET1D[15:0]) These 2 bytes provide the least significant bytes of Tag 1,
when enabled with ET1E. ET1D[15:8] is inserted first, followed by ET1D[7:0].
Register Name:
PP.ET2DHR
Register Description:
Register Address:
Encapsulator Tag 2 Data High Register
20Ah (+ 040h x (n-1), WAN Group Encapsulator n=1 to 4)
Bit 15
ET2D31
Bit 14
ET2D30
0
Bit 13
ET2D29
0
Bit 12
ET2D28
0
Bit 11
ET2D27
0
Bit 10
ET2D26
0
Bit 9
ET2D25
0
Bit 8
ET2D24
0
20Bh:
Default
0
Bit 7
ET2D23
0
Bit 6
ET2D22
0
Bit 5
ET2D21
0
Bit 4
ET2D20
0
Bit 3
ET2D19
0
Bit 2
ET2D18
0
Bit 1
ET2D17
0
Bit 0
ET2D16
0
20Ah:
Default
Bits 0-15: Encapsulator Tag 2 Data (ET2D[31:16]) These 2 bytes provide the most significant bytes of Tag 2,
when enabled with ET2E. ET2D[31:25] is inserted first, followed by ET2D[23:16].
Rev: 063008
232 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
PP.ET2DLR
Register Description:
Register Address:
Encapsulator Tag 2 Data Low Register
20Ch (+ 040h x (n-1), WAN Group Encapsulator n=1 to 4)
Bit 15
ET2D15
Bit 14
ET2D14
0
Bit 13
ET2D13
0
Bit 12
ET2D12
0
Bit 11
ET2D11
0
Bit 10
ET2D10
0
Bit 9
ET2D9
0
Bit 8
ET2D8
0
20Dh:
Default
0
Bit 7
ET2D7
0
Bit 6
ET2D6
0
Bit 5
ET2D5
0
Bit 4
ET2D4
0
Bit 3
ET2D3
0
Bit 2
ET2D2
0
Bit 1
ET2D1
0
Bit 0
ET2D0
0
20Ch:
Default
Bits 0-15: Encapsulator Tag 2 Data (ET2D[15:0]) These 2 bytes provide the least significant bytes of Tag 2,
when enabled with ET2E. ET2D[15:8] is inserted first, followed by ET2D[7:0].
Register Name:
PP.EEIR
Register Description:
Register Address:
Encapsulator Error Insertion Register
20Eh (+ 040h x (n-1), WAN Group Encapsulator n=1 to 4)
Bit 15
EPLIEIE
Bit 14
EDEIE
0
Bit 13
EEFCSEIE
0
Bit 12
EFCFEIE
0
Bit 11
EBDEC1
0
Bit 10
EBDEC0
0
Bit 9
EEI7
0
Bit 8
EEI6
0
20Fh:
Default
0
Bit 7
EEI5
0
Bit 6
EEI4
0
Bit 5
EEI3
0
Bit 4
EEI2
0
Bit 3
EEI1
0
Bit 2
EEI0
0
Bit 1
ESEI
0
Bit 0
-
0
20Eh:
Default
Bit 15: Encapsulator PLI Error Insert Enable (EPLIEIE) When set to 1, a single-bit error insertion is enabled for
the PLI field. This includes the 2 PLI Header bits and the corresponding CHEC.
Bit 14: Encapsulator Data Error Insert Enable (EDEIE) When set to 1, a single-bit error insertion is enabled for
the data field. Errors can only be inserted in the first byte of the payload data. Hence the EBD bit setting has no
effect for inserting payload errors.
Bit 13: Encapsulator Ethernet FCS Error Insert Enable (EFCSEIE) When set to 1, a single-bit error insertion is
enabled for the Ethernet FCS field.
Bit 12: Encapsulator FCS Error Insert Enable (EPLIEIE) When set to 1, a single-bit error insertion is enabled for
the encapsulation FCS field.
Bits 10-11: Encapsulator Byte Decode (EBD[1:0]) These bits determine which of the 4 bytes need error insertion
for the PLI, Ethernet FCS, and Encapsulation FCS fields. These bits have no effect on data error insertion.
Bits 2-9: Encapsulator Error Insert (EIE[7:0]) These 8 bits determine the bit location of the error insertion in the
selected field. Only one error is inserted for each transition of ESEI.
Bit 1: Encapsulator Single Error Insert (ESEI) Changing this bit from a 0 to a 1 causes a single error insertion.
For a second error insertion, the user must first clear this bit.
Register Name:
PP.EFCLSR
Register Description:
Register Address:
Encapsulator Frame Count Latched Status Register
210h (+ 040h x (n-1), WAN Group Encapsulator n=1 to 4)
Rev: 063008
233 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Bit 15
EFCNT15
0
Bit 14
EFCNT14
0
Bit 13
EFCNT13
0
Bit 12
EFCNT12
0
Bit 11
EFCNT11
0
Bit 10
EFCNT10
0
Bit 9
EFCNT9
0
Bit 8
EFCNT8
0
211h:
Default
Bit 7
EFCNT7
0
Bit 6
EFCNT6
0
Bit 5
EFCNT5
0
Bit 4
EFCNT4
0
Bit 3
EFCNT3
0
Bit 2
EFCNT2
0
Bit 1
EFCNT1
0
Bit 0
EFCNT0
0
210h:
Default
Bits 0-15: Encapsulator Frame Count (EFCNT[15:0]) This counter provides the number of frames that have
been encapsulated. The counter is reset upon being read by the microprocessor.
Register Name:
PP.ESMLS
Register Description:
Register Address:
Encapsulator State Machine Latched Status
21Eh (+ 040h x (n-1), WAN Group Encapsulator n=1 to 4)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
SOPLE
0
Bit 10
SOPSE
0
Bit 9
COPLE
0
Bit 8
COPSE
0
-
-
-
-
21Fh:
Default
0
0
0
0
Bit 7
EOPLE
0
Bit 6
EOPSE
0
Bit 5
-
Bit 4
FUF
0
Bit 3
FOVF
0
Bit 2
FLOK
0
Bit 1
FF
0
Bit 0
FE
0
21Eh:
Default
0
Bit 11: (SOPLE) This bit is set upon detection of an internal error.
Bit 10: (SOPSE) This bit is set upon detection of an internal error.
Bit 9: (COPLE) This bit is set upon detection of an internal error.
Bit 8: (COPSE) This bit is set upon detection of an internal error.
Bit 7: (EOPLE) This bit is set upon detection of an internal error.
Bit 6: (EOPSE) This bit is set upon detection of an internal error.
Bit 4: (FUF) This bit is set if the encapsulator FIFO has underflowed.
Bit 3: (FOVF) This bit is set if the encapsulator FIFO has overflowed.
Bit 2: (FLOK) This bit is set if the encapsulator FIFO is ok to accept more data. Cleared on read.
Bit 1: (FF) This bit is set if the encapsulator FIFO is full. Cleared on read.
Bit 0: (FE) This bit is set if the encapsulator FIFO is empty. Cleared on read.
Rev: 063008
234 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
PP.ESMIE
Register Description:
Register Address:
Encapsulator State Machine Interrupt Enable
220h (+ 040h x (n-1), WAN Group Encapsulator n=1 to 4)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
SOPLEIE
0
Bit 10
SOPSEIE
0
Bit 9
COPLEIE
0
Bit 8
COPSEIE
0
-
-
-
-
221h:
Default
0
0
0
0
Bit 7
EOPLEIE
0
Bit 6
EOPSEIE
0
Bit 5
-
Bit 4
FUFIE
0
Bit 3
FOVFIE
0
Bit 2
FLOKIE
0
Bit 1
FFIE
0
Bit 0
FEIE
0
220h:
Default
0
Bit 11: (SOPLEIE) This bit enables an interrupt on the SOPLE condition.
Bit 10: (SOPSEIE) This bit enables an interrupt on the SOPSE condition.
Bit 9: (COPLEIE) This bit enables an interrupt on the COPLE condition.
Bit 8: (COPSEIE) This bit enables an interrupt on the COPSE condition.
Bit 7: (EOPLEIE) This bit enables an interrupt on the EOPLE condition.
Bit 6: (EOPSEIE) This bit enables an interrupt on the EOPSE condition.
Bit 4: (FUFIE) This bit enables an interrupt on the FUF condition.
Bit 3: (FOVFIE) This bit enables an interrupt on the FOVF condition.
Bit 2: (FLOKIE) This bit enables an interrupt on the FLOK condition.
Bit 1: (FFIE) This bit enables an interrupt on the FF condition.
Bit 0: (FEIE) This bit enables an interrupt on the FE condition.
Register Name:
PP.EHFL
Register Description:
Register Address:
Encapsulator HDLC Fill Length
226h (+ 040h x (n-1), WAN Group Encapsulator n=1 to 4)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
227h:
Default
0
0
0
0
0
0
0
0
Bit 7
EHFL7
0
Bit 6
EHFL6
0
Bit 5
EHFL5
0
Bit 4
EHFL4
0
Bit 3
EHFL3
0
Bit 2
EHFL2
0
Bit 1
EHFL1
0
Bit 0
EHFL0
0
226h:
Default
Bits 0-15: Encapsulator HDLC Fill Length (EHFL[7:0]) Used to set the minimum number of HDLC Fill flags to be
inserted after the end of each frame. Only valid when HDLC encapsulation is used.
Rev: 063008
235 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
10.6 Decapsulator Registers
Register Name:
PP.DMCR
Register Description:
Register Address:
Decapsulator Master Control Register
300h (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
DGCM
Bit 14
DPRTSEL
0
Bit 13
DFCSAD
0
Bit 12
DCFCRD
0
Bit 11
DFCS16EN
0
Bit 10
Bit 9
DBBS
0
Bit 8
RBRE
0
301h:
-
0
Default
0
Bit 7
DR1E
0
Bit 6
DR2E
0
Bit 5
DR3E
0
Bit 4
DAE1
0
Bit 3
DAE0
0
Bit 2
DGSC
Bit 1
DHRAE
0
Bit 0
DHCBO
0
300h:
Default
0
Bit 15: Decapsulator GFP CRC Mode (DGCM)
0=GFP Null. Decapsulator does not verify the eHEC value.
1=GFP Linear. Decapsulator verifies the eHEC value and discards failing frames.
Bit 14: Decapsulator Protocol Selection (DPRTSEL)
Selects between GFP and HDLC based forms of encapsulation. Additionally, when transitioning HDLC between
byte and bit modes of operation, this byte is used to reset the HDLC circuitry. In order to initiate a reset the HDLC
circuitry during bit/byte stuffing mode changes, this bit must be set to zero briefly, then set back to 1.
0=GFP Based.
1=HDLC Based.
Bit 13: Decapsulator Frame Check Sequence Append Disable (DFCSAD)– When equal to 0, the incoming
frame’s encapsulation (HDLC/GFP) CRC (FCS) will be validated and removed. When set to 1, the decapsulated
frame will not be expected to contain an encapsulation CRC and no bytes will be removed.
Bit 12: Decapsulator Scrambler Disable (DCFCRD) When set to 1, the X43+1 descrambler is turned off.
Bit 11: Decapsulator 16-bit FCS Enable (DFCS16EN) When set to 1 the decapsulated frame must contain a 16-
bit FCS. When equal to zero, a 32-bit FCS is expected. This bit is relevant if DFCSAD is reset.
Bit 9: Decapsulator Bit Byte Synchronous(DBBS) When set to 1, the Decapsulator expects byte-stuffed HDLC.
When equal to zero, the Decapsulator expects bit-stuffed HDLC. When in GFP mode (DPRTSEL = 0), this bit
should be set to 1. After changing this bit, the HDLC circuitry should be reset using the PP.DMCR.DPRTSEL bit.
Bit-stuffed HDLC is not valid for multi-member VCGs (WAN Groups).
Bit 8: Receive Bit Reorder (RBRE) Controls the endian order of HDLC reception. This bit function is not available
in device revision A1 (GL.IDR.REVn=000).
0 = HDLC payload will be received MSB-first. Default operation.
1 = HDLC payload will be received LSB-first.
Bit 7: Decapsulator Remove Function 1 Enable (DR1E) When set to 1, 4 bytes are removed immediately after
the cHEC bytes (for GFP) or start of HDLC flag (for HDLC). This bit should be set to 1 for X.86, Cisco HDLC and
GFP transport. This bit should be reset to 0 for HDLC traffic with no headers.
Bit 6: Decapsulator Remove Function 2 Enable (DR2E) When set to 1, 4 bytes are removed after the first
remove function. This function should always be used in conjunction with Decapsulator Remove Function 1.
Bit 5: Decapsulator Remove Function 3 Enable (DR3E) When set to 1, 12 bytes are skipped and then 4 bytes
are removed. The 12 bytes are skipped after either Decapsulator Remove Function 1 and/or Decapsulator Remove
Function 2 have been performed (when enabled). When Decapsulator Remove Functions 1 and 2 are disabled, 12
bytes are skipped from the beginning of the frame.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Bits 3-4: Decapsulator Add Enable (DAE[1:0]) Controls the insertion of additional bytes by the decapsulator.
00 = Normal operation.
01 = The 18 byte value from the PP.DA1DR through PP.DA9DR registers will be inserted after the
cHEC bytes in GFP mode, or after the HDLC header/flag when in HDLC mode.
10 = The 14 byte value from the PP.DA1DR through PP.DA7DR registers will be inserted after the
cHEC bytes in GFP mode, or after the HDLC header/flag when in HDLC mode.
11 = Reserved.
Bit 2: Decapsulator GFP Synchronization Control (DGSC) When set, “triple synchronization” is selected. Three
consecutive PLIs and respective cHEC must be correct to enter the Synchronization State. If equal to zero, two
consecutive correct PLIs and cHECs are required. Only applicable to GFP Mode.
Bit 1: Decapsulator HDLC Rate Adaptation (DHRAE)
0= Disabled. Default for non-X.86 (LAPS) modes.
1= Enabled. “7D DD” sequence removed from data stream. For use in X.86 (LAPS) mode.
Bit 0: Decapsulator HDLC CRC Bit Order (DHCBO) Controls the endian order of the HDLC CRC calculation.
This bit function is not available in device revision A1 (GL.IDR.REVn=000).
0 = HDLC CRC will be calculated MSB-first. Default operation.
1 = HDLC CRC will be calculated LSB-first.
Register Name:
PP.DA1DR
Register Description:
Register Address:
Decapsulator Add 1 Data Register
302h (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
D1D15D
Bit 14
D1D14D
0
Bit 13
D1D13D
0
Bit 12
D1D12D
0
Bit 11
D1D11D
0
Bit 10
D1D10D
0
Bit 9
D1D9D
0
Bit 8
D1D8D
0
303h
Default
0
Bit 7
D1D7D
0
Bit 6
D1D6D
0
Bit 5
D1D5D
0
Bit 4
D1D4D
0
Bit 3
D1D3D
0
Bit 2
D1D2D
0
Bit 1
D1D1D
0
Bit 0
D1D0D
0
302h
Default
Bits 0-15: Decapsulator 1 Data High (D1D [15:0]) These 2 bytes provide the data if the addition is enabled with
PP.DMCR.DAE[1:0].
Register Name:
PP.DA2DR
Register Description:
Register Address:
Decapsulator Add 2 Data Register
304h (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
D2D15D
Bit 14
D2D14D
0
Bit 13
D2D13D
0
Bit 12
D2D12D
0
Bit 11
D2D11D
0
Bit 10
D2D10D
0
Bit 9
D2D9D
0
Bit 8
D2D8D
0
305h:
Default
0
Bit 7
D2D7D
0
Bit 6
D2D6D
0
Bit 5
D2D5D
0
Bit 4
D2D4D
0
Bit 3
D2D3D
0
Bit 2
D2D2D
0
Bit 1
D2D1D
0
Bit 0
D2D0D
0
304h:
Default
Bits 0-15: Decapsulator 2 Data (D2D [15:0]) These 2 bytes provide the data if the addition is enabled with
PP.DMCR.DAE[1:0].
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
PP.DA3DR
Register Description:
Register Address:
Decapsulator Add 3 Data Register
306h (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
D3D15D
Bit 14
D3D14D
0
Bit 13
D3D13D
0
Bit 12
D3D12D
0
Bit 11
D3D11D
0
Bit 10
D3D10D
0
Bit 9
D3D9D
0
Bit 8
D3D8D
0
307h:
Default
0
Bit 7
D3D7D
0
Bit 6
D3D6D
0
Bit 5
D3D5D
0
Bit 4
D3D4D
0
Bit 3
D3D3D
0
Bit 2
D3D2D
0
Bit 1
D3D1D
0
Bit 0
D3D0D
0
306h:
Default
Bits 0-15: Decapsulator 3 Data (D3D [15:0]) These 2 bytes provide the data if the addition is enabled with
PP.DMCR.DAE[1:0].
Register Name:
PP.DA4DR
Register Description:
Register Address:
Decapsulator Add 4 Data Register
308h (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
D4D15D
Bit 14
D4D14D
0
Bit 13
D4D13D
0
Bit 12
D4D12D
0
Bit 11
D4D11D
0
Bit 10
D4D10D
0
Bit 9
D4D9D
0
Bit 8
D4D8D
0
309h:
Default
0
Bit 7
D4D7D
0
Bit 6
D4D6D
0
Bit 5
D4D5D
0
Bit 4
D4D4D
0
Bit 3
D4D3D
0
Bit 2
D4D2D
0
Bit 1
D4D1D
0
Bit 0
D4D0D
0
308h:
Default
Bits 0-15: Decapsulator 4 Data (D4D [15:0]) These 2 bytes provide the data if the addition is enabled with
PP.DMCR.DAE[1:0].
Register Name:
PP.DA5DR
Register Description:
Register Address:
Decapsulator Add 5 Data Register
30Ah (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
D5D15D
Bit 14
D5D14D
0
Bit 13
D5D13D
0
Bit 12
D5D12D
0
Bit 11
D5D11D
0
Bit 10
D5D10D
0
Bit 9
D5D9D
0
Bit 8
D5D8D
0
30Bh:
Default
0
Bit 7
D5D7D
0
Bit 6
D5D6D
0
Bit 5
D5D5D
0
Bit 4
D5D4D
0
Bit 3
D5D3D
0
Bit 2
D5D2D
0
Bit 1
D5D1D
0
Bit 0
D5D0D
0
30Ah:
Default
Bits 0-15: Decapsulator 5 Data (D5D [15:0]) These 2 bytes provide the data if the addition is enabled with
PP.DMCR.DAE[1:0].
Rev: 063008
238 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
PP.DA6DR
Register Description:
Register Address:
Decapsulator Add 6 Data Register
30Ch (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
D6D15D
Bit 14
D6D14D
0
Bit 13
D6D13D
0
Bit 12
D6D12D
0
Bit 11
D6D11D
0
Bit 10
D6D10D
0
Bit 9
D6D9D
0
Bit 8
D6D8D
0
30Dh:
Default
0
Bit 7
D6D7D
0
Bit 6
D6D6D
0
Bit 5
D6D5D
0
Bit 4
D6D4D
0
Bit 3
D6D3D
0
Bit 2
D6D2D
0
Bit 1
D6D1D
0
Bit 0
D6D0D
0
30Ch:
Default
Bits 0-15: Decapsulator 6 Data (D6D [15:0]) These 2 bytes provide the data if the addition is enabled with
PP.DMCR.DAE[1:0].
Register Name:
PP.DA7DR
Register Description:
Register Address:
Decapsulator Add 7 Data Register
30Eh (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
D7D15D
Bit 14
D7D14D
0
Bit 13
D7D13D
0
Bit 12
D7D12D
0
Bit 11
D7D11D
0
Bit 10
D7D10D
0
Bit 9
D7D9D
0
Bit 8
D7D8D
0
30Fh:
Default
0
Bit 7
D7D7D
0
Bit 6
D7D6D
0
Bit 5
D7D5D
0
Bit 4
D7D4D
0
Bit 3
D7D3D
0
Bit 2
D7D2D
0
Bit 1
D7D1D
0
Bit 0
D7D0D
0
30Eh:
Default
Bits 0-15: Decapsulator 7 Data High (D7D [15:0]) These 2 bytes provide the data if the addition is enabled
PP.DMCR.DAE[1:0].
Register Name:
PP.DA8DR
Register Description:
Register Address:
Decapsulator Add 8 Data Register
310h (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
D8D15D
Bit 14
D8D14D
0
Bit 13
D8D13D
0
Bit 12
D8D12D
0
Bit 11
D8D11D
0
Bit 10
D8D10D
0
Bit 9
D8D9D
0
Bit 8
D8D8D
0
311h:
Default
0
Bit 7
D8D7D
0
Bit 6
D8D6D
0
Bit 5
D8D5D
0
Bit 4
D8D4D
0
Bit 3
D8D3D
0
Bit 2
D8D2D
0
Bit 1
D8D1D
0
Bit 0
D8D0D
0
310h:
Default
Bits 0-15: Decapsulator 8 Data (D8D [15:0]) These 2 bytes provide the data if the addition is enabled with
PP.DMCR.DAE[1:0].
Rev: 063008
239 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
PP.DA9DR
Register Description:
Register Address:
Decapsulator Add 9 Data Register
312h (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
D9D15D
Bit 14
D9D14D
0
Bit 13
D9D13D
0
Bit 12
D9D12D
0
Bit 11
D9D11D
0
Bit 10
D9D10D
0
Bit 9
D9D9D
0
Bit 8
D9D8D
0
313h:
Default
0
Bit 7
D9D7D
0
Bit 6
D9D6D
0
Bit 5
D9D5D
0
Bit 4
D9D4D
0
Bit 3
D9D3D
0
Bit 2
D9D2D
0
Bit 1
D9D1D
0
Bit 0
D9D0D
0
312h:
Default
Bits 0-15: Decapsulator 9 Data High (D9D [15:0]) These 2 bytes provide the data if the addition is enabled with
PP.DMCR.DAE[1:0].
Register Name:
PP.DMLSR
Register Description:
Register Address:
Decapsulator Master Latched Status Register
314h (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
DGSLS
Bit 14
DGSLLS
0
Bit 13
DGLCLS
0
Bit 12
DGLCSLS
0
Bit 11
DFFLS
0
Bit 10
Bit 9
Bit 8
315h:
Default
-
0
DCHECFLS DTCHECFLS
0
0
0
Bit 7
DFUR
0
Bit 6
DFOVF
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
-
0
Bit 1
-
0
Bit 0
-
0
314h:
Default
Bit 15: Decapsulator GFP Sync Latched Status (DGSLS) When Set the GFP has achieved Synchronization
Latched Status. This bit is cleared upon a read.
Bit 14: Decapsulator GFP Sync Loss Latched Status (DGSLLS) When Set indicates that the GFP has lost
synchronization. This bit is cleared upon a read.
Bit 13: Decapsulator GFP Loss of Client Signal Latched Status (DGLCLS) When Set indicates that the GFP
Loss of Client Signal Management Frame has arrived. This bit is cleared upon a read.
Bit 12: Decapsulator GFP Loss of Client Synchronization Latched Status (DGLCSLS) When Set indicates that
the GFP Loss of Client Synchronization Management Frame has arrived. This bit is cleared upon a read.
Bit 11: Decapsulator FCS Fail Latched Status (DFFLS) When set indicates that the FCS has failed. This bit is
cleared upon a read.
Bit 9: Decapsulator Extension Header eHEC Fail Latched Status (DCHECFLS) When set indicates that the
Extension HEC has failed. This bit is cleared upon a read.
Bit 8: Decapsulator Type HEC Fail Latched Status (DTCHECFLS) When set indicates Type HEC has failed.
Bit 7: Decapsulator FIFO Under run Latched Status (DFUR) When set indicates that the FIFO has under run.
Bit 6: Decapsulator FIFO Overflow Latched Status (DFOVF) When set indicates that the FIFO has overflowed.
Rev: 063008
240 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
PP.DMLSIE
Register Description:
Register Address:
Decapsulator Master Latched Status Interrupt Enable
316h (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
DGSIE
Bit 14
DGSLIE
0
Bit 13
DGLCIE
0
Bit 12
DGLCSIE
0
Bit 11
DFFIE
0
Bit 10
Bit 9
Bit 8
317h:
Default
-
0
DCHECFIE DTCHECFIE
0
0
0
Bit 7
DFURIE
0
Bit 6
DFOVFIE
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
-
0
Bit 1
-
0
Bit 0
-
0
316h:
Default
Bit 15: Decapsulator GFP Sync Interrupt Enable (DGSIE)
Bit 14: Decapsulator GFP Sync Loss Interrupt Enable (DGSLIE)
Bit 13: Decapsulator GFP Loss of Client Signal Interrupt Enable (DGLCIE)
Bit 12: Decapsulator GFP Loss of Client Synchronization Interrupt Enable (DGLCSIE)
Bit 11: Decapsulator FCS Fail Interrupt Enable (DFFIE)
Bit 9: Decapsulator Extension Header eHEC Fail Interrupt Enable (DCHECFIE)
Bit 8: Decapsulator Type HEC Fail Interrupt Enable (DTCHECFIE)
Bit 7: Decapsulator FIFO Under Run Interrupt Enable (DFURIE)
Bit 6: Decapsulator FIFO Overflow Interrupt Enable (DFOVFIE)
Register Name:
PP.DGPLC
Register Description:
Register Address:
Decapsulator Good Packet Latched Counter
318h (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
Bit 14
Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
DGPLC8
0
319h:
DGPLC15 DGPLC14 DGPLC13 DGPLC12 DGPLC11 DGPLC10 DGPLC9
Default
0
0
0
0
0
0
0
Bit 7
DGPLC7
0
Bit 6
DGPLC6
0
Bit 5
DGPLC5
0
Bit 4
DGPLC4
0
Bit 3
DGPLC3
0
Bit 2
DGPLC2
0
Bit 1
DGPLC1
0
Bit 0
DGPLC0
0
318h:
Default
Bit 15-0/ Decapsulator Good Packet Low Latched Counter(DGPLC 15:0) – This bits provide the low word of the
good Frame Counter. This counter is cleared upon a read.
Rev: 063008
241 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
PP.DGBLC
Register Description:
Register Address:
Decapsulator Bad Packet Latched Counter
31Ah (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
DBPLC9
0
Bit 8
DBPLC8
0
31Bh:
DBPLC15 DBPLC14 DBPLC13 DBPLC12 DBPLC11 DBPLC10
Default
0
0
0
0
0
0
Bit 7
DBPLC7
0
Bit 6
DBPLC6
0
Bit 5
DBPLC5
0
Bit 4
DBPLC4
0
Bit 3
DBPLC3
0
Bit 2
DBPLC2
0
Bit 1
DBPLC1
0
Bit 0
DBPLC0
0
31Ah:
Default
Bit 8-15: Decapsulator Bad Packet Latched Counter(DBPLC 7:0) These bits provide the bad frame counter
latched value. The counter is cleared upon a read. The following are counted: Aborts, Runt, FCS Errors, Type
CHEC failures.
Register Name:
PP.DSSR
Register Description:
Register Address:
Decapsulator Synchronization Status Register
31Ch (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
31Dh:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
DGSYNC
0
Bit 1
DGPSYNC
0
Bit 0
DGHUNT
0
31Ch:
Default
Bit 2: Decapsulator GFP Sync Status (DGSYNC) This bit is set when GFP is Synchronized. This bit can be read
after the transition of DFSRWPC.
Bit 1: Decapsulator GFP Pre Sync Status (DGPSYNC) This bit is set when GFP Synchronization Machine is in
the Pre-Synchronized state. This bit can be read after the transition of DFSRWPC.
Bit 0: Decapsulator GFP Hunt Status (DHUNT) This bit is set when GFP Synchronization Machine is in the Hunt
state. This bit can be read after the transition of DFSRWPC.
Rev: 063008
242 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
PP.DHHSR
Register Description:
Register Address:
Decapsulator Header High Status Register
31Eh (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
31Fh:
DHSR31
DHSR30
DHSR29
DHSR28
DHSR27
DHSR26
DHSR25
DHSR24
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
31Eh:
DHSR23
DHSR22
DHSR21
DHSR20
DHSR19
DHSR18
DHSR17
DHSR16
Default
0
0
0
0
0
0
0
0
Bit 15-0: Decapsulator Header High Status (DHSR31:16) – These bits provide the high word of the Header
Bytes that have been received. These are the first 2 bytes after the HDLC start flag and The first 2 bytes after the
GFP PLI and GFP cHEC.
Register Name:
PP.DHLSR
Register Description:
Register Address:
Decapsulator Header Low Status Register
320h (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
321h:
DHSR15
DHSR14
DHSR13
DHSR12
DHSR11
DHSR10
DHSR9
DHSR8
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
320h:
DHSR7
DHSR6
DHSR5
DHSR4
DHSR3
DHSR2
DHSR1
DHSR0
Default
0
0
0
0
0
0
0
0
Bit 15-0: Decapsulator Header Low Status (DHSR15:0) – These bits provide the low word of the Header Bytes
that have been received. These are the bytes 3 and 4 after the HDLC start flag and bytes 3 and 4 after the GFP
PLI and GFP cHEC.
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Register Name:
PP.DFSCR
Register Description:
Register Address:
Decapsulator FIFO Control Register
322h (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
323h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
DEM
0
Bit 2
DSMRE
0
Bit 1
DFPRE
0
Bit 0
DFSRWPC
0
322h:
Default
Note – bit definitions below not symmetric Decap/Encap:
Bit 3: Decapsulator Error Mode (DEM) When set to 1, errored frames are forwarded. Normally they are
discarded. This bit function was located in DMCR bit 0 in device revision A1 (GL.IDR.REVn=000).
Bit 2: Decapsulator State Machine Reset (DSMRE) If this bit is set and DFSRWPC transitions, The
Decapsulator State Machine will be reset.
Bit 1: Decapsulator FIFO Pointer reset Enable (DFPRE) - Setting this bit to a 1 will enable the FIFO to be reset.
The FIFO Read and Write pointer will be reset if DFSRWPC transitions and this bit is set.
Bit 0: Decapsulator FIFO and State Read, Write, and PMU Control (DFSRWPC)- A 0 to 1 transition enables the
FIFO Read and Write Addresses, Status Registers to be read by the processor. The user must wait 4 system
clocks before the reads can be done. This bit is used to control resetting of the FIFO Read and Write Pointers and
the Decapsulator State Machine. This bit is also used as a PMU update for all decapsulator latched counters.
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10.7 VCAT/LCAS Registers
10.7.1 Transmit VCAT Registers
Note: Some registers are on a per-WAN-port basis.
Register Name:
VCAT.TCR1
Register Description:
Register Address:
VCAT Transmit Control Register 1
400h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
TGIDBC
0
Bit 10
TGIDM
0
Bit 9
TLOAD
0
Bit 8
TVBLKEN
0
-
0
-
0
-
0
401h:
Default
Bit 7
V4FM1
0
Bit 6
V4FM0
0
Bit 5
V3FM1
0
Bit 4
V3FM0
0
Bit 3
V2FM1
0
Bit 2
V2FM0
0
Bit 1
V1FM1
0
Bit 0
V1FM0
0
400h:
Default
Bit 11: Transmit GID Bit Convention (TGIDBC) Controls all 4 VCGs. This bit is only used when TGIDM = 1
0 = bit 15 of the TGIDx register is transmitted first.
1 = bit 0 of TGIDx register is transmitted first.
Bit 10: Transmit GID Mode (TGIDM) Controls all 4 VCGs.
0 = PRBS (215 – 1) pattern.
1 = User configured value. The first bit inserted will be when MFI2 = XXXX_0000.
Bit 9: Transmit Configuration Change Load (TLOAD). When all WAN transmit ports have been configured with
the correct SQ assignments, CTRL commands, member count (TCR1.VnMC[3:0]), VCG assignments, and LCAS
Enable (LE[4:1]), a 0-to-1 transition on this bit will load the new configuration on the next VCAT Start of Frame
(SOF). This register will update all VCGs.
Bit 8: Transmit VCAT Block Enable (TVBLKEN) Data path Reset/Disable.
0 = VCAT Block is disabled; data path is disabled
1 = VCAT Block is enabled; data path is enabled
Note: This bit must be set even in Non-VCG modes
Bits 6-7: VCG4 Frame Mode Control (V4FM[1:0])
00 = VCG4 configured for T1
01 = VCG4 configured for E1
10 = VCG4 configured for C-bit DS3 (MUST be mapped to Ports 1 to 8 only)
11 = VCG4 configured for E3 G.832 (MUST be mapped to Ports 1 to 8 only)
Bits 4-5: VCG3 Frame Mode Control (V3FM[1:0])
00 = VCG3 configured for T1
01 = VCG3 configured for E1
10 = VCG3 configured for C-bit DS3 (MUST be mapped to Ports 1 to 8 only)
11 = VCG3 configured for E3 G.832 (MUST be mapped to Ports 1 to 8 only)
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Bits 2-3: VCG2 Frame Mode Control (V2FM[1:0])
00 = VCG2 configured for T1
01 = VCG2 configured for E1
10 = VCG2 configured for C-bit DS3 (MUST be mapped to Ports 1 to 8 only)
11 = VCG2 configured for E3 G.832 (MUST be mapped to Ports 1 to 8 only)
Bits 0-1: VCG1 Frame Mode Control (V1FM[1:0])
00 = VCG1 configured for T1
01 = VCG1 configured for E1
10 = VCG1 configured for C-bit DS3 (MUST be mapped to Ports 1 to 8 only)
11 = VCG1 configured for E3 G.832 (MUST be mapped to Ports 1 to 8 only)
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Register Name:
VCAT.TCR2
Register Description:
Register Address:
VCAT Transmit Control Register 2
402h
Bit 15
TV4MC3
Bit 14
TV4MC2
0
Bit 13
TV4MC1
0
Bit 12
TV4MC0
0
Bit 11
TV3MC3
0
Bit 10
TV3MC2
0
Bit 9
TV3MC1
0
Bit 8
TV3MC0
0
403h:
Default
0
Bit 7
TV2MC3
0
Bit 6
TV2MC2
0
Bit 5
TV2MC1
0
Bit 4
TV2MC0
0
Bit 3
TV1MC3
0
Bit 2
TV1MC2
0
Bit 1
TV1MC1
0
Bit 0
TV1MC0
0
402h:
Default
Bits 12-15: Transmit VCG4 Member Count (TV4MC[3:0]) These bits indicate to the device the number of
members assigned to VCG4
0000 = 1 Member
0001 = 2 Members
0010 = 3 members
…..
1111 = 16 members
Bits 8-11: Transmit VCG3 Member Count (TV3MC[3:0]) These bits indicate to the device the number of
members assigned to VCG3
0000 = 1 Member
0001 = 2 Members
0010 = 3 members
…..
1111 = 16 members
Bits 4-7: Transmit VCG2 Member Count (TV2MC[3:0]) These bits indicate to the device the number of members
assigned to VCG2
0000 = 1 Member
0001 = 2 Members
0010 = 3 members
…..
1111 = 16 members
Bits 0-3: Transmit VCG1 Member Count (TV1MC[3:0]) These bits indicate to the device the number of members
assigned to VCG1
0000 = 1 Member
0001 = 2 Members
0010 = 3 members
…..
1111 = 16 members
Note: If more than one member is assigned to a WAN group, VCAT must be enabled for that group. Updates to this
register take effect after VCGCR.TLOAD transitions.
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Register Name:
VCAT.TLCR1
Register Description:
Register Address:
VCAT Transmit LCAS Control Register 1
406h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
407h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
RSACK4
0
Bit 2
RSACK3
0
Bit 1
RSACK2
0
Bit 0
RSACK1
0
406h:
Default
Bits 0-3: VCGn ReSequence Acknowledge (RSACK[4:1]).
0 = No change
1 = Invert RS-Ack bit
Register Name:
VCAT.TLCR2
Register Description:
Register Address:
VCAT Transmit LCAS Control Register 2
408h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
409h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
ATMSTD4
0
Bit 2
ATMSTD3
0
Bit 1
ATMSTD2
0
Bit 0
ATMSTD1
0
408h:
Default
Bits 0-3: Automatic Transmit MST Disable (ATMSTD[4:1])
0 = RLCAS automatic inserts Transmit MST values for VCGn
1 = Disable RLCAS control of Transmit MST for VCGn
Register Name:
VCAT.TLCR3
Register Description:
Register Address:
VCAT Transmit LCAS Control Register 3
40Ah
Bit 15
V1MST15
Bit 14
V1MST14
1
Bit 13
V1MST13
1
Bit 12
V1MST12
1
Bit 11
V1MST11
1
Bit 10
V1MST10
1
Bit 9
V1MST9
1
Bit 8
V1MST8
1
40Bh:
Default
1
Bit 7
V1MST7
1
Bit 6
V1MST6
1
Bit 5
V1MST5
1
Bit 4
V1MST4
1
Bit 3
V1MST3
1
Bit 2
V1MST2
1
Bit 1
V1MST1
1
Bit 0
V1MST0
1
40Ah:
Default
Bits 0-15: VCG 1 MST Manual Control (V1MST[15:0])
0 = Member n sends MST = OK
1 = Member n sends MST = FAIL
Note: Default upon power-up is SET. These bits latched on SOF if VCAT.TLCR1.ATMSTD1=1.
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Register Name:
VCAT.TLCR4
Register Description:
Register Address:
VCAT Transmit LCAS Control Register 4
40Ch
Bit 15
V2MST15
Bit 14
V2MST14
1
Bit 13
V2MST13
1
Bit 12
V2MST12
1
Bit 11
V2MST11
1
Bit 10
V2MST10
1
Bit 9
V2MST9
1
Bit 8
V2MST8
1
40Dh:
Default
1
Bit 7
V2MST7
1
Bit 6
V2MST6
1
Bit 5
V2MST5
1
Bit 4
V2MST4
1
Bit 3
V2MST3
1
Bit 2
V2MST2
1
Bit 1
V2MST1
1
Bit 0
V2MST0
1
40Ch:
Default
Bits 0-15: VCG 2 MST Manual Control (V2MST[15:0])
0 = Member n sends MST = OK
1 = Member n sends MST = FAIL
Note: Default upon power-up is SET. These bits latched on SOF if VCAT.TLCR1.ATMSTD2=1.
Register Name:
VCAT.TLCR5
Register Description:
Register Address:
VCAT Transmit LCAS Control Register 5
40Eh
Bit 15
V3MST15
Bit 14
V3MST14
1
Bit 13
V3MST13
1
Bit 12
V3MST12
1
Bit 11
V3MST11
1
Bit 10
V3MST10
1
Bit 9
V3MST9
1
Bit 8
V3MST8
1
40Fh:
Default
1
Bit 7
V3MST7
1
Bit 6
V3MST6
1
Bit 5
V3MST5
1
Bit 4
V3MST4
1
Bit 3
V3MST3
1
Bit 2
V3MST2
1
Bit 1
V3MST1
1
Bit 0
V3MST0
1
40Eh:
Default
Bits 15 to 0: VCG 3 MST Manual Control (V3MST[15:0])
0 = Member n sends MST = OK
1 = Member n sends MST = FAIL
Note: Default upon power-up is SET. These bits latched on SOF if VCAT.TLCR1.ATMSTD3=1.
Register Name:
VCAT.TLCR6
Register Description:
Register Address:
VCAT Transmit LCAS Control Register 6
410h
Bit 15
V4MST15
Bit 14
V4MST14
1
Bit 13
V4MST13
1
Bit 12
V4MST12
1
Bit 11
V4MST11
1
Bit 10
V4MST10
1
Bit 9
V4MST9
1
Bit 8
V4MST8
1
411h:
Default
1
Bit 7
V4MST7
1
Bit 6
V4MST6
1
Bit 5
V4MST5
1
Bit 4
V4MST4
1
Bit 3
V4MST3
1
Bit 2
V4MST2
1
Bit 1
V4MST1
1
Bit 0
V4MST0
1
410h:
Default
Bits 0-15: VCG 4 MST Manual Control (V4MST[15:0])
0 = Member n sends MST = OK
1 = Member n sends MST = FAIL
Note: Default upon power-up is SET. These bits latched on SOF if VCAT.TLCR1.ATMSTD4=1.
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Register Name:
VCAT.TCR3
Register Description:
Register Address:
VCAT Transmit Control Register 3
420h (+ 002h x (n-1), Physical WAN Port n=1 to 16)
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
TVSQ3
0
Bit 10
TVSQ2
0
Bit 9
TVSQ1
0
Bit 8
TVSQ0
0
-
0
-
0
-
0
421h:
Default
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
TNVCGC
0
Bit 3
TVGS2
0
Bit 2
TVGS1
0
Bit 1
TVGS0
0
Bit 0
TPA
0
420h:
Default
Bits 8-11: Transmit VCAT Sequence Mapping (TVSQ[3:0]) These four bits are a BCD number that is used in the
“SQ” field of the VCAT MFI on that port. When LCAS is enabled, the internal LCAS engine controls the transmit
sequence number and reading these bits provides the current assigned sequence number for a given port. The
user should take care to not overwrite these bits when LCAS is enabled. When LCAS is not enabled, the user
can write a value to specifically assign a port’s sequence in a VCG. Note that in T3/E3 operation, only sequence
numbers 0-7 are valid.
Bit 4: Transmit Non-VCG Control (TNVCGC)
0 = The VCAT byte position is not used for payload data. Required when placing GFP encapsulated
Ethernet over PDH for compliance with ITU-T G.8040.
1 = The VCAT byte position is used for payload data. Only valid when the port is not configured as a
member of a VCAT group.
Bits 1-3: Transmit Port n VCAT Group Selection (TVGS[2:0])
TVGS[2:0]
000
001
010
011
100
101
110
111
Transmit WAN Group and VCAT Selection
VCAT disabled for WAN Port, WAN Group 1
VCAT enabled for WAN Port, WAN Group 1 (VCG1)
VCAT disabled for WAN Port, WAN Group 2
VCAT enabled for WAN Port, WAN Group 2 (VCG2)
VCAT disabled for WAN Port, WAN Group 3
VCAT enabled for WAN Port, WAN Group 3 (VCG3)
VCAT disabled for WAN Port, WAN Group 4
VCAT enabled for WAN Port, WAN Group 4 (VCG4)
Note: Only one port may be assigned to a Non-VCG.
Bit 0: Transmit Port n Assign (TPA)
0 = Port n is Unused.
1 = Port n is assigned to a WAN Group or VCG.
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Register Name:
VCAT.TLCR8
Register Description:
Register Address:
VCAT Transmit LCAS Control Register 8
440h (+ 002h x (n-1), Physical WAN Port n=1 to 16)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
441h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
CTRL3
0
Bit 2
CTRL2
0
Bit 1
CTRL1
0
Bit 0
CTRL0
0
440h:
Default
Bits 0-3: Port n Control Code (CTRL[3:0]).
CTRL[3:0]
0000
0001
Control Word
FIXED
ADD
0010
0011
NORM
EOS
0101
IDLE
1111
DNU
Register Name:
Register Description:
Register Address:
VCAT.TCR4
VCAT Transmit Control Register 4
470h (+ 002h x (n-1), WAN Group n=1 to 4)
Bit 15
TGID15
Bit 14
TGID14
0
Bit 13
TGID13
0
Bit 12
TGID12
0
Bit 11
TGID11
0
Bit 10
TGID10
0
Bit 9
TGID9
0
Bit 8
TGID8
0
471h:
Default
0
Bit 7
TGID7
0
Bit 6
TGID6
0
Bit 5
TGID5
0
Bit 4
TGID4
0
Bit 3
TGID3
0
Bit 2
TGID2
0
Bit 1
TGID1
0
Bit 0
TGID0
0
470h:
Default
Bits 12-15: Transmit GID Value (TGID[15:0]) These bits contain a user-programmed value to be transmitted
through the VCAT GID. One value is used for all members of each WAN Group. Only used when
VCAT.TCR1.TGIDM = 1.
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10.7.2 VCAT Receive Register Description
Note: Some registers are on a per-WAN-port basis.
Register Name:
VCAT.RCR1
Register Description:
Register Address:
VCAT Receive Control Register 1
500h
Bit 15
Bit 14
Bit 13
Bit 12
RVEN4
0
Bit 11
RGIDBC
0
Bit 10
RVEN3
0
Bit 9
RVEN2
0
Bit 8
RVEN1
0
-
0
-
0
-
0
501h:
Default
Bit 7
-
0
Bit 6
-
0
Bit 5
SVINTD
0
Bit 4
T3T1WG4
0
Bit 3
T3T1WG3
0
Bit 2
T3T1WG2
0
Bit 1
T3T1WG1
0
Bit 0
RVBLKEN
0
500h:
Default
Bit 12: Receive VCAT and Data Path Enable for VCG 4 (RVEN4) Data path reset and enable. This bit function is
not available in device revision A1 (GL.IDR.REVn=000).
0 = VCAT Block is disabled and held in reset; data path is disabled for receive WAN Group #4
1 = VCAT Block is enabled; data path is enabled for receive WAN Group #4
Note: This bit must be set to enable the data path, even when operating in Non-VCG modes
Bit 11: Receive GID Bit Convention (RGIDBC) Controls all 4 VCGs. This bit is only used when TGIDM = 1
0 = bit 15 of the RGIDx register is received first.
1 = bit 0 of RGIDx register is received first.
Bit 10: Receive VCAT and Data Path Enable for VCG 3 (RVEN3) Data path Reset disable. This bit function is not
available in device revision A1 (GL.IDR.REVn=000).
0 = VCAT Block is disabled and held in reset; data path is disabled for receive WAN Group #3
1 = VCAT Block is enabled; data path is enabled for receive WAN Group #3
Note: This bit must be set to enable the data path, even when operating in Non-VCG modes
Bit 9: Receive VCAT and Data Path Enable for VCG 2 (RVEN2) Data path Reset disable. This bit function is not
available in device revision A1 (GL.IDR.REVn=000).
0 = VCAT Block is disabled and held in reset; data path is disabled for receive WAN Group #2
1 = VCAT Block is enabled; data path is enabled for receive WAN Group #2
Note: This bit must be set to enable the data path, even when operating in Non-VCG modes
Bit 8: Receive VCAT and Data Path Enable for VCG 1 (RVEN1) Data path Reset disable. This bit function is not
available in device revision A1 (GL.IDR.REVn=000).
0 = VCAT Block is disabled and held in reset; data path is disabled for receive WAN Group #1
1 = VCAT Block is enabled; data path is enabled for receive WAN Group #1
Note: This bit must be set to enable the data path, even when operating in Non-VCG modes
Bit 5: Sequence Value Integration Disable (SVINTD) Integration of sequence values applies to non-LCAS
operation only.
0 = Sequence value integrated is enabled.
1 = Sequence value integration is disabled.
Bit 4: T3/E3 or T1/E1 Selection for WAN Group 4 (T3T1WG4)
0 = device configured for T1/E1 VCGs
1 = device configured for T3/E3 VCGs (MUST be Ports 1 to 8 only)
Bit 3: T3/E3 or T1/E1 Selection for WAN Group 3 (T3T1WG3)
0 = device configured for T1/E1 VCGs
1 = device configured for T3/E3 VCGs (MUST be Ports 1 to 8 only)
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Bit 2: T3/E3 or T1/E1 Selection for WAN Group 2 (T3T1WG2)
0 = device configured for T1/E1 VCGs
1 = device configured for T3/E3 VCGs (MUST be Ports 1 to 8 only)
Bit 1: T3/E3 or T1/E1 Selection for WAN Group 1 (T3T1WG1)
0 = device configured for T1/E1 VCGs
1 = device configured for T3/E3 VCGs (MUST be Ports 1 to 8 only)
Bit 0: Receive VCAT Block Enable (RVBLKEN) Data path Reset disable.
0 = VCAT Block is disabled; data path is disabled
1 = VCAT Block is enabled; data path is enabled
Note: This bit must be set even in Non-VCG modes
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Register Name:
VCAT.RCR2
Register Description:
Register Address:
VCAT Receive Control Register 2
502h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
503h:
Default
0
0
0
0
0
0
0
0
Bit 7
LE4
0
Bit 6
LE3
0
Bit 5
LE2
0
Bit 4
LE1
0
Bit 3
REALIGN4
0
Bit 2
REALIGN3
0
Bit 1
REALIGN2
0
Bit 0
REALIGN1
0
502h:
Default
Bit 7: LCAS Enable VCG4 (LE4).
0 = VCG 4 is not enabled for LCAS
1 = VCG 4 is enabled for LCAS
Bit 6: LCAS Enable VCG 3 (LE3).
0 = VCG 3 is not enabled for LCAS
1 = VCG 3 is enabled for LCAS
Bit 5: LCAS Enable VCG 2 (LE2).
0 = VCG 2 is not enabled for LCAS
1 = VCG 2 is enabled for LCAS
Bit 4: LCAS Enable VCG 1 (LE1).
0 = VCG 1 is not enabled for LCAS
1 = VCG 1 is enabled for LCAS
Bits 0-3: Manual Re-alignment of VCAT Members for VCGn (REALIGN[4:1]) A 0-to-1 transition of
this bit causes the Re-alignment state machine for VCGn to restart.
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Register Name:
VCAT.RCR3
Register Description:
Register Address:
VCAT Receive Control Register 3
504h
Bit 15
RV4MC3
Bit 14
RV4MC2
0
Bit 13
RV4MC1
0
Bit 12
RV4MC0
0
Bit 11
RV3MC3
0
Bit 10
RV3MC2
0
Bit 9
RV3MC1
0
Bit 8
RV3MC0
0
505h:
Default
0
Bit 7
RV2MC3
0
Bit 6
RV2MC2
0
Bit 5
RV2MC1
0
Bit 4
RV2MC0
0
Bit 3
RV1MC3
0
Bit 2
RV1MC2
0
Bit 1
RV1MC1
0
Bit 0
RV1MC0
0
504h:
Default
Bits 12-15: Receive VCG4 Member Count (RV4MC[3:0]) These bits indicate to the device the number of
members assigned to VCG4.
0000 = 1 Member
0001 = 2 Members
0010 = 3 members
…..
1111 = 16 members
Note: This count represents all members of a VCG, active or not.
Bits 8-11: Receive VCG3 Member Count (RV3MC[3:0]) These bits indicate to the device the number of members
assigned to VCG3.
0000 = 1 Member
0001 = 2 Members
0010 = 3 members
…..
1111 = 16 members
Note: This count represents all members of a VCG, active or not.
Bits 4-7: Receive VCG2 Member Count (RV2MC[3:0]) These bits indicate to the device the number of members
assigned to VCG2.
0000 = 1 Member
0001 = 2 Members
0010 = 3 members
…..
1111 = 16 members
Note: This count represents all members of a VCG, active or not.
Bits 0-3: Receive VCG1 Member Count (RV1MC[3:0]) These bits indicate to the device the number of members
assigned to VCG1.
0000 = 1 Member
0001 = 2 Members
0010 = 3 members
…..
1111 = 16 members
Note: This count represents all members of a VCG, active or not.
Rev: 063008
255 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
VCAT.RISR
Register Description:
Register Address:
VCAT Receive Interrupt Status Register
508h
Bit 15
PISR16
Bit 14
PISR15
1
Bit 13
PISR14
1
Bit 12
PISR13
1
Bit 11
PISR12
1
Bit 10
PISR11
1
Bit 9
PISR10
1
Bit 8
PISR9
1
509h:
Default
1
Bit 7
PISR8
1
Bit 6
PISR7
1
Bit 5
PISR6
1
Bit 4
PISR5
1
Bit 3
PISR4
1
Bit 2
PISR3
1
Bit 1
PISR2
1
Bit 0
PISR1
1
508h:
Default
Bits 0-15: VCAT Port Interrupt Status (PISR[16:1]) This bit is set when the corresponding serial port’s Receive
Serial Status Latched Register (VCAT.RSLSR[1-16]) has one or more bits set and its corresponding Interrupt
Enable bit is also set.
Register Name:
VCAT.RLSR1
Register Description:
Register Address:
VCAT Receive LCAS Status Register 1
50Ah
Bit 15
V1MST15
Bit 14
V1MST14
1
Bit 13
V1MST13
1
Bit 12
V1MST12
1
Bit 11
V1MST11
1
Bit 10
V1MST10
1
Bit 9
V1MST9
1
Bit 8
V1MST8
1
50Bh:
Default
1
Bit 7
V1MST7
1
Bit 6
V1MST6
1
Bit 5
V1MST5
1
Bit 4
V1MST4
1
Bit 3
V1MST3
1
Bit 2
V1MST2
1
Bit 1
V1MST1
1
Bit 0
V1MST0
1
50Ah:
Default
Bits 0-15: V1MST[15:0] VCG1 MST Status
0 = Member n receives MST = OK
1 = Member n receives MST = OK
Note: on reset, this register will be set to all ones
Rev: 063008
256 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
VCAT.RLSR2
Register Description:
Register Address:
VCAT Receive LCAS Status Register 2
50Ch
Bit 15
V2MST15
Bit 14
V2MST14
1
Bit 13
V2MST13
1
Bit 12
V2MST12
1
Bit 11
V2MST11
1
Bit 10
V2MST10
1
Bit 9
V2MST9
1
Bit 8
V2MST8
1
50Dh:
Default
1
Bit 7
V2MST7
1
Bit 6
V2MST6
1
Bit 5
V2MST5
1
Bit 4
V2MST4
1
Bit 3
V2MST3
1
Bit 2
V2MST2
1
Bit 1
V2MST1
1
Bit 0
V2MST0
1
50Ch:
Default
Bits 0-15: V2MST[15:0] VCG2 MST Status
0 = Member n receives MST = OK
1 = Member n receives MST = OK
Note: on reset, this register will be set to all ones
Register Name:
VCAT.RLSR3
Register Description:
Register Address:
VCAT Receive LCAS Status Register 3
50Eh
Bit 15
V3MST15
Bit 14
V3MST14
1
Bit 13
V3MST13
1
Bit 12
V3MST12
1
Bit 11
V3MST11
1
Bit 10
V3MST10
1
Bit 9
V3MST9
1
Bit 8
V3MST8
1
50Fh:
Default
1
Bit 7
V3MST7
1
Bit 6
V3MST6
1
Bit 5
V3MST5
1
Bit 4
V3MST4
1
Bit 3
V3MST3
1
Bit 2
V3MST2
1
Bit 1
V3MST1
1
Bit 0
V3MST0
1
50Eh:
Default
Bits 0-15: V3MST[15:0] VCG3 MST Status
0 = Member n receives MST = OK
1 = Member n receives MST = OK
Note: on reset, this register will be set to all ones
Rev: 063008
257 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
VCAT.RLSR4
Register Description:
Register Address:
VCAT Receive LCAS Status Register 4
510h
Bit 15
V4MST15
Bit 14
V4MST14
1
Bit 13
V4MST13
1
Bit 12
V4MST12
1
Bit 11
V4MST11
1
Bit 10
V4MST10
1
Bit 9
V4MST9
1
Bit 8
V4MST8
1
511h:
Default
1
Bit 7
V4MST7
1
Bit 6
V4MST6
1
Bit 5
V4MST5
1
Bit 4
V4MST4
1
Bit 3
V4MST3
1
Bit 2
V4MST2
1
Bit 1
V4MST1
1
Bit 0
V4MST0
1
510h:
Default
Bits 0-15: V4MST[15:0] VCG4 MST Status
0 = Member n sends MST = OK
1 = Member n sends MST = FAIL
Note: Default upon power-up is all ones. These bits latched on SOF if VCAT.TLCR1.ATMSTD4=1.
Register Name:
VCAT.RRLSR
Register Description:
Register Address:
VCAT Receive Realign Latched Status Register
512h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
VMSTC4
0
Bit 10
VMSTC3
0
Bit 9
VMSTC2
0
Bit 8
VMSTC1
0
-
0
-
0
-
0
513h:
Default
Bit 7
DDE4
0
Bit 6
DDE3
0
Bit 5
DDE2
0
Bit 4
DDE1
0
Bit 3
Bit 2
Bit 1
Bit 0
REALIGNL4 REALIGNL3 REALIGNL2 REALIGNL1
512h:
Default
0
0
0
0
Bits 8-11: MST Change on VCGn (VMSTC[4:1] This bit is set when any of the 16 MST bits associated with VCGn
have changed value.
Bits 4-7: Differential Delay Exceeded on VCGn This bit is set when the delay between members of the
corresponding VCG has exceeded the tolerance. When set, WAN traffic from the VCG will not be forwarded to the
LAN port.
Bits 0-3: Receive Re-Alignment of VCGn (REALIGNL[4:1]) This bit is set when the corresponding realignment
state machine completes successfully.
Rev: 063008
258 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
VCAT.RRSIE
Register Description:
Register Address:
VCAT Receive Realign Status Interrupt Enable
514h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
VMSTCIE4 VMSTCIE3 VMSTCIE2 VMSTCIE1
515h:
Default
0
0
0
0
0
0
0
0
Bit 7
DDEIE4
0
Bit 6
DDEIE3
0
Bit 5
DDEIE2
0
Bit 4
DDEIE1
0
Bit 3
Bit 2
Bit 1
Bit 0
REALIGNIE4 REALIGNIE3 REALIGNIE2 REALIGNIE1
514h:
Default
0
0
0
0
Bit 11: VCG4 MSTC Change Interrupt Enable (VMSTCIE4) This bit enables an interrupt if VMSTC4 is set.
Bit 10: VCG3 MSTC Change Interrupt Enable (VMSTCIE3) This bit enables an interrupt if VMSTC3 is set.
Bit 9: VCG2 MSTC Change Interrupt Enable (VMSTCIE2) This bit enables an interrupt if VMSTC2 is set.
Bit 8: VCG1 MSTC Change Interrupt Enable (VMSTCIE1) This bit enables an interrupt if VMSTC1 is set.
Bit 7: VCG4 Differential Delay Exceeded Interrupt Enable (DDEIE4). This bit enables an interrupt for DDE4.
Bit 6: VCG3 Differential Delay Exceeded Interrupt Enable (DDEIE3). This bit enables an interrupt for DDE3.
Bit 5: VCG2 Differential Delay Exceeded Interrupt Enable (DDEIE2). This bit enables an interrupt for DDE2.
Bit 4: VCG1 Differential Delay Exceeded Interrupt Enable (DDEIE1). This bit enables an interrupt for DDE1.
Bits 0-3: Receive Re-Alignment of VCGn Interrupt Enable (REALIGNIE[4:1]) This bit enables an interrupt
if the corresponding REALIGNLn bit is set.
0 = interrupt disabled
1 = interrupt enabled
Rev: 063008
259 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
VCAT.RCR4
Register Description:
Register Address:
VCAT Receive Control Register 4
530h (+ 002h x (n-1), Physical WAN Port n=1 to 16)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RFRST
-
-
-
-
-
-
-
531h:
Default
0
0
0
0
0
0
0
0
Bit 7
RFM
0
Bit 6
-
0
Bit 5
-
0
Bit 4
RNVCGC
0
Bit 3
RVGS2
0
Bit 2
RVGS1
0
Bit 1
RVGS0
0
Bit 0
RPA
0
530h:
Default
Bit 15: Receive FIFO Reset (RFRST)
0 = The Receive FIFO resumes normal operations
1 = The Receive FIFO is in Reset. The FIFO is emptied, any transfer in progress is halted, the FIFO circuit
is powered down.
Bit 7: Remove and Reframe (RFM) A zero-to-one transition of this bit forces the associated line into the
“removed” state, which is held as long as the bit remains a 1. A one-to-zero transition on this bit causes the
associated receive port to reframe on the VCAT overhead.
Bit 4: Receive Non-VCG Control (RNVCGC)
0 = The VCAT byte position is not used for payload data.
1 = The VCAT byte position is used for payload data. Only valid when the port is not configured as a
member of a VCAT group.
Bits 1-3: Receive Port n VCAT Group Selection (RVGS[2:0])
RVGS[2:0]
000
001
010
011
100
101
110
111
Receive WAN Group and VCG Selection
VCAT disabled for WAN Port, WAN Group 1
VCAT enabled for WAN Port, WAN Group 1 (VCG1)
VCAT disabled for WAN Port, WAN Group 2
VCAT enabled for WAN Port, WAN Group 2 (VCG2)
VCAT disabled for WAN Port, WAN Group 3
VCAT enabled for WAN Port, WAN Group 3 (VCG3)
VCAT disabled for WAN Port, WAN Group 4
VCAT enabled for WAN Port, WAN Group 4 (VCG4)
Note: Only a single WAN port may be assigned to a WAN Group in which VCAT is disabled.
Bit 0: Receive Port n Assign (RPA)
0 = Port n is Unassigned.
1 = Port n is Assigned to a VCG or Non-VCG.
Rev: 063008
260 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
VCAT.RSR1
Register Description:
Register Address:
VCAT Receive Status Register 1
550h (+ 002h x (n-1), Physical WAN Port n=1 to 16)
Bit 15
RVSQ3
Bit 14
RVSQ2
0
Bit 13
RVSQ1
0
Bit 12
RVSQ0
0
Bit 11
CTRL3
0
Bit 10
CTRL2
0
Bit 9
CTRL1
0
Bit 8
CTRL0
0
551h:
Default
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
RSACK
0
Bit 3
-
0
Bit 2
-
0
Bit 1
-
0
Bit 0
LOM
0
550h:
Default
Bits 12-15: Port n Receive Sequence (RVSQ[3:0]) These bits are updated every VCAT Frame on SOF
boundaries. These bits report the previous frame’s Sequence value. (LCAS only)
Bits 8-11: Port n Control Word (CTRL[3:0]) These bits are updated every VCAT Frame on SOF boundaries.
These bits report the previous frame’s Control Word. (LCAS only)
CTRL[3:0]
0000
0001
Control Word
FIXED
ADD
0010
0011
NORM
EOS
0101
IDLE
1111
DNU
Bit 4: RS-ACK Status (RSACK)
0 = RS-ACK for port n for the previous VCAT frame is 0.
1 = RS-ACK for port n for the previous VCAT frame is 1.
Bit 0: Loss of Multiframe Sync (LOM) – This bit corresponds to the Receive VCAT Framer status of the WAN
port.
0 = No LOM for port n
1 = LOM active for port n
Rev: 063008
261 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
VCAT.RSR2
Register Description:
Register Address:
VCAT Receive Status Register 2
570h (+ 002h x (n-1), Physical WAN Port n=1 to 16)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
571h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
CRCE
0
Bit 2
GID
0
Bit 1
SEMF
1
Bit 0
EMF
0
570h:
Default
Bit 3: CRC Error (CRCE) This status bit is set if there was a CRC error in the previous VCAT frame. (LCAS only)
Bit 2: GID Alarm (GID) This status bit is set if the GID of port n does not match the VCG’s GID value.
Bit 1: Severely Errored Multiframe (SEMF) This status bit is set if there were 4 or more MFI errors in the previous
multiframe. Updated on Multiframe boundaries.
Bit 0: Errored Multiframe (EMF) This status bit is set if there was at least one MFI error in the previous
multiframe. Updated on Multiframe boundaries.
Register Name:
VCAT.RSLSR
Register Description:
Register Address:
VCAT Receive Serial Latched Status Register
590h (+ 002h x (n-1), Physical WAN Port n=1 to 16)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
591h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
RSACKL
0
Bit 3
SQL
0
Bit 2
CTRL
0
Bit 1
-
0
Bit 0
LOML
0
590h:
Default
Bit 4: RS-ACK Change Latched (RSACKL) Set when the corresponding RSACK status bit changes state.
Bit 3: SQ Change Latched (SQL) Set when the SQ[3:0] status bits change.
Bit 2: CTRL Code Change Latched (CTRLL) Set when the CTRL[3:0] status bits change.
Bit 0: Loss of Multiframe Sync Change Latched (LOML) Set when the corresponding LOM bit changes from an
inactive (0) to an active (1) state. The user should poll LOM to determine when the LOM condition is cleared.
Rev: 063008
262 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
VCAT.RSIE
Register Description:
Register Address:
VCAT Receive Serial Interrupt Enable Register
5B0h (+ 002h x (n-1), Physical WAN Port n=1 to 16)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
5B1h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
RSACKIE
0
Bit 3
SQIE
0
Bit 2
CTRIE
0
Bit 1
-
0
Bit 0
LOMIE
0
5B0h:
Default
Bit 4: RSACK Change Interrupt Enable (RSACKIE) This bit enables an interrupt if the RSACKL bit is set.
0 = Interrupt for port n is Masked
1 = Interrupt for port n is Enabled
Bit 3: SQ Change Interrupt Enable (SQIE) This bit enables an interrupt if the SQL bit is set.
0 = Interrupt for port n is Masked
1 = Interrupt for port n is Enabled
Bit 2: CTRL Change Interrupt Enable (CTRIE) This bit enables an interrupt if the CTRLL bit is set.
0 = Interrupt for port n is Masked
1 = Interrupt for port n is Enabled
Bit 0: Loss of Multiframe Sync Change Interrupt Enable (LOMIE[16:1]) This bit enables an interrupt if the
LOML bit is set.
0 = Interrupt for port n is Masked
1 = Interrupt for port n is Enabled
Rev: 063008
263 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
VCAT.RSR3
Register Description:
Register Address:
VCAT Receive Status Register 3
5D0h (+ 002h x (n-1), Physical WAN Port n=1 to 16)
Bit 15
RGID15
Bit 14
RGID14
0
Bit 13
RGID13
0
Bit 12
RGID12
0
Bit 11
RGID11
0
Bit 10
RGID10
0
Bit 9
RGID9
0
Bit 8
RGID8
0
5D1h:
Default
0
Bit 7
RGID7
0
Bit 6
RGID6
0
Bit 5
RGID5
0
Bit 4
RGID4
0
Bit 3
RGID3
0
Bit 2
RGID2
0
Bit 1
RGID1
0
Bit 0
RGID0
0
5D0h:
Default
Bits 0 -15: Receive GID (RGID[15:0]) These bits provide the received 16-bit GID value for each of the 16 WAN
Lines. Latches the first bit when MFI2 = XXXX_0000. Bit order is reversed if RGIDBC=1.
Rev: 063008
264 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
10.8 Serial Interface Registers
The Serial Interface contains the Serial transport circuitry and the associated serial port. The Serial Interface
register map consists of registers that are common functions, transmit functions, and receive functions.
Bits that are underlined are read-only; all other bits can be written. All reserved registers and bits with “-“
designation should be written to zero, unless specifically noted in the register definition. When read, the information
from reserved registers and bits designated with “-“ should be discarded.
Counter registers are updated by asserting (low to high transition) the associated performance monitoring update
signal (xxPMU). During the counter register update process, the associated performance monitoring status signal
(xxPMS) is deasserted. The counter register update process consists of loading the counter register with the
current count, resetting the counter, forcing the zero count status indication low for one clock cycle, and then
asserting xxPMS. No events are missed during this update procedure.
A latched bit is set when the associated event occurs, and remains set until it is cleared by reading. Once cleared,
a latched bit will not be set again until the associated event occurs again. Reserved configuration bits and registers
should be written to zero.
10.8.1 Serial Interface Transmit and Common Registers
Serial Interface Transmit Registers are used to control the transmitter associated with each Serial Interface. The
register map is shown in the following Table. Note that throughout this document the HDLC Processor is also
referred to as a “packet processor”.
10.8.2 Serial Interface Transmit Register Bit Descriptions
Register Name:
LI.LCR1
Register Description:
Register Address:
Serial Interface Loopback Control Register 1
600h
Bit 15
LLB16
Bit 14
LLB15
0
Bit 13
LLB14
0
Bit 12
LLB13
0
Bit 11
LLB12
0
Bit 10
LLB11
0
Bit 9
LLB10
0
Bit 8
LLB9
0
601h:
Default
0
Bit 7
LLB8
0
Bit 6
LLB7
0
Bit 5
LLB6
0
Bit 4
LLB5
0
Bit 3
LLB4
0
Bit 2
LLB3
0
Bit 1
LLB2
0
Bit 0
LLB1
0
600h:
Default
Bits 0-15: Line Loopback Enable (LLB[15:0]) Data received on RDATAn will be looped to the Transmit
Serial Port, replacing the data on TDATAn. (Note: TCLKn must be the same clock as RCLKn).
0 = Line Loopback is Disabled
1 = Line Loopback is Enabled
Rev: 063008
265 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
LI.LCR2
Register Description:
Register Address:
Serial Interface Loopback Control Register 2
602h
Bit 15
TLB16
Bit 14
TLB15
0
Bit 13
TLB14
0
Bit 12
TLB13
0
Bit 11
TLB12
0
Bit 10
TLB11
0
Bit 9
TLB10
0
Bit 8
TLB9
0
603h:
Default
0
Bit 7
TLB8
0
Bit 6
TLB7
0
Bit 5
TLB6
0
Bit 4
TLB5
0
Bit 3
TLB4
0
Bit 2
TLB3
0
Bit 1
TLB2
0
Bit 0
TLB1
0
602h:
Default
Bits 0-15: Terminal Loopback Enable(TLB[16:1]). Data transmitted on TDATAn will be internally looped to the
Receive Serial Port and data on RDATAn will be ignored and TCLKn will replace RCLKn.
0 = Terminal Loopback is Disabled
1 = Terminal Loopback is Enabled
Register Name:
LI.TCSR
Register Description:
Register Address:
Serial Interface Transmit Clock Status Register
604h
Bit 15
Bit 14
Bit 13
Bit 12
TMCLKA4
0
Bit 11
-
0
Bit 10
-
0
Bit 9
-
0
Bit 8
TMCLKA3
0
-
0
-
0
-
0
605h:
Default
Bit 7
TCLKA8
0
Bit 6
TCLKA7
0
Bit 5
TCLKA6
0
Bit 4
TCLKA5
0
Bit 3
TCLKA4
0
Bit 2
TCLKA3
0
Bit 1
TCLKA2
0
Bit 0
TCLKA1
0
604h:
Default
Bit 12: Transmit Clock Active (TMCLKA4).
0 = TMCLK4 is not transitioning.
1 = TMCLK4 is active.
Note: This real-time status bit reports whether TMCLK4 has transitioned since the last
read of this register.
Bit 8: Transmit Clock Active (TMCLKA3).
0 = TMCLK3 is not transitioning.
1 = TMCLK3 is active.
Note: This real-time status bit reports whether TMCLK4 has transitioned since the last
read of this register.
Bits 0-7: Transmit Clock Active (TCLKA[8:1])
0 = TMCLKm/TCLKn is not Transitioning
1 = TMCLKm/TCLKn is Active
Note: This real-time status bit reports whether TMCLKm/TCLKn has transitioned since the last
read of this register.
Rev: 063008
266 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
LI.TVCSR
Register Description:
Register Address:
Serial Interface Transmit Voice Clock Status Register
606h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
607h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
-
0
Bit 1
-
0
Bit 0
TVCLKA1
0
606h:
Default
Bit 0: Transmit Voice Clock Active (TCLKA1).
0 = TVCLK1 is not Transitioning
1 = TVCLK1 is Active
Note: This real-time status bit reports whether TVCLKA1 has transitioned since the last read of this register.
Register Name:
LI.RCSR
Register Description:
Register Address:
Serial Interface Receive Clock Status Register
608h
Bit 15
RCLKA16
Bit 14
RCLKA15
0
Bit 13
RCLKA14
0
Bit 12
RCLKA13
0
Bit 11
RCLKA12
0
Bit 10
RCLKA11
0
Bit 9
RCLKA10
0
Bit 8
RCLKA9
0
609h:
Default
0
Bit 7
RCLKA8
0
Bit 6
RCLKA7
0
Bit 5
RCLKA6
0
Bit 4
RCLKA5
0
Bit 3
RCLKA4
0
Bit 2
RCLKA3
0
Bit 1
RCLKA2
0
Bit 0
RCLKA1
0
608h:
Default
Bits 0-15: Receive Clock Active (RCLKA[16:1])
0 = RCLKn is not Transitioning
1 = RCLKn is Active
Note: This real-time status bit reports whether RCLKn has transitioned since the last read of this register.
Rev: 063008
267 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
LI.RVCSR
Register Description:
Register Address:
Serial Interface Receive Voice Clock Status Register
60Ah
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
60Bh:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
-
0
Bit 1
-
0
Bit 0
RVCLKA1
0
60Ah:
Default
Bit 0: Receive Voice Clock Active (RVCLKA1)
0 = RVCLK is not Transitioning
1 = RVCLK is Active
Note: This real-time status bit reports whether RVCLK has transitioned since the last read of this register.
Rev: 063008
268 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
10.8.3 Transmit Per Serial Port Register Description
Register Name:
LI.TCR
Register Description:
Register Address:
Serial Interface Transmit Control Register
640h (+ 008h x (n-1), Physical Serial Port n=1 to 16)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
641h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
TCLKINV
0
Bit 3
-
0
Bit 2
Bit 1
Bit 0
TD_SEL
0
TS_SETUP1 TS_SETUP0
640h:
Default
0
0
Bit 4: TMCLKm/TCLKn Invert (TCLKINV) Note: Valid for m = 1 to 4, n = 1 to 8.
0 = TMCLKm/TCLKn is not inverted
1 = TMCLKm/TCLKn is inverted
Bits 1-2: TSYNC Setup (TS_SETUP[1:0]). These two bits accommodate a TSYNC signal that arrives earlier
than the start of frame.
TS_SETUP[1:0]
TSYNC Arrives
0 cycles early
1 cycle early
00
01
10
11
2 cycles early
3 cycles early
Bit 0: TDATA Select (TD_SEL).
0 = TDATAn is referenced to the associated TMCLKn, TMSYNCn.
1 = TDATAn is referenced to the associated TCLKn, TSYNCn. Not valid for Serial Ports 9-16.
TMCLKn / TMSYNCn
Ports
Assignment when
TD_SEL=0
TMCLK1 / TMSYNC1
TMCLK2 / TMSYNC2
TMCLK3 / TMSYNC3*
TMCLK4 / TMSYNC4*
1-4
5-8
9-12*
13-16*
* Note: For serial ports 9-16, the TD_SEL bit is not available. Ports 9-16 must use TMCLKn and TMSYNCn.
Rev: 063008
269 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
10.8.4 Transmit Voice Port Register Description
Register Name:
LI.TVPCR
Register Description:
Register Address:
Serial Interface Transmit Voice Port Control Register
6C0h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
-
0
Bit 10
-
0
Bit 9
TVFRST
0
Bit 8
TVCLKI
0
-
0
-
0
-
0
6C1h:
Default
Bit 7
TVOPF4
0
Bit 6
TVOPF3
0
Bit 5
TVOPF2
0
Bit 4
TVOPF1
0
Bit 3
TVOPF0
0
Bit 2
TSYNCC
0
Bit 1
PC
0
Bit 0
TPE
0
6C0h:
Default
Bit 9: Transmit Voice FIFO Reset (TVFRST)
0 = The Transmit Voice FIFO resumes normal operations
1 = Transmit Voice FIFO Reset. The FIFO is emptied, any transfer in progress is halted, the FIFO circuit is
powered down, and all incoming data is discarded.
Bit 8: Transmit Voice Clock Invert (TVCLKI).
0 = TVCLK is not inverted
1 = TVCLK is inverted
Bits 3-7: Transmit Voice Octets Per Frame (TVOPF[4:0]). Controls the number of octets that are used for voice
traffic per frame. Note: Max. number of octets allowed to be used for voice is 16.
00001 = 1st byte after Frame sync is a voice channel.
00010 = 1st two bytes after Frame sync are voice channels
Bit 2: TSYNC Control (TSYNCC) This setting is necessary only if voice ports are enabled. TVSYNC MUST be a
frame sync.
0 = TSYNC is a frame sync. Voice bytes output to TDATA from Voice FIFO after every TSYNC.
1 = TSYNC is a multiframe sync. Voice output to TDATA from Voice FIFO based on PC bit.
Bit 1: Port Configuration (PC) Used to divide down multiframe sync to frame sync.
0 = Port is configured for T1.
1 = Port is configured for E1.
Bit 0: Transmit Port Enable (TPE)
0 = Port is Disabled
1 = Port is Enabled
Rev: 063008
270 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
LI.TVFSR
Register Description:
Register Address:
Serial Interface Transmit Voice FIFO Status Register
6C2h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
6C3h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
-
0
Bit 1
TVFU
0
Bit 0
TVFO
0
6C2h:
Default
Bit 1: Transmit Voice FIFO Underflow (TVFU) This bit is set during a Transmit Voice FIFO underflow. An
underflow condition results in a loss of data. This bit remains set as long as the underflow condition exists.
Bit 0: Transmit Voice FIFO Overflow (TVFO) – This bit is set during a Transmit Voice FIFO overflow. An overflow
condition results in a loss of data. This bit remains set as long as the overflow condition exists.
Register Name:
LI.TVFLSR
Register Description:
Register Address:
Serial Interface Transmit Voice FIFO Latched Status Register
6C4h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
6C5h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
-
0
Bit 1
TVFUL
0
Bit 0
TVFOL
0
6C4h:
Default
Bit 1: Transmit Voice FIFO Underflow Latched (TVFUL) This bit is set when a Transmit Voice FIFO underflow
condition occurs. An underflow condition results in a loss of data. This bit remains set as long as the underflow
condition exists.
Bit 0: Transmit Voice FIFO Overflow Latched (TVFOL) This bit is set when a Transmit Voice FIFO overflow
condition occurs. An overflow condition results in a loss of data. This bit remains set as long as the overflow
condition exists.
Rev: 063008
271 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
LI.TVFSRIE
Register Description:
Register Address:
Serial Interface Transmit Voice FIFO Interrupt Enable Register
6C8h
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
6C9h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
-
0
Bit 1
TVFULIE
0
Bit 0
TVFOLIE
0
6C8h:
Default
Bit 1: Transmit Voice FIFO Underflow Interrupt Enable (TVFULIE) This bit enables an interrupt if the TVFUL bit
is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 0: Transmit Voice FIFO Overflow Interrupt Enable (TVFOLIE) – This bit enables an interrupt if the TVFOL bit
is set .
0 = interrupt disabled
1 = interrupt enabled
Rev: 063008
272 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
10.8.5 Receive Per Serial Port Register Description
Register Name:
LI.RCR1
Register Description:
Register Address:
Serial Interface Receive Control Register 1
740h (+ 008h x (n-1), Physical Serial Port n=1 to 16)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
741h:
Default
0
0
0
0
0
0
0
0
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
RCLKINV
0
Bit 3
-
0
Bit 2
-
0
Bit 1
RFRST
0
Bit 0
-
0
740h:
Default
Bit 4: RCLKn Invert (RCLKINV)
0 = RCLKn is not inverted, RDATA samples on rising edge of RCLK.
1 = RCLKn is inverted, RDATA samples on falling edge of RCLK.
Bit 1: Receive FIFO Reset (RFRST)
0 = The Receive FIFO resumes normal operations
1 = Receive FIFO Reset. The FIFO is emptied, any transfer in progress is halted, the FIFO circuit is
powered down, the pointers are reset, and all incoming data is discarded.
Bit 0: Reserved. Set to 0 for proper operation.
Rev: 063008
273 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
10.8.6 Receive Voice Port Register Description
Register Name:
LI.RVPCR
Register Description:
Register Address:
Serial Interface Receive Voice Port Control Register
7C0h
Bit 15
Bit 14
Bit 13
Bit 12
-
0
Bit 11
-
0
Bit 10
-
0
Bit 9
RVFRST
0
Bit 8
RVCLKI
0
-
0
-
0
-
0
7C1h:
Default
Bit 7
RVOPF4
0
Bit 6
RVOPF3
0
Bit 5
RVOPF2
0
Bit 4
RVOPF1
0
Bit 3
RVOPF0
0
Bit 2
RSYNCC
0
Bit 1
PC
0
Bit 0
RPE
0
7C0h:
Default
Bit 9: Receive Voice FIFO Reset (RVFRST)
0 = The Receive Voice FIFO resumes normal operations
1 = Receive Voice FIFO Reset. The FIFO is emptied, any transfer in progress is halted, the FIFO circuit is
powered down, and all incoming data is discarded.
Bit 8: Receive Voice Clock Invert (RVCLKI)
0 = RVCLK is not inverted
1 = RVCLK is inverted
Bits 3-7: Receive Voice Octets Per Frame (RVOPF[4:0]). Controls the number of octets that are used for voice
traffic per frame. Note: Max. number of octets allowed to be used for voice is 16.
00001 = 1st byte after Frame sync is a voice channel.
00010 = 1st two bytes after Frame sync are voice channels…
Bit 2: RSYNC Control (RSYNCC). This setting is necessary only if voice ports are enabled. RVSYNC MUST be a
frame sync.
0 = RSYNC is a frame sync. Voice bytes inserted into Voice FIFO after every RSYNC.
1 = RSYNC is a multiframe sync. Voice bytes inserted into Voice FIFO based on PC register bit.
Bit 1: Port Configuration (PC). Used to divide down multiframe sync to frame sync.
0 = Port is configured for T1.
1 = Port is configured for E1.
Bit 0: Receive Port Enable (RPE)
0 = Port is Disabled
1 = Port is Enabled
Rev: 063008
274 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
10.8.7 MAC Registers
The control registers related to the control of the individual MACs are shown in the following Table. The device
keeps statistics for the packet traffic sent and received. Note that the addresses listed are the indirect addresses
that must be provided to SU.MAC1RADH/SU.MAC1RADL or SU.MAC1AWH/SU.MAC1AWL.
Register Name:
SU.MACCR
Register Description:
Register Address:
MAC Control Register
0000h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
0000h:
Default
Reserved
0
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
0
0
0
0
0
0
0
Bit 23
WDD
0
Bit 22
JD
0
Bit 21
FBE
0
Bit 20
JFE
0
Bit 19
Reserved Reserved
Bit 18
Bit 17
Reserved Reserved
Bit 16
0001h:
Default
0
0
0
0
Bit 15
GMIIMIIS
0
Bit 14
EM
0
Bit 13
DRO
0
Bit 12
LM
0
Bit 11
DM
0
Bit 10
Reserved
0
Bit 9
DRTY
0
Bit 8
APST
0
0002h:
Default
Bit 7
ACST
0
Bit 6
BOLMT1
0
Bit 5
BOLMT0
0
Bit 4
DC
0
Bit 3
TE
0
Bit 2
RE
0
Bit 1
Bit 0
0003h:
Default
Reserved Reserved
0
0
Bit 23: Watchdog Disable (WDD) - When set to 1, the watchdog timer on the receiver is disabled. When equal to
0, the MAC allows only 2048 bytes of data per frame.
Bit 22: Jabber Disable (JD) - When set to 1, the transmitter’s jabber timer is disabled. When equal to 0, the MAC
allows only 2048 bytes to be transmitter per frame.
Bit 21: Frame Burst Enable (FBE) – When set to 1, the MAC allows frame bursting during transmission in half-
duplex mode.
Bit 20: Jumbo Frame Enable (JFE) - When set to 1, the MAC allows the reception of frames up to 9018 bytes in
length without reporting a giant frame error in the receive frame status register. Frames between 9018 and 10240
bytes in length are passed with a giant frame error indication. Jabber Disable and Watchdog Disable bits should be
set to 1 to transmit and receive jumbo frames. This bit should be cleared when operating in full-duplex mode.
Bit 15: GMII / MII Selection (GMIIMIIS)
0 = GMII mode
1 = MII/RMII mode
Bit 14: Endian Mode (EM) - When set to 1, the MAC operates in Big-Endian Mode. When equal to 0, the MAC
operates in Little-Endian Mode. The Endian mode selection is applicable only for the transmit and receive data
paths.
Bit 13: Disable Receive Own (DRO) - When set to 1, the MAC disables the reception of frames while TX_EN is
asserted. When this bit equals zero, transmitted frames are also received by the MAC. This bit should be cleared
when operating in full-duplex mode.
Rev: 063008
275 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Bit 12: Loopback Mode (LM) - When set to 1, all frames destined for the transmit GMII/MII/RMII interface are
internally transferred to the receive GMII/MII/RMII. Frames received on the GMII/MII/RMII are not transferred to the
transmit GMII/MII/RMII interface. Note that there is no SA/DA swapping performed. If SA/DA swapping of LAN
traffic is required, the LAN extract/insertion functions must be used.
Bit 11: Duplex Mode (DM) - When set to 1, the MAC transmits and receives simultaneously (full-duplex).
Bit 9: Disable Retry (DRTY) - When set to 1, the MAC makes only a single attempt to transmit each frame. If a
collision occurs, the MAC ignores the current frame, reports a Frame Abort, reports an excessive collision error,
and proceeds to the next frame. When this bit equals 0, the MAC will retry collided frames based on the settings in
the Backoff Limit bits before signaling a retry error. This bit is applicable to half-duplex mode only.
Bit 8: Automatic Pad Stripping (APST) - When set to 1, all incoming frames with less than 46 byte length are
automatically stripped of the pad characters and FCS. When equal to zero, all frames are received unmodified.
Bit 7: Automatic CRC Stripping (ACST) - When set to 1, the MAC will strip the FCS field on incoming frames only
if the length field is less than or equal to 1500 bytes. All received frames with length field greater than 1500 bytes
will be passed to the receiver without stripping of the FCS field. When equal to zero, all frames are received
unmodified. For most applications of this device, this bit should equal 0.
Bits 5 - 6: Back-Off Limit (BOLMT[1:0])- These two bits allow the user to set the back-off limit used for the
maximum retransmission delay for collided frames. Default operation limits the maximum delay for retransmission
to a countdown of 10 bits from a random number generator. The user can reduce the maximum number of counter
bits as described in the table below. See IEEE 802.3 for details of the back-off algorithm.
Bit 7
Bit 6
Random Number Generator Bits Used
0
0
1
1
0
1
0
1
10
8
4
1
Bit 4: Deferral Check (DC) - When set to 1, the MAC will abort frame transmission if it has deferred for more than
24,288 bit times. The deferral counter starts when the transmitter is ready to transmit a frame, but is prevented
from transmission because RX_CRS is active. If the MAC begins transmission but a collision occurs after the
beginning of transmission, the deferral counter is reset again. If this bit is equal to zero, then the MAC will defer
indefinitely.
Bit 3: Transmitter Enable (TE) - When set to 1, frame transmission is enabled. When equal to zero, transmission
is disabled.
Bit 2: Receiver Enable (RE) - When set to 1, frame reception is enabled. When equal to zero, frames are not
received.
Rev: 063008
276 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.MACFFR
Register Description:
Register Address:
MAC Frame Filter Register
0004h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
0004h:
Default
RAF
0
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
0005h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Reserved
0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0006h:
Default
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
0
0
0
0
0
0
0
Bit 7
PCF
0
Bit 6
Reserve
Bit 5
DBF
0
Bit 4
PAM
0
Bit 3
INVF
0
Bit 2
HFUF
0
Bit 1
HFMF
0
Bit 0
PM
0
0007h:
d
0
Default
Bit 31: Receive All Frames (RAF) - When set to 1, the receiver forwards all frames to the device, even if they do
not pass the destination address filter. When equal to zero, the receiver only forwards those frames that pass the
destination address filter.
Bit 7: Pass Pause Control Frames (PCF) - When set to 1, the receiver forwards all special multicast PAUSE
control frames to the device. The MAC also decodes the PAUSE control frame and disables the transmitter for the
specified amount of time. When equal to zero, the MAC decodes the PAUSE control frame and disables the
transmitter for the specified amount of time, but does not forward the PAUSE frame to the device.
Bit 5: Disable Broadcast Frames (DBF) - When set to 1, the MAC filters all incoming Broadcast frames. When
equal to zero, all broadcast frames are forwarded to the device.
Bit 4: Pass All Multicast (PAM) - When set to 1, all received multicast frames (1st bit of DA = “1”) are forwarded,
irrespective of the settings of the Hash filter and Inverse Filtering bits.
Bit 3: Inverse Filtering (INVF) - When set to 1, the programmable DA filter operates in inverse filtering mode. The
result of the filtering operations by the Hash HFUF/HFMF bits is inverted. When equal to zero, filtering is
determined by the HFUF/HFMF bits.
Bit 2: Hash Mode for Unicast Frames (HFUF) - When set to 1, address filtering operates in the imperfect (hash)
address filtering mode for unicast frames, according to the hash table. When equal to zero, perfect address filtering
is performed on unicast frames using the addresses specified in the MAC address filter registers.
Bit 1: Hash Mode for Multicast Frames (HFMF) - When set to 1, address filtering operates in the imperfect (hash)
address filtering mode for multicast frames, according to the hash table. When this bit equals zero, perfect address
filtering is performed on multicast frames using the addresses specified in the MAC address filter registers.
Bit 0: Promiscuous Mode (PM) – When set to 1, all non-control frames are allowed to pass, including broadcast
frames, regardless of destination address.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
277 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.MACHTHR
Register Description:
Register Address:
MAC Hash Table High Register
0008h (indirect)
Bit 31
HTH[31]
0
Bit 30
HTH[30]
0
Bit 29
HTH[29]
0
Bit 28
HTH[28]
0
Bit 27
HTH[27]
0
Bit 26
HTH[26]
0
Bit 25
HTH[25]
0
Bit 24
HTH[24]
0
0008h:
Default
Bit 23
HTH[23]
0
Bit 22
HTH[22]
0
Bit 21
HTH[21]
0
Bit 20
HTH[20]
0
Bit 19
HTH[19]
0
Bit 18
HTH[18]
0
Bit 17
HTH[17]
0
Bit 16
HTH[16]
0
0009h:
Default
Bit 15
HTH[15]
0
Bit 14
HTH[14]
0
Bit 13
HTH[13]
0
Bit 12
HTH[12]
0
Bit 11
HTH[11]
0
Bit 10
HTH[10]
0
Bit 9
HTH[9]
0
Bit 8
HTH[8]
0
000Ah:
Default
Bit 7
HTH[7]
0
Bit 6
HTH[6]
0
Bit 5
HTH[5]
0
Bit 4
HTH[4]
0
Bit 3
HTH[3]
0
Bit 2
HTH[2]
0
Bit 1
HTH[1]
0
Bit 0
HTH[0]
0
000Bh:
Default
Bits 0-31: Hash Table High (HTH[31:0]) - Contains the upper 32 bits of the Hash table used for group address
filtering.
Register Name:
SU.MACHTLR
Register Description:
Register Address:
MAC Hash Table Low Register
000Ch (indirect)
Bit 31
HTL[31]
0
Bit 30
HTL[30]
0
Bit 29
HTL[29]
0
Bit 28
HTL[28]
0
Bit 27
HTL[27]
0
Bit 26
HTL[26]
0
Bit 25
HTL[25]
0
Bit 24
HTL[24]
0
000Ch:
Default
Bit 23
HTL[23]
0
Bit 22
HTL[22]
0
Bit 21
HTL[21]
0
Bit 20
HTL[20]
0
Bit 19
HTL[19]
0
Bit 18
HTL[18]
0
Bit 17
HTL[17]
0
Bit 16
HTL[16]
0
000Dh:
Default
Bit 15
HTL[15]
0
Bit 14
HTL[14]
0
Bit 13
HTL[13]
0
Bit 12
HTL[12]
0
Bit 11
HTL[11]
0
Bit 10
HTL[10]
0
Bit 9
HTL[9]
0
Bit 8
HTL[8]
0
000Eh:
Default
Bit 7
HTL[7]
0
Bit 6
HTL[6]
0
Bit 5
HTL[5]
0
Bit 4
HTL[4]
0
Bit 3
HTL[3]
0
Bit 2
HTL[2]
0
Bit 1
HTL[1]
0
Bit 0
HTL[0]
0
000Fh:
Default
Bits 0-31: Hash Table Low (HTL[31:0]) - Contains the upper 32 bits of the Hash table used for group address
filtering.
Rev: 063008
278 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.GMIIA
Register Description:
Register Address:
MAC MDIO Management Address Register
0010h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
0010h:
Default
Reserved
0
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
0011h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
PPA[4]
0
Bit 14
PPA[3]
0
Bit 13
PPA[2]
0
Bit 12
PPA[1]
0
Bit 11
PPA[0]
0
Bit 10
GM[4]
0
Bit 9
GM[3]
0
Bit 8
GM[2]
0
0012h:
Default
Bit 7
GM[1]
0
Bit 6
GM[0]
0
Bit 5
Reserved
0
Bit 4
Reserved
0
Bit 3
CR[1]
0
Bit 2
CR[0]
0
Bit 1
GW
0
Bit 0
GB
0
0013h:
Default
Bits 10-15: PHY Physical Layer Address (PPA[4:0]) - Contains the address of the PHY to be accessed.
Bits 6-9: PHY MDIO Register (GM[4:0]) - Contains the address of register within the PHY to be accessed.
Bits 2-3: Clock Range (CR[1:0]) - Selects MDC clock frequency.
00 = divide input clock by 42
01 = divide input clock by 62
10 = divide input clock by 16
11 = divide input clock by 26
Bit 1: PHY MDIO Write (GW) - When set to 1, a write operation will be performed. When equal to zero, a read
operation will be performed.
Bit 0: PHY GMII Busy (GB) - This bit should be set to 1 when writing to SU.GMIIA. The MAC will clear the bit
when it is no longer busy. Do not write to GMIIA or GMIID while this bit is still set to 1. During read operations,
the data in SU.GMIID is invalid until this bit is equal to 0.
Rev: 063008
279 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.GMIID
Register Description:
Register Address:
MAC MDIO Management Data Register
0014h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
0014h:
Default
Reserved
0
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
0015h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
GD[15]
0
Bit 14
GD[14]
0
Bit 13
GD[13]
0
Bit 12
GD[12]
0
Bit 11
GD[11]
0
Bit 10
GD[10]
0
Bit 9
GD[9]
0
Bit 8
GD[8]
0
0016h:
Default
Bit 7
GD[7]
0
Bit 6
GD[6]
0
Bit 5
GD[5]
0
Bit 4
GD[4]
0
Bit 3
GD[3]
0
Bit 2
GD[2]
0
Bit 1
GD[1]
0
Bit 0
GD[0]
0
0017h:
Default
Bits 0-15: MDIO Data (GD[15:0]) - Contains the 16-bit value read from the PHY after a management read
operation, or the 16-bit value to be written during a write operation.
Rev: 063008
280 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.MACFCR
Register Description:
Register Address:
MAC Flow Control Register
0018h (indirect)
Bit 31
PT[15]
0
Bit 30
PT[14]
0
Bit 29
PT[13]
0
Bit 28
PT[12]
0
Bit 27
PT[11]
0
Bit 26
PT[10]
0
Bit 25
PT[9]
0
Bit 24
PT[8]
0
0018h:
Default
Bit 23
PT[7]
0
Bit 22
PT[6]
0
Bit 21
PT[5]
0
Bit 20
PT[4]
0
Bit 19
PT[3]
0
Bit 18
PT[2]
0
Bit 17
PT[1]
0
Bit 16
PT[0]
0
0019h:
Default
Bit 15
Reserved
0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
001Ah:
Default
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
0
0
0
0
0
0
0
Bit 7
Reserved
0
Bit 6
Reserve
Bit 5
Reserved
0
Bit 4
PLT
0
Bit 3
UP
0
Bit 2
RFE
0
Bit 1
TFE
0
Bit 0
FCB
0
001Bh:
d
0
Default
Bits 16-31: Pause Time (PT[15:0]) - Contains the 16-bit value to be used in the time field in transmitted PAUSE
control frames.
Bit 4: Pause Low Threshold (PLT) - Set to 1 for 1000Mbps operation. Should equal 0 for 10/100Mbps operation.
Recommended settings for PT and PLT.
PT[0:15]
PLT
Time
Retransmit Rate
1 Pause Every
1.64ms
Application
Value
Time
Value
10Mbps
100Mbps
1Gbps (MPL <2049)
1Gbps (MPL > 2048)
176 slots
176 slots
44 slots
72 slots
9.01ms
901μs
90.1μs
147μs
0
0
1
1
7.37ms
737μs
73.7μs
131μs
164μs
16.4μs
16.4μs
Notes: “slots” are defined by the IEEE as the amount of time that it takes to transmit 64 bytes for 10/100Mbps and 512
bytes for 1000Mbps. Only the 10/100Mbps applications are applicable for the Port 2 MAC.
Bit 3: Unicast Pause Frame Detect (UP) - When set to 1, the MAC will detect Pause control frames with the
device’s unicast address, in addition to detecting Pause control frames with a multicast address. When equal to
zero, the MAC will only detect Pause control frames with the unique multicast address as specified in the 802.3x
standard.
Bit 2: Receive Flow Control Enable (RFE) - When set to 1, the MAC will receive Pause control frames and
disable the transmitter for the specified pause time. When this bit is equal to zero, the device will not respond to
Pause control frames.
Bit 1: Transmit Flow Control Enable (TFE) - When operating in Full-Duplex mode, if this bit is set, the MAC will
transmit Pause control frames as needed. When equal to zero, the MAC will not transmit Pause control frames.
Bit 0: Flow Control Busy (FCB) - This bit is equal to 1 when the transmission of a Pause control frame is in
progress. If the user writes a “1” to this bit, the device will transmit one Pause control frame.
Rev: 063008
281 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.VLANTR
Register Description:
Register Address:
MAC VLAN TAG REGISTER
001Ch (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
001Ch:
Default
Reserved
0
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
001Dh:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
VLTID[15]
VLTID[14]
VLTID[13]
VLTID[12]
VLTID[11]
VLTID[10]
VLTID[9]
VLTID[8]
001Eh:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VLTID[7]
VLTID[6]
VLTID[5]
VLTID[4]
VLTID[3]
VLTID[2]
VLTID[1]
VLTID[0]
001Fh:
Default
0
0
0
0
0
0
0
0
Bits 0-15: VLAN Tag ID (VLTID[15:0]) - Potentially not needed. Duplicated in other areas.
Rev: 063008
282 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ADDR0H
Register Description:
Register Address:
MAC FILTER ADDRESS 0 HIGH
0040h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR0AE
0040h:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
0041h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR0[47]
MADDR0[46]
MADDR0[45]
MADDR0[44]
MADDR0[43]
MADDR0[42]
MADDR0[41]
MADDR0[40]
0042h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR0[39]
MADDR0[38]
MADDR0[37]
MADDR0[36]
MADDR0[35]
MADDR0[34]
MADDR0[33]
MADDR0[32]
0043h:
Default
0
0
0
0
0
0
0
0
Bit 31: MAC Address Filter 0 Enable (MADDR0AE) - Must be set to 1 if address filtering is enabled.
Bits 0-15: MAC Address Filter 0 (MADDR0[47:32]) - Highest two bytes of MAC Filter Address 0.
Register Name:
SU.ADDR0L
Register Description:
Register Address:
MAC FILTER ADDRESS 0 LOW
0044h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR0[31]
MADDR0[30]
MADDR0[29]
MADDR0[28]
MADDR0[27]
MADDR0[26]
MADDR0[25]
MADDR0[24]
0044h:
Default
0
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
0045h:
MADDR0[23]
MADDR0[22]
MADDR0[21]
MADDR0[20]
MADDR0[19]
MADDR0[18]
MADDR0[17]
MADDR0[16]
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR0[15]
MADDR0[14]
MADDR0[13]
MADDR0[12]
MADDR0[11]
MADDR0[10]
MADDR0[9]
MADDR0[8]
0046h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR0[7]
MADDR0[6]
MADDR0[5]
MADDR0[4]
MADDR0[3]
MADDR0[2]
MADDR0[1]
MADDR0[0]
0047h:
Default
0
0
0
0
0
0
0
0
Bits 0-31: MAC Address Filter 0 (MADDR0[31:0]) - Lowest four bytes of MAC Filter Address 0.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
283 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ADDR1H
Register Description:
Register Address:
MAC FILTER ADDRESS 1 HIGH
0048h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR1AE
0048h:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
0049h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR1[47]
MADDR1[46]
MADDR1[45]
MADDR1[44]
MADDR1[43]
MADDR1[42]
MADDR1[41]
MADDR1[40]
004Ah:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR1[39]
MADDR1[38]
MADDR1[37]
MADDR1[36]
MADDR1[35]
MADDR1[34]
MADDR1[33]
MADDR1[32]
004Bh:
Default
0
0
0
0
0
0
0
0
Bit 31: MAC Address Filter 1 Enable (MADDR1AE)
0 = Address value not used for filtering.
1 = Address used for “perfect” filtering.
Bits 0-15: MAC Address Filter 1 (MADDR1[47:32]) - Highest two bytes of MAC Filter Address 1.
Register Name:
SU.ADDR1L
Register Description:
Register Address:
MAC FILTER ADDRESS 1 LOW
004Ch (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR1[31]
MADDR1[30]
MADDR1[29]
MADDR1[28]
MADDR1[27]
MADDR1[26]
MADDR1[25]
MADDR1[24]
004Ch:
Default
0
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
004Dh:
MADDR1[23]
MADDR1[22]
MADDR1[21]
MADDR1[20]
MADDR1[19]
MADDR1[18]
MADDR1[17]
MADDR1[16]
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR1[15]
MADDR1[14]
MADDR1[13]
MADDR1[12]
MADDR1[11]
MADDR1[10]
MADDR1[9]
MADDR1[8]
004Eh:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR1[7]
MADDR1[6]
MADDR1[5]
MADDR1[4]
MADDR1[3]
MADDR1[2]
MADDR1[1]
MADDR1[0]
004Fh:
Default
0
0
0
0
0
0
0
0
Bits 0-31: MAC Address Filter 1 (MADDR1[31:0]) - Lowest four bytes of MAC Filter Address 1.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
284 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ADDR2H
Register Description:
Register Address:
MAC FILTER ADDRESS 2 HIGH
0050h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR2AE
0050h:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
0051h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR2[47]
MADDR2[46]
MADDR2[45]
MADDR2[44]
MADDR2[43]
MADDR2[42]
MADDR2[41]
MADDR2[40]
0052h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR2[39]
MADDR2[38]
MADDR2[37]
MADDR2[36]
MADDR2[35]
MADDR2[34]
MADDR2[33]
MADDR2[32]
0053h:
Default
0
0
0
0
0
0
0
0
Bit 31: MAC Address Filter 2 Enable (MADDR2AE)
0 = Address value not used for filtering.
1 = Address used for “perfect” filtering.
Bits 0-15: MAC Address Filter 2 (MADDR2[47:32]) - Highest two bytes of MAC Filter Address 2.
Register Name:
SU.ADDR2L
Register Description:
Register Address:
MAC FILTER ADDRESS 2 LOW
0054h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR2[31]
MADDR2[30]
MADDR2[29]
MADDR2[28]
MADDR2[27]
MADDR2[26]
MADDR2[25]
MADDR2[24]
0054h:
Default
0
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
0055h:
MADDR2[23]
MADDR2[22]
MADDR2[21]
MADDR2[20]
MADDR2[19]
MADDR2[18]
MADDR2[17]
MADDR2[16]
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR2[15]
MADDR2[14]
MADDR2[13]
MADDR2[12]
MADDR2[11]
MADDR2[10]
MADDR2[9]
MADDR2[8]
0056h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR2[7]
MADDR2[6]
MADDR2[5]
MADDR2[4]
MADDR2[3]
MADDR2[2]
MADDR2[1]
MADDR2[0]
0057h:
Default
0
0
0
0
0
0
0
0
Bits 0-31: MAC Address Filter 2 (MADDR2[31:0]) - Lowest four bytes of MAC Filter Address 2.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
285 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ADDR3H
Register Description:
Register Address:
MAC FILTER ADDRESS 3 HIGH
0058h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR3AE
0058h:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
0059h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR3[47]
MADDR3[46]
MADDR3[45]
MADDR3[44]
MADDR3[43]
MADDR3[42]
MADDR3[41]
MADDR3[40]
005Ah:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR3[39]
MADDR3[38]
MADDR3[37]
MADDR3[36]
MADDR3[35]
MADDR3[34]
MADDR3[33]
MADDR3[32]
005Bh:
Default
0
0
0
0
0
0
0
0
Bit 31: MAC Address Filter 3 Enable (MADDR3AE)
0 = Address value not used for filtering.
1 = Address used for “perfect” filtering.
Bits 0-15: MAC Address Filter 3 (MADDR3[47:32]) - Highest two bytes of MAC Filter Address 3.
Register Name:
SU.ADDR3L
Register Description:
Register Address:
MAC FILTER ADDRESS 3 LOW
005Ch (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR3[31]
MADDR3[30]
MADDR3[29]
MADDR3[28]
MADDR3[27]
MADDR3[26]
MADDR3[25]
MADDR3[24]
005Ch:
Default
0
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
005Dh:
MADDR3[23]
MADDR3[22]
MADDR3[21]
MADDR3[20]
MADDR3[19]
MADDR3[18]
MADDR3[17]
MADDR3[16]
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR3[15]
MADDR3[14]
MADDR3[13]
MADDR3[12]
MADDR3[11]
MADDR3[10]
MADDR3[9]
MADDR3[8]
005Eh:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR3[7]
MADDR3[6]
MADDR3[5]
MADDR3[4]
MADDR3[3]
MADDR3[2]
MADDR3[1]
MADDR3[0]
005Fh:
Default
0
0
0
0
0
0
0
0
Bits 0-31: MAC Address Filter 3 (MADDR3[31:0]) - Lowest four bytes of MAC Filter Address 3.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
286 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ADDR4H
Register Description:
Register Address:
MAC FILTER ADDRESS 4 HIGH
0060h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR4AE
0060h:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
0061h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR4[47]
MADDR4[46]
MADDR4[45]
MADDR4[44]
MADDR4[43]
MADDR4[42]
MADDR4[41]
MADDR4[40]
0062h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR4[39]
MADDR4[38]
MADDR4[37]
MADDR4[36]
MADDR4[35]
MADDR4[34]
MADDR4[33]
MADDR4[32]
0063h:
Default
0
0
0
0
0
0
0
0
Bit 31: MAC Address Filter 4 Enable (MADDR4AE)
0 = Address value not used for filtering.
1 = Address used for “perfect” filtering.
Bits 0-15: MAC Address Filter 4 (MADDR4[47:32]) - Highest two bytes of MAC Filter Address 4.
Register Name:
SU.ADDR4L
Register Description:
Register Address:
MAC FILTER ADDRESS 4 LOW
0064h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR4[31]
MADDR4[30]
MADDR4[29]
MADDR4[28]
MADDR4[27]
MADDR4[26]
MADDR4[25]
MADDR4[24]
0064h:
Default
0
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
0065h:
MADDR4[23]
MADDR4[22]
MADDR4[21]
MADDR4[20]
MADDR4[19]
MADDR4[18]
MADDR4[17]
MADDR4[16]
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR4[15]
MADDR4[14]
MADDR4[13]
MADDR4[12]
MADDR4[11]
MADDR4[10]
MADDR4[9]
MADDR4[8]
0066h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR4[7]
MADDR4[6]
MADDR4[5]
MADDR4[4]
MADDR4[3]
MADDR4[2]
MADDR4[1]
MADDR4[0]
0067h:
Default
0
0
0
0
0
0
0
0
Bits 0-31: MAC Address Filter 4 (MADDR4[31:0]) - Lowest four bytes of MAC Filter Address 4.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
287 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ADDR5H
Register Description:
Register Address:
MAC FILTER ADDRESS 5 HIGH
0068h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR5AE
0068h:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
0069h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR5[47]
MADDR5[46]
MADDR5[45]
MADDR5[44]
MADDR5[43]
MADDR5[42]
MADDR5[41]
MADDR5[40]
006Ah:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR5[39]
MADDR5[38]
MADDR5[37]
MADDR5[36]
MADDR5[35]
MADDR5[34]
MADDR5[33]
MADDR5[32]
006Bh:
Default
0
0
0
0
0
0
0
0
Bit 31: MAC Address Filter 5 Enable (MADDR5AE)
0 = Address value not used for filtering.
1 = Address used for “perfect” filtering.
Bits 0-15: MAC Address Filter 5 (MADDR5[47:32]) - Highest two bytes of MAC Filter Address 5.
Register Name:
SU.ADDR5L
Register Description:
Register Address:
MAC FILTER ADDRESS 5 LOW
006Ch (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR5[31]
MADDR5[30]
MADDR5[29]
MADDR5[28]
MADDR5[27]
MADDR5[26]
MADDR5[25]
MADDR5[24]
006Ch:
Default
0
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
006Dh:
MADDR5[23]
MADDR5[22]
MADDR5[21]
MADDR5[20]
MADDR5[19]
MADDR5[18]
MADDR5[17]
MADDR5[16]
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR5[15]
MADDR5[14]
MADDR5[13]
MADDR5[12]
MADDR5[11]
MADDR5[10]
MADDR5[9]
MADDR5[8]
006Eh:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR5[7]
MADDR5[6]
MADDR5[5]
MADDR5[4]
MADDR5[3]
MADDR5[2]
MADDR5[1]
MADDR5[0]
006Fh:
Default
0
0
0
0
0
0
0
0
Bits 0-31: MAC Address Filter 5 (MADDR5[31:0]) - Lowest four bytes of MAC Filter Address 5.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
288 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ADDR6H
Register Description:
Register Address:
MAC FILTER ADDRESS 6 HIGH
0070h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR6AE
0070h:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
0071h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR6[47]
MADDR6[46]
MADDR6[45]
MADDR6[44]
MADDR6[43]
MADDR6[42]
MADDR6[41]
MADDR6[40]
0072h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR6[39]
MADDR6[38]
MADDR6[37]
MADDR6[36]
MADDR6[35]
MADDR6[34]
MADDR6[33]
MADDR6[32]
0073h:
Default
0
0
0
0
0
0
0
0
Bit 31: MAC Address Filter 6 Enable (MADDR6AE)
0 = Address value not used for filtering.
1 = Address used for “perfect” filtering.
Bits 0-15: MAC Address Filter 6 (MADDR6[47:32]) - Highest two bytes of MAC Filter Address 6.
Register Name:
SU.ADDR6L
Register Description:
Register Address:
MAC FILTER ADDRESS 6 LOW
0074h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR6[31]
MADDR6[30]
MADDR6[29]
MADDR6[28]
MADDR6[27]
MADDR6[26]
MADDR6[25]
MADDR6[24]
0071h:
Default
0
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
0072h:
MADDR6[23]
MADDR6[22]
MADDR6[21]
MADDR6[20]
MADDR6[19]
MADDR6[18]
MADDR6[17]
MADDR6[16]
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR6[15]
MADDR6[14]
MADDR6[13]
MADDR6[12]
MADDR6[11]
MADDR6[10]
MADDR6[9]
MADDR6[8]
0073h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR6[7]
MADDR6[6]
MADDR6[5]
MADDR6[4]
MADDR6[3]
MADDR6[2]
MADDR6[1]
MADDR6[0]
0074h:
Default
0
0
0
0
0
0
0
0
Bits 0-31: MAC Address Filter 6 (MADDR6[31:0]) - Lowest four bytes of MAC Filter Address 6.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
289 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ADDR7H
Register Description:
Register Address:
MAC FILTER ADDRESS 7 HIGH
0078h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR7AE
0078h:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
0079h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR7[47]
MADDR7[46]
MADDR7[45]
MADDR7[44]
MADDR7[43]
MADDR7[42]
MADDR7[41]
MADDR7[40]
007Ah:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR7[39]
MADDR7[38]
MADDR7[37]
MADDR7[36]
MADDR7[35]
MADDR7[34]
MADDR7[33]
MADDR7[32]
007Bh:
Default
0
0
0
0
0
0
0
0
Bit 31: MAC Address Filter 7 Enable (MADDR7AE)
0 = Address value not used for filtering.
1 = Address used for “perfect” filtering.
Bits 0-15: MAC Address Filter 7 (MADDR7[47:32]) - Highest two bytes of MAC Filter Address 7.
Register Name:
SU.ADDR7L
Register Description:
Register Address:
MAC FILTER ADDRESS 7 LOW
007Ch (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR7[31]
MADDR7[30]
MADDR7[29]
MADDR7[28]
MADDR7[27]
MADDR7[26]
MADDR7[25]
MADDR7[24]
007Ch:
Default
0
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
007Dh:
MADDR7[23]
MADDR7[22]
MADDR7[21]
MADDR7[20]
MADDR7[19]
MADDR7[18]
MADDR7[17]
MADDR7[16]
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR7[15]
MADDR7[14]
MADDR7[13]
MADDR7[12]
MADDR7[11]
MADDR7[10]
MADDR7[9]
MADDR7[8]
007Eh:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR7[7]
MADDR7[6]
MADDR7[5]
MADDR7[4]
MADDR7[3]
MADDR7[2]
MADDR7[1]
MADDR7[0]
007Fh:
Default
0
0
0
0
0
0
0
0
Bits 0-31: MAC Address Filter 7 (MADDR7[31:0]) - Lowest four bytes of MAC Filter Address 7.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
290 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ADDR8H
Register Description:
Register Address:
MAC FILTER ADDRESS 8 HIGH
0080h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR8AE
0080h:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
0081h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR8[47]
MADDR8[46]
MADDR8[45]
MADDR8[44]
MADDR8[43]
MADDR8[42]
MADDR8[41]
MADDR8[40]
0082h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR8[39]
MADDR8[38]
MADDR8[37]
MADDR8[36]
MADDR8[35]
MADDR8[34]
MADDR8[33]
MADDR8[32]
0083h:
Default
0
0
0
0
0
0
0
0
Bit 31: MAC Address Filter 8 Enable (MADDR8AE)
0 = Address value not used for filtering.
1 = Address used for “perfect” filtering.
Bits 0-15: MAC Address Filter 8 (MADDR8[47:32]) - Highest two bytes of MAC Filter Address 8.
Register Name:
SU.ADDR8L
Register Description:
Register Address:
MAC FILTER ADDRESS 8 LOW
0084h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR8[31]
MADDR8[30]
MADDR8[29]
MADDR8[28]
MADDR8[27]
MADDR8[26]
MADDR8[25]
MADDR8[24]
0084h:
Default
0
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
0085h:
MADDR8[23]
MADDR8[22]
MADDR8[21]
MADDR8[20]
MADDR8[19]
MADDR8[18]
MADDR8[17]
MADDR8[16]
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR8[15]
MADDR8[14]
MADDR8[13]
MADDR8[12]
MADDR8[11]
MADDR8[10]
MADDR8[9]
MADDR8[8]
0086h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR8[7]
MADDR8[6]
MADDR8[5]
MADDR8[4]
MADDR8[3]
MADDR8[2]
MADDR8[1]
MADDR8[0]
0087h:
Default
0
0
0
0
0
0
0
0
Bits 0-31: MAC Address Filter 8 (MADDR8[31:0]) - Lowest four bytes of MAC Filter Address 8.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
291 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ADDR9H
Register Description:
Register Address:
MAC FILTER ADDRESS 9 HIGH
0088h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR9AE
0088h:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
0089h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR9[47]
MADDR9[46]
MADDR9[45]
MADDR9[44]
MADDR9[43]
MADDR9[42]
MADDR9[41]
MADDR9[40]
008Ah:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR9[39]
MADDR9[38]
MADDR9[37]
MADDR9[36]
MADDR9[35]
MADDR9[34]
MADDR9[33]
MADDR9[32]
008Bh:
Default
0
0
0
0
0
0
0
0
Bit 31: MAC Address Filter 9 Enable (MADDR9AE)
0 = Address value not used for filtering.
1 = Address used for “perfect” filtering.
Bits 0-15: MAC Address Filter 9 (MADDR9[47:32]) - Highest two bytes of MAC Filter Address 9.
Register Name:
SU.ADDR9L
Register Description:
Register Address:
MAC FILTER ADDRESS 9 LOW
008Ch (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR9[31]
MADDR9[30]
MADDR9[29]
MADDR9[28]
MADDR9[27]
MADDR9[26]
MADDR9[25]
MADDR9[24]
008Ch:
Default
0
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
008Dh:
MADDR9[23]
MADDR9[22]
MADDR9[21]
MADDR9[20]
MADDR9[19]
MADDR9[18]
MADDR9[17]
MADDR9[16]
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR9[15]
MADDR9[14]
MADDR9[13]
MADDR9[12]
MADDR9[11]
MADDR9[10]
MADDR9[9]
MADDR9[8]
008Eh:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR9[7]
MADDR9[6]
MADDR9[5]
MADDR9[4]
MADDR9[3]
MADDR9[2]
MADDR9[1]
MADDR9[0]
008Fh:
Default
0
0
0
0
0
0
0
0
Bits 0-31: MAC Address Filter 9 (MADDR9[31:0]) - Lowest four bytes of MAC Filter Address 9.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
292 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ADDR10H
Register Description:
Register Address:
MAC FILTER ADDRESS 10 HIGH
0090h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR10AE
0090h:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
0091h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR10[47]
MADDR10[46]
MADDR10[45]
MADDR10[44]
MADDR10[43]
MADDR10[42]
MADDR10[41]
MADDR10[40]
0092h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR10[39] MADDR10[38]
MADDR10[37]
MADDR10[36]
MADDR10[35]
MADDR10[34]
MADDR10[33]
MADDR10[32]
0093h:
Default
0
0
0
0
0
0
0
0
Bit 31: MAC Address Filter 10 Enable (MADDR10AE)
0 = Address value not used for filtering.
1 = Address used for “perfect” filtering.
Bits 0-15: MAC Address Filter 10 (MADDR10[47:32]) - Highest two bytes of MAC Filter Address 10.
Register Name:
SU.ADDR10L
Register Description:
Register Address:
MAC FILTER ADDRESS 10 LOW
0094h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR10[31]
MADDR10[30]
MADDR10[29]
MADDR10[28]
MADDR10[27]
MADDR10[26]
MADDR10[25]
MADDR10[24]
0094h:
Default
0
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
0095h:
MADDR10[23]
MADDR10[22]
MADDR10[21]
MADDR10[20]
MADDR10[19]
MADDR10[18]
MADDR10[17]
MADDR10[16]
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR10[15]
MADDR10[14]
MADDR10[13]
MADDR10[12]
MADDR10[11]
MADDR10[10]
MADDR10[9]
MADDR10[8]
0096h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR10[7]
MADDR10[6]
MADDR10[5]
MADDR10[4]
MADDR10[3]
MADDR10[2]
MADDR10[1]
MADDR10[0]
0097h:
Default
0
0
0
0
0
0
0
0
Bits 0-31: MAC Address Filter 10 (MADDR10[31:0]) - Lowest four bytes of MAC Filter Address 10.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
293 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ADDR11H
Register Description:
Register Address:
MAC FILTER ADDRESS 11 HIGH
0098h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR11AE
0098h:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
0099h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR11[47]
MADDR11[46]
MADDR11[45]
MADDR11[44]
MADDR11[43]
MADDR11[42]
MADDR11[41]
MADDR11[40]
009Ah:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR11[39] MADDR11[38]
MADDR11[37]
MADDR11[36]
MADDR11[35]
MADDR11[34]
MADDR11[33]
MADDR11[32]
009Bh:
Default
0
0
0
0
0
0
0
0
Bit 31: MAC Address Filter 11 Enable (MADDR11AE)
0 = Address value not used for filtering.
1 = Address used for “perfect” filtering.
Bits 0-15: MAC Address Filter 11 (MADDR11[47:32]) - Highest two bytes of MAC Filter Address 11.
Register Name:
SU.ADDR11L
Register Description:
Register Address:
MAC FILTER ADDRESS 11 LOW
009Ch (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR11[31]
MADDR11[30]
MADDR11[29]
MADDR11[28]
MADDR11[27]
MADDR11[26]
MADDR11[25]
MADDR11[24]
009Ch:
Default
0
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
009Dh:
MADDR11[23]
MADDR11[22]
MADDR11[21]
MADDR11[20]
MADDR11[19]
MADDR11[18]
MADDR11[17]
MADDR11[16]
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR11[15]
MADDR11[14]
MADDR11[13]
MADDR11[12]
MADDR11[11]
MADDR11[10]
MADDR11[9]
MADDR11[8]
009Eh:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR11[7]
MADDR11[6]
MADDR11[5]
MADDR11[4]
MADDR11[3]
MADDR11[2]
MADDR11[1]
MADDR11[0]
009Fh:
Default
0
0
0
0
0
0
0
0
Bits 0-31: MAC Address Filter 11 (MADDR11[31:0]) - Lowest four bytes of MAC Filter Address 11.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
294 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ADDR12H
Register Description:
Register Address:
MAC FILTER ADDRESS 12 HIGH
00A0h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR12AE
00A0h:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
00A1h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR12[47]
MADDR12[46]
MADDR12[45]
MADDR12[44]
MADDR12[43]
MADDR12[42]
MADDR12[41]
MADDR12[40]
00A2h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR12[39] MADDR12[38]
MADDR12[37]
MADDR12[36]
MADDR12[35]
MADDR12[34]
MADDR12[33]
MADDR12[32]
00A3h:
Default
0
0
0
0
0
0
0
0
Bit 31: MAC Address Filter 12 Enable (MADDR12AE)
0 = Address value not used for filtering.
1 = Address used for “perfect” filtering.
Bits 0-15: MAC Address Filter 12 (MADDR12[47:32]) - Highest two bytes of MAC Filter Address 12.
Register Name:
SU.ADDR12L
Register Description:
Register Address:
MAC FILTER ADDRESS 12 LOW
00A4h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR12[31]
MADDR12[30]
MADDR12[29]
MADDR12[28]
MADDR12[27]
MADDR12[26]
MADDR12[25]
MADDR12[24]
00A4h:
Default
0
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
00A5h:
MADDR12[23]
MADDR12[22]
MADDR12[21]
MADDR12[20]
MADDR12[19]
MADDR12[18]
MADDR12[17]
MADDR12[16]
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR12[15]
MADDR12[14]
MADDR12[13]
MADDR12[12]
MADDR12[11]
MADDR12[10]
MADDR12[9]
MADDR12[8]
00A6h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR12[7]
MADDR12[6]
MADDR12[5]
MADDR12[4]
MADDR12[3]
MADDR12[2]
MADDR12[1]
MADDR12[0]
00A7h:
Default
0
0
0
0
0
0
0
0
Bits 0-31: MAC Address Filter 12 (MADDR12[31:0]) - Lowest four bytes of MAC Filter Address 12.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
295 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ADDR13H
Register Description:
Register Address:
MAC FILTER ADDRESS 13 HIGH
00A8h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR13AE
00A8h:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
00A9h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR13[47]
MADDR13[46]
MADDR13[45]
MADDR13[44]
MADDR13[43]
MADDR13[42]
MADDR13[41]
MADDR13[40]
00AAh:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR13[39] MADDR13[38]
MADDR13[37]
MADDR13[36]
MADDR13[35]
MADDR13[34]
MADDR13[33]
MADDR13[32]
00ABh:
Default
0
0
0
0
0
0
0
0
Bit 31: MAC Address Filter 13 Enable (MADDR13AE)
0 = Address value not used for filtering.
1 = Address used for “perfect” filtering.
Bits 0-15: MAC Address Filter 13 (MADDR13[47:32]) - Highest two bytes of MAC Filter Address 13.
Register Name:
SU.ADDR13L
Register Description:
Register Address:
MAC FILTER ADDRESS 13 LOW
00ACh (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR13[31]
MADDR13[30]
MADDR13[29]
MADDR13[28]
MADDR13[27]
MADDR13[26]
MADDR13[25]
MADDR13[24]
00ACh:
Default
0
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
00ADh:
MADDR13[23]
MADDR13[22]
MADDR13[21]
MADDR13[20]
MADDR13[19]
MADDR13[18]
MADDR13[17]
MADDR13[16]
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR13[15]
MADDR13[14]
MADDR13[13]
MADDR13[12]
MADDR13[11]
MADDR13[10]
MADDR13[9]
MADDR13[8]
00AEh:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR13[7]
MADDR13[6]
MADDR13[5]
MADDR13[4]
MADDR13[3]
MADDR13[2]
MADDR13[1]
MADDR13[0]
00AFh:
Default
0
0
0
0
0
0
0
0
Bits 0-31: MAC Address Filter 13 (MADDR13[31:0]) - Lowest four bytes of MAC Filter Address 13.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
296 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ADDR14H
Register Description:
Register Address:
MAC FILTER ADDRESS 14 HIGH
00B0h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR14AE
00B0h:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
00B1h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR14[47]
MADDR14[46]
MADDR14[45]
MADDR14[44]
MADDR14[43]
MADDR14[42]
MADDR14[41]
MADDR14[40]
00B2h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR14[39] MADDR14[38]
MADDR14[37]
MADDR14[36]
MADDR14[35]
MADDR14[34]
MADDR14[33]
MADDR14[32]
00B3h:
Default
0
0
0
0
0
0
0
0
Bit 31: MAC Address Filter 14 Enable (MADDR14AE)
0 = Address value not used for filtering.
1 = Address used for “perfect” filtering.
Bits 0-15: MAC Address Filter 14 (MADDR14[47:32]) - Highest two bytes of MAC Filter Address 14.
Register Name:
SU.ADDR14L
Register Description:
Register Address:
MAC FILTER ADDRESS 14 LOW
00B4h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR14[31]
MADDR14[30]
MADDR14[29]
MADDR14[28]
MADDR14[27]
MADDR14[26]
MADDR14[25]
MADDR14[24]
00B4h:
Default
0
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
00B5h:
MADDR14[23]
MADDR14[22]
MADDR14[21]
MADDR14[20]
MADDR14[19]
MADDR14[18]
MADDR14[17]
MADDR14[16]
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR14[15]
MADDR14[14]
MADDR14[13]
MADDR14[12]
MADDR14[11]
MADDR14[10]
MADDR14[9]
MADDR14[8]
00B6h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR14[7]
MADDR14[6]
MADDR14[5]
MADDR14[4]
MADDR14[3]
MADDR14[2]
MADDR14[1]
MADDR14[0]
00B7h:
Default
0
0
0
0
0
0
0
0
Bits 0-31: MAC Address Filter 14 (MADDR14[31:0]) - Lowest four bytes of MAC Filter Address 14.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
297 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ADDR15H
Register Description:
Register Address:
MAC FILTER ADDRESS 15 HIGH
00B8h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR15AE
00B8h:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
00B9h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR15[47]
MADDR15[46]
MADDR15[45]
MADDR15[44]
MADDR15[43]
MADDR15[42]
MADDR15[41]
MADDR15[40]
00BAh:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR15[39] MADDR15[38]
MADDR15[37]
MADDR15[36]
MADDR15[35]
MADDR15[34]
MADDR15[33]
MADDR15[32]
00BBh:
Default
0
0
0
0
0
0
0
0
Bit 31: MAC Address Filter 15 Enable (MADDR15AE)
0 = Address value not used for filtering.
1 = Address used for “perfect” filtering.
Bits 0-15: MAC Address Filter 15 (MADDR15[47:32]) - Highest two bytes of MAC Filter Address 15.
Register Name:
SU.ADDR15L
Register Description:
Register Address:
MAC FILTER ADDRESS 15 LOW
00BCh (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
MADDR15[31]
MADDR15[30]
MADDR15[29]
MADDR15[28]
MADDR15[27]
MADDR15[26]
MADDR15[25]
MADDR15[24]
00B5h:
Default
0
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
00B6h:
MADDR15[23]
MADDR15[22]
MADDR15[21]
MADDR15[20]
MADDR15[19]
MADDR15[18]
MADDR15[17]
MADDR15[16]
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
MADDR15[15]
MADDR15[14]
MADDR15[13]
MADDR15[12]
MADDR15[11]
MADDR15[10]
MADDR15[9]
MADDR15[8]
00B7h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MADDR15[7]
MADDR15[6]
MADDR15[5]
MADDR15[4]
MADDR15[3]
MADDR15[2]
MADDR15[1]
MADDR15[0]
00B8h:
Default
0
0
0
0
0
0
0
0
Bits 0-31: MAC Address Filter 15 (MADDR15[31:0]) - Lowest four bytes of MAC Filter Address 15.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
298 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.PCSCR
Register Description:
Register Address:
MAC PHYSICAL CODING SUBLAYER (PCS) CONTROL REGISTER
00C0h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
00C0h:
Default
Reserved
0
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved
0
Bit 16
ECD
0
00C1h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
Bit 15
Reserved
0
Bit 14
ELE
0
Bit 13
ANE
0
Bit 12
Bit 11
Bit 10
Bit 9
RAN
0
Bit 8
Reserved
0
00C2h:
Default
Reserved Reserved Reserved
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00C3h:
Reserved Reserved Reserved
Reserved Reserved Reserved
Reserved Reserved
Default
0
0
0
0
0
0
0
0
This register configures and initiates auto-negotiation of the external PHY device. It also enables PHY loopback.
Bit 16: Enable Comma Detect (ECD) - When set to 1, the MAC is enabled for comma detection and word
resynchronization.
Bit 14: External Loopback Enable (ELE) - When set to 1, causes the external PHY to loopback the transmit data
to the receiver.
Bit 13: Auto-Negotiation Enable (ANE) - When set to 1, the MAC will automatically negotiate the link speed with
the remote node. When equal to zero, auto-negotiation is disabled.
Bit 9: Restart Auto-Negotiation (RAN) - When set to 1 and ANE=1, the MAC will initiate auto-negotiation. This bit
will clear itself after auto-negotiation is started. Should be equal to zero during normal operation.
Rev: 063008
299 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.ANSR
Register Description:
Register Address:
MAC AUTO-NEGOTIATION STATUS REGISTER
00C4h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
00C4h:
Default
Reserved
0
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
00C5h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Reserved
0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Reserved
0
Bit 8
ES
1
00C6h:
Default
Reserved Reserved Reserved Reserved Reserved
0
0
0
0
0
Bit 7
Bit 6
Bit 5
ANC
0
Bit 4
Reserved
0
Bit 3
ANS
1
Bit 2
LS
0
Bit 1
Bit 0
00C7h:
Default
Reserved Reserved
Reserved Reserved
0
0
0
0
Bit 8: MAC Extended Status Support (ES) - This bit is always set to 1, to indicate that the MAC supports
extended status information.
Bit 5: Auto-Negotiation Complete (ANC) - This bit is set to 1 when auto-negotiation is complete. The bit is equal
to zero after auto-negotiation is initiated, and remains zero until completion of auto-negotiation.
Bit 3: Auto-Negotiation Support (ANS) - This bit is always set to 1, to indicate that the MAC supports extended
auto-negotiation.
Bit 2: Link Status (LS) - When set to 1, this bit indicates that the Ethernet link is connected. This bit is only
updated after a read operation. In order to see the current status, the bit must be read twice.
Rev: 063008
300 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.LSR
Register Description:
Register Address:
MAC MII/RMII/GMII STATUS REGISTER
00D8h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
00D8h:
Default
Reserved
0
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
00D9h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Reserved
0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
00DAh:
Default
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
0
Bit 3
Bit 2
Bit 1
Bit 0
LINKM
0
00DBh:
Default
Reserved Reserved Reserved
LINKUP LNKSPD[1] LNKSPD[0]
0
0
0
0
0
0
Bit 3: MII/RMII/GMII Link Status (LINKUP) – When equal to 1, the link is communicating. When equal to zero, the
link is not operational.
Bits 1-2: Link Speed (LNKSPD[1:0]) – Indicates the current link speed.
00 = 2.5MHz
01 = 25MHz
10 = 125MHz
Bit 0: Link Mode (LINKM) – Indicates the current link mode.
0 = Half-Duplex
1 = Full-Duplex
Rev: 063008
301 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.MMCCTRL
Register Description:
Register Address:
MAC MANAGEMENT COUNTER CONTROL REGISTER
0100h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
0100h:
Default
Reserved
0
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
0
0
0
0
0
0
0
Bit 23
Reserved
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved Reserved
Bit 16
0101h:
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
Bit 15
Reserved
0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0102h:
Default
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ROR
0
Bit 1
CSR
0
Bit 0
CRST
0
0103h:
Default
Reserved Reserved Reserved
Reserved Reserved
0
0
0
0
0
Bit 2: Reset on Read (ROR) – When set to 1, each management counter will reset to zero after a read access of
the least-significant byte. When equal to zero, the counters will only be reset by the CRST bit.
Bit 1: Counter Stop Rollover (CSR) – When set to 1, each counter will saturate at the maximum value and not roll
over. When equal to zero, each counter can rollover to zero after the maximum value is exceeded.
Bit 0: Counter Reset (CRST) – Set to 1 to initiate a reset of all management counters. Set to zero for normal
operation.
0 = Normal operation.
1 = Reset all management counters.
Rev: 063008
302 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.MMCRSR
Register Description:
Register Address:
MAC MANAGEMENT COUNTER RECEIVE STATUS REGISTER
0104h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
0104h:
Default
Reserved
0
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
0105h:
RXWDOG
RXVLAN
RXOVFL
RXPAUSE
RXRANGE
RXLNERR
RXUFC
RX1K_MAX
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RX512_1K
RX256_511
RX128_255
RX65_127
RX0_64
RXOVRSZ
RXUNDRSZ
RXJBBR
0106h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXRUNT
RXALGN
RXCRC
RXMFC
RXGBFC
RXGBC
RXBC
RXFC
0107h:
Default
0
0
0
0
0
0
0
0
Bits 1-23: Receive Counter Half-Full Status – Each bit is set to 1 when the corresponding MAC MMC counter
reaches half of the maximum value.
Register Name:
SU.MMCTSR
Register Description:
Register Address:
MAC MANAGEMENT COUNTER TRANSMIT STATUS REGISTER
0108h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Reserved
0
Bit 24
TXVLAN
0108h:
Reserved
0
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
0109h:
TXPAUSE
TXXCSVDF
TXFCNT
TXBCNT
TXCERR
TXXCSVCL
TXLTCL
TXDFRD
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXMLTICL
TXSNGLCL
TXUFE
TXBFC
TXMFC
TXUCAST
TX1K_MAX
TX512_1K
010Ah:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX256_511
TX128_255
TX65_127
TX0_64
TXGMFC
TXGBFC
TXFC
TXBC
010Bh:
Default
0
0
0
0
0
0
0
0
Bits 1-24: Transmit Counter Half-Full Status – Each bit is set to 1 when the corresponding MAC MMC counter
reaches half of the maximum value.
Rev: 063008
303 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.MMCRIM
Register Description:
Register Address:
MAC MANAGEMENT COUNTER RECEIVE INTERRUPT MASK
010Ch (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
010Ch:
Default
Reserved
0
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
0
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
010Dh:
RXWDOG
RXVLAN
RXOVFL
RXPAUSE
RXRANGE
RXLNERR
RXUCAST
RX1K_MAX
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RX512_1K
RX256_511
RX128_255
RX65_127
RX0_64
RXOVRSZ
RXUNDRSZ
RXJBBR
010Eh:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXRUNT
RXALGN
RXCRC
RXMFC
RXGBFC
RXGBC
RXBC
RXFC
010Fh:
Default
0
0
0
0
0
0
0
0
Bits 1-23: Receive Counter Half-Full Interrupt Mask
0 = The corresponding bit in SU.MMCRSR can generate an interrupt.
1 = The corresponding bit in SU.MMCRSR is masked, and will not generate an interrupt.
Register Name:
SU.MMCTIM
Register Description:
Register Address:
MAC MANAGEMENT COUNTER TRANSMIT INTERRUPT MASK
0110h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Reserved
0
Bit 24
TXVLAN
0110h:
Reserved
0
Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
0111h:
TXPAUSE
TXXCSVDF
TXFCNT
TXBCNT
TXCERR
TXXCSVCL
TXLTCL
TXDFRD
Default
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXMLTICL
TXSNGLCL
TXUFE
TXBFC
TXMFC
TXUCAST
TX1K_MAX
TX512_1K
0112h:
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX256_511
TX128_255
TX65_127
TX0_64
TXGMFC
TXGBFC
TXFC
TXBC
0113h:
Default
0
0
0
0
0
0
0
0
Bits 1-24: Transmit Counter Half-Full Interrupt Mask
0 = The corresponding bit in SU.MMCTSR can generate an interrupt.
1 = The corresponding bit in SU.MMCTSR is masked, and will not generate an interrupt.
Rev: 063008
304 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.TXBC
Register Description:
Register Address:
MAC MMC TRANSMIT BYTE COUNTER
0114h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXBC[31]
TXBC[30]
TXBC[29]
TXBC[28]
TXBC[27]
TXBC[26]
TXBC[25]
TXBC[24]
0114h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXBC[23]
TXBC[22]
TXBC[21]
TXBC[20]
TXBC[19]
TXBC[18]
TXBC[17]
TXBC[16]
0115h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXBC[15]
TXBC[14]
TXBC[13]
TXBC[12]
TXBC[11]
TXBC[10]
TXBC[9]
TXBC[8]
0116h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXBC[7]
TXBC[6]
TXBC[5]
TXBC[4]
TXBC[3]
TXBC[2]
TXBC[1]
TXBC[0]
0117h:
Bits 1-31: Transmit Byte Counter (TXBC[31:0]) – Contains the number of bytes (octets) transmitted, exclusive of
both preamble and retried bytes, in both good and bad frames.
Register Name:
SU.TXFC
Register Description:
Register Address:
MAC MMC TRANSMIT FRAME COUNTER
0118h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXFC[31]
TXFC[30]
TXFC[29]
TXFC[28]
TXFC[27]
TXFC[26]
TXFC[25]
TXFC[24]
0118h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXFC[23]
TXFC[22]
TXFC[21]
TXFC[20]
TXFC[19]
TXFC[18]
TXFC[17]
TXFC[16]
0119h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXFC[15]
TXFC[14]
TXFC[13]
TXFC[12]
TXFC[11]
TXFC[10]
TXFC[9]
TXFC[8]
011Ah:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXFC[7]
TXFC[6]
TXFC[5]
TXFC[4]
TXFC[3]
TXFC[2]
TXFC[1]
TXFC[0]
011Bh:
Bits 1-31: Transmit Frame Counter (TXFC[31:0]) – Contains the number of frames transmitted, including both
good and bad frames.
Rev: 063008
305 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.TXGBFC
Register Description:
Register Address:
MAC MMC TRANSMIT GOOD BROADCAST FRAMES COUNTER
011Ch (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXGBFC[31]
TXGBFC[30] TXGBFC[29] TXGBFC[28] TXGBFC[27] TXGBFC[26]
TXGBFC[25] TXGBFC[24]
011Ch:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXGBFC[23]
TXGBFC[22] TXGBFC[21] TXGBFC[20] TXGBFC[19] TXGBFC[18]
TXGBFC[17] TXGBFC[16]
011Dh:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXGBFC[15]
TXGBFC[14] TXGBFC[13] TXGBFC[12] TXGBFC[11] TXGBFC[10]
TXGBFC[9]
TXGBFC[8]
011Eh:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXGBFC[7]
TXGBFC[6]
TXGBFC[5]
TXGBFC[4]
TXGBFC[3]
TXGBFC[2]
TXGBFC[1]
TXGBFC[0]
011Fh:
Bits 1-31: Transmit Good Broadcast Frames Counter (TXGBFC[31:0]) – Contains the number of good
broadcast frames transmitted, exclusive of both preamble and retried bytes. Does not contain bad frames.
Register Name:
SU.TXGMFC
Register Description:
Register Address:
MAC MMC TRANSMIT GOOD MULTICAST FRAMES COUNTER
0120h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXGMFC[31] TXGMFC[30] TXGMFC[29] TXGMFC[28] TXGMFC[27] TXGMFC[26] TXGMFC[25] TXGMFC[24]
0120h:
0121h:
0122h:
0123h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXGMFC[23] TXGMFC[22] TXGMFC[21] TXGMFC[20] TXGMFC[19] TXGMFC[18] TXGMFC[17] TXGMFC[16]
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXGMFC[15] TXGMFC[14] TXGMFC[13] TXGMFC[12] TXGMFC[11] TXGMFC[10]
TXGMFC[9]
TXGMFC[8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXGMFC[7]
TXGMFC[6]
TXGMFC[5]
TXGMFC[4]
TXGMFC[3]
TXGMFC[2]
TXGMFC[1]
TXGMFC[0]
Bits 1-31: Transmit Good Multicast Frames Counter (TXGMFC[31:0]) – Contains the number of good multicast
frames transmitted.
Rev: 063008
306 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.TX0_64
Register Description:
Register Address:
MAC MMC TRANSMIT 0-64 BYTE FRAME COUNTER
0124h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TX0_64[31]
TX0_64[30]
TX0_64[29]
TX0_64[28]
TX0_64[27]
TX0_64[26]
TX0_64[25]
TX0_64[24]
0124h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TX0_64[23]
TX0_64[22]
TX0_64[21]
TX0_64[20]
TX0_64[19]
TX0_64[18]
TX0_64[17]
TX0_64[16]
0125h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TX0_64[15]
TX0_64[14]
TX0_64[13]
TX0_64[12]
TX0_64[11]
TX0_64[10]
TX0_64[9]
TX0_64[8]
0126h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX0_64[7]
TX0_64[6]
TX0_64[5]
TX0_64[4]
TX0_64[3]
TX0_64[2]
TX0_64[1]
TX0_64[0]
0127h:
Bits 1-31: Transmit 0-64 Byte Frames Counter (TX0_64[31:0]) – Contains the number of frames transmitted with
sizes of 64 bytes or less. Includes both good and bad frames.
Register Name:
SU.TX65_127
Register Description:
Register Address:
MAC MMC TRANSMIT 65-127 BYTE FRAMES COUNTER
0128h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TX65_127[31] TX65_127[30] TX65_127[29] TX65_127[28] TX65_127[27] TX65_127[26] TX65_127[25] TX65_127[24]
0128h:
0129h:
012Ah:
012Bh:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TX65_127[23] TX65_127[22] TX65_127[21] TX65_127[20] TX65_127[19] TX65_127[18] TX65_127[17] TX65_127[16]
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TX65_127[15] TX65_127[14] TX65_127[13] TX65_127[12] TX65_127[11] TX65_127[10] TX65_127[9] TX65_127[8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX65_127[7] TX65_127[6] TX65_127[5]
TX65_127[4] TX65_127[3] TX65_127[2]
TX65_127[1] TX65_127[0]
Bits 1-31: Transmit 65-127 Byte Frames Counter (TX65_127[31:0]) – Contains the number of frames
transmitted with sizes of 65 to 127 bytes. Includes both good and bad frames.
Rev: 063008
307 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.TX128_255
Register Description:
Register Address:
MAC MMC TRANSMIT 128-255 BYTE FRAME COUNTER
012Ch (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TX128_255[31]
TX128_255[30] TX128_255[29] TX128_255[28] TX128_255[27] TX128_255[26]
TX128_255[25] TX128_255[24]
012Ch:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TX128_255[23]
TX128_255[22] TX128_255[21] TX128_255[20] TX128_255[19] TX128_255[18]
TX128_255[17] TX128_255[16]
012Dh:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TX128_255[15]
TX128_255[14] TX128_255[13] TX128_255[12] TX128_255[11] TX128_255[10]
TX128_255[9]
TX128_255[8]
012Eh:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX128_255[7]
TX128_255[6]
TX128_255[5]
TX128_255[4]
TX128_255[3]
TX128_255[2]
TX128_255[1]
TX128_255[0]
012Fh:
Bits 1-31: Transmit 128-255 Byte Frames Counter (TX128_255[31:0]) – Contains the number of frames
transmitted with sizes of 128 to 255 bytes. Includes both good and bad frames.
Register Name:
SU.TX256_511
Register Description:
Register Address:
MAC MMC TRANSMIT 256-511 BYTE FRAMES COUNTER
0130h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TX256_511[31]
TX256_511[30] TX256_511[29] TX256_511[28] TX256_511[27] TX256_511[26]
TX256_511[25] TX256_511[24]
0130h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TX256_511[23]
TX256_511[22] TX256_511[21] TX256_511[20] TX256_511[19] TX256_511[18]
TX256_511[17] TX256_511[16]
0131h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TX256_511[15]
TX256_511[14] TX256_511[13] TX256_511[12] TX256_511[11] TX256_511[10]
TX256_511[9]
TX256_511[8]
0132h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX256_511[7]
TX256_511[6]
TX256_511[5]
TX256_511[4]
TX256_511[3]
TX256_511[2]
TX256_511[1]
TX256_511[0]
0133h:
Bits 1-31: Transmit 256-511 Byte Frames Counter (TX256_511[31:0]) – Contains the number of frames
transmitted with sizes of 256 to 511 bytes. Includes both good and bad frames.
Rev: 063008
308 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.TX512_1K
Register Description:
Register Address:
MAC MMC TRANSMIT 512-1023 BYTE FRAME COUNTER
0134h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TX512_1K[31]
TX512_1K[30]
TX512_1K[29]
TX512_1K[28]
TX512_1K[27]
TX512_1K[26]
TX512_1K[25]
TX512_1K[24]
0134h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TX512_1K[23]
TX512_1K[22]
TX512_1K[21]
TX512_1K[20]
TX512_1K[19]
TX512_1K[18]
TX512_1K[17]
TX512_1K[16]
0135h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TX512_1K[15]
TX512_1K[14]
TX512_1K[13]
TX512_1K[12]
TX512_1K[11]
TX512_1K[10]
TX512_1K[9]
TX512_1K[8]
0136h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX512_1K[7]
TX512_1K[6]
TX512_1K[5]
TX512_1K[4]
TX512_1K[3]
TX512_1K[2]
TX512_1K[1]
TX512_1K[0]
0137h:
Bits 1-31: Transmit 512-1023 Byte Frames Counter (TX512_1K[31:0]) – Contains the number of frames
transmitted with sizes of 512 to 1023 bytes. Includes both good and bad frames.
Register Name:
SU.TX1K_MAX
Register Description:
Register Address:
MAC MMC TRANSMIT 1024-MAX BYTE FRAMES COUNTER
0138h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TX1K_MAX[31] TX1K_MAX[30] TX1K_MAX[29] TX1K_MAX[28] TX1K_MAX[27] TX1K_MAX[26]
TX1K_MAX[25] TX1K_MAX[24]
0138h:
0139h:
013Ah:
013Bh:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TX1K_MAX[23] TX1K_MAX[22] TX1K_MAX[21] TX1K_MAX[20] TX1K_MAX[19] TX1K_MAX[18]
TX1K_MAX[17] TX1K_MAX[16]
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TX1K_MAX[15] TX1K_MAX[14] TX1K_MAX[13] TX1K_MAX[12] TX1K_MAX[11] TX1K_MAX[10]
TX1K_MAX[9]
TX1K_MAX[8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX1K_MAX[7]
TX1K_MAX[6]
TX1K_MAX[5]
TX1K_MAX[4]
TX1K_MAX[3]
TX1K_MAX[2]
TX1K_MAX[1]
TX1K_MAX[0]
Bits 1-31: Transmit 1024-MAX Byte Frames Counter (TX1K_MAX[31:0]) – Contains the number of frames
transmitted with sizes of 1024 to the maximum allowed bytes. Includes both good and bad frames.
Rev: 063008
309 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.TXUCAST
Register Description:
Register Address:
MAC MMC TRANSMIT UNICAST FRAME COUNTER
013Ch (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXUCAST[31]
TXUCAST[30]
TXUCAST[29]
TXUCAST[28]
TXUCAST[27]
TXUCAST[26]
TXUCAST[25]
TXUCAST[24]
013Ch:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXUCAST[23]
TXUCAST[22]
TXUCAST[21]
TXUCAST[20]
TXUCAST[19]
TXUCAST[18]
TXUCAST[17]
TXUCAST[16]
013Dh:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXUCAST[15]
TXUCAST[14]
TXUCAST[13]
TXUCAST[12]
TXUCAST[11]
TXUCAST[10]
TXUCAST[9]
TXUCAST[8]
013Eh:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXUCAST[7]
TXUCAST[6]
TXUCAST[5]
TXUCAST[4]
TXUCAST[3]
TXUCAST[2]
TXUCAST[1]
TXUCAST[0]
013Fh:
Bits 1-31: Transmit Unicast Frames Counter (TXUCAST[31:0]) – Contains the number of frames transmitted
with a unicast address. Includes both good and bad frames.
Register Name:
SU.TXMFC
Register Description:
Register Address:
MAC MMC TRANSMIT MULTICAST FRAMES COUNTER
0140h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXMFC[31]
TXMFC[30]
TXMFC[29]
TXMFC[28]
TXMFC[27]
TXMFC[26]
TXMFC[25]
TXMFC[24]
0140h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXMFC[23]
TXMFC[22]
TXMFC[21]
TXMFC[20]
TXMFC[19]
TXMFC[18]
TXMFC[17]
TXMFC[16]
0141h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXMFC[15]
TXMFC[14]
TXMFC[13]
TXMFC[12]
TXMFC[11]
TXMFC[10]
TXMFC[9]
TXMFC[8]
0142h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXMFC[7]
TXMFC[6]
TXMFC[5]
TXMFC[4]
TXMFC[3]
TXMFC[2]
TXMFC[1]
TXMFC[0]
0143h:
Bits 1-31: Transmit Multicast Frames Counter (TXMFC[31:0]) – Contains the number of frames transmitted with
a multicast address. Includes both good and bad frames.
Rev: 063008
310 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.TXBFC
Register Description:
Register Address:
MAC MMC TRANSMIT BROADCAST FRAME COUNTER
0144h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXBFC[31]
TXBFC[30]
TXBFC[29]
TXBFC[28]
TXBFC[27]
TXBFC[26]
TXBFC[25]
TXBFC[24]
0144h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXBFC[23]
TXBFC[22]
TXBFC[21]
TXBFC[20]
TXBFC[19]
TXBFC[18]
TXBFC[17]
TXBFC[16]
0145h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXBFC[15]
TXBFC[14]
TXBFC[13]
TXBFC[12]
TXBFC[11]
TXBFC[10]
TXBFC[9]
TXBFC[8]
0146h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXBFC[7]
TXBFC[6]
TXBFC[5]
TXBFC[4]
TXBFC[3]
TXBFC[2]
TXBFC[1]
TXBFC[0]
0147h:
Bits 1-31: Transmit Broadcast Frames Counter (TXBFC[31:0]) – Contains the number of frames transmitted
with a broadcast address. Includes both good and bad frames.
Register Name:
SU.TXUFE
Register Description:
Register Address:
MAC MMC TRANSMIT UNDERFLOW FRAMES COUNTER
0148h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXUFE[31]
TXUFE[30]
TXUFE[29]
TXUFE[28]
TXUFE[27]
TXUFE[26]
TXUFE[25]
TXUFE[24]
0148h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXUFE[23]
TXUFE[22]
TXUFE[21]
TXUFE[20]
TXUFE[19]
TXUFE[18]
TXUFE[17]
TXUFE[16]
0149h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXUFE[15]
TXUFE[14]
TXUFE[13]
TXUFE[12]
TXUFE[11]
TXUFE[10]
TXUFE[9]
TXUFE[8]
014Ah:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXUFE[7]
TXUFE[6]
TXUFE[5]
TXUFE[4]
TXUFE[3]
TXUFE[2]
TXUFE[1]
TXUFE[0]
014Bh:
Bits 1-31: Transmit Underflow Frames Counter (TXUFE[31:0]) – Contains the number of frames aborted due to
underflow errors.
Rev: 063008
311 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.TXSNGLCL
Register Description:
Register Address:
MAC MMC TRANSMIT SINGLE COLLISION FRAME COUNTER
014Ch (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXSNGLCL[31] TXSNGLCL[30] TXSNGLCL[29] TXSNGLCL[28] TXSNGLCL[27] TXSNGLCL[26] TXSNGLCL[25] TXSNGLCL[24]
014Ch:
014Dh:
014Eh:
014Fh:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXSNGLCL[23] TXSNGLCL[22] TXSNGLCL[21] TXSNGLCL[20] TXSNGLCL[19] TXSNGLCL[18] TXSNGLCL[17] TXSNGLCL[16]
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXSNGLCL[15] TXSNGLCL[14] TXSNGLCL[13] TXSNGLCL[12] TXSNGLCL[11] TXSNGLCL[10]
TXSNGLCL[9]
TXSNGLCL[8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXSNGLCL[7]
TXSNGLCL[6]
TXSNGLCL[5]
TXSNGLCL[4]
TXSNGLCL[3]
TXSNGLCL[2]
TXSNGLCL[1]
TXSNGLCL[0]
Bits 1-31: Transmit Single Collision Frames Counter (TXSNGLCL[31:0]) – Contains the number of frames
successfully transmitted after a single collision. Applicable in half-duplex mode only.
Register Name:
SU.TXMLTICL
Register Description:
Register Address:
MAC MMC TRANSMIT MULTIPLE COLLISION FRAMES COUNTER
0150h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXMLTICL[31]
TXMLTICL[30]
TXMLTICL[29]
TXMLTICL[28]
TXMLTICL[27]
TXMLTICL[26]
TXMLTICL[25]
TXMLTICL[24]
0150h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXMLTICL[23]
TXMLTICL[22]
TXMLTICL[21]
TXMLTICL[20]
TXMLTICL[19]
TXMLTICL[18]
TXMLTICL[17]
TXMLTICL[16]
0151h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXMLTICL[15]
TXMLTICL[14]
TXMLTICL[13]
TXMLTICL[12]
TXMLTICL[11]
TXMLTICL[10]
TXMLTICL[9]
TXMLTICL[8]
0152h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXMLTICL[7]
TXMLTICL[6]
TXMLTICL[5]
TXMLTICL[4]
TXMLTICL[3]
TXMLTICL[2]
TXMLTICL[1]
TXMLTICL[0]
0153h:
Bits 1-31: Transmit Multiple Collision Frames Counter (TXMLTICL[31:0]) – Contains the number of frames
successfully transmitted after multiple collisions. Applicable in half-duplex mode only.
Rev: 063008
312 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.TXDFRD
Register Description:
Register Address:
MAC MMC TRANSMIT DEFERRED FRAME COUNTER
0154h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXDFRD[31]
TXDFRD[30]
TXDFRD[29]
TXDFRD[28]
TXDFRD[27]
TXDFRD[26]
TXDFRD[25]
TXDFRD[24]
0154h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXDFRD[23]
TXDFRD[22]
TXDFRD[21]
TXDFRD[20]
TXDFRD[19]
TXDFRD[18]
TXDFRD[17]
TXDFRD[16]
0155h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXDFRD[15]
TXDFRD[14]
TXDFRD[13]
TXDFRD[12]
TXDFRD[11]
TXDFRD[10]
TXDFRD[9]
TXDFRD[8]
0156h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXDFRD[7]
TXDFRD[6]
TXDFRD[5]
TXDFRD[4]
TXDFRD[3]
TXDFRD[2]
TXDFRD[1]
TXDFRD[0]
0157h:
Bits 1-31: Transmit Deferred Frames Counter (TXDFRD[31:0]) – Contains the number of frames successfully
transmitted after deferral. Applicable in half-duplex mode only.
Register Name:
SU.TXLTCL
Register Description:
Register Address:
MAC MMC TRANSMIT LATE COLLISION FRAMES COUNTER
0158h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXLTCL[31]
TXLTCL[30]
TXLTCL[29]
TXLTCL[28]
TXLTCL[27]
TXLTCL[26]
TXLTCL[25]
TXLTCL[24]
0158h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXLTCL[23]
TXLTCL[22]
TXLTCL[21]
TXLTCL[20]
TXLTCL[19]
TXLTCL[18]
TXLTCL[17]
TXLTCL[16]
0159h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXLTCL[15]
TXLTCL[14]
TXLTCL[13]
TXLTCL[12]
TXLTCL[11]
TXLTCL[10]
TXLTCL[9]
TXLTCL[8]
015Ah:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXLTCL[7]
TXLTCL[6]
TXLTCL[5]
TXLTCL[4]
TXLTCL[3]
TXLTCL[2]
TXLTCL[1]
TXLTCL[0]
015Bh:
Bits 1-31: Transmit Late Collision Frames Counter (TXLTCL[31:0]) – Contains the number of frames aborted
due to late collisions. Applicable in half-duplex mode only.
Rev: 063008
313 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.TXXCSVCL
Register Description:
Register Address:
MAC MMC TRANSMIT EXCESSIVE COLLISION COUNTER
015Ch (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXXCSVCL[31] TXXCSVCL[30] TXXCSVCL[29] TXXCSVCL[28] TXXCSVCL[27] TXXCSVCL[26] TXXCSVCL[25] TXXCSVCL[24]
015Ch:
015Dh:
015Eh:
015Fh:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXXCSVCL[23] TXXCSVCL[22] TXXCSVCL[21] TXXCSVCL[20] TXXCSVCL[19] TXXCSVCL[18] TXXCSVCL[17] TXXCSVCL[16]
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXXCSVCL[15] TXXCSVCL[14] TXXCSVCL[13] TXXCSVCL[12] TXXCSVCL[11] TXXCSVCL[10]
TXXCSVCL[9]
TXXCSVCL[8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXXCSVCL[7]
TXXCSVCL[6]
TXXCSVCL[5]
TXXCSVCL[4]
TXXCSVCL[3]
TXXCSVCL[2]
TXXCSVCL[1]
TXXCSVCL[0]
Bits 1-31: Transmit Excessive Collision Counter (TXXCSVCL[31:0]) – Contains the number of frames aborted
due to excessive collisions. Applicable in half-duplex mode only.
Register Name:
SU.TXCRERR
Register Description:
Register Address:
MAC MMC TRANSMIT CARRIER ERROR COUNTER
0160h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXCRERR[31]
TXCRERR[30]
TXCRERR[29]
TXCRERR[28]
TXCRERR[27]
TXCRERR[26]
TXCRERR[25]
TXCRERR[24]
0160h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXCRERR[23]
TXCRERR[22]
TXCRERR[21]
TXCRERR[20]
TXCRERR[19]
TXCRERR[18]
TXCRERR[17]
TXCRERR[16]
0161h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXCRERR[15]
TXCRERR[14]
TXCRERR[13]
TXCRERR[12]
TXCRERR[11]
TXCRERR[10]
TXCRERR[9]
TXCRERR[8]
0162h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXCRERR[7]
TXCRERR[6]
TXCRERR[5]
TXCRERR[4]
TXCRERR[3]
TXCRERR[2]
TXCRERR[1]
TXCRERR[0]
0163h:
Bits 1-31: Transmit Carrier Error Counter (TXCRERR[31:0]) – Contains the number of frames aborted due to
carrier error (no carrier or loss of carrier).
Rev: 063008
314 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.TXGBC
Register Description:
Register Address:
MAC MMC TRANSMIT GOOD BYTE COUNTER
0164h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXGBC[31]
TXGBC[30]
TXGBC[29]
TXGBC[28]
TXGBC[27]
TXGBC[26]
TXGBC[25]
TXGBC[24]
0164h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXGBC[23]
TXGBC[22]
TXGBC[21]
TXGBC[20]
TXGBC[19]
TXGBC[18]
TXGBC[17]
TXGBC[16]
0165h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXGBC[15]
TXGBC[14]
TXGBC[13]
TXGBC[12]
TXGBC[11]
TXGBC[10]
TXGBC[9]
TXGBC[8]
0166h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXGBC[7]
TXGBC[6]
TXGBC[5]
TXGBC[4]
TXGBC[3]
TXGBC[2]
TXGBC[1]
TXGBC[0]
0167h:
Bits 1-31: Transmit Good Byte Counter (TXGBC[31:0]) – Contains the number of transmitted bytes in good
frames, exclusive of preamble bytes.
Register Name:
SU.TXGFC
Register Description:
Register Address:
MAC MMC TRANSMIT GOOD FRAME COUNTER
0168h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXGFC[31]
TXGFC[30]
TXGFC[29]
TXGFC[28]
TXGFC[27]
TXGFC[26]
TXGFC[25]
TXGFC[24]
0168h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXGFC[23]
TXGFC[22]
TXGFC[21]
TXGFC[20]
TXGFC[19]
TXGFC[18]
TXGFC[17]
TXGFC[16]
0169h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXGFC[15]
TXGFC[14]
TXGFC[13]
TXGFC[12]
TXGFC[11]
TXGFC[10]
TXGFC[9]
TXGFC[8]
016Ah:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXGFC[7]
TXGFC[6]
TXGFC[5]
TXGFC[4]
TXGFC[3]
TXGFC[2]
TXGFC[1]
TXGFC[0]
016Bh:
Bits 1-31: Transmit Good Frame Counter (TXGFC[31:0]) – Contains the number of good frames transmitted.
Rev: 063008
315 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.TXXCSVDF
Register Description:
Register Address:
MAC MMC TRANSMIT EXCESSIVE DEFERRAL COUNTER
016Ch (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXXCSVDF[31] TXXCSVDF[30] TXXCSVDF[29] TXXCSVDF[28] TXXCSVDF[27] TXXCSVDF[26] TXXCSVDF[25] TXXCSVDF[24]
016Ch:
016Dh:
016Eh:
016Fh:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXXCSVDF[23] TXXCSVDF[22] TXXCSVDF[21] TXXCSVDF[20] TXXCSVDF[19] TXXCSVDF[18] TXXCSVDF[17] TXXCSVDF[16]
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXXCSVDF[15] TXXCSVDF[14] TXXCSVDF[13] TXXCSVDF[12] TXXCSVDF[11] TXXCSVDF[10]
TXXCSVDF[9]
TXXCSVDF[8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXXCSVDF[7] TXXCSVDF[6]
TXXCSVDF[5]
TXXCSVDF[4]
TXXCSVDF[3]
TXXCSVDF[2]
TXXCSVDF[1]
TXXCSVDF[0]
Bits 1-31: Transmit Excessive Deferral Counter (TXXCSVDF[31:0]) – Contains the number of frames aborted
due to excessive deferral. Applicable in half-duplex mode only.
Register Name:
SU.TXPAUSE
Register Description:
Register Address:
MAC MMC TRANSMIT PAUSE FRAME COUNTER
0170h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXPAUSE[31]
TXPAUSE[30]
TXPAUSE[29]
TXPAUSE[28]
TXPAUSE[27]
TXPAUSE[26]
TXPAUSE[25]
TXPAUSE[24]
0170h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXPAUSE[23]
TXPAUSE[22]
TXPAUSE[21]
TXPAUSE[20]
TXPAUSE[19]
TXPAUSE[18]
TXPAUSE[17]
TXPAUSE[16]
0171h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXPAUSE[15]
TXPAUSE[14]
TXPAUSE[13]
TXPAUSE[12]
TXPAUSE[11]
TXPAUSE[10]
TXPAUSE[9]
TXPAUSE[8]
0172h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXPAUSE[7]
TXPAUSE[6]
TXPAUSE[5]
TXPAUSE[4]
TXPAUSE[3]
TXPAUSE[2]
TXPAUSE[1]
TXPAUSE[0]
0173h:
Bits 1-31: Transmit Pause Frame Counter (TXPAUSE[31:0]) – Contains the number of good Pause frames
transmitted.
Rev: 063008
316 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.TXVLANF
Register Description:
Register Address:
MAC MMC TRANSMIT VLAN FRAME COUNTER
0174h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
TXVLANF[31]
TXVLANF[30]
TXVLANF[29]
TXVLANF[28]
TXVLANF[27]
TXVLANF[26]
TXVLANF[25]
TXVLANF[24]
0174h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
TXVLANF[23]
TXVLANF[22]
TXVLANF[21]
TXVLANF[20]
TXVLANF[19]
TXVLANF[18]
TXVLANF[17]
TXVLANF[16]
0175h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TXVLANF[15]
TXVLANF[14]
TXVLANF[13]
TXVLANF[12]
TXVLANF[11]
TXVLANF[10]
TXVLANF[9]
TXVLANF[8]
0176h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXVLANF[7]
TXVLANF[6]
TXVLANF[5]
TXVLANF[4]
TXVLANF[3]
TXVLANF[2]
TXVLANF[1]
TXVLANF[0]
0177h:
Bits 1-31: Transmit VLAN Frame Counter (TXVLANF[31:0]) – Contains the number of good VLAN frames
transmitted.
Register Name:
SU.RXFC
Register Description:
Register Address:
MAC MMC RECEIVE FRAME COUNTER
0180h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXFC[31]
RXFC[30]
RXFC[29]
RXFC[28]
RXFC[27]
RXFC[26]
RXFC[25]
RXFC[24]
0180h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXFC[23]
RXFC[22]
RXFC[21]
RXFC[20]
RXFC[19]
RXFC[18]
RXFC[17]
RXFC[16]
0181h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXFC[15]
RXFC[14]
RXFC[13]
RXFC[12]
RXFC[11]
RXFC[10]
RXFC[9]
RXFC[8]
0182h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXFC[7]
RXFC[6]
RXFC[5]
RXFC[4]
RXFC[3]
RXFC[2]
RXFC[1]
RXFC[0]
0183h:
Bits 1-31: Receive Frame Counter (RXFC[31:0]) – Contains the number of frames received, both good and bad
frames included.
Rev: 063008
317 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.RXBC
Register Description:
Register Address:
MAC MMC RECEIVE BYTE COUNTER
0184h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXBC[31]
RXBC[30]
RXBC[29]
RXBC[28]
RXBC[27]
RXBC[26]
RXBC[25]
RXBC[24]
0184h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXBC[23]
RXBC[22]
RXBC[21]
RXBC[20]
RXBC[19]
RXBC[18]
RXBC[17]
RXBC[16]
0185h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXBC[15]
RXBC[14]
RXBC[13]
RXBC[12]
RXBC[11]
RXBC[10]
RXBC[9]
RXBC[8]
0186h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXBC[7]
RXBC[6]
RXBC[5]
RXBC[4]
RXBC[3]
RXBC[2]
RXBC[1]
RXBC[0]
0187h:
Bits 1-31: Receive Byte Counter (RXBC[31:0]) – Contains the number of good and bad bytes received, exclusive
of preamble bytes.
Register Name:
SU.RXGBC
Register Description:
Register Address:
MAC MMC RECEIVE GOOD BYTE COUNTER
0188h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXGBC[31]
RXGBC[30]
RXGBC[29]
RXGBC[28]
RXGBC[27]
RXGBC[26]
RXGBC[25]
RXGBC[24]
0188h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXGBC[23]
RXGBC[22]
RXGBC[21]
RXGBC[20]
RXGBC[19]
RXGBC[18]
RXGBC[17]
RXGBC[16]
0189h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXGBC[15]
RXGBC[14]
RXGBC[13]
RXGBC[12]
RXGBC[11]
RXGBC[10]
RXGBC[9]
RXGBC[8]
018Ah:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXGBC[7]
RXGBC[6]
RXGBC[5]
RXGBC[4]
RXGBC[3]
RXGBC[2]
RXGBC[1]
RXGBC[0]
018Bh:
Bits 1-31: Receive Good Byte Counter (RXGBC[31:0]) – Contains the number of bytes received in good frames,
exclusive of preamble bytes.
Rev: 063008
318 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.RXGBFC
Register Description:
Register Address:
MAC MMC RECEIVE GOOD BROADCAST FRAME COUNTER
018Ch (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXGBFC[31]
RXGBFC[30]
RXGBFC[29]
RXGBFC[28]
RXGBFC[27]
RXGBFC[26]
RXGBFC[25]
RXGBFC[24]
018Ch:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXGBFC[23]
RXGBFC[22]
RXGBFC[21]
RXGBFC[20]
RXGBFC[19]
RXGBFC[18]
RXGBFC[17]
RXGBFC[16]
018Dh:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXGBFC[15]
RXGBFC[14]
RXGBFC[13]
RXGBFC[12]
RXGBFC[11]
RXGBFC[10]
RXGBFC[9]
RXGBFC[8]
018Eh:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXGBFC[7]
RXGBFC[6]
RXGBFC[5]
RXGBFC[4]
RXGBFC[3]
RXGBFC[2]
RXGBFC[1]
RXGBFC[0]
018Fh:
Bits 1-31: Receive Good Broadcast Frame Counter (RXGBFC[31:0]) – Contains the number of good broadcast
frames received.
Register Name:
SU.RXMFC
Register Description:
Register Address:
MAC MMC RECEIVE MULTICAST FRAME COUNTER
0190h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXMFC[31]
RXMFC[30]
RXMFC[29]
RXMFC[28]
RXMFC[27]
RXMFC[26]
RXMFC[25]
RXMFC[24]
0190h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXMFC[23]
RXMFC[22]
RXMFC[21]
RXMFC[20]
RXMFC[19]
RXMFC[18]
RXMFC[17]
RXMFC[16]
0191h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXMFC[15]
RXMFC[14]
RXMFC[13]
RXMFC[12]
RXMFC[11]
RXMFC[10]
RXMFC[9]
RXMFC[8]
0192h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXMFC[7]
RXMFC[6]
RXMFC[5]
RXMFC[4]
RXMFC[3]
RXMFC[2]
RXMFC[1]
RXMFC[0]
0193h:
Bits 1-31: Receive Good Multicast Frame Counter (RXMFC[31:0]) – Contains the number of good Multicast
frames received.
Rev: 063008
319 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.RXCRC
Register Description:
Register Address:
MAC MMC RECEIVE CRC ERROR COUNTER
0194h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXCRC[31]
RXCRC[30]
RXCRC[29]
RXCRC[28]
RXCRC[27]
RXCRC[26]
RXCRC[25]
RXCRC[24]
0194h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXCRC[23]
RXCRC[22]
RXCRC[21]
RXCRC[20]
RXCRC[19]
RXCRC[18]
RXCRC[17]
RXCRC[16]
0195h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXCRC[15]
RXCRC[14]
RXCRC[13]
RXCRC[12]
RXCRC[11]
RXCRC[10]
RXCRC[9]
RXCRC[8]
0196h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXCRC[7]
RXCRC[6]
RXCRC[5]
RXCRC[4]
RXCRC[3]
RXCRC[2]
RXCRC[1]
RXCRC[0]
0197h:
Bits 1-31: Receive CRC Error Counter (RXCRC[31:0]) – Contains the number of frames received with CRC
errors.
Register Name:
SU.RXALGN
Register Description:
Register Address:
MAC MMC RECEIVE ALIGNMENT ERROR COUNTER
0198h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXALGN[31]
RXALGN[30]
RXALGN[29]
RXALGN[28]
RXALGN[27]
RXALGN[26]
RXALGN[25]
RXALGN[24]
0198h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXALGN[23]
RXALGN[22]
RXALGN[21]
RXALGN[20]
RXALGN[19]
RXALGN[18]
RXALGN[17]
RXALGN[16]
0199h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXALGN[15]
RXALGN[14]
RXALGN[13]
RXALGN[12]
RXALGN[11]
RXALGN[10]
RXALGN[9]
RXALGN[8]
019Ah:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXALGN[7]
RXALGN[6]
RXALGN[5]
RXALGN[4]
RXALGN[3]
RXALGN[2]
RXALGN[1]
RXALGN[0]
019Bh:
Bits 1-31: Receive Alignment Error Counter (RXALGN[31:0]) – Contains the number of frames received with
alignment (dribble) errors.
Rev: 063008
320 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.RXRUNT
Register Description:
Register Address:
MAC MMC RECEIVE RUNT ERROR COUNTER
019Ch (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXRUNT[31]
RXRUNT[30]
RXRUNT[29]
RXRUNT[28]
RXRUNT[27]
RXRUNT[26]
RXRUNT[25]
RXRUNT[24]
019Ch:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXRUNT[23]
RXRUNT[22]
RXRUNT[21]
RXRUNT[20]
RXRUNT[19]
RXRUNT[18]
RXRUNT[17]
RXRUNT[16]
019Dh:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXRUNT[15]
RXRUNT[14]
RXRUNT[13]
RXRUNT[12]
RXRUNT[11]
RXRUNT[10]
RXRUNT[9]
RXRUNT[8]
019Eh:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXRUNT[7]
RXRUNT[6]
RXRUNT[5]
RXRUNT[4]
RXRUNT[3]
RXRUNT[2]
RXRUNT[1]
RXRUNT[0]
019Fh:
Bits 1-31: Receive Runt Error Counter (RXRUNT[31:0]) – Contains the number of runt frames received.
Register Name:
SU.RXJBBR
Register Description:
Register Address:
MAC MMC RECEIVE JABBER ERROR COUNTER
01A0h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXJBBR[31]
RXJBBR[30]
RXJBBR[29]
RXJBBR[28]
RXJBBR[27]
RXJBBR[26]
RXJBBR[25]
RXJBBR[24]
01A0h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXJBBR[23]
RXJBBR[22]
RXJBBR[21]
RXJBBR[20]
RXJBBR[19]
RXJBBR[18]
RXJBBR[17]
RXJBBR[16]
01A1h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXJBBR[15]
RXJBBR[14]
RXJBBR[13]
RXJBBR[12]
RXJBBR[11]
RXJBBR[10]
RXJBBR[9]
RXJBBR[8]
01A2h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXJBBR[7]
RXJBBR[6]
RXJBBR[5]
RXJBBR[4]
RXJBBR[3]
RXJBBR[2]
RXJBBR[1]
RXJBBR[0]
01A3h:
Bits 1-31: Receive Jabber Error Counter (RXJBBR[31:0]) – Contains the number of frames received with length
greater 1518 (including the CRC) and with CRC errors.
Rev: 063008
321 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.RXUNDRSZ
Register Description:
Register Address:
MAC MMC RECEIVE UNDERSIZE FRAME COUNTER
01A4h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXUNDRSZ[31] RXUNDRSZ[30] RXUNDRSZ[29] RXUNDRSZ[28] RXUNDRSZ[27] RXUNDRSZ[26] RXUNDRSZ[25] RXUNDRSZ[24]
01A4h:
01A5h:
01A6h:
01A7h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXUNDRSZ[23] RXUNDRSZ[22] RXUNDRSZ[21] RXUNDRSZ[20] RXUNDRSZ[19] RXUNDRSZ[18] RXUNDRSZ[17] RXUNDRSZ[16]
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXUNDRSZ[15] RXUNDRSZ[14] RXUNDRSZ[13] RXUNDRSZ[12] RXUNDRSZ[11] RXUNDRSZ[10] RXUNDRSZ[9]
RXUNDRSZ[8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXUNDRSZ[7] RXUNDRSZ[6] RXUNDRSZ[5]
RXUNDRSZ[4] RXUNDRSZ[3]
RXUNDRSZ[2]
RXUNDRSZ[1] RXUNDRSZ[0]
Bits 1-31: Receive Undersize Frame Counter (RXUNDRSZ[31:0]) – Contains the number of frames received
with a size less than 64 bytes and a good CRC.
Register Name:
SU.RXOVRSZ
Register Description:
Register Address:
MAC MMC RECEIVE OVERSIZE FRAME COUNTER
01A8h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXOVRSZ[31]
RXOVRSZ[30]
RXOVRSZ[29]
RXOVRSZ[28]
RXOVRSZ[27]
RXOVRSZ[26]
RXOVRSZ[25]
RXOVRSZ[24]
01A8h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXOVRSZ[23]
RXOVRSZ[22]
RXOVRSZ[21]
RXOVRSZ[20]
RXOVRSZ[19]
RXOVRSZ[18]
RXOVRSZ[17]
RXOVRSZ[16]
01A9h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXOVRSZ[15]
RXOVRSZ[14]
RXOVRSZ[13]
RXOVRSZ[12]
RXOVRSZ[11]
RXOVRSZ[10]
RXOVRSZ[9]
RXOVRSZ[8]
01AAh:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXOVRSZ[7]
RXOVRSZ[6]
RXOVRSZ[5]
RXOVRSZ[4]
RXOVRSZ[3]
RXOVRSZ[2]
RXOVRSZ[1]
RXOVRSZ[0]
01ABh:
Bits 1-31: Receive Oversize Frame Counter (RXOVRSZ[31:0]) – Contains the number of frames received with
length greater than the maximum size with a valid CRC.
Rev: 063008
322 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.RX0_64
Register Description:
Register Address:
MAC MMC RECEIVE 0-64 BYTE FRAME COUNTER
01ACh (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RX0_64[31]
RX0_64[30]
RX0_64[29]
RX0_64[28]
RX0_64[27]
RX0_64[26]
RX0_64[25]
RX0_64[24]
01ACh:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RX0_64[23]
RX0_64[22]
RX0_64[21]
RX0_64[20]
RX0_64[19]
RX0_64[18]
RX0_64[17]
RX0_64[16]
01ADh:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RX0_64[15]
RX0_64[14]
RX0_64[13]
RX0_64[12]
RX0_64[11]
RX0_64[10]
RX0_64[9]
RX0_64[8]
01AEh:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX0_64[7]
RX0_64[6]
RX0_64[5]
RX0_64[4]
RX0_64[3]
RX0_64[2]
RX0_64[1]
RX0_64[0]
01AFh:
Bits 1-31: Receive 0-64 Byte Frames Counter (RX0_64[31:0]) – Contains the number of frames received with
sizes of 64 bytes or less. Includes both good and bad frames.
Register Name:
SU.RX65_127
Register Description:
Register Address:
MAC MMC RECEIVE 65-127 BYTE FRAME COUNTER
01B0h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RX65_127[31]
RX65_127[30]
RX65_127[29]
RX65_127[28]
RX65_127[27]
RX65_127[26]
RX65_127[25]
RX65_127[24]
01B0h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RX65_127[23]
RX65_127[22]
RX65_127[21]
RX65_127[20]
RX65_127[19]
RX65_127[18]
RX65_127[17]
RX65_127[16]
01B1h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RX65_127[15]
RX65_127[14]
RX65_127[13]
RX65_127[12]
RX65_127[11]
RX65_127[10]
RX65_127[9]
RX65_127[8]
01B2h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX65_127[7]
RX65_127[6]
RX65_127[5]
RX65_127[4]
RX65_127[3]
RX65_127[2]
RX65_127[1]
RX65_127[0]
01B3h:
Bits 1-31: Receive 65-127 Byte Frames Counter (RX65_127[31:0]) – Contains the number of frames received
with sizes of 65 to 127 bytes. Includes both good and bad frames.
Rev: 063008
323 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.RX128_255
Register Description:
Register Address:
MAC MMC RECEIVE 128-255 BYTE FRAME COUNTER
01B4h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RX128_255[31] RX128_255[30] RX128_255[29] RX128_255[28] RX128_255[27] RX128_255[26] RX128_255[25] RX128_255[24]
01B4h:
01B5h:
01B6h:
01B7h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RX128_255[23] RX128_255[22] RX128_255[21] RX128_255[20] RX128_255[19] RX128_255[18] RX128_255[17] RX128_255[16]
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RX128_255[15] RX128_255[14] RX128_255[13] RX128_255[12] RX128_255[11] RX128_255[10]
RX128_255[9]
RX128_255[8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX128_255[7]
RX128_255[6]
RX128_255[5]
RX128_255[4]
RX128_255[3]
RX128_255[2]
RX128_255[1]
RX128_255[0]
Bits 1-31: Receive 128-255 Byte Frames Counter (RX128_255[31:0]) – Contains the number of frames received
with sizes of 128 to 255 bytes. Includes both good and bad frames.
Register Name:
SU.RX256_511
Register Description:
Register Address:
MAC MMC RECEIVE 256-511 BYTE FRAME COUNTER
01B8h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RX256_511[31] RX256_511[30] RX256_511[29] RX256_511[28] RX256_511[27] RX256_511[26] RX256_511[25] RX256_511[24]
01B8h:
01B9h:
01BAh:
01BBh:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RX256_511[23] RX256_511[22] RX256_511[21] RX256_511[20] RX256_511[19] RX256_511[18] RX256_511[17] RX256_511[16]
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RX256_511[15] RX256_511[14] RX256_511[13] RX256_511[12] RX256_511[11] RX256_511[10]
RX256_511[9]
RX256_511[8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX256_511[7]
RX256_511[6]
RX256_511[5]
RX256_511[4]
RX256_511[3]
RX256_511[2]
RX256_511[1]
RX256_511[0]
Bits 1-31: Receive 256-511 Byte Frames Counter (RX256_511[31:0]) – Contains the number of frames received
with sizes of 256 to 511 bytes. Includes both good and bad frames.
Rev: 063008
324 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.RX512_1K
Register Description:
Register Address:
MAC MMC RECEIVE 512-1023 BYTE FRAME COUNTER
01BCh (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RX512_1K[31]
RX512_1K[30]
RX512_1K[29]
RX512_1K[28]
RX512_1K[27]
RX512_1K[26]
RX512_1K[25]
RX512_1K[24]
01BCh:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RX512_1K[23]
RX512_1K[22]
RX512_1K[21]
RX512_1K[20]
RX512_1K[19]
RX512_1K[18]
RX512_1K[17]
RX512_1K[16]
01BDh:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RX512_1K[15]
RX512_1K[14]
RX512_1K[13]
RX512_1K[12]
RX512_1K[11]
RX512_1K[10]
RX512_1K[9]
RX512_1K[8]
01BEh:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX512_1K[7]
RX512_1K[6]
RX512_1K[5]
RX512_1K[4]
RX512_1K[3]
RX512_1K[2]
RX512_1K[1]
RX512_1K[0]
01BFh:
Bits 1-31: Receive 512-1023 Byte Frames Counter (RX512_1K[31:0]) – Contains the number of frames received
with sizes of 512 to 1023 bytes. Includes both good and bad frames.
Register Name:
SU.RX1K_MAX
Register Description:
Register Address:
MAC MMC RECEIVE 1024-MAX BYTE FRAME COUNTER
01C0h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RX1K_MAX[31] RX1K_MAX[30] RX1K_MAX[29] RX1K_MAX[28] RX1K_MAX[27] RX1K_MAX[26] RX1K_MAX[25] RX1K_MAX[24]
01C0h:
01C1h:
01C2h:
01C3h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RX1K_MAX[23] RX1K_MAX[22] RX1K_MAX[21] RX1K_MAX[20] RX1K_MAX[19] RX1K_MAX[18] RX1K_MAX[17] RX1K_MAX[16]
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RX1K_MAX[15] RX1K_MAX[14] RX1K_MAX[13] RX1K_MAX[12] RX1K_MAX[11] RX1K_MAX[10]
RX1K_MAX[9]
RX1K_MAX[8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX1K_MAX[7] RX1K_MAX[6]
RX1K_MAX[5]
RX1K_MAX[4]
RX1K_MAX[3]
RX1K_MAX[2]
RX1K_MAX[1]
RX1K_MAX[0]
Bits 1-31: Receive 1024-MAX Byte Frames Counter (RX1K_MAX[31:0]) – Contains the number of frames
received with sizes of 1024 to the maximum bytes. Includes both good and bad frames.
Rev: 063008
325 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.RXUFC
Register Description:
Register Address:
MAC MMC RECEIVE UNICAST FRAME COUNTER
01C4h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXUFC[31]
RXUFC[30]
RXUFC[29]
RXUFC[28]
RXUFC[27]
RXUFC[26]
RXUFC[25]
RXUFC[24]
01C4h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXUFC[23]
RXUFC[22]
RXUFC[21]
RXUFC[20]
RXUFC[19]
RXUFC[18]
RXUFC[17]
RXUFC[16]
01C5h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXUFC[15]
RXUFC[14]
RXUFC[13]
RXUFC[12]
RXUFC[11]
RXUFC[10]
RXUFC[9]
RXUFC[8]
01C6h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXUFC[7]
RXUFC[6]
RXUFC[5]
RXUFC[4]
RXUFC[3]
RXUFC[2]
RXUFC[1]
RXUFC[0]
01C7h:
Bits 1-31: Receive Unicast Frame Counter (RXUFC[31:0]) – Contains the number of good unicast frames
received.
Register Name:
SU.RXLNERR
Register Description:
Register Address:
MAC MMC RECEIVE LENGTH ERROR COUNTER
01C8h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXLNERR[31]
RXLNERR[30]
RXLNERR[29]
RXLNERR[28]
RXLNERR[27]
RXLNERR[26]
RXLNERR[25]
RXLNERR[24]
01C8h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXLNERR[23]
RXLNERR[22]
RXLNERR[21]
RXLNERR[20]
RXLNERR[19]
RXLNERR[18]
RXLNERR[17]
RXLNERR[16]
01C9h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXLNERR[15]
RXLNERR[14]
RXLNERR[13]
RXLNERR[12]
RXLNERR[11]
RXLNERR[10]
RXLNERR[9]
RXLNERR[8]
01CAh:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXLNERR[7]
RXLNERR[6]
RXLNERR[5]
RXLNERR[4]
RXLNERR[3]
RXLNERR[2]
RXLNERR[1]
RXLNERR[0]
01CBh:
Bits 1-31: Receive Length Error Counter (RXLNERR[31:0]) – Contains the number of frames received with
length errors.
Rev: 063008
326 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.RXRANGE
Register Description:
Register Address:
MAC MMC RECEIVE OUT OF RANGE COUNTER
01CCh (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXRANGE[31]
RXRANGE[30] RXRANGE[29] RXRANGE[28]
RXRANGE[27]
RXRANGE[26]
RXRANGE[25]
RXRANGE[24]
01CCh:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXRANGE[23]
RXRANGE[22] RXRANGE[21] RXRANGE[20]
RXRANGE[19]
RXRANGE[18]
RXRANGE[17]
RXRANGE[16]
01CDh:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXRANGE[15]
RXRANGE[14] RXRANGE[13] RXRANGE[12]
RXRANGE[11]
RXRANGE[10]
RXRANGE[9]
RXRANGE[8]
01CEh:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXRANGE[7]
RXRANGE[6]
RXRANGE[5]
RXRANGE[4]
RXRANGE[3]
RXRANGE[2]
RXRANGE[1]
RXRANGE[0]
01CFh:
Bits 1-31: Receive Out of Range Counter (RXRANGE[31:0]) – Contains the number of frames received with an
invalid Ethernet Length/Type field.
Register Name:
SU.RXPAUSE
Register Description:
Register Address:
MAC MMC RECEIVE PAUSE FRAME COUNTER
01D0h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXPAUSE[31]
RXPAUSE[30]
RXPAUSE[29]
RXPAUSE[28]
RXPAUSE[27]
RXPAUSE[26]
RXPAUSE[25]
RXPAUSE[24]
01D0h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXPAUSE[23]
RXPAUSE[22]
RXPAUSE[21]
RXPAUSE[20]
RXPAUSE[19]
RXPAUSE[18]
RXPAUSE[17]
RXPAUSE[16]
01D1h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXPAUSE[15]
RXPAUSE[14]
RXPAUSE[13]
RXPAUSE[12]
RXPAUSE[11]
RXPAUSE[10]
RXPAUSE[9]
RXPAUSE[8]
01D2h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXPAUSE[7]
RXPAUSE[6]
RXPAUSE[5]
RXPAUSE[4]
RXPAUSE[3]
RXPAUSE[2]
RXPAUSE[1]
RXPAUSE[0]
01D3h:
Bits 1-31: Receive Pause Frame Counter (RXPAUSE[31:0]) – Contains the number of good Pause frames
received.
Rev: 063008
327 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.RXOVFL
Register Description:
Register Address:
MAC MMC RECEIVE OVERFLOW COUNTER
01D4h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXOVFL[31]
RXOVFL[30]
RXOVFL[29]
RXOVFL[28]
RXOVFL[27]
RXOVFL[26]
RXOVFL[25]
RXOVFL[24]
01D4h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXOVFL[23]
RXOVFL[22]
RXOVFL[21]
RXOVFL[20]
RXOVFL[19]
RXOVFL[18]
RXOVFL[17]
RXOVFL[16]
01D5h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXOVFL[15]
RXOVFL[14]
RXOVFL[13]
RXOVFL[12]
RXOVFL[11]
RXOVFL[10]
RXOVFL[9]
RXOVFL[8]
01D6h:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXOVFL[7]
RXOVFL[6]
RXOVFL[5]
RXOVFL[4]
RXOVFL[3]
RXOVFL[2]
RXOVFL[1]
RXOVFL[0]
01D7h:
Bits 1-31: Receive Overflow Counter (RXOVFL[31:0]) – Contains the number of frames discarded due to a
receive FIFO overflow.
Register Name:
SU.RXVLAN
Register Description:
Register Address:
MAC MMC RECEIVE VLAN FRAME COUNTER
01D8h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXVLAN[31]
RXVLAN[30]
RXVLAN[29]
RXVLAN[28]
RXVLAN[27]
RXVLAN[26]
RXVLAN[25]
RXVLAN[24]
01D8h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXVLAN[23]
RXVLAN[22]
RXVLAN[21]
RXVLAN[20]
RXVLAN[19]
RXVLAN[18]
RXVLAN[17]
RXVLAN[16]
01D9h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXVLAN[15]
RXVLAN[14]
RXVLAN[13]
RXVLAN[12]
RXVLAN[11]
RXVLAN[10]
RXVLAN[9]
RXVLAN[8]
01DAh:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXVLAN[7]
RXVLAN[6]
RXVLAN[5]
RXVLAN[4]
RXVLAN[3]
RXVLAN[2]
RXVLAN[1]
RXVLAN[0]
01DBh:
Bits 1-31: Receive VLAN Frame Counter (RXVLAN[31:0]) – Contains the number of good and bad VLAN frames
received.
Rev: 063008
328 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Register Name:
SU.RXWDOG
Register Description:
Register Address:
MAC MMC RECEIVE WATCHDOG ERROR COUNTER
01DCh (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
RXWDOG[31]
RXWDOG[30]
RXWDOG[29]
RXWDOG[28]
RXWDOG[27]
RXWDOG[26]
RXWDOG[25]
RXWDOG[24]
01DCh:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RXWDOG[23]
RXWDOG[22]
RXWDOG[21]
RXWDOG[20]
RXWDOG[19]
RXWDOG[18]
RXWDOG[17]
RXWDOG[16]
01DDh:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RXWDOG[15]
RXWDOG[14]
RXWDOG[13]
RXWDOG[12]
RXWDOG[11]
RXWDOG[10]
RXWDOG[9]
RXWDOG[8]
01DEh:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXWDOG[7]
RXWDOG[6]
RXWDOG[5]
RXWDOG[4]
RXWDOG[3]
RXWDOG[2]
RXWDOG[1]
RXWDOG[0]
01DFh:
Bits 1-31: Receive Watchdog Error Counter (RXWDOG[31:0]) – Contains the number of frames discarded due
to a receive watchdog timer error.
Note – the SU.RXWDOG register may be unnecessary and thus may be removed.
Register Name:
SU.MACMCR
Register Description:
Register Address:
MAC Miscellaneous Control Register
1018h (indirect)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
-
-
-
-
-
-
-
-
1018h:
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
-
-
-
FTF
-
-
-
-
1019h:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
-
-
-
-
-
-
101Ah:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
101Bh:
Bit 20: Flush Transmit FIFO (FTF) When this bit is written to 1, the MAC transmit FIFO is reset and cleared. This
bit automatically resets to zero when the reset operation is complete. Transmission should be disabled during the
flush transmit FIFO operation. Typically, the user will want to flush the transmit FIFO prior to enabling transmission
to avoid transmitting possible frame fragments that may be in the FIFO.
Rev: 063008
329 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
11. Functional Timing
11.1 Functional SPI Interface Timing
Note: The transmit and receive order of the address and data bits are selected by the SPI_SWAP pin. The R/W
(read/write) MSB bit and B (burst) LSB bit position is not affected by the SPI_SWAP pin setting.
11.1.1 SPI Transmission Format and CPHA Polarity
When SPI_CPHA = 0, CS may be de-asserted between accesses. An access is defined as one or two control
bytes followed by a data byte. CS cannot be de-asserted between the control bytes, or between the last control
byte and the data byte. When SPI_CPHA = 0, CS may also remain asserted between accesses. If it remains
asserted and the BURST bit is set, no additional control bytes are expected after the first control byte(s) and data
are transferred. If the BURST bit is set, the address will be incremented for each additional byte of data transferred
until CS is de-asserted. If CS remains asserted and the BURST bit is not set, a control byte(s) is expected following
the data byte, and the address for the next access will be received from that. Anytime CS is de-asserted, the
BURST access is terminated.
When SPI_CPHA = 1, CS may remain asserted for more than one access without being toggled high and then low
again between accesses. If the BURST bit is set, the address should increment and no additional control bytes are
expected. If the BURST bit is not set, each data byte will be followed by the control byte(s) for the next access.
Additionally, CS may also be de-asserted between accesses when SPI_CPHA =1. In the case, any BURST access
is terminated, and the next byte received when CS is re-asserted will be a control byte.
The following diagrams describe the functionality of the SPI port for the four combinations of SPI_CPOL and
SPI_CPHA. They indicate the clock edge that samples the data and the level of the clock during no-transfer events
(high or low). Since the SPI port acts as a slave device, the master device provides the clock. The user must
configure the SPI_CPOL and SPI_CPHA pins to describe which type of clock that the master device is providing.
Note that due to the address space of the device, the unused bits A13, A12, and A11 should always be zero.
Figure 11-1. SPI Serial Port Access For Read Mode, SPI_CPOL=0, SPI_CPHA = 0
SPI_CLK
CS
SPI_MOSI
A7
LSB MSB
1
A13
A12
A11
A10
A9
A8
A6
A5
A4
A3
A2
A1
A0
B
MSB
LSB
SPI_MISO
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
Figure 11-2. SPI Serial Port Access For Read Mode, SPI_CPOL = 1, SPI_CPHA = 0
SPI_CLK
CS
A7
LSB MSB
SPI_MOSI
1
A13
A12
A11
A10
A9
A8
A6
A5
A4
A3
A2
A1
A0
B
MSB
LSB
SPI_MISO
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
Rev: 063008
330 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 11-3. SPI Serial Port Access For Read Mode, SPI_CPOL = 0, SPI_CPHA = 1
SPI_CLK
CS
SPI_MOSI
A7
1
A13
A12
A11
A10
A9
A8
A6
A5
A4
A3
A2
A1
A0
B
MSB
LSB
MSB
LSB
SPI_MISO
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
Figure 11-4. SPI Serial Port Access For Read Mode, SPI_CPOL = 1, SPI_CPHA = 1
SPI_CLK
CS
SPI_MOSI
A7
LSB MSB
1
A13
A12
A11
A10
A9
A8
A6
A5
A4
A3
A2
A1
A0
B
MSB
LSB
SPI_MISO
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
Figure 11-5. SPI Serial Port Access For Write Mode, SPI_CPOL = 0, SPI_CPHA = 0
SPI_CLK
CS
D7
D6
D5
D4
D3
D2
D1
D0
SPI_MOSI
B
0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MSB
LSB
MSB
LSB MSB
LSB
SPI_MISO
Figure 11-6. SPI Serial Port Access For Write Mode, SPI_CPOL = 1, SPI_CPHA = 0
SPI_CLK
CS
SPI_MOSI
D7
D6
D5
D4
D3
D2
D1
D0
B
0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MSB
LSB
MSB
LSB MSB
LSB
SPI_MISO
Rev: 063008
331 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 11-7. SPI Serial Port Access For Write Mode, SPI_CPOL = 0, SPI_CPHA = 1
SPI_CLK
CS
D7
LSB MSB
D6
D5
D4
D3
D2
D1
D0
SPI_MOSI
B
0
A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MSB
LSB MSB
LSB
SPI_MISO
Figure 11-8. SPI Serial Port Access For Write Mode, SPI_CPOL = 1, SPI_CPHA = 1
SPI_CLK
CS
SPI_MOSI
D7
D6
D5
D4
D3
D2
D1
D0
B
0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MSB
LSB
MSB
LSB MSB
LSB
SPI_MISO
Rev: 063008
332 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
11.2 Functional Serial Interface Timing
The Serial Interface provides flexible timing to interconnect with a wide variety of serial devices. Figure 11-9 shows
the basic functional timing relationship for the transmit serial port interface. TCLK may be gapped during Framing
Overhead positions or to support Fractional T1/E1/T3/E3, as shown in Figure 11-11. The device provides the
TSYNC signal as a frame or byte boundary indication to an external interface. TSYNC is normally active high on
the first bit of the multiframe, but can be programmed to occur up to three cycles early, as shown in Figure 11-12.
TSYNC is minimally one pulse wide, but may be active for multiple clock cycles.
Figure 11-9. Transmit Serial Port Interface, without VCAT
TCLK
TSYNC
TDATA
MSB Encapsulated Ethernet Data
MSB Encapsulated Ethernet Data
MSB Encapsulated Ethernet Data
Figure 11-10. Transmit Serial Port Interface with VCAT
TCLK
TSYNC
TDATA
MSB
VCAT OH
MSB Encapsulated Ethernet Data
MSB Encapsulated Ethernet Data
Figure 11-11. Transmit Serial Port Interface, with Gapped Clock
TCLK
TSYNC
TDATA
LSB.....
MSB Encapsulated Ethernet Data
MSB Encapsulated Ethernet Data
MSB Encapsulated Ethernet
Rev: 063008
333 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
The figure below demonstrates the TSYNC pulse configured to arrive 2 clock cycles before the byte boundary
through the use of the LI.TCR register.
Figure 11-12. Transmit Serial Port Interface with VCAT, early TSYNC (2 cycles)
TCLK
TSYNC
MSB
VCAT OH
MSB
Encapsulated Ethernet Data
MSB
Encapsulated Ethernet
TDATA
Figure 11-13 shows the basic functional timing relationship for the receive serial port interface. RCLK may be
gapped during Framing Overhead positions or to support Fractional T1/E1/T3/E3, as shown in Figure 11-15. The
RSYNC signal must be provided to the device as a frame, multiframe, or byte boundary indication. VCAT
applications require a multiframe boundary. The expected position of the RSYNC pulse is not programmable, and
must be provided as indicated. Note that the first clock after the RSYNC will sample the LSB of the last byte of the
previous frame.
Figure 11-13. Receive Serial Port Interface, without VCAT, rising edge sampling
RCLK
RSYNC
RDATA
LSB
MSB Encapsulated Ethernet Data
MSB Encapsulated Ethernet Data
MSB Encapsulated Ethernet Data
Figure 11-14. Receive Serial Port Interface with VCAT, rising edge sampling
RCLK
RSYNC
RDATA
LSB
MSB
VCAT OH
MSB Encapsulated Ethernet Data
MSB Encapsulated Ethernet Data
Figure 11-15. Receive Serial Port Interface with Gapped Clock (T1)
RCLK
RSYNC
RDATA
Fbit MSB Encapsulated Ethernet Data
MSB Encapsulated Ethernet Data
MSB
Encapsulated Ethernet
LSB
Rev: 063008
334 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
11.3 Voice Port Functional Timing Diagrams
Figure 11-16. Transmit Voice Port Interface with PCM Octets
TCLK(I)
TSYNC(I)
LSB
MSB
PCM OCTET 1(prev frame)
PCM OCTET 2
ETHERNET DATA 1
TDATA(O)
TVCLK(I)
TVSYNC(I)
TVDEN(I)
PCM OCTET 1
10 11 12 13 14
PCM OCTET 2
TVDATA(I)
15 16
1
2
3
4
5
6
7
8
9
17 18 19 20 21 22 23 24
Figure 11-17 shows the receive serial port timing relationship when the data stream contains PCM octets. This
example shows two PCM octets being demuxed from the Ethernet data. RVSYNC is minimum one clock period
wide, but may be high multiple clock periods. Note that the PCM octets output on RVDATA are buffered for one
RVSYNC period, i.e. the PCM octets are delayed one frame. Voice data may be output at any point between frame
syncs, output when RVDEN is low.
Figure 11-17. Receive Voice Port Interface with PCM Octets
RCLK(I)
RSYNC(I)
LSB
MSB
PCM OCTET 1
PCM OCTET 2
ETHERNET DATA 1
RDATA(I)
RVCLK(I)
RVSYNC(I)
RVDEN(I)
PCM OCTET 1(prev frame)
PCM OCTET 2
RVDATA(O)
15 16
1
2
3
4
5
6
7
8
9
10 11 12 13 14
17 18 19 20 21 22 23 24
Rev: 063008
335 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
11.4 MII/RMII and GMII Interfaces
In GMII Mode, TX_EN is high with the first bit of the preamble. For 10Mbps operation, the data bit outputs are
updated every 10 clocks.
Figure 11-18. GMII Transmit Interface Functional Timing
REF_CLK
TXD[1:0
P
R
E
A
M
B
L
E
F
C
S
]
TX_E
N
GMII Receive data on RXD[1:0] is expected to be synchronous with the rising edge of ______. The data is only
valid if RX_CRS is high. The external PHY asynchronously drives RX_CRS low during carrier loss.
Figure 11-19. GMII Receive Interface Functional Timing
REF_CLK
P
R
E
A
M
B
L
E
F
C
S
RXD[1:0]
RX_CRS
Rev: 063008
336 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Each MII Interface Transmit Port has its own TX_CLK and data interface. The data TXD [3:0] operates
synchronously with TX_CLK. The LSB is presented first. TX_CLK should be 2.5MHz for 10Mbps operation and
25MHz for 100Mbps operation. TX_EN is valid at the same time as the first byte of the preamble. In DTE Mode
TX_CLK is input from the external PHY. In DCE Mode, the device provides TX_CLK, derived from an external
reference (SYSCLKI).
In Half-Duplex (DTE) Mode, the device supports RX_CRS and COL signals. RX_CRS is active when the PHY
detects transmit or receive activity. If there is a collision as indicated by the COL input, the device will replace the
data nibbles with jam nibbles. After a “random“ time interval, the frame is retransmitted. The MAC will try to send
the frame a maximum of 16 times. The jam sequence consists of 55555555h. Note that the COL signal and
RX_CRS can be asynchronous to the TX_CLK and are only valid in half duplex mode.
Figure 11-20. MII Transmit Functional Timing
TX_CLK
F
C
S
P
R
E
A
E
M
B
L
E
TXD[3:0]
TX_EN
Figure 11-21. MII Transmit Half Duplex with a Collision Functional Timing
TX_CLK
P
R
E
A
M
B
L
E
J
J
J
J
J
J
J
J
TXD[3:0]
TX_EN
RX_CRS
COL
Receive Data (RXD[3:0]) is clocked from the external PHY synchronously with RX_CLK. The RX_CLK signal is
2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation. RX_DV is asserted by the PHY from the first
Nibble of the preamble in 100Mbps operation or first nibble of SFD for 10Mbps operation. The data on RXD[3:0] is
not accepted by the MAC if RX_DV is low or RX_ERR is high (in DTE mode). RX_ERR should be tied low when in
DCE Mode.
Figure 11-22. MII Receive Functional Timing
RX_CLK
F
C
S
P
R
E
A
E
M
B
L
E
RXD[3:0]
RX_CRS
Rev: 063008
337 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
In RMII Mode, TX_EN is high with the first bit of the preamble. The TXD[1:0] is synchronous with the 50MHz
REF_CLK. For 10Mbps operation, the data bit outputs are updated every 10 clocks.
Figure 11-23. RMII Transmit Interface Functional Timing
REF_CLK
P
R
E
A
M
B
L
E
F
C
S
TXD[1:0]
TX_EN
RMII Receive data on RXD[1:0] is expected to be synchronous with the rising edge of the 50MHz REF_CLK. The
data is only valid if RX_CRS is high. The external PHY asynchronously drives RX_CRS low during carrier loss.
Figure 11-24. RMII Receive Interface Functional Timing
REF_CLK
P
R
E
A
M
B
L
E
F
C
S
RXD[1:0]
RX_CRS
Rev: 063008
338 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
12. Operating Parameters
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Lead with respect to VSS (except VDD) ...............................–0.5V to +5.5V
Supply Voltage Range (VDD3.3) with Respect to VSS ............................................–0.3V to +3.6V
Supply Voltage Range (VDD1.8) with Respect to VSS ............................................–0.3V to +2.0V
Ambient Operating Temperature Range*...................................................................–40ºC to +85ºC
Junction Operating Temperature Range ...................................................................–40ºC to +125ºC
Storage Temperature .................................................................................................–55ºC to +125ºC
Soldering Temperature .............................................................................................See J-STD-020 specification
These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
*Ambient Operating Temperature Range is assuming the device is mounted on a JEDEC standard test board in a convection cooled JEDEC
test enclosure.
Note: The “typ” values listed in this document are not production tested.
Note: All A/C timing parameters are guaranteed by design.
Table 12-1. Recommended DC Operating Conditions
(VDD3.3 = 3.3V ±5%,VDD2.5 = 2.5 ± 5%, VDD1.8 = 1.8 ± 5%, Tj = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
2.00
-0.30
TYP
MAX
5.5
UNITS
Logic 1 (Pins Other Than SDRAM)
Logic 0 (Pins Other Than SDRAM)
VIH
V
V
VIL
+0.80
VREF +
0.31
Logic 1, DDR SDRAM Interface
Logic 0, DDR SDRAM Interface
VIHDDR
VILDDR
2.625
V
V
VREF –
0.31
-0.30
VDD3.3
VDD2.5
VDDQ
3.135
2.375
2.375
1.71
3.3
2.5
2.5
1.8
1.8
3.465
2.625
2.625
1.89
V
V
V
V
V
V
Supply (VDD3.3) ±5%
Supply (VDD2.5) ±5%
Supply (VDDQ) ±5%
VDD1.8
AVDD
Supply (VDD1.8) ±5%
Supply (AVDD) ±5%
1.71
1.89
VREF DDR Voltage Reference
VVREF
1.1875
1.3125
Rev: 063008
339 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Table 12-2. DC Electrical Characteristics
(Tj = -40°C to +85°C.)
PARAMETER
I/O Supply Current (VDD3.3 = 3.465V)
Core Supply Current (VDD1.8 = 1.89)
AVDD 1.8V Supply Current
VDDQ 2.5V Supply Current
Power-Down I/O Current
SYMBOL CONDITIONS
MIN
TYP
30
MAX
50
300
10
150
1
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
pF
IDDIO
IDDCORE
IAVDD
IVDDQ
IPDIO
IPDCORE
IPDAVDD
IPDVDDQ
CIO
Notes 1, 2
Notes 1, 2
Notes 1, 2
Notes 1, 2
Note 3
260
5
120
Power-Down Core Current
Power-Down AVDD Current
Power-Down VDDQ Current
Lead Capacitance
Note 3
1
Note 3
5
Note 3
1
7
Input Leakage
IIL
-10
-100
-10
+10
-10
μA
μA
μA
V
Input Leakage (pins with internal pull-up)
Output Leakage (when Hi-Z)
Output Voltage (IOH = -4.0mA)
Output Voltage (IOL = +4.0mA)
Output Voltage (IOH = -8.0mA)
Output Voltage (IOL = +12.0mA)
IILP
ILO
+10
VOH
4 ma outputs
4 ma outputs
8 ma outputs
12 ma outputs
2.4
VOL
0.4
0.4
V
VOH
2.4
1.9
V
VOL
V
Output Voltage DDR SDRAM
(IOH = -8.1mA)
DDR SDRAM
outputs
VOHDDR
VOLDDR
V
V
Output Voltage DDR SDRAM
(IOL = +8.1mA)
DDR SDRAM
outputs
0.4
Note 1: Typical total power consumption for the DS33X162 at 400Mbps is approximately 1W.
Note 2: All outputs loaded with rated capacitance; all inputs between VDD and VSS; inputs with pullups connected to VDD.
Note 3: All disable and power-down bits set, RST held low, outputs not loaded.
Rev: 063008
340 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
12.1 Thermal Characteristics
Table 12-3. Thermal Characteristics
PARAMETER
Ambient Temperature
MIN
TYP
MAX
+85°C
+125°C
NOTES
1
-40°C
Junction Temperature
Theta-JA (θJA) in Still Air for
2
2
+29.9°C/W
+47.1°C/W
256-Ball CSBGA (17mm)2
Theta-JA (θJA) in Still Air for
144-Ball CSBGA (10mm)2
Note 1: The package is mounted on a four-layer JEDEC standard test board.
Note 2: Theta-JA (θJA) is the junction to ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard test board.
Rev: 063008
341 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
12.2 Transmit and Receive GMII Interface
Table 12-4. Transmit GMII Interface
1000Mbps
PARAMETER
SYMBOL
UNITS
MIN
TYP
MAX
GTX_CLK, RX_CLK Period
GTX_CLK Frequency
t1
1/t1
t3
7.5
8
8.5
ns
MHz
ns
125 - 100ppm
125
125 + 100ppm
GTX_CLK, RX_CLK High Time
GTX_CLK, RX_CLK Low Time
2.5
2.5
t2
ns
GTX_CLK to TXD, TX_ENn Output
Delay
t4
0.5
5.0
ns
Figure 12-1. Transmit GMII Interface Timing
t1
t2
GTX_CLK
t3
t4
t4
TXD[1:0]n
TX_ENn
Rev: 063008
342 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Table 12-5. Receive GMII Interface
1000Mbps
PARAMETER
SYMBOL
UNITS
MIN
TYP
MAX
RX_CLK Period
t5
1/t5
t6
7.5
ns
MHz
ns
RX_CLK Frequency
125
RX_CLK High Period
2.5
2.5
2.0
0.0
RX_CLK Low Period
t7
ns
RXD, RX_DV to RX_CLK Setup Time
RX_CLK to RXD, RX_DV Hold Time
t8
ns
t9
ns
Figure 12-2. Receive GMII Interface Timing
t5
t7
RX_CLKn
t6
t8
t9
RXD[3:0]n
t9
t8
RX_DVn
Rev: 063008
343 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
12.3 Transmit and Receive MII Interface
Table 12-6. Transmit MII Interface
10Mbps
TYP
100Mbps
TYP
PARAMETER
TX_CLK Period
SYMBOL
UNITS
MIN
MAX
MIN
MAX
t1
t2
t3
400
40
ns
ns
ns
TX_CLK Low Time
TX_CLK High Time
140
140
260
260
14
14
26
26
TX_CLK to TXD, TX_EN
Delay
t4
0
20
0
20
ns
Figure 12-3. Transmit MII Interface Timing
t1
t2
TX_CLKn
TXD[3:0]n
t3
t4
t4
TX_ENn
Rev: 063008
344 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Table 12-7. Receive MII Interface
10Mbps
TYP
100Mbps
TYP
PARAMETER
RX_CLK Period
SYMBOL
UNITS
MIN
MAX
MIN
MAX
t5
t6
t7
400
40
ns
ns
ns
RX_CLK Low Time
RX_CLK High Time
140
140
260
260
14
14
26
26
RXD, RX_DV to RX_CLK
Setup Time
t8
t9
5
5
5
5
20
ns
ns
RX_CLK to RXD, RX_DV
Hold Time
Figure 12-4. Receive MII Interface Timing
t5
t7
RX_CLKn
t6
t8
t9
RXD[3:0]n
RX_DVn
t9
t8
Rev: 063008
345 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
12.4 Transmit and Receive RMII Interface
Table 12-8. Transmit RMII Interface
10Mbps
TYP
100Mbps
TYP
PARAMETER
SYMBOL
UNITS
MIN
MAX
MIN
MAX
50MHz
±
50ppm
50MHz
±
50ppm
REF_CLK Frequency
REF_CLK Period
t1
t2
t3
20
20
ns
ns
ns
REF_CLK Low Time
REF_CLK High Time
7
7
13
13
7
7
13
13
REF_CLK to TXD,
TX_EN Delay
t4
3
10
3
10
ns
Figure 12-5. Transmit RMII Interface Timing
t1
t2
REF_CLK
t3
t4
TXD[1:0]
TX_EN
t4
Rev: 063008
346 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Table 12-9. Receive RMII Interface
10Mbps
TYP
100Mbps
TYP
PARAMETER
SYMBOL
UNITS
MIN
MAX
MIN
MAX
50MHz
±
50ppm
50MHz
±
50ppm
REF_CLK Frequency
MHz
REF_CLK Period
t1
t2
t3
20
20
ns
ns
ns
REF_CLK Low Time
REF_CLK High Time
7
7
13
13
7
7
13
13
RXD, RX_CRS to
REF_CLK Setup Time
t8
t9
5
5
5
5
ns
ns
REF_CLK to RXD,
RX_CRS Hold Time
Figure 12-6. Receive RMII Interface Timing
t5
t7
REF_CLK
t6
t8
t9
RXD[3:0]
t9
t8
RX_CRS
Rev: 063008
347 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
12.5 MDIO Interface
Table 12-10. MDIO Interface
PARAMETER
MDC Frequency
SYMBOL
MIN
TYP
2.016
496
MAX
UNITS
MHz
ns
2.5
MDC Period
t1
t2
t3
t4
t5
t6
400
160
160
0
MDC Low Time
ns
MDC High Time
ns
MDC to MDIO Output Delay
MDIO Input Setup Time
MDIO Input Hold Time
20
ns
10
0
ns
ns
Figure 12-7. MDIO Interface Timing
t1
t2
MDC
t3
t4
MDIO
MDC
t6
t5
MDIO
Rev: 063008
348 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
12.6 Transmit and Receive WAN Interface
Table 12-11. Transmit WAN Interface
PARAMETER
TCLK Frequency
SYMBOL
MIN
TYP
MAX
52
UNITS
MHz
ns
TCLK Period
t1
t2
t3
t4
t5
t6
19.2
8
1000
550
550
11
TCLK Low Time
ns
TCLK High Time
8
ns
TCLK to TDATA Output Delay
TSYNC Setup Time
TSYNC Hold Time
ns
7
7
ns
ns
Figure 12-8. Transmit WAN Timing (Noninverted TCLK)
t1
t2
TCLKn
t3
t4
TDATAn
t5
TSYNCn
t6
Rev: 063008
349 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Table 12-12. Receive WAN Interface
PARAMETER
RCLK Frequency
SYMBOL
MIN
TYP
MAX
52
UNITS
MHz
ns
RCLK Period
t1
t2
t3
t4
t4
t5
t5
19.2
8
1000
1000
1000
RCLK Low Time
ns
RCLK High Time
RDATAn Setup Time
RSYNCn Setup Time
RDATAn Hold Time
RSYNCn Hold Time
8
ns
7
ns
7
ns
2
ns
2
ns
Figure 12-9. Receive WAN Timing (Noninverted RCLK)
t1
t2
RCLKn
t3
t4
t4
t5
RDATAn
RSYNCn
t5
t5
t4
Rev: 063008
350 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
12.7 Transmit and Receive Voice Port Interface
Table 12-13. Transmit Voice Port Interface
PARAMETER
TVCLK Frequency
SYMBOL
MIN
TYP
MAX
UNITS
1/t1
16.384
MHz
%
TVCLK Clock Duty Cycle (High/Low)
T3/T2
40
50
60
4
TVCLK Rise or Fall Times (20% to 80%)
ns
TVDATA, TVDEN, TVSYNC to TVCLK
Setup Time
T4
T5
6
0
ns
ns
TVCLK to TVDATA, TVDEN, TVSYNC
Hold Time
Figure 12-10. Transmit Voice Port Interface Timing
t1
t2
TVCLK
t3
t4
t4
t5
TVDATA
t5
TVDEN
t5
t4
TVSYNC
Rev: 063008
351 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Table 12-14. Receive Voice Port Interface
PARAMETER
RVCLK Frequency
SYMBOL
MIN
TYP
MAX
UNITS
1/T1
16.384
MHz
%
RVCLK Clock Duty Cycle (High/Low)
RVCLK Rise or Fall Times (20% to 80%)
RVDEN, RVSYNC to RVCLK Setup Time
RVCLK to RVDEN, RVSYNC Hold Time
RVCLK to RVDATA Output Delay
T3/T2
40
50
60
4
ns
t5
t6
6
0
2
ns
ns
T4
10
ns
Figure 12-11. Receive Voice Port Interface Timing
t1
t2
RVCLK
t3
t4
RVDATA
t5
t6
RVSYNC
RVDEN
Rev: 063008
352 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
12.8 DDR SDRAM Interface
Table 12-15. DDR SDRAM Interface
PARAMETER
SD_CLK Output Period
SYMBOL
MIN
TYP
MAX
UNITS
t1
ns
7.5
8.5
ns
ns
SD_CLK Output High Period
t2
t3
t4
t5
t6
t7
t8
t9
3.6
3.6
3
4.4
4.4
5
SD_CLK Output Low Period
Address and Control Output Hold Time
SDATA Setup to SD_UDQS, SD_LDQS
SDATA Output hold to SD_UDQS, SD_LDQS
SD_UDQS, SD_LDQS Write Preamble
SD_UDQS, SD_LDQS Write Postamble
ns
ns
ns
ns
ns
ns
0.8
0.8
6
10
3.2
1
4.8
SD_UDQS, SD_LDQS to SD_UDM, SD_LDM
Hold Time
SD_UDM, SD_LDM to SD_UDQS, SD_LDQS
Setup Time
t10
1
ns
SD_UDQS, SD_LDQS to SDATA (Read)
SD_CLK to SD_LDQS, SD_UDQS (Read)
SD_LDQS, SD_UDQS High Pulse Width
SD_LDQS, SD_UDQS Low Pulse Width
t11
t12
t13
t14
-1
-1
+1
+1
ns
ns
ns
ns
3.4
3.4
4.5
4.5
Rev: 063008
353 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 12-12. DDR SDRAM Interface Timing
P0
P1
P2
P3
SD_CLK
SD_CLK
t1
t2
t3
WRITE
t4
Address /
Control
t5 t6
SDATA
t14
SD_UDQS
SD_LDQS
t7
t8
t13
t9
SD_UDM
SD_LDM
t10
READ
SD_CLK
SD_CLK
SD_UDQS
SD_LDQS
t12
SDATA
t11
Rev: 063008
354 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
12.9 AC Characteristics—Microprocessor Bus Interface Timing
Table 12-16. Parallel Microprocessor Bus
(VDD = 3.3V ± 5%, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Setup Time for A[10:0] Valid to Either RD, or
WR Active
t1
10
ns
Setup Time for CS Active to Either RD, or WR
Active
t2
t3
t4
t5
0
ns
ns
ns
ns
Delay Time from Either RD or DS Active to
DATA[7:0] Valid
75
20
Hold Time from Either RD or WR Inactive to
CS Inactive
0
Hold Time from CS or RD or DS Inactive to
DATA[7:0] Tri-State
2
80
10
2
t6
t7
t8
t9
ns
ns
ns
ns
Wait Time from WR Active to Latch Data
Data Setup Time to WR Inactive
Data Hold Time from WR Inactive
Address Hold from WR inactive
0
Write Access to Subsequent Write/Read
Access Delay Time
80
t10
ns
Rev: 063008
355 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 12-13. Intel Bus Read Timing (MODE = 0)
t9
Address Valid
ADDR[12:0]
Data Valid
DATA[7:0]
t5
WR
t1
CS
t2
t3
t4
t10
RD
Figure 12-14. Intel Bus Write Timing (MODE = 0)
t9
Address Valid
ADDR[12:0]
DATA[7:0]
t7
t8
t1
RD
CS
t2
t6
t4
t10
WR
Rev: 063008
356 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 12-15. Motorola Bus Read Timing (MODE = 1)
t9
Address Valid
ADDR[12:0]
Data Valid
DATA[7:0]
t5
t1
RW
CS
t2
t3
t4
t10
DS
Figure 12-16. Motorola Bus Write Timing (MODE = 1)
t9
Address Valid
ADDR[12:0]
DATA[7:0]
t7
t8
t1
W
R
CS
DS
t2
t6
t4
t10
Rev: 063008
357 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Table 12-17. Multiplexed Microprocessor Bus
PARAMETER
Input Rise/Fall Times
SYMBOL
MIN
TYP
MAX
UNITS
20
ns
t1
t2
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to WR, RD, or DS active
CS Setup to DS, WR, or RD active
Output Data Delay Time from DS or RD
DS, WR, or RD Inactive to CS inactive
Data Hold on Read
t3
75
20
t4
0
2
t5
t7
10
2
Data Setup to WR, or DS active
Data Hold on Write
t8
t9
2
ALE Fall to DS, WR, or RD active
DS, WR, or RD Inactive to DS, WR, or RD
Active
t10
t11
80
10
Address Valid to ALE active
Rev: 063008
358 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 12-17. Multiplexed Intel Bus Read Timing (MODE = 0)
ADDR[12:0]
DATA[7:0]
Data Valid
Address Valid
t5
WR
CS
t1
t2
t3
t4
t10
RD
t9
t11
ALE
Figure 12-18. Multiplexed Intel Bus Write Timing (MODE = 0)
ADDR[12:0]
Address Valid
DATA[7:0]
Data Valid
t7
t8
RD
t1
CS
t4
t10
t2
t9
t3
WR
t11
ALE
Rev: 063008
359 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 12-19. Multiplexed Motorola Bus Read Timing (MODE = 1)
ADDR[12:0]
DATA[7:0]
Data Valid
Address Valid
t5
RW
t1
CS
t2
t3
t4
t10
DS
t11
t9
ALE
Figure 12-20. Multiplexed Motorola Bus Write Timing (MODE = 1)
ADDR[12:0]
Address Valid
DATA[7:0]
Data Valid
t7
t8
RW
t1
CS
t2
t9
t3
t4
t10
DS
t11
ALE
Rev: 063008
360 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Table 12-18. SPI Microprocessor Bus Mode
SYMBOL (1)
CHARACTERISTIC (2)
Operating Frequency
MIN
MAX UNITS
10
—
—
—
—
—
—
—
25
—
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
t1
Cycle Time
100
15
15
50
50
5
t2
t3
t4
t5
t6
t7
t8
t9
Enable Lead Time
Enable Lag Time
Clock (SPI_CLK) High Time
Clock (SPI_CLK) Low Time
Data Setup Time (input)
Data Hold Time (input)
Disable Time (3)
15
—
5
Data Hold Time
Note 1:
Note 2:
Note 3:
Symbols refer to dimensions in the following figure.
100 pF load on all SPI pins.
Hold time to high-impedance state.
Figure 12-21. SPI Interface Timing Diagram
T3
CS
T2
T1
SPI_CLK
T4
T5
T9
T8
NOTE 2
MSB
BITS 6 - 1
LSB
SPI_MISO
SPI_MOSI
T6
T7
MSB
BIT 15
BITS 13 - 0
Rev: 063008
361 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
12.10 JTAG Interface
Table 12-19. JTAG Interface
(VDD = 3.3V ±5%, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
MIN
TYP
1000
500
MAX
UNITS
ns
JTCLK Clock Period
t1
t2 : t3
t4
JTCLK Clock High:Low Time (Note 1)
JTCLK to JTDI, JTMS Setup Time
JTCLK to JTDI, JTMS Hold Time
JTCLK to JTDO Delay
50
2
ns
ns
t5
2
ns
t6
2
50
50
ns
JTCLK to JTDO HIZ Delay
t7
2
ns
t8
100
ns
JTRST Width Low Time
Note 1: Clock can be stopped high or low.
Figure 12-22. JTAG Interface Timing
t1
t2
t3
JTCLK
t4
t5
JTDI, JTMS,
JTRST
t6
t7
JTD0
t8
JTRST
Rev: 063008
362 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
13. JTAG Information
The device supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTEST. Optional public
instructions included are HIGHZ, CLAMP, and IDCODE. See Table 13-1. The device contains the following as
required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
Test Access Port (TAP)
TAP Controller
Bypass Register
Boundary Scan Register
Device Identification Register
Instruction Register
The Test Access Port has the necessary interface pins; JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin
descriptions for details. Refer to IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994 for details about
the Boundary Scan Architecture and the Test Access Port.
Figure 13-1. JTAG Functional Block Diagram
BOUNDRY SCAN
REGISTER
IDENTIFICATION
REGISTER
MUX
BYPASS
REGISTER
INSTRUCTION
REGISTER
TEST ACCESS PORT
SELECT
CONTROLLER
TRI-STATE
VDD
VDD
VDD
10kΩ
10kΩ
10kΩ
JTDI
JTMS
JTCLK
JTDO
JTRST
Rev: 063008
363 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
13.1 JTAG TAP Controller State Machine Description
This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. The TAP
controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK.
13.1.1 TAP Controller State Machine
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK.
See Figure 13-2 for a diagram of the state machine operation.
13.1.1.1Test-Logic-Reset
Upon power-up, the TAP Controller is in the Test-Logic-Reset state. The Instruction register will contain the
IDCODE instruction. All system logic of the device will operate normally.
13.1.1.2Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and test
registers will remain idle.
13.1.1.3Select-DR-Scan
All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the controller into the
Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the
controller to the Select-IR-Scan state.
13.1.1.4Capture-DR
Data may be parallel-loaded into the test data registers selected by the current instruction. If the instruction does
not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its
current value. On the rising edge of JTCLK, the controller will go to the Shift-DR state if JTMS is LOW or it will go to
the Exit1-DR state if JTMS is HIGH.
13.1.1.5Shift-DR
The test data register selected by the current instruction is connected between JTDI and JTDO and will shift data
one stage towards its serial output on each rising edge of JTCLK. If a test register selected by the current
instruction is not placed in the serial path, it will maintain its previous state.
13.1.1.6Exit1-DR
While in this state, a rising edge on JTCLK will put the controller in the Update-DR state, which terminates the
scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW will put the controller in the Pause-
DR state.
13.1.1.7Pause-DR
Shifting of the test registers is halted while in this state. All test registers selected by the current instruction will
retain their previous state. The controller will remain in this state while JTMS is LOW. A rising edge on JTCLK with
JTMS HIGH will put the controller in the Exit2-DR state.
13.1.1.8Exit2-DR
A rising edge on JTCLK with JTMS HIGH while in this state will put the controller in the Update-DR state and
terminate the scanning process. A rising edge on JTCLK with JTMS LOW will enter the Shift-DR state.
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
13.1.1.9Update-DR
A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of the test
registers into the data output latches. This prevents changes at the parallel output due to changes in the shift
register.
13.1.1.10Select-IR-Scan
All test registers retain their previous state. The instruction register will remain unchanged during this state. With
JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and will initiate a scan
sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the
Test-Logic-Reset state.
13.1.1.11Capture-IR
The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is
loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller will enter the
Exit1-IR state. If JTMS is LOW on the rising edge of JTCLK, the controller will enter the Shift-IR state.
13.1.1.12Shift-IR
In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one
stage for every rising edge of JTCLK towards the serial output. The parallel register, as well as all test registers,
remains at their previous states. A rising edge on JTCLK with JTMS HIGH will move the controller to the Exit1-IR
state. A rising edge on JTCLK with JTMS LOW will keep the controller in the Shift-IR state while moving data one
stage thorough the instruction shift register.
13.1.1.13Exit1-IR
A rising edge on JTCLK with JTMS LOW will put the controller in the Pause-IR state. If JTMS is HIGH on the rising
edge of JTCLK, the controller will enter the Update-IR state and terminate the scanning process.
13.1.1.14Pause-IR
Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK will put the
controller in the Exit2-IR state. The controller will remain in the Pause-IR state if JTMS is LOW during a rising edge
on JTCLK.
13.1.1.15Exit2-IR
A rising edge on JTCLK with JTMS LOW will put the controller in the Update-IR state. The controller will loop back
to Shift-IR if JTMS is HIGH during a rising edge of JTCLK in this state.
13.1.1.16Update-IR
The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of
JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising
edge on JTCLK with JTMS held low will put the controller in the Run-Test-Idle state. With JTMS HIGH, the
controller will enter the Select-DR-Scan state.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 13-2. TAP Controller State Diagram
Test Logic
Reset
1
0
1
1
1
Run Test/
Idle
Select
DR-Scan
Select
IR-Scan
0
0
0
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
1
0
1
1
1
Exit DR
Exit IR
0
0
Pause DR
Pause IR
0
0
1
1
0
0
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
13.2 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the
TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in
the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial output at
JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS HIGH will move the controller
to the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift register to the
instruction parallel output. Instructions supported by the device and its respective operational binary codes are
shown in Table 13-1.
Table 13-1. Instruction Codes for IEEE 1149.1 Architecture
INSTRUCTION
SAMPLE:PRELOAD
BYPASS
SELECTED REGISTER
Boundary Scan
Bypass
Boundary Scan
Bypass
Bypass
Device Identification
INSTRUCTION CODES
010
111
000
011
100
001
EXTEST
CLAMP
HIGHZ
IDCODE
13.2.1 SAMPLE:PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation
of the device by using the Capture-DR state. SAMPLE:PRELOAD also allows the device to shift data into the
boundary scan register via JTDI using the Shift-DR state.
13.2.2 BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the
one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device’s normal
operation.
13.2.3 EXTEST
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction
register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output
pins are driven. The boundary scan register is connected between JTDI and JTDO. The Capture-DR will sample all
digital inputs into the boundary scan register.
13.2.4 CLAMP
All digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass
register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
13.2.5 HIGHZ
All digital outputs of the device are placed in a high-impedance state. The BYPASS register is connected between
JTDI and JTDO.
13.2.6 IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test register is
selected. The device identification code is loaded into the identification register on the rising edge of JTCLK
following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via
JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output. The
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
ID code will always have a 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and
number of continuation bytes followed by 16 bits for the device and 4 bits for the version.
13.3 JTAG ID Codes
Table 13-2. ID Code Structure
REVISION
ID[31:28]
DEVICE CODE
ID[27:12]
MANUFACTURER’S CODE
ID[11:1]
REQUIRED
ID[0]
DEVICE
DS33Xyy rev A1
DS33Xyy rev B1
0000
0001
0000 0000 0000 0110
0000 0000 0000 0110
000 1010 0001
000 1010 0001
1
1
13.4 Test Registers
IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An
optional test register has been included in the device. This test register is the identification register and is used in
conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
13.4.1 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells
and is n bits in length.
13.4.2 Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions, which
provides a short path between JTDI and JTDO.
13.4.3 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
13.5 JTAG Functional Timing
This functional timing for the JTAG circuits shows:
•
•
•
•
•
The JTAG controller starting from reset state.
Shifting out the first 4 LSB bits of the IDCODE.
Shifting in the BYPASS instruction (111) while shifting out the mandatory X01 pattern.
Shifting the TDI pin to the TDO pin through the bypass shift register.
An asynchronous reset occurs while shifting.
Figure 13-3. JTAG Functional Timing
IDCODE
(INST)
(STATE)
JTCLK
IDCODE
BYPASS
Update
DR
Shift IR
Test
Logic Idle
Run Test Select DR
Idle Scan
Capture
DR
Exit1
DR
Select DR
Scan
Select IR
Scan
Capture
IR
Exit1
IR
Update
IR
Select DR
Scan
Capture
DR
Shift
DR
Reset
Shift
DR
JTRST
JTMS
X
X
X
JTDI
X
X
JTDO
X
Output
Pin
Output pin level change if in "EXTEST" instruction mode
Rev: 063008
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________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
14. Pin Configuration
14.1 DS33X162/X161/X82/X81/X42/X41 Pin Configuration—256-Ball CSBGA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
F
JTCLK
SDA[3]
SDA[10]
SDCS
SDA[12]
SRAS
SWE
SD_CLK SD_CLK
VSS
VDDQ
VDDQ
SDATA[6] SDATA[4]
VDDQ
VDDQ
JTRST
JTMS
SDA[2]
SDA[1]
JTDI
SBA[1]
SDA[0]
SDA[4]
VDD1.8
SBA[0]
SDA[6]
SDA[7]
SDA[8]
VDD2.5
AVDD
SDA[9]
SDA[11]
VSSQ
VSSQ
VSS
SCAS
VSS
VDD2.5
VSSQ
VREF SDATA[12] SDATA[13] SDATA[15] SDATA[7]
SDATA[9] SDATA[11] SDATA[14] SDATA[5] SD_LDQS
VSSQ
VDDQ
VDDQ
COL1
SDATA[2] SDATA[1]
SDATA[3] SDATA[0]
SD_CLKE
N
RDATA1
RCLK1
SDA[5]
VDD1.8
RCLK5
SD_UDM SD_UDQS SDATA[8]
VDDQ
VDD3.3
VSS
VDD1.8 SDATA[10] SD_LDM
VSSQ
VSSQ
MDC
VSSQ
SYSCLKI
VSS
JTDO
VDD2.5
VDD3.3
RCLK2
RST
VSS
VDD3.3
VSS
AVSS
VSS
A10
VDD3.3 RX_CRS1
RXD[1] /
VDD1.8
RXD[2] /
RXD1[2]
RSYNC1 RDATA6 RDATA5
RXD1[1]
RXD[0] /
RXD1[0]
G
H
J
RCLK3
RSYNC3 RSYNC5 RDATA3
VDD3.3
VSS
VSS
RDATA2
DNC
CS
VSS
A8
VDD1.8
VDD1.8
MODE
A6
MDIO
RX_DV1 RX_CLK1
TXD[3] /
TXD1[3]
RXD[3] /
RXD1[3]
RSYNC4 RDATA4 RSYNC6
RCLK4
RCLK8
DNC
RSYNC2
VSS
VSS
VDD1.8
INT
RX_ERR1
HIZ
TXD[0] /
TXD1[0]
TXD[2] /
TXD1[2]
RCLK6
RCLK10
RCLK9
RCLK7
VDD3.3
DNC
D0 /
ALE
D2 /
RD / DS
WR / RW
A0
RX_CRS2
TX_EN1
SPI_SEL
D6 /
SPI_CPHA
TXD[1] /
TXD1[1]
RXD[7] /
RXD2[3]
K
L
RDATA7 RDATA9 RDATA10 RSYNC9
D4
A2
A4
A9
SPI_MISO SPI_CLK
D1 /
D3
D5 /SPI_
SWAP
RXD[6] /
RXD2[2]
RDATA8 RSYNC8 RSYNC11 RDATA12 RCLK13
RSYNC10 RCLK11
A1
A3
A5
A7
TX_ERR1
COL2
SPI_MOSI
D7 /
SPI_CPOL
RXD[5] /
RXD2[1]
M
N
P
R
T
VDD1.8 RSYNC13 TDATA5 TSYNC3
TCLK5
VDD3.3
TMCLK4 RX_DV2 RX_ERR2
VSS
RMII_SEL TX_CLK1
TXD[4] /
RXD[4] /
RXD2[0]
RDATA11 RCLK12 RDATA15 RDATA16 RSYNC7 TDATA6 TDATA7 TSYNC7 TDATA4 TDATA9 TDATA11 TDATA15 RX_CLK2 TMSYNC4
TXD2[0]
TXD[5] /
TXD2[1]
RSYNC12 RDATA13 RSYNC15 VDD3.3
TCLK2
TCLK1
VSS
TDATA3 TSYNC4 TSYNC6
TCLK4
TCLK6
TCLK8
TCLK7
TDATA16 TDATA14 DCEDTES TDATA13
TDATA10 TDATA12 VDD1.8 GTX_CLK
TMCLK3 TMSYNC3 REF_CLK VDD3.3
TX_EN2
TX_ERR2
TX_CLK2
TXD[6] /
TXD2[2]
RDATA14 RSYNC14 RCLK16
VSS
TSYNC1 TSYNC5
TCLK3
TDATA8
TXD[7] /
TXD2[3]
RCLK14
DNC
RSYNC16 RCLK15
TDATA1 TDATA2 TSYNC2 TSYNC8
Note: Shaded pins do not apply to all devices in the product family. See the pin listing for specific pin availability. In the high port
count devices, the shaded input pins DO NOT HAVE PULLUP/PULLDOWN resistors. Consideration must be taken during
board design to bias the inputs appropriately, and to float output pins (TDATA5-TDATA16, TX_EN2, TX_ERR2) if lower port
count designs are to be potentially stuffed with higher port count devices.
Rev: 063008
370 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
14.2 DS33W41/DS33W11 Pin Configuration—256-Ball CSBGA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
F
JTCLK
SDA[3]
SDA[10]
SDCS
SDA[12]
SRAS
SWE
SD_CLK SD_CLK
VSS
VDDQ
VDDQ
SDATA[6] SDATA[4]
VDDQ
VDDQ
JTRST
JTMS
SDA[2]
SDA[1]
JTDI
SBA[1]
SDA[0]
SDA[4]
VDD1.8
RVCLK
RVDEN
SBA[0]
SDA[6]
SDA[7]
SDA[8]
VDD2.5
AVDD
SDA[9]
SDA[11]
VSSQ
VSSQ
VSS
SCAS
VSS
VDD2.5
VSSQ
VREF SDATA[12] SDATA[13] SDATA[15] SDATA[7]
SDATA[9] SDATA[11] SDATA[14] SDATA[5] SD_LDQS
VSSQ
VDDQ
VDDQ
COL1
SDATA[2] SDATA[1]
SDATA[3] SDATA[0]
SD_CLKE
N
RDATA1
RCLK1
SDA[5]
VDD1.8
RVSYNC
RDATA3
RCLK4
SD_UDM SD_UDQS SDATA[8]
VDDQ
VDD3.3
VSS
VDD1.8 SDATA[10] SD_LDM
VSSQ
VSSQ
MDC
VSSQ
SYSCLKI
VSS
JTDO
VDD2.5
VDD3.3
RCLK2
RST
VSS
VDD3.3
VSS
AVSS
VSS
A10
VDD3.3 RX_CRS1
RXD[1] /
VDD1.8
RXD[2] /
RXD1[2]
RSYNC1 RVDATA
RXD1[1]
RXD[0] /
RXD1[0]
G
H
J
RCLK3
RSYNC3
VDD3.3
VSS
VSS
RDATA2
DNC
CS
VSS
A8
VDD1.8
VDD1.8
MODE
A6
MDIO
RX_DV1 RX_CLK1
TXD[3] /
TXD1[3]
RXD[3] /
RXD1[3]
RSYNC4 RDATA4
DNC
RSYNC2
VSS
VSS
VDD1.8
INT
RX_ERR1
HIZ
TXD[0] /
TXD1[0]
TXD[2] /
TXD1[2]
DNC
D0 /
ALE
D2 /
RD / DS
WR / RW
A0
SPI_SEL
D6 /
SPI_CPHA
TXD[1] /
TXD1[1]
RXD[7] /
RXD2[3]
K
L
VDD3.3
D4
A2
A4
A9
TX_EN1
SPI_MISO SPI_CLK
D1 /
D3
D5 /SPI_
SWAP
RXD[6] /
RXD2[2]
A1
A3
A5
A7
TX_ERR1
SPI_MOSI
D7 /
SPI_CPOL
RXD[5] /
RXD2[1]
M
N
P
R
T
VDD1.8
TVDATA TSYNC3
TVDEN
TVCLK
VDD3.3
VSS
RMII_SEL TX_CLK1
TXD[4] /
TXD2[0]
RXD[4] /
RXD2[0]
TDATA4
TCLK4
TXD[5] /
TXD2[1]
VDD3.3
VSS
TCLK2
TCLK1
VSS
TDATA3 TSYNC4
TSYNC1 TVSYNC
DCEDTES
TXD[6] /
TXD2[2]
TCLK3
VDD1.8 GTX_CLK
REF_CLK VDD3.3
TXD[7] /
TXD2[3]
DNC
RCLK15
TDATA1 TDATA2 TSYNC2
Note 1: Shaded pins do not apply to the DS33W11. See the pin listing for specific pin availability.
Note 2: The TVDEN pin is an input on the DS33W41/DS33W11, and is an output pin on other devices in the product family.
Rev: 063008
371 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
14.3 DS33X11 Pin Configuration—144-Ball CSBGA
1
2
3
4
5
6
7
8
9
10
11
12
VSS
VDDQ
SDA[0]
SDA[9]
SDCS
VSS
SD_CLK
SD_CLK
SDATA[15]
SDATA[4]
SDATA[0]
VSS
A
B
C
D
E
F
VDD2.5
SDA[4]
SDA[3]
SDA[5]
VDD1.8
RCLK1
VDD3.3
RSYNC1
VSS
SDA[2]
SDA[6]
SDA[1]
SDA[7]
RST
SDA[8]
SDA[10]
SDA[12]
VSS
SDA[11]
SBA[1]
SRAS
SWE
VSS
VDD2.5
VREF
SD_LDM
VSS
VSS
VDDQ
SDATA[10]
SDATA[8]
SDATA[9]
SD_LDQS
TX_EN1
TX_ERR1
TXD[2]
SDATA[14]
SDATA[12]
SDATA[13]
SDATA[11]
RX_DV1
RX_ERR1
TXD[3]
SDATA[5]
SDATA[7]
SDATA[6]
VDDQ
SDATA[1]
SDATA[3]
SDATA[2]
VSS
VDDQ
AVSS
SBA[0]
SCAS
SD_UDQS
SD_UDM
VSS
AVDD
VDDQ
SD_CLKEN
DNC
SYSCLKI
VSS
VDD3.3
JTCLK
JTDI
DNC
HIZ
VDD3.3
VSS
JTMS
JTRST
INT
VDD1.8
VDD3.3
VSS
VDD1.8
VDD3.3
VSS
COL1
RX_CRS1
VDD1.8
RX_CLK1
VDD3.3
TX_CLK1
VSS
G
H
J
JTDO
MDIO
MDC
RXD[2]
RXD[0]
RXD[6]
RXD[4]
GTX_CLK
RXD[3]
RXD[1]
RXD[7]
RXD[5]
VDD1.8
RDATA1
VSS
CS
SPI_MISO
SPI_MOSI
SPI_CLK
TSYNC1
SPI_SWAP
SPI_CPHA
SPI_CPOL
VDD1.8
TXD[0]
TXD[1]
DNC
VSS
RMII_SEL
DCEDTES
VDD3.3
TXD[5]
TXD[7]
K
L
VDD1.8
VSS
DNC
TDATA1
TCLK1
VSS
TXD[4]
TXD[6]
VDD3.3
VSS
REF_CLK
VSS
M
Note that the parallel bus is not available in the 144-pin DS33X11, and the SPI slave port must be used for processor control.
Rev: 063008
372 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
15. Package Information
The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for
each package is a link to the latest package outline information. For the latest package outline drawings and land patterns, go to
www.maxim-ic.com/packages.
15.1 256-Ball CSBGA, 17mm x 17mm (56-G6017-001)
Rev: 063008
373 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
15.2 144-Ball CSBGA, 10mm x 10mm (56-G6008-003)
Rev: 063008
374 of 375
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
16. Document Revision History
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
012108
Initial release (initial preliminary release 060607).
—
85
Added Section 8.19.3: Programmable Ethernet Destination Address Filtering.
Corrected AR.BFTOA bit names.
113, 223
131, 279
164
Corrected SU.GMIIA bits 10:6 names.
Corrected WNVDF bit definition (SU.WEM, bit 7).
Corrected LLIP[2:1] bit definition (SU.LIM, bits 3:2).
Clarified LP1PF[2:1] and LP1ETF[2:1] bit definitions (SU.LP1C, bits 4:1).
Clarified LP2PF[2:1] and LP2ETF[2:1] bit definitions (SU.LP2C, bits 4:1).
171
178
179
050808
Corrected AR.WQ1EA bits 15:8 names to correctly match the register bit map in
Table 10-2.
210
Clarified WISPL bit definition (AR.MQC, bit 3).
221
230
236
276
277
1
Updated EBBYS bit definition (PP.EMCR, bit 8).
Updated DBBS bit definition (PP.DMCR, bit 9).
Clarified LM bit definition (SU.MACCR, bit 12).
Added PM bit definition (SU.MACFFR, bit 0).
060508
063008
Removed future status from DS33W11 in the Ordering Information table.
Removed future status from DS33W41, DS33X41, DS33X42, DS33X82, and
DS33X161 in the Ordering Information table.
1
Rev: 063008
375 of 375
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are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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