DS3232MZ/V+ [MAXIM]
±5ppm, I2C Real-Time Clock with SRAM; 为± 5ppm的， I2C实时时钟与SRAM
| 型号： | DS3232MZ/V+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ±5ppm, I2C Real-Time Clock with SRAM |
| 文件： | 总23页 (文件大小：2166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-6247; Rev 1; 8/12
General Description
Features
2
The DS3232M is a low-cost, extremely accurate, I C
S Timekeeping Accuracy ±±ppm ꢀ±(ꢁ0.4 2ecꢂnoꢃ
real-time clock (RTC) with 236 bytes of battery-backed
SRAM. The device incorporates a battery input and
maintains accurate timekeeping when main power to the
device is interrupted. The integration of the microelec-
tromechanical systems (MEMS) resonator enhances the
long-term accuracy of the device and reduces the piece-
part count in a manufacturing line.
Day) frꢂm -0(NC tꢂ +8±NC
S 4.6 Bytes ꢂf Battery-Backeo User 2RAM
S Battery Backup fꢂr Cꢂntinuꢂus Timekeeping
S Lꢂw Pꢂwer Cꢂnsumptiꢂn
S Functiꢂnally Cꢂmpatible tꢂ D2.4.4
S Cꢂmplete Clꢂck Calenoar Functiꢂnality Incluoing
2ecꢂnos, Minutes, Hꢂurs, Day, Date, Mꢂnth, ano
Year with Leap Year Cꢂmpensatiꢂn Up tꢂ Year
41((
The RTC maintains seconds, minutes, hours, day, date,
month, and year information. The date at the end of the
month is automatically adjusted for months with fewer
than 31 days, including corrections for leap year. The
clock operates in either the 24-hour or 12-hour format
with an AM/PM indicator. Two programmable time-of-day
alarms and a 1Hz output are provided. Address and data
S Twꢂ Time-ꢂf-Day Alarms
S 1Hz ano .4ꢁ768kHz Outputs
S Reset Output ano Pushbuttꢂn Input with
2
are transferred serially through an I C bidirectional bus.
Debꢂunce
A precision temperature-compensated voltage reference
4
S Fast ꢀ0((kHz) I C-Cꢂmpatible 2erial Bus
and comparator circuit monitors the status of V
to
CC
S +4ꢁ.V tꢂ +0ꢁ±V 2upply Vꢂltage
detect power failures, to provide a reset output, and to
automatically switch to the backup supply when neces-
sary. Additionally, the RST pin is monitored as a pushbut-
ton input for generating a microprocessor reset. See the
Block Diagram for more details.
S Digital Temp 2ensꢂr with ±.NC Accuracy
S -0(NC tꢂ +8±NC Temperature Range
S 8-Pin 2O ꢀ1±( mils) Package
S Unoerwriters Labꢂratꢂries ꢀUL) Recꢂgnizeo
Applications
Typical Operating Circuit
Power Meters
Industrial Applications
V
V
CC
CC
Ordering Information appears at end of data sheet.
SCL
DS3232M
I/O PORT
SDA
INT/SQW
32KHZ
INTERRUPTS
CPU
RST
V
BAT
PUSH-
BUTTON
RESET
For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/DS3232M.related
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may
be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
DS3232M
±±55pm, C,Real-Tipe,Clock,with,SRAM,
2
AB2OLUTE MAXIMUM RATING2
Voltage Range on Any Pin Relative to GND........-0.3V to +6.0V
Operating Temperature Range.......................... -40NC to +85NC
Storage Temperature Range............................ -55NC to +125NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITION2
(T = -40NC to +85NC, unless otherwise noted.) (Note 1)
A
PARAMETER
Supply Voltage
2YMBOL
CONDITION2
MIN
2.3
TYP
3.3
MAX
4.5
UNIT2
V
CC
V
V
2.3
3.0
4.5
BAT
0.7 x
V
+
CC
0.3
Logic 1
Logic 0
V
V
V
IH
V
CC
0.3 x
V
V
-0.3
IL
CC
ELECTRICAL CHARACTERI2TIC2—FREQUENCY AND TIMEKEEPING
(V
or V
= +3.3V, T = -40NC to +85NC, unless otherwise noted. Typical values are at V
= +3.3V, V
= +3.0V, and
BAT
CC
BAT
A
CC
T
= +25NC, unless otherwise noted.) (Note 1)
A
PARAMETER
2YMBOL
Df/f
CONDITION2
MIN
TYP
MAX
UNIT2
1Hz Frequency Tolerance
Measured over R 10s interval
Q5
ppm
OUT
1Hz Frequency Stability vs. V
Voltage
CC
Df/V
tK
Q1
ppm/V
Seconds/
Day
Timekeeping Accuracy
Q0.432
Q2.5
A
32kHz Frequency Tolerance
Df/f
%
OUT
DC ELECTRICAL CHARACTERI2TIC2—GENERAL
(V
= +2.3V to +4.5V, T = -40NC to +85NC, unless otherwise noted. Typical values are at V
= +3.3V, V
= +3.0V, and
BAT
CC
A
CC
T
= +25NC, unless otherwise noted.) (Note 1)
A
PARAMETER
2YMBOL
CONDITION2
MIN
TYP
MAX
250
UNIT2
Active Supply Current
(I C Active)
I
(Note 2)
125
µA
CCA
2
Standby Supply Current
(I C Inactive)
I
(Notes 2, 3)
100
175
µA
CCS
2
4
DS3232M
±±55pm, C,Real-Tipe,Clock,with,SRAM,
2
DC ELECTRICAL CHARACTERI2TIC2—GENERAL ꢀcꢂntinueo)
(V
= +2.3V to +4.5V, T = -40NC to +85NC, unless otherwise noted. Typical values are at V
= +3.3V, V
= +3.0V, and
BAT
CC
A
CC
T
= +25NC, unless otherwise noted.) (Note 1)
A
PARAMETER
2YMBOL
CONDITION2
MIN
TYP
200
MAX
350
UNIT2
Temperature Conversion Current
(I C Inactive)
I
µA
V
CCSCONV
2
Power-Fail Voltage
V
2.45
2.575
2.70
0.4
PF
OL
OL
Logic 0 Output
(32KHZ, INT/SQW, SDA)
V
V
I
I
= 3mA
= 1mA
V
OL
OL
0.4
V
Logic 0 Output (RST)
Active supply > 3.3V, I
Active supply > 2.7V, I
Active supply > 2.3V, I
= -1mA
2.0
2.0
2.0
OH
OH
OH
Logic 1 Output (32KHZ)
V
= -0.75mA
= -0.14mA
V
OH
Output Leakage
(32KHZ, INT/SQW, SDA)
I
-0.1
+0.1
µA
LO
Input Leakage (SCL)
I
-0.1
-200
-100
+0.1
+10
µA
µA
nA
NC
LI
I
RST I/O Leakage
OL
V
Leakage
I
T = +25NC
A
25
Q3
+100
BAT
BATLKG
Temperature Accuracy
Temperature Conversion Time
Pushbutton Debounce
TEMP
V
or V
= +3.3V
ACC
CONV
CC
BAT
t
10
ms
ms
ms
ms
PB
250
250
25
DB
RST
OSF
Reset Active Time
t
Oscillator Stop Flag (OSF) Delay
t
(Note 4)
100
DC ELECTRICAL CHARACTERI2TIC2—V
CURRENT CON2UMPTION
BAT
(V
= 0V, V
= +2.3V to +4.5V, T = -40NC to +85NC, unless otherwise noted. Typical values are at V
= 0V, V
= +3.0V, and
BAT
CC
BAT
A
CC
T
= +25NC, unless otherwise noted.) (Note 1)
A
PARAMETER
2YMBOL
CONDITION2
MIN
TYP
MAX
UNIT2
Active Battery Current
(I C Active)
I
(Note 2)
25
1.8
200
75
µA
BATA
2
Timekeeping Battery Current
I
EN32KHZ = 0, INTCN = 1 (Note 2)
3.0
µA
µA
BATT
2
(I C Inactive)
Temperature Conversion Current
I
350
BATTC
2
(I C Inactive)
Data Retention Current
(Oscillator Stopped and I C
2
I
T
= +25NC
100
nA
BATDR
A
Inactive)
.
DS3232M
±±55pm, C,Real-Tipe,Clock,with,SRAM,
2
AC ELECTRICAL CHARACTERI2TIC2—POWER 2WITCH
(T = -40NC to +85NC, unless otherwise noted.) (Note 1, Figure 2)
A
PARAMETER
2YMBOL
CONDITION2
MIN
TYP
MAX
UNIT2
V
V
Fall Time, V
to
CC
PFMAX
t
300
Fs
VCCF
PFMIN
V
V
Rise Time, V
to
CC
PFMIN
t
0
Fs
VCCR
PFMAX
Recovery at Power-Up
t
(Note 5)
250
300
ms
REC
4
AC ELECTRICAL CHARACTERI2TIC2—I C INTERFACE
(V
or V
= +2.3V to +4.5V, T = -40NC to +85NC, unless otherwise noted. Typical values are at V
= +3.3V, V
= +3.0V, and
BAT
CC
BAT
A
CC
T
= +25NC, unless otherwise noted.) (Notes 1, 6, Figure 1)
A
PARAMETER
2YMBOL
CONDITION2
MIN
TYP
MAX
UNIT2
SCL Clock Frequency
f
0
400
kHz
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
0.6
Fs
Fs
BUF
Hold Time (Repeated) START
Condition
t
HD:STA
Low Period of SCL
High Period of SCL
Data Hold Time
t
1.3
0.6
0
Fs
Fs
Fs
ns
Fs
LOW
t
HIGH
t
0.9
HD:DAT
Data Set-Up Time
START Set-Up Time
t
100
0.6
SU:DAT
t
SU:STA
20 +
0.1C
SDA and SCL Rise Time
SDA and SCL Fall Time
t
(Note 7)
(Note 7)
300
300
ns
ns
R
B
20 +
t
F
0.1C
B
STOP Set-Up Time
t
0.6
Fs
SU:STO
SDA, SCL Input Capacitance
C
(Note 8)
10
pF
BIN
Nꢂte 1: Limits are 100% tested at T = +25°C and T = +85°C. Limits over the operating temperature range and relevant supply
A
A
voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Nꢂte 4: Includes the temperature conversion current (averaged).
Nꢂte .: Does not include RST leakage if V
< V
.
CC
PF
Nꢂte 0: The parameter t
is the period of time the oscillator must be stopped for the OSF flag to be set.
OSF
2
Nꢂte ±: The state of RST does not affect the I C interface or RTC functions.
Nꢂte 6: Interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with standard mode
2
I C timing.
Nꢂte 7: C = total capacitance of one bus line in picofarads.
B
Nꢂte 8: Guaranteed by design and not 100% production tested.
0
DS3232M
2
±±55pm, C,Real-Tipe,Clock,with,SRAM,
Timing Diagrams
SDA
SCL
t
BUF
t
F
t
SP
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
t
R
HD:STA
t
SU:STO
t
t
SU:DAT
HD:DAT
STOP
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO V
AND V
.
ILMAX
IHMIN
2
Figure 1. I C Timing
t
t
VCCF
VCCR
V
PFMAX
V
PFMIN
V
CC
t
REC
RST
Figure 2. Power Switch Timing
RST
PB
DB
t
RST
Figure 3. Pushbutton Reset Timing
±
DS3232M
2
±±55pm, C,Real-Tipe,Clock,with,SRAM,
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
RST OUTPUT VOLTAGE
vs. OUTPUT CURRENT
POWER-SUPPLY CURRENT
vs. POWER-SUPPLY VOLTAGE
BATTERY CURRENT
vs. BATTERY VOLTAGE
200
180
160
140
120
100
80
3.0
2.5
2.0
1.5
1.0
0.5
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 2.3V,
V
= 0V,
V
= 2.45V
CC
BAT
CC
EN32KHZ = 0,
INTCN = 1
EN32KHZ = 0,
INTCN = 1
T = +85°C
A
T = +85°C
A
T = +25°C
T = +25°C
A
A
T = -40°C
A
60
T = -40°C
A
V
PF
40
2.3
2.8
3.3
3.8
4.3
2.3
2.8
3.3
3.8
4.3
0
1
2
3
4
5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
OUTPUT CURRENT (mA)
INT/SQW OUTPUT VOLTAGE
vs. OUTPUT CURRENT
POWER-SUPPLY CURRENT
vs. SCL FREQUENCY
THERMOMETER ERROR
vs. TEMPERATURE
0.5
0.4
0.3
0.2
0.1
0
170
160
150
140
130
120
110
100
90
5
4
EN32KHZ = 0,
SDA = INACTIVE
V
= 3.3V
CC
V
= 2.7V
CC
3
4.0V
2
1
3.0V
0
-1
-2
-3
-4
-5
2.6V
80
70
0
2
4
6
8
10
0
100
200
300
400
-40
-10
20
50
80
OUTPUT CURRENT (mA)
SCL FREQUENCY (kHz)
TEMPERATURE (°C)
6
DS3232M
2
±±55pm, C,Real-Tipe,Clock,with,SRAM,
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
1Hz FREQUENCY ERROR
(DELTA FROM T0)
1Hz FREQUENCY ERROR
(MEASURED EVERY SECOND)
1Hz FREQUENCY ERROR
(MEASURED EVERY SECOND)
5
4
10
8
10
8
V
A
= 3.3V,
T = +25°C
V
A
= 3.3V,
T = +25°C
V
A
= 3.3V,
CC
T = +25°C
CC
CC
3
6
6
2
4
4
1
2
2
0
0
0
-1
-2
-3
-4
-5
-2
-4
-6
-8
-10
-2
-4
-6
-8
-10
0
5
10
15
20
25
30
0
5
10
15
20
25
30
0
5
10
15
20
25
30
TIME (MINUTES)
TIME (SECONDS)
TIME (MINUTES)
1Hz FREQUENCY ERROR
(10s THERMAL UPDATES
MEASURED EVERY SECOND)
1Hz FREQUENCY ERROR
(1s THERMAL UPDATES
MEASURED EVERY SECOND)
TIMEKEEPING ACCURACY
vs. TEMPERATURE
10
8
10
8
50
0
V
V
= 3.3V,
= 0V,
= +25°C
V
V
= 3.3V,
BAT
DS3232M ACCURACY
BAT
CC
= 0V,
CC
6
6
T
A
T = +25°C
A
4
4
2
2
-50
TYPICAL 20ppm
CRYSTAL,
0
0
UNCOMPENSATED
-2
-4
-6
-8
-10
-2
-4
-6
-8
-10
-100
-150
-200
0
5
10
15
20
25
30
0
5
10
15
20
25
30
-40
-20
0
20
40
60
80
TIME (SECONDS)
TIME (SECONDS)
TEMPERATURE (°C)
7
DS3232M
2
±±55pm, C,Real-Tipe,Clock,with,SRAM,
Pin Configuration
TOP VIEW
+
32KHZ
1
2
3
4
8
7
6
5
SCL
SDA
V
CC
DS3232M
INT/SQW
RST
V
BAT
GND
SO
Pin Description
PIN
NAME
FUNCTION
32.768KHZ Output (Push-Pull Output, 50% Duty Cycle). If enabled (EN32KHZ = 1), the 32kHz output is
1
32KHZ
active on V . If enabled for battery operation (BB32KHZ = 1), the output is also active on V
. When
CC
BAT
disabled, the output is forced low. This pin can be left unconnected if not used.
DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1FF to 1.0FF capacitor.
Connect to ground if not used.
2
3
V
CC
Active-Low Interrupt or 1Hz Square-Wave Output. This open-drain pin requires an external pullup resistor
connected to a supply at 4.5V or less. It can be left open if not used. This multifunction pin is determined
by the state of the INTCN bit in the Control register (0Eh). When INTCN is set to logic 0, this pin outputs
a 1Hz square wave. When INTCN is set to logic 1, a match between the timekeeping registers and either
of the alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the INTCN bit is set to
logic 1 when power is first applied, the pin defaults to an interrupt output with alarms disabled.
INT/
SQW
Active-Low Reset. This pin is an open-drain input/output. It indicates the status of V
relative to the V
PF
CC
specification. As V
falls below V , the RST pin is driven low. When V
exceeds V , for t
, the
CC
PF
CC
PF
RST
RST pin is pulled high by the internal pullup resistor. The active-low, open-drain output is combined with
a debounced pushbutton input function. This pin can be activated by a pushbutton reset request. It has
4
RST
an internal 50kI (R ) nominal value pullup resistor to V . No external pullup resistors should be con-
PU
CC
nected. If the oscillator is disabled, t
is bypassed and RST immediately goes high.
REC
5
6
GND
Ground
Backup Power-Supply Input. When using the device with the V
pin should be decoupled using a 0.1FF to 1.0FF low-leakage capacitor. When using the device with the V
input as the backup power source, the capacitor is not required. If V
input as the primary power source, this
BAT
BAT
V
is not used, connect to ground. The
BAT
BAT
device is UL recognized to ensure against reverse charging when used with a primary lithium battery. Go to
wwwꢁmaxim-icꢁcꢂmꢃqaꢃinfꢂꢃul for more information.
2
Serial-Data Input/Output. This pin is the data input/output for the I C serial interface. This open-drain pin
7
8
SDA
SCL
requires an external pullup resistor. The pullup voltage can be up to 4.5V, regardless of the voltage on V
.
CC
2
Serial-Clock Input. This pin is the clock input for the I C serial interface and is used to synchronize data
movement on the serial interface. The pullup voltage can be up to 4.5V, regardless of the voltage on V
.
CC
8
DS3232M
2
±±55pm, C,Real-Tipe,Clock,with,SRAM,
Block Diagram
*SELECTED
POWER
P
DS3232M
DIVIDER
32KHZ
N
N
INT/SQW
TIME-BASE
RESONATOR
1Hz
INTERRUPT
OR 1Hz
SELECT
V
BAT
V
CC
POWER
DIGITAL
CONTROL*
ADJUSTMENT
RST
TEMP
N
SENSOR
FACTORY TRIM
GND
CONTROL AND STATUS
REGISTERS
2
SDA
SCL
I C
CLOCK/CALENDAR
WITH ALARM
INTERFACE
SRAM
either the 24-hour or 12-hour format with an AM/PM indi-
cator. The internal registers are accessible though an I C
Detailed Description
2
bus interface. A temperature-compensated voltage refer-
The DS3232M is a serial real-time clock (RTC) driven by
an internal, temperature-compensated, microelectrome-
chanical systems (MEMS) resonator. The oscillator pro-
vides a stable and accurate reference clock and main-
tains the RTC to within Q0.432 seconds-per-day accu-
racy from -40NC to +85NC. The RTC is a low-power clock/
calendar with two programmable time-of-day alarms. INT/
SQW provides either an interrupt signal due to alarm
conditions or a 1Hz square wave. The clock/calendar
provides seconds, minutes, hours, day, date, month, and
year information. The date at the end of the month is auto-
matically adjusted for months with fewer than 31 days,
including corrections for leap year. The clock operates in
ence and comparator circuit monitors the level of V
to
CC
detect power failures and to automatically switch to the
backup supply when necessary. The RST pin provides
an external pushbutton function and acts as an indica-
tor of a power-fail event. Also available are 236 bytes of
general-purpose battery-backed SRAM.
Operation
The Block Diagram shows the device’s main elements.
Each of the major blocks is described separately in the
following sections.
9
DS3232M
2
±±55pm, C,Real-Tipe,Clock,with,SRAM,
High-Accuracy Time Base
+3.3V
The temperature sensor, oscillator, and digital adjust-
ment controller logic form the highly accurate time base.
The controller reads the output of the on-board tempera-
ture sensor and adjusts the final 1Hz output to maintain
the required accuracy. The device is trimmed at the
factory to maintain a tight accuracy over the operating
V
CC
V
BAT
temperature range. When the device is powered by V
,
CC
the adjustment occurs once a second. When the device
is powered by V , the adjustment occurs once every
BAT
10s to conserve power. Adjusting the 1Hz time base less
often does not affect the device’s long-term timekeeping
accuracy. The device also contains an Aging Offset reg-
ister that allows a constant offset (positive or negative) to
be added to the factory-trimmed adjustment value.
Figure 4. Single Supply (V
Only)
CC
V
CC
Power-Supply Configurations
The DS3232M can be configured to operate on a single
V
BAT
power supply (using either V
or V
) or in a dual-
BAT
CC
supply configuration, which provides a backup supply
source to keep the timekeeping circuits alive during
absence of primary system power.
Figure 4 illustrates a single-supply configuration using
V
only, with the V
input grounded. When V < V
,
CC
BAT
CC
PF
Figure 5. Single Supply (V
Only)
the RST output is asserted (active low). Temperature con-
BAT
versions are executed once per second.
Figure 5 illustrates a single-supply configuration using
+3.3V
V
only, with the V
input grounded. The RST output
BAT
CC
V
CC
is disabled and is held at ground through the connection
of the internal pullup resistor. Temperature conversions
are executed once every 10s.
V
BAT
Figure 6 illustrates a dual-supply configuration, using
the V
supply for normal system operation and the
supply for backup power. In this configuration, the
CC
V
BAT
power-selection function is provided by a temperature-
compensated voltage reference and a comparator circuit
that monitors the V
level. When V
is greater than
CC
CC
Figure 6. Dual Power Supply
V
, the device is powered by V . When V
is less
PF
CC
CC
than V but greater than V
by V . If V
, the device is powered
BAT
PF
is less than V and is less than V
, the
BAT
CC
CC
PF
device is powered by V
(see Table 1).
BAT
When V
low). When V
< V , the RST output is asserted (active
PF
CC
CC
is the presently selected power source,
temperature conversions are executed once per second.
When V is the presently selected power source, tem-
BAT
perature conversions are executed once every 10s.
1(
DS3232M
±±55pm, C,Real-Tipe,Clock,with,SRAM,
2
Table 1ꢁ Pꢂwer Cꢂntrꢂl
CONFIGURATION
CONDITION
IꢃO ACTIVE
IꢃO INACTIVE
RST
V
V
> V
< V
Inactive (High)
Active (Low)
V
Only
CC
PF
CC
I
I
CCS
CCA
(Figure 4)
CC
PF
I
EOSC = 0
EOSC = 1
V
Only
BATT
BAT
I
Disabled (Low)
Inactive (High)
Active (Low)
BATA
(Figure 5)
I
BATDR
V
> V
I
I
CCS
CC
PF
CCA
Dual Supply
(Figure 6)
V
V
> V
< V
I
V
V
> V
< V
I
CCS
CC
BAT
CCA
CC
BAT
V
< V
CC
PF
I
I
BATT
CC
BAT
BATA
CC
BAT
To preserve the battery, the first time V
is applied
the oscillator is stopped (EOSC = 1). This mode can be
used to minimize battery requirements for periods when
maintaining time and date information is not necessary,
e.g., while the end system is waiting to be shipped to a
customer.
BAT
to the device the oscillator does not start up until V
CC
2
exceeds V
or until a valid I C address is written to
PF
the device. Typical oscillator startup time is less than
1s. Approximately 2s after V
is applied, or a valid
CC
2
I C address is written, the device makes a temperature
measurement and applies the calculated correction to
the oscillator. Once the oscillator is running, it continues
Pushbutton Reset Function
The device provides for a pushbutton switch to be con-
nected to the RST input/output pin. When the device is
not in a reset cycle, it continuously monitors RST for a
low-going edge. If an edge transition is detected, the
device debounces the switch by pulling RST low. After
to run as long as a valid power source is available (V
CC
or V
), and the device continues to measure the tem-
BAT
perature and correct the oscillator frequency. On the first
application of V
power, or (if V
powered) when a
CC
BAT
the internal timer has expired (PB ), the device con-
DB
2
valid I C address is written to the device, the time and
date registers are reset to 01/01/00 01 00:00:00 (DD/MM/
YY DOW HH:MM:SS).
tinues to monitor the RST line. If the line is still low, the
device continuously monitors the line looking for a rising
edge. Upon detecting release, the device forces RST
V
BAT
Operation
low and holds it low for t
cate a power-fail condition. When V
. RST is also used to indi-
RST
There are several modes of operation that affect the
is lower than V
,
PF
CC
amount of V
is powered by V
the active battery current I
serial interface is inactive, the timekeeping current I
current that is drawn. While the device
an internal power-fail signal is generated, which forces
RST low. When V returns to a level above V , RST
BAT
and the serial interface is active,
BAT
CC
PF
is drawn. When the
is held low for approximately 250ms (t
) to allow the
BATA
REC
power supply to stabilize. If the oscillator is not running
when V is applied, t is bypassed and RST imme-
BATT
(which includes the averaged temperature-conversion
CC
REC
current I
current I
) is used. The temperature-conversion
BATTC
is specified since the system must be
BATTC
diately goes high. Assertion of the RST output, whether
by pushbutton or power-fail detection, does not affect
the device’s internal operation. RST output operation and
able to support the periodic higher current pulse and
still maintain a valid voltage level. The data-retention
pushbutton monitoring are only available if V
available.
power is
CC
current I
is the current drawn by the device when
BATDR
11
DS3232M
±±55pm, C,Real-Tipe,Clock,with,SRAM,
2
00h, the current time is transferred to a second set of
registers. The time information is read from these sec-
ondary registers, while the clock can continue to run.
This eliminates the need to reread the registers in case
the main registers update during a read.
Real-Time Clock (RTC)
With the 1Hz source from the temperature-compensated
oscillator, the RTC provides seconds, minutes, hours,
day, date, month, and year information. The date at the
end of the month is automatically adjusted for months
with fewer than 31 days, including corrections for leap
year. The clock operates in either the 24-hour or the
12-hour format with an AM/PM indicator. The clock pro-
vides two programmable time-of-day alarms. INT/SQW
can be enabled to generate either an interrupt due to an
alarm condition or a 1Hz square wave. This selection is
controlled by the INTCN bit in the Control register.
Clock and Calendar
The time and calendar information is obtained by reading
the appropriate register bytes. Table 2 shows the RTC
registers. The time and calendar data are set or initialized
by writing the appropriate register bytes. The contents of
the time and calendar registers are in the binary-coded
decimal (BCD) format. The device can be run in either
12-hour or 24-hour mode. Bit 6 of the Hours register is
defined as the 12-hour or 24-hour mode select bit. When
high, the 12-hour mode is selected. In the 12-hour mode,
bit 5 is the AM/PM bit with logic-high being PM. In the
24-hour mode, bit 5 is the 20-hour bit (20–23 hours).
The century bit (bit 7 of the Month register) is toggled
when the Years register overflows from 99 to 00. The
day-of-week register increments at midnight. Values that
correspond to the day of week are user-defined but must
be sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on). Illogical time and date entries result
in undefined operation. When reading or writing the time
and date registers, secondary buffers are used to prevent
errors when the internal registers update. When reading
the time and date registers, the secondary buffers are
2
I C Interface
2
The I C interface is accessible whenever either V
or
CC
V
BAT
is at a valid level. If a microcontroller connected
to the device resets because of a loss of V
event, it is possible that the microcontroller and device’s
or other
CC
2
I C communications could become unsynchronized,
e.g., the microcontroller resets while reading data from
the device. When the microcontroller resets, the device’s
2
I C interface can be placed into a known state by tog-
gling SCL until SDA is observed to be at a high level. At
that point the microcontroller should pull SDA low while
SCL is high, generating a START condition.
SRAM
The DS3232M provides 236 bytes of general-purpose
2
battery-backed read/write memory. The I C address
2
synchronized to the internal registers on any I C START
ranges from 14h–FFh. The SRAM can be written or read
and when the register pointer rolls over to zero. The time
information is read from these secondary registers, while
the clock continues to run. This eliminates the need to
reread the registers in case the main registers update
during a read. The countdown chain is reset whenever
the seconds register is written. Write transfers occur on
the acknowledge from the device. Once the countdown
chain is reset, to avoid rollover issues the remaining time
and date registers must be written within 1s.
whenever V
ating voltage.
or V
is greater than the minimum oper-
CC
BAT
Address Map
Table 2 shows the address map for the device’s time-
keeping registers. During a multibyte access, when
the address pointer reaches the end of the register
space (12h), it wraps around to location 00h. On an
2
I C START or address pointer incrementing to location
14
DS3232M
±±55pm, C,Real-Tipe,Clock,with,SRAM,
2
Table 4ꢁ Timekeeping Registers
BIT 7
M2B
BIT (
L2B
ADDRE22
BIT 6
BIT ±
BIT 0
BIT .
BIT 4
BIT 1
FUNCTION
RANGE
00h
01h
0
0
10 Seconds
10 Minutes
AM/PM
Seconds
Seconds
Minutes
00–59
00–59
Minutes
Hour
1–12 +
AM/PM
00–23
10
Hours
02h
0
Hours
12/24
20
Hours
03h
04h
0
0
0
0
0
0
0
Day
Day
1–7
10 Date
Date
Month
Year
Date
01–31
10
Month
01–12 +
Century
05h
06h
07h
Century
0
0
Month/Century
10 Year
Year
00–99
Alarm 1
Seconds
A1M1
A1M2
10 Seconds
Seconds
00–59
Alarm 1
Minutes
08h
09h
10 Minutes
Minutes
Hour
00–59
AM/PM
1–12 +
AM/PM
00–23
10
Hours
A1M3
Alarm 1 Hours
12/24
20
Hours
Day
Alarm 1 Day
Alarm 1 Date
1–7
0Ah
0Bh
A1M4
A2M2
10 Date
DY/DT
Date
1–31
Alarm 2
Minutes
10 Minutes
Minutes
Hour
00–59
AM/PM
1–12 +
AM/PM
00–23
10
0Ch
0Dh
A2M3
A2M4
Alarm 2 Hours
12/24
20
Hours
Hours
Day
Alarm 2 Day
Alarm 2 Date
Control
1–7
1–31
—
10 Date
DY/DT
Date
0Eh
0Fh
10h
BBSQW
BB32KHZ
DATA
CONV
0
NA
0
NA
INTCN
A2IE
A2F
A1IE
A1F
EOSC
OSF
EN32KHZ
DATA
BSY
Status
—
SIGN
DATA
DATA
DATA
DATA
DATA
Aging Offset
—
Temperature
MSB
11h
12h
SIGN
DATA
DATA
DATA
DATA
0
DATA
0
DATA
0
DATA
0
DATA
0
DATA
0
—
—
Temperature
LSB
13h
SWRST
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
Test
—
14h–FFh
SRAM
00h–FFh
Note: Unless otherwise specified, the registers’ state is not defined when power is first applied.
1.
DS3232M
±±55pm, C,Real-Tipe,Clock,with,SRAM,
2
not listed in the table result in illogical operation. The
DY/DT bits (bit 6 of the alarm day/date registers) con-
trol whether the alarm value stored in bits 0–5 of that
register reflects the day of the week or the date of the
month. If DY/DT is written to logic 0, the alarm is the
result of a match with date of the month. If DY/DT is
written to logic 1, the alarm is the result of a match
with day of the week. When the RTC register values
match alarm register settings, the corresponding alarm
flag A1F or A2F bit is set to logic 1. If the correspond-
ing alarm interrupt enable A1IE or A2IE bit is also set
to logic 1, the alarm condition activates the INT/SQW
signal if the INTCN bit is set to logic 1. The match is
tested on the once-per-second update of the time and
date registers.
Alarms
The device contains two time-of-day/date alarms.
Alarm 1 can be set by writing to registers 07h–0Ah.
Alarm 2 can be set by writing to registers 0Bh–0Dh.
See Table 2. The alarms can be programmed (by the
alarm enable and INTCN bits in the Control register)
to activate the INT/SQW output on an alarm match
condition. Bit 7 of each of the time-of-day/date alarm
registers are mask bits (Table 2). When all the mask
bits for each alarm are logic 0, an alarm only occurs
when the values in the timekeeping registers match the
corresponding values stored in the time-of-day/date
alarm registers. The alarms can also be programmed
to repeat every second, minute, hour, day, or date.
Table 3 shows the possible settings. Configurations
Table .ꢁ Alarm Mask Bits
ALARM 1 REGI2TER MA2K BIT2 ꢀBIT 7)
ALARM RATE
DYꢃDT
A1M0
A1M.
A1M4
A1M1
X
X
X
X
0
1
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Alarm once a second
Alarm when seconds match
Alarm when minutes and seconds match
Alarm when hours, minutes, and seconds match
Alarm when date, hours, minutes, and seconds match
Alarm when day, hours, minutes, and seconds match
ALARM 4 REGI2TER MA2K BIT2 ꢀBIT 7)
ALARM RATE
DYꢃDT
A4M0
A4M.
A4M4
X
X
X
0
1
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Alarm once per minute (00 seconds of every minute)
Alarm when minutes match
Alarm when hours and minutes match
Alarm when date, hours, and minutes match
Alarm when day, hours, and minutes match
10
DS3232M
2
±±55pm, C,Real-Tipe,Clock,with,SRAM,
Control Register (0Eh)
BIT 7
BIT 6
BBSQW
0
BIT ±
CONV
0
BIT 0
NA
1
BIT .
NA
1
BIT 4
INTCN
1
BIT 1
A2IE
0
BIT (
A1IE
0
EOSC
0
EOSC: Enable oscillator. When set to logic 0, the oscillator is started. When set to logic 1, the oscillator is
stopped when the device switches to V . This bit is clear (logic 0) when power is first applied. When the
BAT
BIT 7
BIT 6
device is powered by V , the oscillator is always on regardless of the status of the EOSC bit. When the oscil-
CC
lator is disabled, all register data is static.
BB2QW: Battery-backed square-wave enable. When set to logic 1 with INTCN = 0 and V
< V , this bit
PF
CC
enables the 1Hz square wave. When BBSQW is logic 0, INT/SQW goes high impedance when V
falls below
CC
V
. This bit is disabled (logic 0) when power is first applied.
PF
CONV: Convert temperature. Setting this bit to 1 forces the temperature sensor to convert the temperature
into digital code and execute the temperature compensate algorithm to update the oscillator’s accuracy. The
device cannot be forced to execute the temperature-compensate algorithm faster than once per second. A
user-initiated temperature conversion does not affect the internal update cycle. The CONV bit remains at a 1
from the time it is written until the temperature conversion is completed, at which time both CONV and BSY go
to 0. The CONV bit should be used when monitoring the status of a user-initiated conversion. See Figure 7 for
more details.
BIT 5
BITS 4:3
BIT 2
NA: Not applicable. These bits have no affect on the device and can be set to either 0 or 1.
INTCN: Interrupt control. This bit controls the INT/SQW output signal. When the INTCN bit is set to logic 0, a
1Hz square wave is output on INT/SQW. When the INTCN bit is set to logic 1, a match between the timekeep-
ing registers and either of the alarm registers activates the INT/SQW output (if the alarm is also enabled). The
corresponding alarm flag is always set regardless of the state of the INTCN bit. The INTCN bit is set to a logic
1 when power is first applied.
A4IE: Alarm 2 interrupt enable. When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status reg-
ister to assert INT/SQW (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the
A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied.
BIT 1
BIT 0
A1IE: Alarm 1 interrupt enable. When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status reg-
ister to assert INT/SQW (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the
A1F bit does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied.
1±
DS3232M
±±55pm, C,Real-Tipe,Clock,with,SRAM,
2
V
POWERED
CC
INTERNAL 1Hz
CLOCK
BSY
CONV
THE DEVICE CLEARS THE CONV BIT
AFTER THE TEMPERATURE CONVERSION
HAS COMPLETED
BSY IS HIGH DURING
THE TEMPERATURE CONVERSION
THE USER SETS THE CONV BIT
V
BAT
POWERED
10 SECONDS
INTERNAL 1Hz
CLOCK
BSY
CONV
THE DEVICE CLEARS THE CONV BIT
THE USER SETS THE CONV BIT
AFTER THE TEMPERATURE CONVERSION
HAS COMPLETED
Figure 7. CONV Control Bit and BSY Status Bit Operation
16
DS3232M
2
±±55pm, C,Real-Tipe,Clock,with,SRAM,
Status Register (0Fh)
BIT 7
OSF
1
BIT 6
BB32KHZ
1
BIT ±
BIT 0
BIT .
EN32KHZ
1
BIT 4
BSY
X
BIT 1
A2F
X
BIT (
A1F
X
0
0
0
0
O2F: Oscillator stop flag. A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for
some period and could be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time
that the oscillator stops. This bit remains at logic 1 until written to logic 0. The following are examples of
conditions that can cause the OSF bit to be set:
BIT 7
1) The first time power is applied.
2) The voltages present on both VCC and VBAT are insufficient to support the oscillator.
3) The EOSC bit is turned off in battery-backed mode.
4) External influences on the oscillator (i.e., noise, leakage, etc.).
BB.4KHZ: Battery-backed 32kHz output (BB32KHZ). This bit enables the 32kHz output when the device is pow-
ered from VBAT (provided the 32kHz output is enabled with the EN32KHZ bit). If BB32KHZ = 0, the 32kHz output
is forced low when the device is powered by VBAT.
BIT 6
BITS 5:4
BIT 3
Unused (0). These bits have no meaning and are fixed at 0 when read.
EN.4KHZ: Enabled 32.768kHz output. This bit enables and disables the 32KHZ output. When set to a logic 0,
the 32KHZ output is high impedance. On initial power-up, this bit is set to a logic 1 and the 32KHZ output is
enabled and produces a 32.768kHz square wave if the oscillator is enabled.
B2Y: Busy. This bit indicates the device is busy executing temperature conversion function. It goes to logic 1
when the conversion signal to the temperature sensor is asserted, and then it is cleared when the device has
completed the temperature conversion. See the Block Diagram for more details.
BIT 2
BIT 1
BIT 0
A4F: Alarm 2 flag. A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. If the
A2IE bit is logic 1 and the INTCN bit is set to logic 1, INT/SQW is also asserted. A2F is cleared when written to
logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
A1F: Alarm 1 flag. A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. If the
A1IE bit is logic 1 and the INTCN bit is set to logic 1, INT/SQW is also asserted. A1F is cleared when written to
logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
17
DS3232M
2
±±55pm, C,Real-Tipe,Clock,with,SRAM,
Aging Offset Register (10h)
BIT 7
SIGN
0
BIT 6
DATA
0
BIT ±
DATA
0
BIT 0
DATA
0
BIT .
DATA
0
BIT 4
DATA
0
BIT 1
DATA
0
BIT (
DATA
0
The Aging Offset register takes a user-provided value to add to or subtract from the factory-trimmed value that adjusts the
accuracy of the time base. Use of the Aging Offset register is not needed to achieve the accuracy as defined in the Electrical
Characteristics tables.
The Aging Offset code is encoded in two’s complement, with bit 7 representing the SIGN bit. One LSB typically represents a
0.12ppm change in frequency. The change in ppm per LSB is the same over the operating temperature range. Positive offsets
slow the time base and negative offsets quicken the time base.
Temperature Registers (11h–12h)
Temperature Register ꢀUpper Byte = 11h)
BIT 7
SIGN
0
BIT 6
DATA
0
BIT ±
DATA
0
BIT 0
DATA
0
BIT .
DATA
0
BIT 4
DATA
0
BIT 1
DATA
0
BIT (
DATA
0
Temperature Register ꢀLꢂwer Byte = 14h)
BIT 7
DATA
0
BIT 6
DATA
0
BIT ±
BIT 0
BIT .
BIT 4
BIT 1
BIT (
0
0
0
0
0
0
0
0
0
0
0
0
Temperature is represented as a 10-bit code with a resolution of 0.25°C and is accessible at location 11h and 12h. The tem-
perature is encoded in two’s complement format. The upper 8 bits, the integer portion, are at location 11h and the lower 2 bits,
the fractional portion, are at location 12h. For example, 00011001 01b = +25.25°C. Upon power reset, the registers are set to
a default temperature of 0°C and the controller starts a temperature conversion. The temperature is read upon initial applica-
2
tion of V
or I C access on V
and once every second afterwards with V
power or once every 10s with V
power. The
CC
BAT
CC
BAT
Temperature registers are also updated after each user-initiated conversion and are read only.
18
DS3232M
2
±±55pm, C,Real-Tipe,Clock,with,SRAM,
Test Register (13h)
BIT 7
SWRST
0
BIT 6
BIT ±
BIT 0
BIT .
BIT 4
BIT 1
BIT (
NAME:
POR*:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*POR is defined as the first application of power to the device, either V
or V
.
BAT
CC
This register is used for factory test. Bits 6:0 are locked and always read as zeros. Writing to bit locations 6:0 has no affect on the
device. If the SWRST bit is set to Logic 1, the device immediately resets all internal logic and registers (except the SRAM) to their
factory-default POR state.
The device reset occurs during the normal acknowledge time slot following the receipt of the data byte carrying that SWRST
instruction; a NACK occurs due to the resetting action (see Figure 8). The I/O master should terminate the I/O string with a nor-
mal STOP instruction (on the 28th SCL clock). The SWRST bit is automatically cleared to logic 0.
SLAVE ACKs
NACK DURING SWRST
SDA
SCL
1
1
0
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
SLAVE ADDRESS
R/W
REGISTER ADDRESS
DATA
Figure 8. Software Reset I/O Execution
SRAM (14h–FFh)
BIT 7
D7
BIT 6
D6
BIT ±
D5
BIT 0
D4
BIT .
D3
BIT 4
D2
BIT 1
D1
BIT (
D0
NAME:
POR*:
X
X
X
X
X
X
X
X
*POR is defined as the first application of power to the device, either V
or V
.
BAT
CC
19
DS3232M
2
±±55pm, C,Real-Tipe,Clock,with,SRAM,
transfer. A repeated START condition is issued identi-
cally to a normal START condition. See Figure 1 for
applicable timing.
2
I C Serial Port Operation
2
I C Slave Address
The device’s slave address byte is D0h. The first byte
sent to the device includes the device identifier, device
address, and the R/W bit (Figure 9). The device address
sent by the I C master must match the address assigned
to the device.
Bit Write: Transitions of SDA must occur during
the low state of SCL. The data on SDA must remain
valid and unchanged during the entire high pulse of
SCL plus the setup and hold time requirements (see
Figure 1). Data is shifted into the device during the
rising edge of the SCL.
2
2
I C Definitions
Bit Reao: At the end of a write operation, the master
must release the SDA bus line for the proper amount
of setup time (see Figure 1) before the next rising
edge of SCL during a bit read. The device shifts out
each bit of data on SDA at the falling edge of the pre-
vious SCL pulse and the data bit is valid at the rising
edge of the current SCL pulse. Remember that the
master generates all SCL clock pulses including when
it is reading bits from the slave.
The following terminology is commonly used to describe
2
I C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
2lave Devices: Slave devices send and receive data
at the master’s request.
Bus Iole ꢂr Nꢂt Busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states. When the bus is idle,
it often initiates a low-power mode for slave devices.
Acknꢂwleoge ꢀACK ano NACK): An acknowledge
(ACK) or not acknowledge (NACK) is always the ninth
bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
during a write operation) performs an ACK by trans-
mitting a 0 during the ninth bit. A device performs
a NACK by transmitting a 1 during the ninth bit.
Timing for the ACK and NACK is identical to all other
bit writes. An ACK is the acknowledgment that the
device is properly receiving data. A NACK is used to
terminate a read sequence or as an indication that the
device is not receiving data.
2TART Cꢂnoitiꢂn: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 1 for applicable timing.
2TOP Cꢂnoitiꢂn: A STOP condition is generated
by the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See Figure 1 for
applicable timing.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgment from
the slave to the master. The 8 bits transmitted by the
master are done according to the bit write definition
and the acknowledgment is read using the bit read
definition.
Repeateo 2TART Cꢂnoitiꢂn: The master can use
a repeated START condition at the end of one data
transfer to indicate that it immediately initiates a new
data transfer following the current one. Repeated
STARTs are commonly used during read operations
to identify a specific memory address to begin a data
Byte Reao: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the
bit read definition, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to
terminate communication so the slave returns control
of SDA to the master.
LSB
R/W
MSB
1
1
0
1
0
0
0
DEVICE
IDENTIFIER
READ/
WRITE BIT
2
Figure 9. I C Slave Address Byte
4(
DS3232M
±±55pm, C,Real-Tipe,Clock,with,SRAM,
2
2
2
2lave Aooress Byte: Each slave on the I C bus
I C Communication
2
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/W bit in the least significant bit. The
device’s slave address is D0h and cannot be modi-
fied by the user. When the R/W bit is 0 (such as in
D0h), the master is indicating it writes data to the
slave. If R/W = 1 (D1h in this case), the master is
indicating it wants to read from the slave. If an incor-
rect slave address is written, the device assumes the
See Figure 10 for an I C communication example.
Writing a 2ingle Byte tꢂ a 2lave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write
the byte of data, and generate a STOP condition.
Remember the master must read the slave’s acknowl-
edgment during all byte write operations.
Writing Multiple Bytes tꢂ a 2lave: To write multiple
bytes to a slave, the master generates a START con-
dition, writes the slave address byte (R/W = 0), writes
the starting memory address, writes multiple data
bytes, and generates a STOP condition.
2
master is communicating with another I C device and
ignore the communication until the next START condi-
tion is sent.
Reaoing a 2ingle Byte frꢂm a 2lave: Unlike the write
operation that uses the specified memory address
byte to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the slave,
the master generates a START condition, writes the
2
Memꢂry Aooress: During an I C write operation, the
master must transmit a memory address to identify
the memory location where the slave is to store the
data. The memory address is always the second byte
transmitted during a write operation following the
slave address byte.
2
TYPICAL I C WRITE TRANSACTION
MSB
1
LSB
R/W
MSB
LSB
MSB
LSB
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START
1
0
1
0
0
0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
STOP
READ/
WRITE
REGISTER ADDRESS
SLAVE
ADDRESS
DATA
2
EXAMPLE I C TRANSACTIONS
D0h
0Eh
44h
A) SINGLE BYTE WRITE
-WRITE CONTROL REGISTER
TO 44h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
1 1 0 1 0 0 0 0
0 0 0 0 1 1 1 0
0 1 0 0 0 1 0 0
STOP
START
D0h
0Eh
D1h
1 1 0 1 0 0 0 1
DATA
B) SINGLE BYTE READ
-READ CONTROL REGISTER
SLAVE
ACK
SLAVE
ACK
REPEATED
START
SLAVE
ACK
MASTER
NACK
START 1 1 0 1 0 0 0 0
0 0 0 0 1 1 1 0
VALUE
STOP
D0h
04h
02h
11h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
C) MULTIBYTE WRITE
-WRITE DATE REGISTER
TO "02" AND MONTH
REGISTER TO "11"
START 1 1 0 1 0 0 0 0
0 0 0 0 0 1 0 0
0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 1
STOP
D1h
1 1 0 1 0 0 0 1
DATA
DATA
VALUE
D0h
0Ch
SLAVE
ACK
SLAVE
ACK
REPEATED
START
SLAVE
ACK
MASTER
ACK
MASTER
NACK
D) MULTIBYTE READ
-READ ALARM 2 HOURS
AND DATE VALUES
START 1 1 0 1 0 0 0 0
0 0 0 0 1 1 0 0
VALUE
STOP
2
Figure 10. I C Transactions
41
DS3232M
±±55pm, C,Real-Tipe,Clock,with,SRAM,
2
slave address byte with R/W = 1, reads the data byte
Using Open-Drain Outputs
The INT/SQW output is open drain and requires an exter-
nal pullup resistor to realize logic-high output level. Pullup
resistor values between 1kI and 10MI are typical.
with a NACK to indicate the end of the transfer, and
generates a STOP condition. However, since requir-
ing the master to keep track of the memory address
counter is impractical, use the method for manipulat-
ing the address counter for reads.
The RST output is also open drain, but is provided with
an internal 50kI pullup resistor (R ) to V . External
PU
CC
Manipulating the Aooress Cꢂunter fꢂr Reaos: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the mas-
ter generates a START condition, writes the slave
address byte (R/W = 0), writes the memory address
where it desires to read, generates a repeated START
condition, writes the slave address byte (R/W = 1),
reads data with ACK or NACK as applicable, and
generates a STOP condition. See Figure 6 for a read
example using the repeated START condition to
specify the starting memory location.
pullup resistors should not be added.
SDA and SCL Pullup Resistors
SDA is an open-drain output and requires an external
pullup resistor to realize a logic-high level.
Because the device does not use clock cycle stretching,
a master using either an open-drain output with a pullup
resistor or CMOS output driver (push-pull) could be used
for SCL.
Battery Charge Protection
The device contains Maxim’s redundant battery-charge
protection circuit to prevent any charging of the external
battery.
Reaoing Multiple Bytes frꢂm a 2lave: The read
operation can be used to read multiple bytes with a
single transfer. When reading bytes from the slave,
the master simply ACKs the data byte if it desires to
read another byte before terminating the transaction.
After the master reads the last byte it must NACK to
indicate the end of the transfer and then it generates
a STOP condition.
Ordering Information
PART
DS3232MZ+
DS3232MZ/V+
TEMP RANGE
-40NC to +85NC
-40NC to +85NC
PIN-PACKAGE
8 SO
8 SO
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS3232M,
Package Information
decouple the V
and/or V
power supplies with
CC
BAT
For the latest package outline information and land patterns
(footprints), go to wwwꢁmaxim-icꢁcꢂmꢃpackages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
0.1FF and/or 1.0FF capacitors. Use a high-quality,
ceramic, surface-mount capacitor if possible. Surface-
mount components minimize lead inductance, which
improves performance, and ceramic capacitors tend to
have adequate high-frequency response for decoupling
applications.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NOꢁ
LAND
PATTERN NOꢁ
If communications during battery operation are not
8 SO
S8MK+1
41-((01
9(-((96
required, the V
decoupling capacitor can be omitted.
BAT
44
DS3232M
2
±±55pm, C,Real-Tipe,Clock,with,SRAM,
Revision History
REVI2ION REVI2ION
PAGE2
DE2CRIPTION
CHANGED
NUMBER
DATE
0
1
3/12
Initial release
—
8/12
Added an automotive qualified part option to the Ordering Information table
22
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
4.
©
2012 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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