DS3231S-C15/T&R [MAXIM]
Real Time Clock, 1 Timer(s), CMOS, PDSO16, 0.300 INCH, SOIC-16;
| 型号： | DS3231S-C15/T&R |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Real Time Clock, 1 Timer(s), CMOS, PDSO16, 0.300 INCH, SOIC-16 时钟 光电二极管 外围集成电路 |
| 文件： | 总20页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 6; 10/08
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
DS231
General Description
Features
2
♦ Accuracy 2ppm from 0°C to +40°C
The DS3231 is a low-cost, extremely accurate I C real-
time clock (RTC) with an integrated temperature-
compensated crystal oscillator (TCXO) and crystal. The
device incorporates a battery input, and maintains accu-
rate timekeeping when main power to the device is inter-
rupted. The integration of the crystal resonator enhances
the long-term accuracy of the device as well as reduces
the piece-part count in a manufacturing line. The DS3231
is available in commercial and industrial temperature
ranges, and is offered in a 16-pin, 300-mil SO package.
♦ Accuracy 3.5ppm from -40°C to +85°C
♦ Battery Backup Input for Continuous
Timekeeping
♦ Operating Temperature Ranges
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
♦ Low-Power Consumption
♦ Real-Time Clock Counts Seconds, Minutes,
Hours, Day, Date, Month, and Year with Leap Year
Compensation Valid Up to 2100
The RTC maintains seconds, minutes, hours, day, date,
month, and year information. The date at the end of the
month is automatically adjusted for months with fewer
than 31 days, including corrections for leap year. The
clock operates in either the 24-hour or 12-hour format
with an AM/PM indicator. Two programmable time-of-
day alarms and a programmable square-wave output
are provided. Address and data are transferred serially
♦ Two Time-of-Day Alarms
♦ Programmable Square-Wave Output
2
♦ Fast (400kHz) I C Interface
♦ 3.3V Operation
♦ Digital Temp Sensor Output: 3°C Accuracy
♦ Register for Aging Trim
♦ RST Output/Pushbutton Reset Debounce Input
2
through an I C bidirectional bus.
®
♦ Underwriters Laboratories (UL ) Recognized
A precision temperature-compensated voltage refer-
ence and comparator circuit monitors the status of V
CC
to detect power failures, to provide a reset output, and
to automatically switch to the backup supply when nec-
essary. Additionally, the RST pin is monitored as a
pushbutton input for generating a µP reset.
Ordering Information
TOP
PART
TEMP RANGE PIN-PACKAGE
MARK
DS3231S
DS3231SN
DS3231S#
0°C to +70°C 16 SO
DS3231SN# -40°C to +85°C 16 SO
Applications
Utility Power Meters
# Denotes a RoHS-compliant device that may include lead that
is exempt under RoHS requirements. The lead finish is JESD97
category e3, and is compatible with both lead-based and lead-
free soldering processes. A "#" anywhere on the top mark
denotes a RoHS-compliant device.
Servers
Telematics
GPS
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
V
CC
V
CC
R
PU
= t /C
R B
V
CC
R
R
PU
PU
V
CC
SCL
SDA
INT/SQW
32kHz
SCL
SDA
μP
V
BAT
RST
RST
DS3231
PUSHBUTTON
RESET
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
GND
UL is a registered trademark of Underwriters Laboratories, Inc.
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Range...............................-40°C to +85°C
Lead Temperature
Voltage Range on V , V
, 32kHz, SCL, SDA, RST,
CC BAT
INT/SQW Relative to Ground.............................-0.3V to +6.0V
(Soldering, 10s).....................................................+260°C/10s
Soldering Temperature....................................See the Handling,
PC Board Layout, and Assembly section.
Operating Temperature Range
(noncondensing) .............................................-40°C to +85°C
Junction Temperature......................................................+125°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DS231
RECOMMENDED DC OPERATING CONDITIONS
(T = T
A
to T
, unless otherwise noted.) (Notes 1, 2)
MAX
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
2.3
2.3
TYP
3.3
MAX
5.5
UNITS
V
CC
V
V
Supply Voltage
V
BAT
3.0
5.5
0.7 x
V
+
0.3
CC
Logic 1 Input SDA, SCL
Logic 0 Input SDA, SCL
V
V
V
IH
V
CC
+0.3 x
V
V
-0.3
IL
CC
ELECTRICAL CHARACTERISTICS
(V
CC
= 2.3V to 5.5V, V
= Active Supply (see Table 1), T = T
to T
, unless otherwise noted.) (Typical values are at V
=
CC
MIN
MAX
CC
A
3.3V, V
= 3.0V, and T = +25°C, unless otherwise noted.) (Notes 1, 2)
A
BAT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
200
UNITS
V
= 3.63V
= 5.5V
CC
Active Supply Current
I
(Notes 3, 4)
μA
CCA
V
300
CC
2
I C bus inactive, 32kHz
V
= 3.63V
= 5.5V
110
170
CC
CC
Standby Supply Current
I
output on, SQW output off
(Note 4)
μA
CCS
V
2
V
V
= 3.63V
= 5.5V
575
650
2.70
I C bus inactive, 32kHz
CC
Temperature Conversion Current
Power-Fail Voltage
I
μA
V
CCSCONV
output on, SQW output off
CC
V
2.45
-1
2.575
PF
OL
OL
LO
Logic 0 Output, 32kHz,
INT/SQW, SDA
V
V
I
I
= 3mA
= 1mA
0.4
0.4
+1
V
OL
OL
Logic 0 Output, RST
V
Output Leakage Current 32kHz,
INT/SQW, SDA
I
Output high impedance
0
μA
Input Leakage SCL
I
-1
+1
μA
μA
LI
RST Pin I/O Leakage
I
RST high impedance (Note 5)
-200
+10
OL
V
Leakage Current
BAT
I
25
100
nA
BATLKG
(V Active)
CC
2
_____________________________________________________________________
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
DS231
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.3V to 5.5V, V
= Active Supply (see Table 1), T = T
to T
, unless otherwise noted.) (Typical values are at V
MAX
=
MIN
CC
A
CC
3.3V, V
= 3.0V, and T = +25°C, unless otherwise noted.) (Notes 1, 2)
A
BAT
PARAMETER
SYMBOL
CONDITIONS
= 3.3V
MIN
TYP
MAX
UNITS
Output Frequency
f
V
CC
= 3.3V or V
BAT
32.768
kHz
OUT
V
V
= 3.3V or
= 3.3V,
0°C to +40°C
2
CC
Frequency Stability vs.
Temperature (Commercial)
ꢀf/f
ꢀf/f
ppm
BAT
OUT
OUT
>40°C to +70°C
3.5
aging offset = 00h
-40°C to <0°C
0°C to +40°C
>40°C to +85°C
3.5
2
V
V
= 3.3V or
= 3.3V,
CC
Frequency Stability vs.
Temperature (Industrial)
ppm
BAT
aging offset = 00h
3.5
Frequency Stability vs. Voltage
ꢀf/V
1
ppm/V
-40°C
0.7
0.1
0.4
0.8
+25°C
+70°C
+85°C
Trim Register Frequency
Sensitivity per LSB
ꢀf/LSB
Specified at:
ppm
Temperature Accuracy
Crystal Aging
Temp
V
= 3.3V or V
= 3.3V
BAT
-3
+3
°C
CC
First year
1.0
5.0
After reflow,
not production tested
ꢀf/f
ppm
O
0–10 years
ELECTRICAL CHARACTERISTICS
(V
CC
= 0V, V
= 2.3V to 5.5V, T = T
to T
, unless otherwise noted.) (Note 1)
MAX
MIN
BAT
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
70
UNITS
V
V
= 3.63V
= 5.5V
EOSC = 0, BBSQW = 0,
SCL = 400kHz (Note 4)
BAT
Active Battery Current
I
μA
BATA
150
BAT
EOSC = 0, BBSQW = 0,
EN32kHz = 1,
SCL = SDA = 0V or
V
V
= 3.63V
= 5.5V
0.84
1.0
3.0
BAT
Timekeeping Battery Current
I
μA
BATT
3.5
BAT
SCL = SDA = V
(Note 4)
BAT
EOSC = 0, BBSQW = 0,
SCL = SDA = 0V or
V
V
= 3.63V
= 5.5V
575
BAT
Temperature Conversion Current
Data-Retention Current
I
μA
nA
BATTC
SCL = SDA = V
650
100
BAT
BAT
I
EOSC = 1, SCL = SDA = 0V, +25°C
BATTDR
_____________________________________________________________________
3
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
AC ELECTRICAL CHARACTERISTICS
(V
CC
= V
to V
or V
= V
to V
, V
> V , T = T
to T
, unless otherwise noted.) (Note 1)
MAX
MIN
CC(MIN)
CC(MAX)
BAT
BAT(MIN)
BAT(MAX) BAT
CC
A
PARAMETER
SCL Clock Frequency
SYMBOL
CONDITIONS
MIN
100
0
TYP
MAX
400
UNITS
Fast mode
f
kHz
SCL
BUF
Standard mode
Fast mode
100
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0
DS231
Bus Free Time Between STOP
and START Conditions
t
μs
μs
μs
μs
μs
ns
μs
ns
ns
μs
Standard mode
Fast mode
Hold Time (Repeated) START
Condition (Note 6)
t
HD:STA
Standard mode
Fast mode
Low Period of SCL Clock
High Period of SCL Clock
Data Hold Time (Notes 7, 8)
Data Setup Time (Note 9)
START Setup Time
t
LOW
Standard mode
Fast mode
t
HIGH
Standard mode
Fast mode
0.9
0.9
t
t
t
HD:DAT
SU:DAT
SU:STA
Standard mode
Fast mode
0
100
250
0.6
4.7
20 +
Standard mode
Fast mode
Standard mode
Fast mode
300
1000
300
Rise Time of Both SDA and SCL
Signals (Note 10)
t
R
0.1C
B
Standard mode
Fast mode
Fall Time of Both SDA and SCL
Signals (Note 10)
20 +
t
F
0.1C
B
Standard mode
Fast mode
300
0.6
4.7
Setup Time for STOP Condition
t
SU:STO
Standard mode
Capacitive Load for Each Bus
Line (Note 10)
C
400
pF
pF
ns
B
Capacitance for SDA, SCL
C
10
30
I/O
SP
Pulse Width of Spikes That Must
Be Suppressed by the Input Filter
t
Pushbutton Debounce
PB
250
250
100
125
ms
ms
ms
ms
DB
RST
OSF
Reset Active Time
t
Oscillator Stop Flag (OSF) Delay
Temperature Conversion Time
t
(Note 11)
t
200
CONV
POWER-SWITCH CHARACTERISTICS
(T = T
A
to T
)
MAX
MIN
PARAMETER
Fall Time; V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
to
to
CC
PF(MAX)
t
300
μs
VCCF
PF(MIN)
V
CC
V
Rise Time; V
PF(MIN)
PF(MAX)
t
0
μs
VCCR
Recovery at Power-Up
t
(Note 12)
250
300
ms
REC
4
_____________________________________________________________________
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
DS231
Pushbutton Reset Timing
RST
PB
DB
t
RST
Power-Switch Timing
V
CC
V
PF(MAX)
V
PF
V
PF
V
PF(MIN)
t
VCCF
t
VCCR
t
REC
RST
_____________________________________________________________________
5
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
2
Data Transfer on I C Serial Bus
SDA
SCL
DS231
t
BUF
t
t
F
SP
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
t
R
t
HD:STA
SU:STO
t
t
SU:DAT
HD:DAT
STOP
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO V
AND V
.
IH(MIN)
IL(MAX)
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.
Note 1: Limits at -40°C are guaranteed by design and not production tested.
Note 2: All voltages are referenced to ground.
Note 3:
I
—SCL clocking at max frequency = 400kHz.
CCA
Note 4: Current is the averaged input current, which includes the temperature conversion current.
Note 5: The RST pin has an internal 50kΩ (nominal) pullup resistor to V
Note 6: After this period, the first clock pulse is generated.
.
CC
Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
of the SCL signal)
IH(MIN)
to bridge the undefined region of the falling edge of SCL.
Note 8: The maximum t
needs only to be met if the device does not stretch the low period (t
) of the SCL signal.
HD:DAT
LOW
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement t
≥ 250ns must then be met. This
SU:DAT
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line t
before the SCL line is released.
t
= 1000 + 250 = 1250ns
R(MAX)
SU:DAT
+
Note 10: C —total capacitance of one bus line in pF.
B
Note 11: The parameter t
is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
OSF
0.0V ≤ V
≤ V
and 2.3V ≤ V
≤ 3.4V.
CC
CC(MAX)
BAT
Note 12: This delay applies only if the oscillator is enabled and running. If the EOSC bit is a 1, t
is bypassed and RST immediate-
REC
2
ly goes high. The state of RST does not affect the I C interface, RTC, or TCXO.
6
_____________________________________________________________________
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
DS231
Typical Operating Characteristics
(V
CC
= +3.3V, T = +25°C, unless otherwise noted.)
A
STANDBY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
150
125
100
75
1.2
1.1
1.0
0.9
0.8
0.7
0.6
BSY = 0, SCL = SDA = V
V
CC
= 0V, BSY = 0,
CC
SDA = SCL = V OR V
BAT
CC
RST ACTIVE
EN32kHz = 1
EN32kHz = 0
50
25
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
2.3
3.3
4.3
5.3
V
(V)
V
BAT
(V)
CC
SUPPLY CURRENT
vs. TEMPERATURE
FREQUENCY DEVIATION
vs. TEMPERATURE vs. AGING VALUE
1.0
0.9
0.8
0.7
0.6
60
50
V
CC
= 0, EN32kHz = 1, BSY = 0,
SDA = SCL = V OR GND
BAT
8
40
-33
30
20
0
10
0
-10
-20
-30
-40
32
127
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
DELTA TIME AND FREQUENCY
vs. TEMPERATURE
DS3231 toc05
20
0
0
CRYSTAL
+20ppm
-20
-40
-20
-40
-60
-80
-100
TYPICAL CRYSTAL,
UNCOMPENSATED
-60
-80
-100
-120
-140
-160
-180
-200
DS3231
ACCURACY
BAND
CRYSTAL
-20ppm
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
_____________________________________________________________________
7
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
Block Diagram
32kHz
OSCILLATOR AND
X1
DS231
CAPACITOR ARRAY
N
CONTROL LOGIC/
DIVIDER
SQUARE-WAVE BUFFER;
INT/SQW CONTROL
INT/SQW
X2
1Hz
N
V
CC
TEMPERATURE
SENSOR
ALARM, STATUS, AND
CONTROL REGISTERS
V
BAT
POWER CONTROL
GND
1Hz
CLOCK AND CALENDAR
REGISTERS
SCL
SDA
2
I C INTERFACE AND
ADDRESS REGISTER
DECODE
USER BUFFER
(7 BYTES)
V
CC
VOLTAGE REFERENCE;
DEBOUNCE CIRCUIT;
PUSHBUTTON RESET
RST
N
DS3231
8
_____________________________________________________________________
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
DS231
Pin Description
PIN
NAME
FUNCTION
32kHz Output. This open-drain pin requires an external pullup resistor. When enabled, the output operates
on either power supply. It may be left open if not used.
1
32kHz
DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1μF to 1.0μF capacitor.
If not used, connect to ground.
2
3
V
CC
Active-Low Interrupt or Square-Wave Output. This open-drain pin requires an external pullup resistor
connected to a supply at 5.5V or less. This multifunction pin is determined by the state of the INTCN bit in
the Control Register (0Eh). When INTCN is set to logic 0, this pin outputs a square wave and its frequency is
determined by RS2 and RS1 bits. When INTCN is set to logic 1, then a match between the timekeeping
registers and either of the alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the
INTCN bit is set to logic 1 when power is first applied, the pin defaults to an interrupt output with alarms
INT/SQW
disabled. The pullup voltage can be up to 5.5V, regardless of the voltage on V . If not used, this pin can be
CC
left floating.
Active-Low Reset. This pin is an open-drain input/output. It indicates the status of V relative to the
CC
V
specification. As V falls below V , the RST pin is driven low. When V exceeds V , for t
, the RST
PF
CC
PF
CC
PF
RST
pin is pulled high by the internal pullup resistor. The active-low, open-drain output is combined with a
debounced pushbutton input function. This pin can be activated by a pushbutton reset request. It has an
4
RST
internal 50kꢀ nominal value pullup resistor to V . No external pullup resistors should be connected. If the
CC
oscillator is disabled, t
is bypassed and RST immediately goes high.
REC
5–12
13
N.C.
GND
No Connection. Must be connected to ground.
Ground
Backup Power-Supply Input. This pin should be decoupled using a 0.1μF to 1.0μF low-leakage capacitor.
2
If the I C interface is inactive whenever the device is powered by the V
input, the decoupling capacitor
BAT
14
V
BAT
is not required. If V
is not used, connect to ground. UL recognized to ensure against reverse charging
BAT
when used with a lithium battery. Go to www.maxim-ic.com/qa/info/ul.
2
Serial Data Input/Output. This pin is the data input/output for the I C serial interface. This open-drain pin
15
16
SDA
SCL
requires an external pullup resistor. The pullup voltage can be up to 5.5V, regardless of the voltage on V
.
CC
2
Serial Clock Input. This pin is the clock input for the I C serial interface and is used to synchronize data
movement on the serial interface. Up to 5.5V can be used for this pin, regardless of the voltage on V
.
CC
clock operates in either the 24-hour or 12-hour format
Detailed Description
with an AM/PM indicator. The internal registers are
The DS3231 is a serial RTC driven by a temperature-
compensated 32kHz crystal oscillator. The TCXO pro-
vides a stable and accurate reference clock, and
maintains the RTC to within 2 minutes per year accu-
racy from -40°C to +85°C. The TCXO frequency output
is available at the 32kHz pin. The RTC is a low-power
clock/calendar with two programmable time-of-day
alarms and a programmable square-wave output. The
INT/SQW provides either an interrupt signal due to
alarm conditions or a square-wave output. The clock/cal-
endar provides seconds, minutes, hours, day, date,
month, and year information. The date at the end of the
month is automatically adjusted for months with fewer
than 31 days, including corrections for leap year. The
2
accessible though an I C bus interface.
A temperature-compensated voltage reference and
comparator circuit monitors the level of V
to detect
CC
power failures and to automatically switch to the back-
up supply when necessary. The RST pin provides an
external pushbutton function and acts as an indicator
of a power-fail event.
Operation
The block diagram shows the main elements of the
DS3231. The eight blocks can be grouped into four
functional groups: TCXO, power control, pushbutton
function, and RTC. Their operations are described sep-
arately in the following sections.
_____________________________________________________________________
9
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
active battery current, I
, is drawn. When the serial
32kHz TCXO
The temperature sensor, oscillator, and control logic
form the TCXO. The controller reads the output of the
on-chip temperature sensor and uses a lookup table to
determine the capacitance required, adds the aging
correction in AGE register, and then sets the capaci-
tance selection registers. New values, including
changes to the AGE register, are loaded only when a
change in the temperature value occurs, or when a
user-initiated temperature conversion is completed.
Temperature conversion occurs on initial application of
BATA
interface is inactive, timekeeping current (I
), which
BATT
includes the averaged temperature conversion current,
, is used (refer to Application Note 3644: Power
I
BATTC
Considerations for Accurate Real-Time Clocks for
details). Temperature conversion current, I , is
BATTC
specified since the system must be able to support the
periodic higher current pulse and still maintain a valid
voltage level. Data retention current, I
current drawn by the part when the oscillator is
stopped (EOSC = 1). This mode can be used to mini-
mize battery requirements for times when maintaining
time and date information is not necessary, e.g., while
the end system is waiting to be shipped to a customer.
DS231
, is the
BATTDR
V
and once every 64 seconds afterwards.
CC
Power Control
This function is provided by a temperature-compensat-
ed voltage reference and a comparator circuit that
Pushbutton Reset Function
The DS3231 provides for a pushbutton switch to be
connected to the RST output pin. When the DS3231 is
not in a reset cycle, it continuously monitors the RST
signal for a low going edge. If an edge transition is
detected, the DS3231 debounces the switch by pulling
the RST low. After the internal timer has expired
monitors the V
level. When V
is greater than V
CC
,
PF
.
CC
CC
PF
the part is powered by V . When V
is less than V
CC
but greater than V
, the DS3231 is powered by V
BAT
CC
, the
BAT
If V
is less than V
and is less than V
CC
PF
device is powered by V
. See Table 1.
BAT
(PB ), the DS3231 continues to monitor the RST line.
DB
Table 1. Power Control
If the line is still low, the DS3231 continuously monitors
the line looking for a rising edge. Upon detecting
release, the DS3231 forces the RST pin low and holds it
SUPPLY CONDITION
ACTIVE SUPPLY
V
CC
V
CC
V
CC
V
CC
< V , V < V
V
BAT
PF CC
BAT
BAT
BAT
BAT
low for t
.
RST
< V , V > V
V
PF CC
CC
CC
CC
RST is also used to indicate a power-fail condition.
When V is lower than V , an internal power-fail sig-
> V , V < V
V
PF CC
CC
PF
> V , V > V
V
PF CC
nal is generated, which forces the RST pin low. When
returns to a level above V , the RST pin is held
V
CC
PF
REC
low for approximately 250ms (t
) to allow the power
To preserve the battery, the first time V
is applied to
BAT
supply to stabilize. If the oscillator is not running (see
the device, the oscillator will not start up until V
CC
2
the Power Control section) when V is applied, t is
exceeds V , or until a valid I C address is written to
CC
REC
PF
bypassed and RST immediately goes high. Assertion of
the RST output, whether by pushbutton or power-fail
detection, does not affect the internal operation of the
DS3231.
the part. Typical oscillator startup time is less than one
second. Approximately 2 seconds after V
or a valid I C address is written, the device makes a
temperature measurement and applies the calculated
correction to the oscillator. Once the oscillator is run-
ning, it continues to run as long as a valid power
is applied,
CC
2
Real-Time Clock
With the clock source from the TCXO, the RTC provides
seconds, minutes, hours, day, date, month, and year
information. The date at the end of the month is auto-
matically adjusted for months with fewer than 31 days,
including corrections for leap year. The clock operates
in either the 24-hour or 12-hour format with an AM/PM
indicator.
source is available (V
or V
), and the device con-
CC
BAT
tinues to measure the temperature and correct the
oscillator frequency every 64 seconds.
On the first application of power (V ) or when a valid
CC
2
I C address is written to the part (V
), the time and
BAT
date registers are reset to 01/01/00 01 00:00:00
(MM/DD/YY DOW HH:MM:SS).
The clock provides two programmable time-of-day
alarms and a programmable square-wave output. The
INT/SQW pin either generates an interrupt due to alarm
condition or outputs a square-wave signal and the
selection is controlled by the bit INTCN.
V
BAT
Operation
There are several modes of operation that affect the
amount of V current that is drawn. While the device
BAT
is powered by V
and the serial interface is active,
BAT
10
____________________________________________________________________
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
DS231
Figure 1. Timekeeping Registers
BIT 7
MSB
BIT 0
LSB
ADDRESS
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
FUNCTION
RANGE
00h
01h
0
0
10 Seconds
10 Minutes
AM/PM
10 Hour
0
Seconds
Seconds
Minutes
00–59
00–59
Minutes
Hour
1–12 + AM/PM
02h
0
12/24
10 Hour
0
Hours
00–23
03h
04h
0
0
0
0
0
Day
Day
1–7
10 Date
Date
Month
Year
Date
01–31
Month/
Century
01–12 +
Century
05h
Century
0
0
10 Month
10 Hour
10 Hour
06h
07h
08h
10 Year
Year
00–99
00–59
00–59
A1M1
A1M2
10 Seconds
10 Minutes
AM/PM
Seconds
Minutes
Alarm 1 Seconds
Alarm 1 Minutes
1–12 + AM/PM
09h
A1M3
12/24
Hour
Alarm 1 Hours
00–23
10 Hour
Day
Date
Alarm 1 Day
Alarm 1 Date
1–7
0Ah
0Bh
0Ch
A1M4
A2M2
A2M3
DY/DT
10 Date
1–31
00–59
10 Minutes
AM/PM
Minutes
Alarm 2 Minutes
1–12 + AM/PM
12/24
Hour
Alarm 2 Hours
00–23
10 Hour
Day
Alarm 2 Day
Alarm 2 Date
Control
1–7
1–31
—
0Dh
A2M4
DY/DT
10 Date
Date
0Eh
0Fh
10h
11h
12h
EOSC
OSF
BBSQW
0
CONV
0
RS2
0
RS1
EN32kHz
DATA
DATA
0
INTCN
BSY
A2IE
A2F
A1IE
A1F
Control/Status
Aging Offset
MSB of Temp
LSB of Temp
—
SIGN
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
0
DATA
DATA
0
DATA DATA
DATA DATA
DATA
DATA
0
—
—
0
0
—
Note: Unless otherwise specified, the registers’ state is not defined when power is first applied.
event, it is possible that the microcontroller and
Address Map
2
DS3231 I C communications could become unsyn-
Figure 1 shows the address map for the DS3231 time-
keeping registers. During a multibyte access, when the
address pointer reaches the end of the register space
chronized, e.g., the microcontroller resets while read-
ing data from the DS3231. When the microcontroller
2
resets, the DS3231 I C interface may be placed into a
2
(12h), it wraps around to location 00h. On an I C
known state by toggling SCL until SDA is observed to
be at a high level. At that point the microcontroller
should pull SDA low while SCL is high, generating a
START condition.
START or address pointer incrementing to location 00h,
the current time is transferred to a second set of regis-
ters. The time information is read from these secondary
registers, while the clock may continue to run. This
eliminates the need to reread the registers in case the
main registers update during a read.
Clock and Calendar
The time and calendar information is obtained by read-
ing the appropriate register bytes. Figure 1 illustrates
the RTC registers. The time and calendar data are set
or initialized by writing the appropriate register bytes.
The contents of the time and calendar registers are in
2
I C Interface
2
The I C interface is accessible whenever either V
or
CC
V
is at a valid level. If a microcontroller connected
BAT
to the DS3231 resets because of a loss of V
or other
CC
____________________________________________________________________ 11
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
the binary-coded decimal (BCD) format. The DS3231
can be run in either 12-hour or 24-hour mode. Bit 6 of
Alarms
The DS3231 contains two time-of-day/date alarms.
Alarm 1 can be set by writing to registers 07h to 0Ah.
Alarm 2 can be set by writing to registers 0Bh to 0Dh.
The alarms can be programmed (by the alarm enable
and INTCN bits of the control register) to activate the
INT/SQW output on an alarm match condition. Bit 7 of
each of the time-of-day/date alarm registers are mask
bits (Table 2). When all the mask bits for each alarm
are logic 0, an alarm only occurs when the values in the
timekeeping registers match the corresponding values
stored in the time-of-day/date alarm registers. The
alarms can also be programmed to repeat every sec-
ond, minute, hour, day, or date. Table 2 shows the pos-
sible settings. Configurations not listed in the table will
result in illogical operation.
the hours register is defined as the 12- or 24-hour
mode select bit. When high, the 12-hour mode is
selected. In the 12-hour mode, bit 5 is the AM/PM bit
with logic-high being PM. In the 24-hour mode, bit 5 is
the second 10-hour bit (20–23 hours). The century bit
(bit 7 of the month register) is toggled when the years
register overflows from 99 to 00.
DS231
The day-of-week register increments at midnight.
Values that correspond to the day of week are user-
defined but must be sequential (i.e., if 1 equals
Sunday, then 2 equals Monday, and so on). Illogical
time and date entries result in undefined operation.
When reading or writing the time and date registers, sec-
ondary (user) buffers are used to prevent errors when
the internal registers update. When reading the time and
date registers, the user buffers are synchronized to the
internal registers on any START and when the register
pointer rolls over to zero. The time information is read
from these secondary registers, while the clock contin-
ues to run. This eliminates the need to reread the regis-
ters in case the main registers update during a read.
The DY/DT bits (bit 6 of the alarm day/date registers)
control whether the alarm value stored in bits 0 to 5 of
that register reflects the day of the week or the date of
the month. If DY/DT is written to logic 0, the alarm will
be the result of a match with date of the month. If
DY/DT is written to logic 1, the alarm will be the result of
a match with day of the week.
The countdown chain is reset whenever the seconds regis-
ter is written. Write transfers occur on the acknowledge
from the DS3231. Once the countdown chain is reset, to
avoid rollover issues the remaining time and date registers
must be written within 1 second. The 1Hz square-wave out-
put, if enabled, transitions high 500ms after the seconds
data transfer, provided the oscillator is already running.
When the RTC register values match alarm register set-
tings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is
set to logic 1. If the corresponding Alarm Interrupt
Enable ‘A1IE’ or ‘A2IE’ is also set to logic 1 and the
INTCN bit is set to logic 1, the alarm condition will acti-
vate the INT/SQW signal. The match is tested on the
once-per-second update of the time and date registers.
Table 2. Alarm Mask Bits
ALARM 1 REGISTER MASK BITS (BIT 7)
DY/DT
ALARM RATE
A1M4
A1M3
A1M2
A1M1
X
X
X
X
0
1
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Alarm once per second
Alarm when seconds match
Alarm when minutes and seconds match
Alarm when hours, minutes, and seconds match
Alarm when date, hours, minutes, and seconds match
Alarm when day, hours, minutes, and seconds match
ALARM 2 REGISTER MASK BITS (BIT 7)
DY/DT
ALARM RATE
A2M4
A2M3
A2M2
X
X
X
0
1
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Alarm once per minute (00 seconds of every minute)
Alarm when minutes match
Alarm when hours and minutes match
Alarm when date, hours, and minutes match
Alarm when day, hours, and minutes match
12
____________________________________________________________________
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
DS231
Control Register (0Eh)
BIT 7
EOSC
0
BIT 6
BBSQW
0
BIT 5
CONV
0
BIT 4
RS2
1
BIT 3
RS1
1
BIT 2
INTCN
1
BIT 1
A2IE
0
BIT 0
A1IE
0
NAME:
POR:
Special-Purpose Registers
SQUARE-WAVE OUTPUT FREQUENCY
The DS3231 has two additional registers (control and
status) that control the real-time clock, alarms, and
square-wave output.
SQUARE-WAVE OUTPUT
FREQUENCY
RS2
RS1
0
0
1
1
0
1
0
1
1Hz
Control Register (0Eh)
Bit 7: Enable Oscillator (EOSC). When set to logic 0,
the oscillator is started. When set to logic 1, the oscilla-
1.024kHz
4.096kHz
8.192kHz
tor is stopped when the DS3231 switches to V
. This
BAT
bit is clear (logic 0) when power is first applied. When
the DS3231 is powered by V , the oscillator is always
CC
the square wave has been enabled. The following table
shows the square-wave frequencies that can be select-
ed with the RS bits. These bits are both set to logic 1
(8.192kHz) when power is first applied.
on regardless of the status of the EOSC bit. When
EOSC is disabled, all register data is static.
Bit 6: Battery-Backed Square-Wave Enable
(BBSQW). When set to logic 1 and the DS3231 is being
Bit 2: Interrupt Control (INTCN). This bit controls the
INT/SQW signal. When the INTCN bit is set to logic 0, a
square wave is output on the INT/SQW pin. When the
INTCN bit is set to logic 1, then a match between the
timekeeping registers and either of the alarm registers
activates the INT/SQW output (if the alarm is also
enabled). The corresponding alarm flag is always set
regardless of the state of the INTCN bit. The INTCN bit
is set to logic 1 when power is first applied.
powered by the V
pin, this bit enables the square-
BAT
wave or interrupt output when V
is absent. When
CC
BBSQW is logic 0, the INT/SQW pin goes high imped-
ance when V
falls below the power-fail trip point. This
CC
bit is disabled (logic 0) when power is first applied.
Bit 5: Convert Temperature (CONV). Setting this bit to
1 forces the temperature sensor to convert the temper-
ature into digital code and execute the TCXO algorithm
to update the capacitance array to the oscillator. This
can only happen when a conversion is not already in
progress. The user should check the status bit BSY
before forcing the controller to start a new TCXO exe-
cution. A user-initiated temperature conversion does
not affect the internal 64-second update cycle.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to
logic 1, this bit permits the alarm 2 flag (A2F) bit in the
status register to assert INT/SQW (when INTCN = 1).
When the A2IE bit is set to logic 0 or INTCN is set to
logic 0, the A2F bit does not initiate an interrupt signal.
The A2IE bit is disabled (logic 0) when power is first
applied.
A user-initiated temperature conversion does not affect
the BSY bit for approximately 2ms. The CONV bit
remains at a 1 from the time it is written until the conver-
sion is finished, at which time both CONV and BSY go
to 0. The CONV bit should be used when monitoring
the status of a user-initiated conversion.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to
logic 1, this bit permits the alarm 1 flag (A1F) bit in the
status register to assert INT/SQW (when INTCN = 1).
When the A1IE bit is set to logic 0 or INTCN is set to
logic 0, the A1F bit does not initiate the INT/SQW sig-
nal. The A1IE bit is disabled (logic 0) when power is
first applied.
Bits 4 and 3: Rate Select (RS2 and RS1). These bits
control the frequency of the square-wave output when
____________________________________________________________________ 13
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
Status Register (0Fh)
BIT 7
OSF
1
BIT 6
BIT 5
BIT 4
BIT 3
EN32kHz
1
BIT 2
BSY
X
BIT 1
A2F
X
BIT 0
A1F
X
NAME:
POR:
0
0
0
0
0
0
DS231
ters. If the A1IE bit is logic 1 and the INTCN bit is set to
logic 1, the INT/SQW pin is also asserted. A1F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Status Register (0Fh)
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator either is stopped or was
stopped for some period and may be used to judge the
validity of the timekeeping data. This bit is set to logic 1
any time that the oscillator stops. The following are exam-
ples of conditions that can cause the OSF bit to be set:
Aging Offset
The aging offset register takes a user-provided value to
add to or subtract from the codes in the capacitance
array registers. The code is encoded in two’s comple-
ment, with bit 7 representing the sign bit. One LSB rep-
resents one small capacitor to be switched in or out of
the capacitance array at the crystal pins. The aging off-
set register capacitance value is added or subtracted
from the capacitance value that the device calculates
for each temperature compensation. The offset register
is added to the capacitance array during a normal tem-
perature conversion, if the temperature changes from
the previous conversion, or during a manual user con-
version (setting the CONV bit). To see the effects of the
aging register on the 32kHz output frequency immedi-
ately, a manual conversion should be started after each
aging register change.
1) The first time power is applied.
2) The voltages present on both V
insufficient to support oscillation.
and V
are
BAT
CC
3) The EOSC bit is turned off in battery-backed mode.
4) External influences on the crystal (i.e., noise, leak-
age, etc.).
This bit remains at logic 1 until written to logic 0.
Bit 3: Enable 32kHz Output (EN32kHz). This bit con-
trols the status of the 32kHz pin. When set to logic 1, the
32kHz pin is enabled and outputs a 32.768kHz square-
wave signal. When set to logic 0, the 32kHz pin goes to
a high-impedance state. The initial power-up state of
this bit is logic 1, and a 32.768kHz square-wave signal
appears at the 32kHz pin after a power source is
applied to the DS3231 (if the oscillator is running).
Positive aging values add capacitance to the array,
slowing the oscillator frequency. Negative values
remove capacitance from the array, increasing the
oscillator frequency.
Bit 2: Busy (BSY). This bit indicates the device is busy
executing TCXO functions. It goes to logic 1 when the
conversion signal to the temperature sensor is asserted
and then is cleared when the device is in the 1-minute
idle state.
The change in ppm per LSB is different at different
temperatures. The frequency vs. temperature curve is
shifted by the values used in this register. At +25°C,
one LSB typically provides about 0.1ppm change in
frequency.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag
bit indicates that the time matched the alarm 2 regis-
ters. If the A2IE bit is logic 1 and the INTCN bit is set to
logic 1, the INT/SQW pin is also asserted. A2F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Use of the aging register is not needed to achieve the
accuracy as defined in the EC tables, but could be
used to help compensate for aging at a given tempera-
ture. See the Typical Operating Characteristics section
for a graph showing the effect of the register on accu-
racy over temperature.
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag
bit indicates that the time matched the alarm 1 regis-
Aging Offset (10h)
BIT 7
Sign
0
BIT 6
Data
0
BIT 5
Data
0
BIT 4
Data
0
BIT 3
Data
0
BIT 2
Data
0
BIT 1
Data
0
BIT 0
Data
0
NAME:
POR:
14
____________________________________________________________________
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
DS231
Temperature Register (Upper Byte) (11h)
BIT 7
Sign
0
BIT 6
Data
0
BIT 5
Data
0
BIT 4
Data
0
BIT 3
Data
0
BIT 2
Data
0
BIT 1
Data
0
BIT 0
Data
0
NAME:
POR:
Temperature Register (Lower Byte) (12h)
BIT 7
Data
0
BIT 6
Data
0
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
POR:
0
0
0
0
0
0
0
0
0
0
0
0
line while the clock line is high are interpreted as
control signals.
Temperature Registers (11h–12h)
Temperature is represented as a 10-bit code with a res-
olution of 0.25°C and is accessible at location 11h and
12h. The temperature is encoded in two’s complement
format. The upper 8 bits, the integer portion, are at
location 11h and the lower 2 bits, the fractional portion,
are in the upper nibble at location 12h. For example,
00011001 01b = +25.25°C. Upon power reset, the reg-
isters are set to a default temperature of 0°C and the
controller starts a temperature conversion. The temper-
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain
high.
START data transfer: A change in the state of the
data line from high to low, while the clock line is high,
defines a START condition.
ature is read on initial application of V
or I2C access
STOP data transfer: A change in the state of the
data line from low to high, while the clock line is high,
defines a STOP condition.
CC
on V
and once every 64 seconds afterwards. The
BAT
temperature registers are updated after each user-initi-
ated conversion and on every 64-second conversion.
The temperature registers are read-only.
Data valid: The state of the data line represents
valid data when, after a START condition, the data
line is stable for the duration of the high period of the
clock signal. The data on the line must be changed
during the low period of the clock signal. There is
one clock pulse per bit of data.
2
I C Serial Data Bus
2
The DS3231 supports a bidirectional I C bus and data
transmission protocol. A device that sends data onto
the bus is defined as a transmitter and a device receiv-
ing data is defined as a receiver. The device that con-
trols the message is called a master. The devices that
are controlled by the master are slaves. The bus must
be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions. The DS3231
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number
of data bytes transferred between the START and
the STOP conditions is not limited, and is determined
by the master device. The information is transferred
byte-wise and each receiver acknowledges with a
ninth bit.
2
operates as a slave on the I C bus. Connections to the
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device
must generate an extra clock pulse, which is associ-
ated with this acknowledge bit.
bus are made through the SCL input and open-drain
SDA I/O lines. Within the bus specifications, a standard
mode (100kHz maximum clock rate) and a fast mode
(400kHz maximum clock rate) are defined. The DS3231
works in both modes.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
The following bus protocol has been defined (Figure 2):
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain stable
whenever the clock line is high. Changes in the data
____________________________________________________________________ 15
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
MSB FIRST
MSB
LSB
MSB
LSB
SDA
SLAVE
ADDRESS
R/W
8
ACK
9
DATA
ACK
9
DATA
ACK/
NACK
DS231
SCL
1–7
1–7
8
1–7
8
9
IDLE
START
CONDITION
REPEATED IF MORE BYTES
ARE TRANSFERRED
STOP CONDITION
REPEATED START
2
Figure 2. I C Data Transfer Overview
slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte. Data is transferred with the most
significant bit (MSB) first.
Figures 3 and 4 detail how data transfer is accom-
Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
2
plished on the I C bus. Depending upon the state of
the R/W bit, two types of data transfer are possible:
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
<SLAVE
ADDRESS> <R/W> <WORD ADDRESS (n)>
<DATA (n)>
XXXXXXXX
<DATA (n + 1)>
XXXXXXXX
<DATA (n + X)
XXXXXXXX
S
1101000 XXXXXXXX
0
A
A
A
A
A
P
...
S - START
A - ACKNOWLEDGE (ACK)
P - STOP
SLAVE TO MASTER
MASTER TO SLAVE
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
Figure 3. Data Write—Slave Receiver Mode
<SLAVE
ADDRESS> <R/W>
<DATA (n)>
XXXXXXXX
<DATA (n + 1)>
<DATA (n + 2)>
XXXXXXXX
<DATA (n + X)>
XXXXXXXX
S
1101000
1
A
A
XXXXXXXX
A
A
A
P
...
S - START
MASTER TO SLAVE
SLAVE TO MASTER
A - ACKNOWLEDGE (ACK)
P - STOP
A - NOT ACKNOWLEDGE (NACK)
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
Figure 4. Data Read—Slave Transmitter Mode
16
____________________________________________________________________
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
DS231
<SLAVE
ADDRESS> <R/W>
<WORD ADDRESS (n)> <SLAVE ADDRESS (n)> <R/W>
XXXXXXXX Sr 1101000 A
S
1101000
0
A
A
1
<DATA (n)>
XXXXXXXX
<DATA (n + 1)>
XXXXXXXX
<DATA (n + 2)>
XXXXXXXX
<DATA (n + X)>
XXXXXXXX
A
A
A
A
P
...
S - START
Sr - REPEATED START
A - ACKNOWLEDGE (ACK)
P - STOP
MASTER TO SLAVE
SLAVE TO MASTER
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
A - NOT ACKNOWLEDGE (NACK)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
Figure 5. Data Write/Read (Write Pointer, Then Read)—Slave Receive and Transmit
master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last
received byte, a not acknowledge is returned.
acknowledging the transfer. The master may then
transmit zero or more bytes of data, with the DS3231
acknowledging each byte received. The register
pointer increments after each data byte is trans-
ferred. The master generates a STOP condition to
terminate the data write.
The master device generates all the serial clock puls-
es and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated
START condition. Since a repeated START condition
is also the beginning of the next serial transfer, the
bus will not be released. Data is transferred with the
most significant bit (MSB) first.
Slave transmitter mode (DS3231 read mode): The
first byte is received and handled as in the slave
receiver mode. However, in this mode, the direction
bit indicates that the transfer direction is reversed.
Serial data is transmitted on SDA by the DS3231
while the serial clock is input on SCL. START and
STOP conditions are recognized as the beginning
and end of a serial transfer. Address recognition is
performed by hardware after reception of the slave
address and direction bit. The slave address byte is
the first byte received after the master generates a
START condition. The slave address byte contains
the 7-bit DS3231 address, which is 1101000, fol-
lowed by the direction bit (R/W), which is 1 for a
read. After receiving and decoding the slave
address byte, the DS3231 outputs an acknowledge
on SDA. The DS3231 then begins to transmit data
starting with the register address pointed to by the
register pointer. If the register pointer is not written to
before the initiation of a read mode, the first address
that is read is the last one stored in the register point-
er. The DS3231 must receive a not acknowledge to
end a read.
The DS3231 can operate in the following two modes:
Slave receiver mode (DS3231 write mode): Serial
data and clock are received through SDA and SCL.
After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recog-
nized as the beginning and end of a serial transfer.
Address recognition is performed by hardware after
reception of the slave address and direction bit. The
slave address byte is the first byte received after the
master generates the START condition. The slave
address byte contains the 7-bit DS3231 address,
which is 1101000, followed by the direction bit (R/W),
which is 0 for a write. After receiving and decoding
the slave address byte, the DS3231 outputs an
acknowledge on SDA. After the DS3231 acknowl-
edges the slave address + write bit, the master
transmits a word address to the DS3231. This sets
the register pointer on the DS3231, with the DS3231
____________________________________________________________________ 17
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
signal line. All N.C. (no connect) pins must be connect-
Handling, PC Board Layout,
and Assembly
The DS3231 package contains a quartz tuning-fork
crystal. Pick-and-place equipment can be used, but
precautions should be taken to ensure that excessive
shocks are avoided. Ultrasonic cleaning should be
avoided to prevent damage to the crystal.
ed to ground.
Moisture-sensitive packages are shipped from the fac-
tory dry packed. Handling instructions listed on the
package label must be followed to prevent damage
during reflow. Refer to the IPC/JEDEC J-STD-020 stan-
dard for moisture-sensitive device (MSD) classifications
and reflow profiles. Exposure to reflow is limited to 2
times maximum.
DS231
Avoid running signal traces under the package, unless
a ground plane is placed between the package and the
Pin Configuration
Chip Information
TRANSISTOR COUNT: 33,000
TOP VIEW
SUBSTRATE CONNECTED TO GROUND
PROCESS: CMOS
32kHz
1
2
3
4
5
6
7
8
16 SCL
15 SDA
V
CC
Thermal Information
Theta-JA: +73°C/W
INT/SQW
RST
14 V
BAT
13 GND
12 N.C.
11 N.C.
10 N.C.
Theta-JC: +23°C/W
DS3231S
N.C.
N.C.
Package Information
For the latest package outline information and land patterns, go
N.C.
to www.maxim-ic.com/packages.
N.C.
9
N.C.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
SO
16 SO
—
21-0042
18
____________________________________________________________________
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
DS231
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
1/05
Initial release.
—
1, 3
1
Changed Digital Temp Sensor Output from ±2°C to ±3°C.
Updated Typical Operating Circuit.
1
2/05
Changed T = -40°C to +85°C to T = T
to T .
MAX
2, 3, 4
8
A
A
MIN
Updated Block Diagram.
Added “UL Recognized” to Features; added lead-free packages and removed S
from top mark info in Ordering Information table; added ground connections to
the N.C. pin in the Typical Operating Circuit.
1
Added “noncondensing” to operating temperature range; changed V MIN from
PF
2.35V to 2.45V.
2
Added aging offset specification.
Relabeled TOC4.
3
7
Added arrow showing input on X1 in the Block Diagram.
8
Updated pin descriptions for V and V
CC
.
9
BAT
2
6/05
2
Added the I C Interface section.
10
11
13
Figure 1: Added sign bit to aging and temperature registers; added MSB and LSB.
Corrected title for rate select bits frequency table.
Added note that frequency stability over temperature spec is with aging offset
register = 00h; changed bit 7 from Data to Sign (Crystal Aging Offset Register).
14
15
17
Changed bit 7 from Data to Sign (Temperature Register); correct pin definitions
2
in I C Serial Data Bus section.
Modified the Handing, PC Board Layout, and Assembly section to refer to
J-STD-020 for reflow profiles for lead-free and leaded packages.
3
4
11/05
10/06
Changed lead-free packages to RoHS-compliant packages.
1
1
Changed RST and UL bullets in Features.
Changed EC condition “V > V
” to “V = Active Supply (see Table 1).”
2, 3
6
CC
BAT
CC
Modified Note 12 to correct t
operation.
REC
Added various conditions text to TOCs 1, 2, and 3.
7
Added text to pin descriptions for 32kHz, V , and RST.
CC
9
Table 1: Changed column heading “Powered By” to “Active Supply”; changed
10
13
14
“applied” to “exceeds V ” in the Power Control section.
PF
Indicated BBSQW applies to both SQW and interrupts; simplified temp convert
description (bit 5); added “output” to INT\SQW (bit 2).
Changed the Crystal Aging section to the Aging Offset section; changed “this
bit indicates” to “this bit controls” for the enable 32kHz output bit.
Added Warning note to EC table notes; updated Note 12.
6
7
Updated the Typical Operating Characteristics graphs.
In the Power Control section, added information about the POR state of the time
and date registers; in the Real-Time Clock section, added to the description of
the RST function.
5
4/08
10
11
In Figure 1, corrected the months date range for 04h from 00–31 to 01–31.
____________________________________________________________________ 19
2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
Revision History (continued)
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
Updated the Typical Operating Circuit.
NUMBER
DATE
1
Removed the V parameter from the Recommended DC Operating Conditions
PU
table and added verbiage about the pullup to the Pin Description table for
INT/SQW, SDA, and SCL.
2, 9
DS231
Added the Delta Time and Frequency vs. Temperature graph in the Typical
Operating Characteristics section.
7
8
6
10/08
Updated the Block Diagram.
Added the V
Operation section, improved some sections of text for the
BAT
10
32kHz TCXO and Pushbutton Reset Function sections.
Added the register bit POR values to the register tables.
13, 14, 15
14, 15
Updated the Aging Offset and Temperature Registers (11h–12h) sections.
2
Updated the I C timing diagrams (Figures 3, 4, and 5).
16, 17
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
is a registered trademark of Dallas Semiconductor Corporation.
is a registered trademark of Maxim Integrated Products, Inc.
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