DS28E22P+T [MAXIM]
DeepCover Secure Authenticator with 1-Wire SHA-256 and 2Kb User EEPROM;
| 型号： | DS28E22P+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | DeepCover Secure Authenticator with 1-Wire SHA-256 and 2Kb User EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总6页 (文件大小：875K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ABRIDGED DATA SHEET
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DeepCover Secure Authenticator with
1-Wire SHA-256 and 2Kb User EEPROM
DS28E22
General Description
DeepCover embedded security solutions cloak sensitive
Features
● Symmetric Key-Based Bidirectional Secure
M
data under multiple layers of advanced physical security to
provide the most secure key storage possible.
Authentication Model Based on SHA-256
● Dedicated Hardware-Accelerated SHA Engine for
The DeepCover Secure Authenticator (DS28E22) com-
bines crypto-strong, bidirectional, secure challenge-and-
response authentication functionality with an implemen-
tation based on the FIPS 180-3-specified Secure Hash
Algorithm (SHA-256). A 2Kb user-programmable EEPROM
array provides nonvolatile storage of application data and
additional protected memory holds a read-protected secret
for SHA-256 operations and settings for user memory
control. Each device has its own guaranteed unique 64-bit
ROM identification number (ROM ID) that is factory pro-
grammed into the chip. This unique ROM ID is used as a
fundamental input parameter for cryptographic operations
and also serves as an electronic serial number within
the application. A bidirectional security model enables
two-way authentication between a host system and slave-
embedded DS28E22. Slave-to-host authentication is used
by a host system to securely validate that an attached or
embedded DS28E22 is authentic. Host-to-slave authenti-
cation is used to protect DS28E22 user memory from being
modified by a nonauthentic host. The SHA-256 message
authentication code (MAC), which the DS28E22 gener-
ates, is computed from data in the user memory, an on-
chip secret, a host random challenge, and the 64-bit ROM
ID. The DS28E22 communicates over the single-contact
Generating SHA-256 MACs
● Strong Authentication with a High Bit Count, User-
Programmable Secret, and Input Challenge
● 2048 Bits of User EEPROM Partitioned Into 8 Pages
of 256 Bits
● User-Programmable and Irreversible EEPROM
Protection Modes Including Authentication, Write and
Read Protect, and OTP/EPROM Emulation
● Unique, Factory-Programmed 64-Bit Identification
Number
● Single-Contact 1-Wire Interface Communicates with
Host at Up to 76.9kbps
● Operating Range: 3.3V ±10%, -40NC to +85NC
● Low-Power 5µA (typ) Standby
● ±8kV Human Body Model ESD Protection (typ)
● 6-Pin TDFN, 6-Lead TSOC Packages
Typical Application Circuit
3.3V
R
P
M
1-Wire bus at overdrive speed. The communication fol-
lows the 1-Wire protocol with the ROM ID acting as node
address in the case of a multiple-device 1-Wire network.
R
= 1.1kΩ
P
V
CC
2
MAXIMUM I C BUS CAPACITANCE 320pF
SDA
SCL
2
(I C PORT)
DS2465
µC
Applications
1-Wire LINE
SLPZ
IO
●
●
●
●
●
●
●
Authentication of Network-Attached Appliances
Printer Cartridge ID/Authentication
DS28E22
Reference Design License Management
System Intellectual Property Protection
Sensor/Accessory Authentication and Calibration
Secure Feature Setting for Configurable Systems
Key Generation and Exchange for Cryptographic
Systems
Ordering Information appears at end of data sheet.
DeepCover and 1-Wire are registered trademarks of Maxim Integrated Products, Inc.
219-0020; Rev 3; 7/21
©
2021 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887 U.S.A.
|
Tel: 781.329.4700
|
© 2021 Analog Devices, Inc. All rights reserved.
ABRIDGED DATA SHEET
DS28E22
DeepCover Secure Authenticator with
1-Wire SHA-256 and 2Kb User EEPROM
ABSOLUTE MAXIMUM RATINGS
IO Voltage Range to GND...................................... -0.5V to 4.0V
IO Sink Current...................................................................20mA
Operating Temperature Range.......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -55NC to +125NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(T = -40NC to +85NC, unless otherwise noted.) (Note 1)
A
PARAMETER
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
R
(Note 2)
= 3.3V Q10% (Note 3)
2.97
300
3.63
V
I
PUP
1-Wire Pullup Resistance
Input Capacitance
V
1500
PUP
PUP
C
(Notes 4, 5)
IO pin at V
1500
5
pF
FA
V
IO
Input Load Current
I
19.5
0.3
L
PUP
High-to-Low Switching Threshold
Input Low Voltage
V
TL
(Notes 6, 7)
(Notes 2, 8)
(Notes 6, 9)
(Notes 6, 10)
0.65 x V
PUP
V
V
IL
Low-to-High Switching Threshold
Switching Hysteresis
Output Low Voltage
V
TH
V
HY
V
OL
0.75 x V
0.3
V
PUP
V
I
= 4mA (Note 11)
0.4
V
OL
Recovery Time
t
R
= 1500I (Notes 2, 12)
5
Fs
Fs
REC
PUP
Time-Slot Duration
t
(Notes 2, 13)
13
SLOT
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Reset Low Time
t
(Note 2)
48
48
8
80
10
Fs
Fs
Fs
RSTL
Reset High Time
t
(Note 14)
(Notes 2, 15)
RSTH
Presence-Detect Sample Time
t
MSP
IO PIN: 1-Wire WRITE
Write-Zero Low Time
t
t
(Notes 2, 16)
(Notes 2, 16)
8
16
2
Fs
Fs
W0L
W1L
Write-One Low Time
0.25
IO PIN: 1-Wire READ
Read Low Time
t
(Notes 2, 17)
(Notes 2, 17)
0.25
2 - d
Fs
Fs
RL
Read Sample Time
t
t
+ d
2
MSR
RL
EEPROM
Programming Current
I
V
= 3.63V (Notes 5, 18)
1
mA
ms
PROG
PUP
Programming Time for a 32-Bit
Segment or Page Protection
t
10
PRD
Refer to the full data sheet.
Programming Time for the Secret
Write/Erase Cycling Endurance
Data Retention
t
100
ms
—
PRS
N
T
T
= +85NC (Notes 21, 22)
100k
10
CY
A
t
= +85NC (Notes 23, 24, 25)
Years
DR
A
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ABRIDGED DATA SHEET
DS28E22
DeepCover Secure Authenticator with
1-Wire SHA-256 and 2Kb User EEPROM
ELECTRICAL CHARACTERISTICS (continued)
(T = -40NC to +85NC, unless otherwise noted.) (Note 1)
A
PARAMETER
SHA-256 ENGINE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Computation Current
Computation Time
I
t
1
3
mA
ms
CSHA
Refer to the full data sheet.
CSHA
Note 1: Limits are 100% production tested at T = +25°C and/or T = +85°C. Limits over the operating temperature range and
A
A
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: System requirement.
Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 4: Typical value represents the internal parasite capacitance when V
is first applied. Once the parasite capacitance is
PUP
charged, it does not affect normal communication.
Note 5: Guaranteed by design and/or characterization only; not production tested.
Note 6: , V , and V are a function of the internal supply voltage, which is a function of V
V
, R
, 1-Wire timing, and
TL TH
HY
PUP PUP
capacitive loading on IO. Lower V
, higher R
, shorter t
, and heavier capacitive loading all lead to lower values
PUP
PUP
REC
of V , V , and V
.
TL TH
HY
Note 7: Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 8: The voltage on IO must be less than or equal to V at all times when the master is driving IO to a logic-zero level.
ILMAX
Note 9: Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 10: After V is crossed during a rising edge on IO, the voltage on IO must drop by at least V to be detected as logic-zero.
TH
HY
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: Defines maximum possible bit rate. Equal to 1/(t
+ t
).
W0LMIN
RECMIN
Note 14: An additional reset or communication sequence cannot begin until the reset high time has expired.
Note 15: Interval after t during which a bus master can read a logic 0 on IO if there is a DS28E22 present. The power-up pres-
RSTL
ence detect pulse could be outside this interval, but will be complete within 2ms after power-up.
Note 16: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V to V . The actual
IL
TH
maximum duration for the master to pull the line low is t
+ t - ε and t
+ t - ε, respectively.
W1LMAX
F
W0LMAX F
Note 17: d in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V to the input-high
IL
RLMAX
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
+ t .
F
Note 18: Current drawn from IO during the EEPROM programming interval or SHA-256 computation. The pullup circuit on IO during
the programming interval or SHA-256 computation should be such that the voltage at IO is greater than or equal to 2.0V.
Note 19: Refer to the full data sheet.
Note 20: Refer to the full data sheet.
Note 21: Write-cycle endurance is tested in compliance with JESD47G.
Note 22: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 23: Data retention is tested in compliance with JESD47G.
Note 24: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 25: EEPROM writes can become nonfunctional after the data retention time is exceeded. Long-term storage at elevated tem-
peratures is not recommended.
Note 26: Refer to the full data sheet.
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ABRIDGED DATA SHEET
DS28E22
DeepCover Secure Authenticator with
1-Wire SHA-256 and 2Kb User EEPROM
Pin Configuration
TOP VIEW
TOP VIEW
+
DS28E22
GND
IO
1
2
3
6
5
4
N.C.
N.C.
N.C.
+
N.C.
IO
1
2
3
6
5
4
N.C.
N.C.
N.C.
DS28E22
N.C.
GND
TSOC
EP
TDFN
(3mm × 3mm)
Pin Description
PIN
NAME
FUNCTION
TSOC
TDFN-EP
1
2
3
2
GND
IO
Ground Reference
1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor.
Not Connected
3, 4, 5, 6
1, 4, 5, 6
N.C.
Exposed Pad (TDFN only). Solder evenly to the board’s ground plane for proper operation.
Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional
information.
—
—
EP
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ABRIDGED DATA SHEET
DS28E22
DeepCover Secure Authenticator with
1-Wire SHA-256 and 2Kb User EEPROM
Note to readers: This document is an abridged version of the full data sheet. Additional device information is available
only in the full version of the data sheet. To request the full data sheet, go to www.maximintegrated.com/DS28E22
and click on Request Full Data Sheet.
Ordering Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PART
TEMP RANGE PIN-PACKAGE
DS28E22P+
DS28E22P+T
DS28E22Q+T
-40°C to +85°C 6 TSOC
-40°C to +85°C 6 TSOC (4k pcs)
-40°C to +85°C 6 TDFN-EP* (2.5k pcs)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
6 TSOC
D6+1
21-0382
21-0137
90-0321
90-0058
6 TDFN-EP
T633+2
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ABRIDGED DATA SHEET
DS28E22
DeepCover Secure Authenticator with
1-Wire SHA-256 and 2Kb User EEPROM
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
1
9/12
Initial release
—
11/12
Updated title of data sheet
1–43
Defined the EEPROM t
and added t
parameters in the Electrical
PRS
PRD
Characteristics table, thereby updating Figures 7a, 7b, 7e, 7f, 7g, 7h, and the 1-Wire
Communication Examples; removed future status from the TSOC packages in the
2, 3, 23, 24,
27–30, 38−42
2
3
12/12
7/21
Ordering Information table; data retention parameter specified at T = +85°C
A
Updated Electrical Characteristics table
2
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that
may result from its use.Specifications subject to change without notice. No license is granted by implicationor
otherwise under any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the
property of their respective owners.
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