DS2148TN+_技术文档

DS2148/DS21Q48

5V E1/T1/J1 Line Interface Unit

www.maxim-ic.com

PIN CONFIGURATION

FEATURES

ꢀ Complete E1, T1, or J1 Line Interface Unit

(LIU)

TOP VIEW

44

ꢀ Supports Both Long- and Short-Haul Trunks

ꢀ Internal Software-Selectable Receive-Side

Termination for 75Ω/100Ω/120Ω

1

DS2148

ꢀ 5V Power Supply

ꢀ 32-Bit or 128-Bit Crystal-Less Jitter

Attenuator Requires Only a 2.048MHz

Master Clock for Both E1 and T1 with

Option to Use 1.544MHz for T1

ꢀ Generates the Appropriate Line Build-Outs,

With and Without Return Loss, for E1 and

DSX-1 and CSU Line Build-Outs for T1

ꢀ AMI, HDB3, and B8ZS, Encoding/Decoding

ꢀ 16.384MHz, 8.192MHz, 4.096MHz, or

2.048MHz Clock Output Synthesized to

Recovered Clock

44 TQFP

DS2148

ꢀ Programmable Monitor Mode for Receiver

ꢀ Loopbacks and PRBS Pattern Generation/

Detection with Output for Received Errors

ꢀ Generates/Detects In-Band Loop Codes, 1 to

16 Bits including CSU Loop Codes

ꢀ 8-Bit Parallel or Serial Interface with

Optional Hardware Mode

49 CSBGA

(7mm x 7mm)

See Section

8

for 144-pin CSBGA pinout.

ORDERING INFORMATION

ꢀ Multiplexed and Nonmultiplexed Parallel

Bus Supports Intel or Motorola

TEMP

PIN-

PART

CHANNEL

RANGE

PACKAGE

DS2148TN

DS2148TN+

DS2148T

DS2148T+

DS2148GN

DS2148G

DS2148G+

DS21Q48N

DS21Q48

Single

Four

44 TQFP

49 CSBGA

144 CSBGA

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

0°C to +70°C

ꢀ Detects/Generates Blue (AIS) Alarms

ꢀ NRZ/Bipolar Interface for Tx/Rx Data I/O

ꢀ Transmit Open-Circuit Detection

ꢀ Receive Carrier Loss (RCL) Indication

(G.775)

ꢀ High-Z State for TTIP and TRING

ꢀ 50mA (RMS) Current Limiter

Four

+ Denotes lead-free/RoHS-compliant package.

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.

1 of 73

REV: 011206

DS2148/DS21Q48

TABLE OF CONTENTS

1

DETAILED DESCRIPTION.................................................................................................. 5

1.1 FUNCTION DESCRIPTION..................................................................................................................5

1.2 DOCUMENT REVISION HISTORY .......................................................................................................6

2

3

PIN DESCRIPTION............................................................................................................ 10

HARDWARE MODE .......................................................................................................... 23

3.1 REGISTER MAP .............................................................................................................................23

3.2 PARALLEL PORT OPERATION .........................................................................................................24

3.3 SERIAL PORT OPERATION..............................................................................................................24

4

CONTROL REGISTERS.................................................................................................... 28

4.1 DEVICE POWER-UP AND RESET.....................................................................................................31

STATUS REGISTERS ....................................................................................................... 34

5

6

DIAGNOSTICS .................................................................................................................. 39

6.1 IN-BAND LOOP CODE GENERATION AND DETECTION ......................................................................39

6.2 LOOPBACKS ..................................................................................................................................43

6.2.1 Remote Loopback (RLB) ......................................................................................................43

6.2.2 Local Loopback (LLB)...........................................................................................................43

6.2.3 Analog Loopback (ALB)........................................................................................................44

6.2.4 Dual Loopback (DLB)............................................................................................................44

6.3 PRBS GENERATION AND DETECTION ............................................................................................44

6.4 ERROR COUNTER..........................................................................................................................44

6.4.1 Error Counter Update............................................................................................................45

6.5 ERROR INSERTION ........................................................................................................................45

ANALOG INTERFACE ...................................................................................................... 46

7

7.1 RECEIVER .....................................................................................................................................46

7.2 TRANSMITTER ...............................................................................................................................47

7.3 JITTER ATTENUATOR .....................................................................................................................47

7.4 G.703 SYNCHRONIZATION SIGNAL.................................................................................................48

8

9

DS21Q48 QUAD LIU ......................................................................................................... 55

DC CHARACTERISTICS................................................................................................... 59

9.1 THERMAL CHARACTERISTICS ................................................................................................60

10 AC CHARACTERISTICS................................................................................................... 61

11 PACKAGE INFORMATION ............................................................................................... 70

11.1 44-PIN TQFP (56-G4012-001).....................................................................................................70

11.2 49-BALL CSGBA (7MM X 7MM) (56-G6006-001)...........................................................................71

11.3 144-BALL CSBGA (17MM X 17MM) (56-G6011-001).....................................................................72

2 of 73

DS2148/DS21Q48

LIST OF FIGURES

Figure 1-1. DS2148 Block Diagram............................................................................................................7

Figure 1-2. Receive Logic...........................................................................................................................8

Figure 1-3. Transmit Logic..........................................................................................................................9

Figure 2-1. Parallel Port Mode Pinout (BIS1 = 0, BIS0 = 1 or 0) (TQFP Package) ..................................21

Figure 2-2. Serial Port Mode Pinout (BIS1 = 1, BIS0 = 0) (TQFP Package) ............................................21

Figure 2-3. Hardware Mode Pinout (BIS1 = 1, BIS0 = 1) (TQFP Package) .............................................22

Figure 3-1. Serial Port Operation for Read Access (R = 1) Mode 1 .........................................................25

Figure 3-2. Serial Port Operation for Read Access Mode 2 .....................................................................25

Figure 3-3. Serial Port Operation for Read Access Mode 3 .....................................................................26

Figure 3-4. Serial Port Operation for Read Access Mode 4 .....................................................................26

Figure 3-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2..............................................27

Figure 3-6. Serial Port Operation for Write Access (R = 0) Modes 3 and 4..............................................27

Figure 7-1. Basic Interface .......................................................................................................................49

Figure 7-2. Protected Interface Using Internal Receive Termination........................................................50

Figure 7-3. Protected Interface Using External Receive Termination.......................................................51

Figure 7-4. E1 Transmit Pulse Template..................................................................................................52

Figure 7-5. T1 Transmit Pulse Template..................................................................................................53

Figure 7-6. Jitter Tolerance ......................................................................................................................54

Figure 7-7. Jitter Attenuation ....................................................................................................................54

Figure 8-1. 144-Pin CSBGA (17mm x 17mm) Pinout...............................................................................58

Figure 10-1. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 0) .......................................................62

Figure 10-2. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 0) .......................................................62

Figure 10-3. Motorola Bus Timing (PBTS = 1, BIS1 = 0, BIS0 = 0)..........................................................63

Figure 10-4. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) .......................................................65

Figure 10-5. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) .......................................................65

Figure 10-6. Motorola Bus Read Timing (PBTS = 1, BIS1 = 0, BIS0 = 1)................................................66

Figure 10-7. Motorola Bus Write Timing (PBTS = 1, BIS1 = 0, BIS0 = 1) ................................................66

Figure 10-8. Serial Bus Timing (BIS1 = 1, BIS0 = 0)................................................................................67

Figure 10-9. Receive Side Timing ............................................................................................................68

Figure 10-10. Transmit Side Timing .........................................................................................................69

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DS2148/DS21Q48

LIST OF TABLES

Table 2-1. Bus Interface Selection ...........................................................................................................10

Table 2-2. Pin Assignment in Parallel Port Mode.....................................................................................10

Table 2-3. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name, DS2148T) ...............................12

Table 2-4. Pin Assignment in Serial Port Mode........................................................................................14

Table 2-5. Pin Descriptions in Serial Port Mode (Sorted by Pin Name, DS2148T) ..................................15

Table 2-6. Pin Assignment in Hardware Mode.........................................................................................17

Table 2-7. Pin Description in Hardware Mode (Sorted by Pin Name, DS2148T) .....................................18

Table 2-8. Loopback Control in Hardware Mode......................................................................................20

Table 2-9. Transmit Data Control in Hardware Mode...............................................................................20

Table 2-10. Receive Sensitivity Settings ..................................................................................................20

Table 2-11. Monitor Gain Settings............................................................................................................20

Table 2-12. Internal Rx Termination Select..............................................................................................20

Table 2-13. MCLK Selection.....................................................................................................................20

Table 3-1. Register Map...........................................................................................................................23

Table 4-1. MCLK Selection.......................................................................................................................29

Table 4-2. Receive Sensitivity Settings ....................................................................................................31

Table 4-3. Backplane Clock Select...........................................................................................................32

Table 4-4. Monitor Gain Settings..............................................................................................................32

Table 4-5. Internal Rx Termination Select................................................................................................33

Table 5-1. Received Alarm Criteria ..........................................................................................................35

Table 5-2. Receive Level Indication .........................................................................................................38

Table 6-1. Transmit Code Length.............................................................................................................40

Table 6-2. Receive Code Length..............................................................................................................40

Table 6-3. Definition of Received Errors...................................................................................................44

Table 6-4. Function of ECRS Bits and RNEG Pin ....................................................................................45

Table 7-1. Line Build-Out Select for E1 in Register CCR4 (ETS = 0).......................................................48

Table 7-2. Line Build-Out Select for T1 in Register CCR4 (ETS = 1).......................................................48

Table 7-3. Transformer Specifications for 5V Operation ..........................................................................48

Table 8-1. DS21Q48 Pin Assignment.......................................................................................................55

Table 9-1. Recommended DC Operating Conditions...............................................................................59

Table 9-2. Capacitance ............................................................................................................................59

Table 9-3. DC Characteristics ..................................................................................................................59

Table 9-4. Thermal Characteristics—DS21Q48 CSBGA Package...........................................................60

Table 9-5. Theta-JA (θ_JA) vs. Airflow ........................................................................................................60

Table 10-1. AC Characteristics—Multiplexed Parallel Port (BIS1 = 0, BIS0 = 0) ....................................61

Table 10-2. AC Characteristics—Nonmultiplexed Parallel Port (BIS1 = 0, BIS0 = 1)..............................64

Table 10-3. AC Characteristics—Serial Port (BIS1 = 1, BIS0 = 0) ...........................................................67

Table 10-4. AC Characteristics—Receive Side........................................................................................68

Table 10-5. AC Characteristics—Transmit Side.......................................................................................69

4 of 73

DS2148/DS21Q48

1 DETAILED DESCRIPTION

The DS2148 is a complete selectable E1 or T1 Line Interface Unit (LIU) for short- and long-haul

applications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts

automatically to the incoming signal and can be programmed for 0dB to 12dB or 0dB to 43dB for E1

applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary

G.703 E1 waveshapes in 75Ω or 120Ω applications and DSX-1 line built-outs or CSU line built-outs of

0dB, -7.5dB, -15dB, and -22.5dB for T1 applications. The crystal-less onboard jitter attenuator requires

only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK

in T1 applications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can

be placed in either the transmit or receive data paths. An X 2.048MHz output clock synthesized to RCLK

is available for use as a backplane system clock (where n = 1, 2, 4, or 8). The DS2148 has diagnostic

capabilities such as loopbacks and PRBS pattern generation/detection. 16-bit loop-up and loop-down

codes can be generated and detected. The device can be controlled via an 8-bit parallel muxed or

nonmuxed port, serial port or used in hardware mode. The device fully meets all of the latest E1 and T1

specifications including ANSI T1.403-1999, ANSI T1.408, AT&T TR 62411, ITU G.703, G.704, G.706,

G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703, JTI.431, JJ-20.1, TBR12,

TBR13, and CTR4.

1.1 Function Description

The analog AMI/HDB3 waveform off the E1 line or the AMI/B8ZS waveform off the T1 line is

transformer coupled into the RTIP and RRING pins of the DS2148. The user has the option to use

internal software-selectable receive-side termination for 75Ω/100Ω/120Ω applications or external

termination. The device recovers clock and data from the analog signal and passes it through the jitter

attenuation MUX outputting the received line clock at RCLK and bipolar or NRZ data at RPOS and

RNEG. The DS2148 contains an active filter that reconstructs the analog-received signal for the nonlinear

losses that occur in transmission. The receive circuitry also is configurable for various monitor

applications. The device has a usable receive sensitivity of 0dB to -43dB (E1) and 0dB to -36dB (T1),

which allows the device to operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in

length. Data input at TPOS and TNEG is sent via the jitter attenuation MUX to the waveshaping circuitry

and line driver. The DS2148 will drive the E1 or T1 line from the TTIP and TRING pins via a coupling

transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or

short-haul (DSX-1) lines for T1.

5 of 73

DS2148/DS21Q48

1.2 Document Revision History

1) 100Ω/60Ω termination reversed in Internal Rx Termination Select tables, 091799.

2) Add DS21Q48 pinout, 092899.

3) Correct VSM pin number in Q48 (12 x 12 BGA) from G5 to G4, 120699.

4) Add timing diagram for Status Register (write access mode); Add mechanical dimensions for the

quad version, 032900.

5) Timing diagram for Status Register (write access mode) added; elaboration on burst mode bit; add

mechanical dimensions for the quad version, 050300.

6) Changes to datasheet to indicate 5V only part, 011801.

7) Added supply current measurement; added thermal characteristics of quad package, 092001.

8) Corrected typos and removed instances of 3V operation, 082504.

9) In Absolute Maximum Ratings, changed the spec for soldering temperature from IPC/JEDEC J-STD-

020A to J-STD-020; defined the storage temperature range as –55°C to +125°C.

10) Added lead-free packages to Ordering Information table on page 1; updated style of data sheet,

011206.

6 of 73

DS2148/DS21Q48

Figure 1-1. DS2148 Block Diagram

JACLK

Jitter

Attenuator

MUX

2.048MHz to

16.384MHz or

8.192MHz or

4.096MHz or

2.048MHz

Power Connections

1.544MHz PLL

VCO / PLL

BPCLK

Synthesizer

RPOS

RCLK

RNEG

RRING

RTIP

See Figure 3-2

PBEO

Unframed

All Ones

Insertion

MUX

RCL/LOTC

TPOS

TCLK

TNEG

TRING

TTIP

See Figure 3-3

HRST*

TEST

BIS1

Control and Test Port

(routed to all blocks)

rdware Interfaces share device pins)

MUX (the Serial, Parallel, and Ha

BIS0

Hardware

Interface

Control and

Serial Interface

Parallel Interface

Interrupt

21

8

5

7 of 73

DS2148/DS21Q48

Figure 1-2. Receive Logic

Clock

Invert

RCLK

RPOS

From

Routed to

All Blocks

Remote

Loopback

CCR2.0

mux

NRZ Data

B8ZS/HDB3

Decoder

RNEG

BPV/CV/EXZ

CCR1.6

PBEO

CCR2.3

All Ones

Detector

Loop Code

Detector

PRBS

4 or 8 Zero Detect

16 Zero Detect

Detector

CCR6.2/ RIR1.5

CCR6.0/

CCR6.1

SR.4 RIR1.3 SR.6

SR.7

SR.0

CCR6.0

mux

RIR1.7

RIR1.6

16-Bit Error

CCR1.4

Counter (ECR)

rx bd

8 of 73

DS2148/DS21Q48

Figure 1-3. Transmit Logic

CCR3.4

CCR3.3

CCR1.6

CCR2.2

PRBS Generator

CCR3.0

OR

Gate

CCR3.1

Loop Code Generator

mux

1

0

B8ZS/

HDB3

Coder

Logic

Error

Insert

TPOS

TNEG

OR

Gate

BPV

mux

To

Insert

Remote

Loopback

0

1

0

1

Clock

TCLK

Invert

mux

JACLK

(derived

from

mux

CCR2.1

Routed to

All Blocks

OR

MCLK)

Gate

RCLK

AND

Gate

CCR1.1

Loss Of Transmit

Clock Detect

CCR1.2

CCR1.0

tx bd

SR.5

To LOTC Output Pin

9 of 73

DS2148/DS21Q48

2 PIN DESCRIPTION

The DS2148 can be controlled in a parallel port mode, a serial port mode, or a hardware mode (Table 2-1,

Table 2-2, and Table 2-3). The parallel and serial port modes are described in Section 3.2 and 3.3, and the

hardware mode is described below.

Table 2-1. Bus Interface Selection

BIS1

BIS0

PBTS

BUS INTERFACE TYPE

Muxed Intel

0

1

0

1

0

1

0

1

0

1

-

Muxed Motorola

Nonmuxed Intel

Nonmuxed Motorola

Serial Port

-

Hardware

Table 2-2. Pin Assignment in Parallel Port Mode

DS2148T

DS2148G

PIN#

C3

PARALLEL

PORT MODE

CS

I/O

PIN #

1

I

2

C2

RD(DS)

WR(R/W)

ALE(AS)

NA

3

B1

I

4

D2

C1

I

5

I

6

D3

D1

E1

I

NA

7

I/O

I

A4

8

A3

9

F2

I

A2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

F1

I

A1

G1

E3

I

A0

I/O

I

D7/AD7

D6/AD6

D5/AD5

D4/AD4

D3/AD3

D2/AD2

D1/AD1

D0/AD0

VSM

F3

G2

F4

G3

E4

G4

F5

G5

F6

-

V_DD

G6

E5

V_SS

I/O

O

I

INT

E6

PBEO

RCL/LOTC

TEST

F7

D6

D5

D7

I

RTIP

RRING

10 of 73

DS2148/DS21Q48

DS2148T

PIN #

29

DS2148G

PIN#

C6

PARALLEL

PORT MODE

HRST

I/O

I

30

C7

MCLK

BPCLK

BIS0

31

B6

O

I

32

B7

33

A7

I

BIS1

34

C5

O

-

TTIP

35

B5

V_SS

36

A6

-

V_DD

37

B4

O

I

TRING

RPOS

38

C4

39

A4

RNEG

RCLK

TPOS

40

B3

41

A3

42

B2

I

TNEG

TCLK

PBTS

43

A2

I

44

A1

I

11 of 73

DS2148/DS21Q48

Table 2-3. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name,

DS2148T)

NAME

A0

11

to

I/O

FUNCTION

Address Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 = 1),

serves as the address bus. In multiplexed bus operation (BIS1 = 0, BIS0 =

0), these pins are not used and should be tied low.

to

I

A4

7

Address Latch Enable (Address Strobe). When using the parallel port

(BIS1 = 0) in multiplexed bus mode (BIS0 = 0), serves to demultiplex the

bus on a positive-going edge. In nonmultiplexed bus mode (BIS0 = 1),

should be tied low.

ALE(AS)

4

I

Bus Interface Select Bits 0 & 1. Used to select bus interface option. See

Table 2-1 for details.

BIS0/BIS1

BPCLK

32/33

31

Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz

clock output that is referenced to RCLK selectable via CCR5.7 and

CCR5.6. In hardware mode, defaults to 16.384MHz output.

Active-Low Chip Select. Must be low to read or write to the device.

Data Bus/Address/Data Bus. In non-multiplexed bus operation (BIS1 =

0, BIS0 = 1), serves as the data bus. In multiplexed bus operation (BIS1 =

0, BIS0 = 0), serves as an 8-bit multiplexed address/data bus.

Active-Low Hardware Reset. Bringing HRST low will reset the DS2148

setting all control bits to their default state of all zeros.

O

I

CS

D0/AD0

to

1

19

to

I/O

D7/AD7

12

HRST

29

23

I

Active-Low Interrupt. Flags host controller during conditions and

change of conditions defined in the Status Register. Active low, open

drain output.

INT

O

Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is

applied at this pin. This clock is used internally for both clock/data

recovery and for jitter attenuation. Use of a T1 1.544MHz clock source is

optional.

MCLK

NA

30

-

I

See Note 1 on clock accuracy at the end of this table.

Not Assigned. Should be tied low.

PRBS Bit Error Output. The receiver will constantly search for a 2¹⁵-1 or

a 2²⁰-1 PRBS depending on the ETS bit setting (CCR1.7). Remains high if

out of synchronization with the PRBS pattern. Goes low when

synchronized to the PRBS pattern. Any errors in the received pattern after

synchronization will cause a positive going pulse (with same period as E1

or T1 clock) synchronous with RCLK. PRBS bit errors can also be

reported to the ECR1 and ECR2 registers by setting CCR6.2 to a logic 1.

Parallel Bus Type Select. When using the parallel port (BIS1 = 0), set

high to select Motorola bus timing, set low to select Intel bus timing. This

pin controls the function of the RD(DS), ALE(AS), and WR(R/W) pins. If

PBTS = 1 and BIS1 = 0, then these pins assume the Motorola function

listed in parenthesis (). In serial port mode, this pin should be tied low.

Receive Clock. Buffered recovered clock from the line. Synchronous to

MCLK in absence of signal at RTIP and RRING.

PBEO

24

O

PBTS

44

I

RCLK

40

2

O

I

Active-Low Read Input (Data Strobe). DS is active low when in

nonmultiplexed, Motorola mode. See the bus timing diagrams in Section

10.

RD(DS)

Receive Carrier Loss/Loss of Transmit Clock. An output which will

toggle high during a receive carrier loss (CCR2.7 = 0) or will toggle high

if the TCLK pin has not been toggled for 5µs ±2µs (CCR2.7 = 1). CCR2.7

defaults to logic 0 when in hardware mode.

RCL/LOTC

25

O

12 of 73

DS2148/DS21Q48

NAME

I/O

FUNCTION

Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the

falling edge (CCR2.0 = 1) of RCLK with the bipolar data out of the line

interface. Set NRZE (CCR1.6) to a one for NRZ applications. In NRZ

mode, data will be output on RPOS while a received error will cause a

positive-going pulse synchronous with RCLK at RNEG. See Section 6.4

for details.

RNEG

39

O

Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the

falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the line

interface. Set NRZE (CCR1.6) to a one for NRZ applications. In NRZ

mode, data will be output on RPOS while a received error will cause a

positive-going pulse synchronous with RCLK at RNEG. See Section 6.2

for details.

RPOS

38

O

Receive Tip and Ring. Analog inputs for clock recovery circuitry. These

pins connect via a 1:1 transformer to the line. See Section 5 for details.

Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to clock

data through the transmit side formatter. Can be sourced internally by

MCLK or RCLK. See Common Control Register 1 and Figure 1-3.

Tri-state Control. Set high to tri-state all outputs and I/O pins (including

the parallel control port). Set low for normal operation. Useful in board

level testing.

RTIP/RRING

TCLK

27/28

43

I

TEST

26

42

I

Transmit Negative Data. Sampled on the falling edge (CCR2.1 = 0) or

the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto

the line.

TNEG

Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0) or the

rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto the

line.

TPOS

41

I

Transmit Tip and Ring. Analog line driver outputs. These pins connect

via a step-up transformer to the line. See Section 5 for details.

5.0V ±5% Positive Supply

TTIP/TRING

34/37

O

V_DD

VSM

V_SS

21/36

20

22/35

-

I

-

Voltage Supply Mode. Should be tied high for 5V operation

Signal Ground

WR

Active-Low Write Input (Read/Write). See the bus timing diagrams in

Section 10.

3

I

(R/W)

13 of 73

DS2148/DS21Q48

Table 2-4. Pin Assignment in Serial Port Mode

DS2148T

PIN #

1

DS2148G

PIN#

C3

C2

B1

D2

C1

D3

D1

E1

SERIAL

PORT MODE

CS

I/O

I

2

NA

3

I

NA

4

I

NA

5

I

SCLK

SDI

6

I

7

I/O

I

SDO

8

ICES

OCES

NA

9

F2

I

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

F1

I

G1

E3

I

NA

I/O

I

NA

F3

NA

G2

F4

NA

G3

E4

NA

G4

F5

NA

G5

F6

VSM

V_DD

-

G6

E5

V_SS

INT

I/O

O

I

E6

PBEO

RCL/LOTC

TEST

RTIP

RRING

HRST

MCLK

BPCLK

BIS0

BIS1

TTIP

V_SS

F7

D6

D5

D7

C6

C7

B6

B7

A7

C5

B5

A6

B4

C4

A4

B3

A3

B2

A2

A1

I

O

I

O

-

V_DD

O

I

TRING

RPOS

RNEG

RCLK

TPOS

TNEG

TCLK

NA

I

14 of 73

DS2148/DS21Q48

Table 2-5. Pin Descriptions in Serial Port Mode (Sorted by Pin Name,

DS2148T)

NAME

I/O

FUNCTION

Bus Interface Select Bits 0 & 1. Used to select bus interface option. See

Table 2-1 for details.

BIS0/BIS1

32/33

I

Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz

clock output that is referenced to RCLK selectable via CCR5.7 and

CCR5.6. In hardware mode, defaults to 16.384MHz output.

Active-Low Chip Select. Must be low to read or write to the device.

Hardware Reset. Bringing HRST low will reset the DS2148 setting all

control bits to their default state of all zeros.

BPCLK

31

O

CS

1

I

HRST

29

Input Clock Edge Select. Selects whether the serial port data input (SDI)

is sampled on rising (ICES =0) or falling edge (ICES = 1) of SCLK.

Active-Low Interrupt. Flags host controller during conditions and change

of conditions defined in the Status Register. Active low, open drain output.

Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is

applied at this pin. This clock is used internally for both clock/data

recovery and for jitter attenuation. Use of a T1 1.544MHz clock source is

optional. See Note 1 on clock accuracy at the end of this table.

Not Assigned. Should be tied low.

ICES

8

I

INT

23

O

MCLK

30

I

NA

-

I

Output Clock Edge Select. Selects whether the serial port data output

(SDO) is valid on the rising (OCES = 1) or falling edge (OCES = 0) of

SCLK.

OCES

9

PRBS Bit Error Output. The receiver will constantly search for a 2¹⁵-1

or a 2²⁰-1 PRBS depending on the ETS bit setting (CCR1.7). Remains

high if out of synchronization with the PRBS pattern. Goes low when

synchronized to the PRBS pattern. Any errors in the received pattern after

synchronization will cause a positive going pulse (with same period as E1

or T1 clock) synchronous with RCLK. PRBS bit errors can also be

reported to the ECR1 and ECR2 registers by setting CCR6.2 to a logic 1.

Receive Clock. Buffered recovered clock from the line. Synchronous to

MCLK in absence of signal at RTIP and RRING.

Receive Carrier Loss/Loss of Transmit Clock. An output which will

toggle high during a receive carrier loss (CCR2.7 = 0) or will toggle high

if the TCLK pin has not been toggled for 5 µs ± 2 µs (CCR2.7 = 1).

CCR2.7 defaults to logic 0 when in hardware mode.

PBEO

24

O

RCLK

40

25

O

RCL/LOTC

Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the

falling edge (CCR2.0 = 1) of RCLK with the bipolar data out of the line

interface. Set NRZE (CCR1.6) to a one for NRZ applications. In NRZ

mode, data will be output on RPOS while a received error will cause a

positive-going pulse synchronous with RCLK at RNEG. See Section 6.4

for details.

Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the

falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the line

interface. Set NRZE (CCR1.6) to a one for NRZ applications. In NRZ

mode, data will be output on RPOS while a received error will cause a

positive-going pulse synchronous with RCLK at RNEG. See Section 6.4

for details.

Receive Tip and Ring. Analog inputs for clock recovery circuitry. These

pins connect via a 1:1 transformer to the line. See Section 5 for details.

Serial Clock. Serial bus clock input.

RNEG

RPOS

39

38

O

RTIP/RRING

SCLK

27/28

5

I

15 of 73

DS2148/DS21Q48

NAME

I/O

FUNCTION

Serial Data Input. Sampled on rising edge (ICES = 0) or the falling edge

(ICES = 1) of SCLK.

SDI

6

I

Serial Data Output. Valid on the falling edge (OCES = 0) or the rising

edge (OCES = 1) of SCLK.

SDO

7

O

I

Transmit Clock. A 2.048 MHz or 1.544 MHz primary clock. Used to

clock data through the transmit side formatter. Can be sourced internally

by MCLK or RCLK. See Common Control Register 1 and Figure 1-3.

Tri-State Control. Set high to tri-state all outputs and I/O pins (including

the parallel control port). Set low for normal operation. Useful in board

level testing.

TCLK

43

TEST

26

42

I

Transmit Negative Data. Sampled on the falling edge (CCR2.1 = 0) or

the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto

the line.

TNEG

Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0) or the

rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto the

line.

TPOS

41

I

Transmit Tip and Ring . Analog line driver outputs. These pins connect

via a step-up transformer to the line. See Section 5 for details.

5.0V ±5% Positive Supply

TTIP/TRING

34/37

O

V_DD

VSM

V_SS

21/36

20

22/35

-

I

-

Voltage Supply Mode. Should be tied high for 5V operation.

Signal Ground

16 of 73

DS2148/DS21Q48

Table 2-6. Pin Assignment in Hardware Mode

DS2148T

PIN #

1

DS2148G

PIN#

C3

C2

B1

D2

C1

D3

D1

E1

HARDWARE

MODE

EGL

I/O

I

2

ETS

3

I

NRZE

SCLKE

L2

4

I

5

I

6

I

L1

7

I/O

I

L0

8

DJA

9

F2

I

JAMUX

JAS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

F1

I

G1

E3

I

HBE

I/O

I

CES

F3

TPD

G2

F4

TX0

TX1

G3

E4

LOOP0

LOOP1

MM0

MM1

VSM

V_DD

G4

F5

G5

F6

-

G6

E5

V_SS

I/O

O

I

RT1

E6

PBEO

RCL

F7

D6

D5

D7

C6

C7

B6

B7

A7

C5

B5

A6

B4

C4

A4

B3

A3

B2

A2

A1

TEST

RTIP

RRING

HRST

MCLK

BPCLK

BIS0

I

O

I

BIS1

O

-

TTIP

V_SS

-

V_DD

O

I

TRING

RPOS

RNEG

RCLK

TPOS

TNEG

TCLK

RT0

I

17 of 73

DS2148/DS21Q48

Table 2-7. Pin Description in Hardware Mode (Sorted by Pin Name, DS2148T)

NAME

BIS0/BIS1

BPCLK

32/33

31

I/O

I

FUNCTION

Bus Interface Select Bits 0 & 1. Used to select bus interface option. BIS0 = 1

and BIS1 = 1 selects hardware mode.

Backplane Clock. 16.384MHz output.

Receive & Transmit Clock Edge Select. Selects which RCLK edge to update

RPOS and RNEG and which TCLK edge to sample TPOS and TNEG.

0 = update RNEG/RPOS on rising edge of RCLK; sample TPOS/TNEG on

falling edge of TCLK

O

CES

DJA

12

8

I

1 = update RNEG/RPOS on falling edge of RCLK; sample TPOS/TNEG on

rising edge of TCLK

Disable Jitter Attenuator

0 = jitter attenuator enabled

1 = jitter attenuator disabled

Receive Equalizer Gain Limit. This pin controls the sensitivity of the receive

equalizer.

EGL E1 (ETS = 0)

0 = -12dB (short haul)

EGL

ETS

1

2

I

1 = -43dB (long haul)

EGL T1 (ETS = 1)

0 = -36dB (long haul)

1 = -30dB (limited long haul)

E1/T1 Select.

0 = E1

1 = T1

Receive & Transmit HDB3/B8ZS Enable.

0 = enable HDB3 (E1)/B8ZS (T1)

1 = disable HDB3 (E1)/B8ZS (T1)

HBE

11

29

I

HRST

Hardware Reset. Bringing HRST low will reset the DS2148.

Jitter Attenuator MUX. Controls the source for JACLK. See Figure 1-1 and

Table 2-13.

E1 (ETS = 0)

JAMUX

9

I

MCLK = 2.048MHz

T1 (ETS = 1)

0

MCLK = 2.048MHz

MCLK = 1.544MHz

1

0

Jitter Attenuator Select

JAS

10

I

0 = place the jitter attenuator on the receive side

1 = place the jitter attenuator on the transmit side

Transmit LIU Waveshape Select Bits 0 & 1 [H/W Mode]. These inputs

determine the waveshape of the transmitter. See Table 7-1 and Table 7-2.

Loopback Select Bits 0 & 1 [H/W Mode]. These inputs determine the active

loopback mode (if any). See Table 2-8.

L0/L1/L2

7/6/5

I

LOOP0/

LOOP1

16/17

Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied

at this pin. This clock is used internally for both clock/data recovery and for jitter

attenuation. Use of a T1 1.544MHz clock source is optional. G.703 requires an

accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an

accuracy of ±32ppm for T1 interfaces.

Monitor Mode Select Bits 0 & 1 [H/W Mode]. These inputs determine if the

receive equalizer is in a monitor mode. See Table 2-11.

Not Assigned. Should be tied low.

MCLK

30

I

MM0/MM1

NA

18/19

-

I

18 of 73

DS2148/DS21Q48

NAME

I/O

FUNCTION

NRZ Enable [H/W Mode]

0 = Bipolar data at RPOS/RNEG and TPOS/TNEG

NRZE

3

I

1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a positive going

pulse when device receives a BPV, CV, or EXZ.

PRBS Bit Error Output. The receiver will constantly search for a QRSS (T1)

or a 2¹⁵-1 (E1) PRBS depending on whether T1 or E1 mode is selected. Remains

high if out of synchronization with the PRBS pattern. Goes low when

synchronized to the PRBS pattern. Any errors in the received pattern after

synchronization will cause a positive going pulse (with same period as E1 or T1

clock) synchronous with RCLK.

PBEO

24

O

Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK

in absence of signal at RTIP and RRING.

RCLK

RCL

40

25

O

Receive Carrier Loss. An output which will toggle high during a receive carrier

loss.

Receive Negative Data. Updated on the rising edge (CES = 0) or the falling

edge (CES = 1) of RCLK with the bipolar data out of the line interface. Set

NRZE to a one for NRZ applications. In NRZ mode, data will be output on

RPOS while a received error will cause a positive-going pulse synchronous with

RCLK at RNEG. See Section 6.4 for details.

RNEG

39

38

O

Receive Positive Data. Updated on the rising edge (CES = 0) or the falling edge

(CES = 1) of RCLK with bipolar data out of the line interface. Set NRZE pin to a

one for NRZ applications. In NRZ mode, data will be output on RPOS while a

received error will cause a positive-going pulse synchronous with RCLK at

RNEG. See Section 6.4 for details.

RPOS

Receive LIU Termination Select Bits 0 & 1 [H/W Mode]. These inputs

determine the receive termination. See Table 2-12.

RT0/RT1

44/23

27/28

I

RTIP/

Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins

connect via a 1:1 transformer to the line. See Section 5 for details.

Receive & Transmit Synchronization Clock Enable.

RRING

SCLKE

4

I

0 = disable 2.048MHz synchronization transmit and receive mode

1 = enable 2.048MHz synchronization transmit and receive mode

Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to clock data

through the transmit side formatter.

TCLK

TEST

43

26

42

I

Tri-State Control. Set high to tri-state all outputs and I/O pins (including the

parallel control port). Set low for normal operation. Useful in board level testing.

Transmit Negative Data. Sampled on the falling edge (CES = 0) or the rising

edge (CES = 1) of TCLK for data to be transmitted out onto the line.

Transmit Power-Down

TNEG

TPD

13

I

0 = normal transmitter operation

1 = powers down the transmitter and tri-states the TTIP and TRING pins

Transmit Positive Data. Sampled on the falling edge (CES = 0) or the rising

edge (CES = 1) of TCLK for data to be transmitted out onto the line.

Transmit Tip and Ring. Analog line driver outputs. These pins connect via a

step-up transformer to the line. See Section 5 for details.

TPOS

41

I

O

I

TTIP/

34/37

TRING

Transmit Data Source Select Bits 0 & 1 [H/W Mode]. These inputs determine

the source of the transmit data. See Table 2-9.

TX0/TX1

14/15

V_DD

VSM

V_SS

21/36

20

22/35

-

I

-

5.0V ±5% Positive Supply

Voltage Supply Mode. Should be tied high for 5V operation

Signal Ground

Note 1: G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an accuracy of ±32ppm for T1

interfaces.

19 of 73

DS2148/DS21Q48

Table 2-8. Loopback Control in Hardware Mode

LOOPBACK

Remote Loopback

Local Loopback

Analog Loopback

No Loopback

SYMBOL

RLB

LLB

CONTROL BIT

CCR6.6

CCR6.7

CCR6.4

–

LOOP1

LOOP0

1

0

1

0

1

0

ALB

–

Table 2-9. Transmit Data Control in Hardware Mode

CONTROL

BIT

TRANSMIT DATA

SYMBOL

TX1

TX0

Transmit Unframed All Ones

Transmit Alternating Ones and Zeros

Transmit PRBS

TUA1

TAOZ

TPRBSE

–

CCR3.7

CCR3.5

CCR3.4

–

1

0

1

0

1

0

TPOS and TNEG

Table 2-10. Receive Sensitivity Settings

EGL

ETS

(CCR1.7)

0 (E1)

RECEIVE SENSITIVITY

(CCR4.4)

0

1

0

-12dB (short haul)

-43dB (long haul)

-30dB (limited long haul)

-36dB (long haul)

0 (E1)

1 (T1)

Table 2-11. Monitor Gain Settings

MM1

MM0

INTERNAL LINEAR

GAIN BOOST (dB)

(CCR5.5)

(CCR5.4)

0

1

0

1

0

1

Normal operation (no boost)

20

26

32

Table 2-12. Internal Rx Termination Select

RT1

RT0

INTERNAL RECEIVE

TERMINATION CONFIGURATION

Internal receive-side termination disabled

Internal receive-side 120Ω enabled

Internal receive-side 100Ω enabled

Internal receive-side 75Ω enabled

(CCR5.1)

(CCR5.0)

0

1

0

1

0

1

Table 2-13. MCLK Selection

JAMUX

MCLK

ETS

(CCR1.3)

(CCR1.7)

2.048MHz

1.544MHz

0

1

0

1

20 of 73

DS2148/DS21Q48

Figure 2-1. Parallel Port Mode Pinout (BIS1 = 0, BIS0 = 1 or 0) (TQFP

Package)

1 CS*

BIS1 33

tie low

2 RD (DS)

3 WR* (R/W*)

4 ALE (AS)

5 NA

BIS0 32 tie low (MUX) or high (non-MUX)

BPCLK 31

MCLK 30

HRST* 29

RRING 28

RTIP 27

DS2148

Parallel Port

Operation

6 NA

7 A4

(Note: tie all NA pins low)

8 A3

TEST 26

9 A2

RCL/LOTC 25

10 A1

PBEO 24

INT* 23

11 A0

Figure 2-2. Serial Port Mode Pinout (BIS1 = 1, BIS0 = 0) (TQFP Package)

1 CS*

2 NA

BIS1 33

tie high

BIS0 32 tie low

BPCLK 31

MCLK 30

3 NA

4 NA

DS2148

Serial Port

Operation

5 SCLK

6 SDI

HRST* 29

RRING 28

RTIP 27

7 SDO

8 ICES

9 OCES

10 NA

11 NA

(Note: tie all NA pins low)

TEST 26

RCL/LOTC 25

PBEO 24

INT* 23

21 of 73

DS2148/DS21Q48

Figure 2-3. Hardware Mode Pinout (BIS1 = 1, BIS0 = 1) (TQFP Package)

1

2

3

4

5

6

7

8

9

EGL

ETS

NRZE

SCLKE

L2

BIS1 33

BIS0 32

tie high

BPCLK 31

MCLK 30

HRST* 29

RRING 28

RTIP 27

TEST 26

RCL 25

DS2148

Hardware

Operation

L1

L0

DJA

JAMUX

10 JAS

11 HBE

PBEO 24

RT1 23

22 of 73

DS2148/DS21Q48

3 HARDWARE MODE

In hardware mode (BIS1 = 1, BIS0 = 1), pins 1-19, 23, 25, 31, and 44 are redefined to be used for

initializing the DS2148. BPCLK (pin 31) defaults to a 16.384MHz output when in hardware mode. The

RCL/LOTC (pin 25) is designated to RCL when in hardware mode. JABDS (CCR4.2) defaults to logic 0.

The RHBE (CCR2.3) and THBE (CCR2.2) control bits are combined and controlled by HBE at pin 11

while the RSCLKE (CCR5.3) and TSCLKE (CCR5.2) bits are combined and controlled by SCLKE at

pin 4. TCES (CCR2.1) and RCES (CCR2.0) are combined and controlled by CES at pin 12. The

transmitter functions are combined and controlled by TX1 (pin 15) and TX0 (pin 14). LOOP1 (pin 17)

and LOOP0 (pin 16) control the loopback functions. All other control bits default to the logic 0 setting.

3.1 Register Map

Table 3-1. Register Map

SERIAL PORT

PARALLEL

MODE

NAME

REGISTER NAME

R/W

PORT MODE

(Notes 2–5)

(msb)

(lsb)

CCR1

CCR2

CCR3

CCR4

CCR5

CCR6

SR

Common Control Register 1

R/W

R

R/W

R

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

Note 1

B000 000A

B000 001A

B000 010A

B000 011A

B000 100A

B000 101A

B000 110A

B000 111A

B001 000A

B001 001A

B001 010A

B001 011A

B001 100A

B001 101A

B001 110A

B001 111A

B010 000A

B010 001A

B010 010A

B010 011A

B010 100A

B010 101A

–

Common Control Register 2

Common Control Register 3

Common Control Register 4

Common Control Register 5

Common Control Register 6

Status Register

IMR

Interrupt Mask Register

Receive Information Register 1

Receive Information Register 2

In-Band Code Control Register

Transmit Code Definition Register 1

Transmit Code Definition Register 2

Receive Up Code Definition Register 1

Receive Up Code Definition Register 2

Receive Down Code Definition Register 1

Receive Down Code Definition Register 2

Error Count Register 1

RIR1

RIR2

IBCC

R/W

R

TCD1

TCD2

RUPCD1

RUPCD2

RDNCD1

RDNCD2

ECR1

ECR2

TEST1

TEST2

TEST3

–

Error Count Register 2

R

Test 1

R/W

–

Test 2

Test 3

–

NOTES:

1) Register addresses 16h to 1Fh do not exist.

2) In the Serial Port Mode, the LSB is on the right hand side.

3) In the Serial Port Mode, data is read and written LSB first.

4) In the Serial Port Mode, the A bit (the LSB) determines whether the access is a read (A = 1) or a write

(A = 0).

5) In the Serial Port Mode, the B bit (the MSB) determines whether the access is a burst access (B = 1) or a single

register access (B = 0).

23 of 73

DS2148/DS21Q48

3.2 Parallel Port Operation

When using the parallel interface on the DS2148 (BIS1 = 0) the user has the option for either multiplexed

bus operation (BIS1 = 0, BIS0 = 0) or nonmultiplexed bus operation (BIS1 = 0, BIS0 = 1). The DS2148

can operate with either Intel or Motorola bus timing configurations. If the PBTS pin is tied low, Intel

timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed

in parentheses. See the timing diagrams in Section 10 for more details.

3.3 Serial Port Operation

Setting BIS1 = 1 and BIS0 = 0 enables the serial bus interface on the DS2148. Port read/write timing is

unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host.

See Section 10 for the AC timing of the serial port. All serial port accesses are LSB first. See Figure 3-1,

Figure 3-2, Figure 3-3, and Figure 3-4 for more details.

Reading or writing to the internal registers requires writing one address/command byte prior to

transferring register data. The first bit written (LSB) of the address/command byte specifies whether the

access is a read (1) or a write (0). The next 5 bits identify the register address. Bit 7 is reserved and must

be set to 0 for proper operation.

The last bit (MSB) of the address/command byte is the burst mode bit. When the burst bit is enabled

(B = 1) and a READ operation is performed, addresses 0 through 15h are read sequentially, starting at

address 0h. And when the burst bit is enabled and a WRITE operation is performed, addresses 0 through

16h are written sequentially, starting at address 0h. Burst operation is stopped once address 15h is read.

See Figure 3-5 and Figure 3-6 for more details.

All data transfers are initiated by driving the CS input low. When input clock-edge select (ICES) is low,

input data is latched on the rising edge of SCLK and when ICES is high, input data is latched on the

falling edge of SCLK. When output clock-edge select (OCES) is low, data is output on the falling edge of

SCLK and when OCES is high, data is output on the rising edge of SCLK. Data is held until the next

falling or rising edge. All data transfers are terminated if the CS input transitions high. Port control logic

is disabled and SDO is tri-stated when CS is high.

24 of 73

DS2148/DS21Q48

Figure 3-1. Serial Port Operation for Read Access (R = 1) Mode 1

ICES = 1 (sample SDI on the falling edge of SCLK)

OCES = 1 (update SDO on rising edge of SCLK)

SCLK

CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SDI

A0

A1

A2

A3

A4

0

B

1

(lsb)

(msb)

READ ACCESS ENABLED

SDO

D0

D1

D2

D3

D4

D5

D6

D7

(lsb)

(msb)

Figure 3-2. Serial Port Operation for Read Access Mode 2

ICES = 1 (sample SDI on the falling edge of SCLK)

OCES = 0 (update SDO on falling edge of SCLK)

SCLK

CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SDI

A0

A1

A2

A3

A4

0

B

1

(lsb)

(msb)

SDO

D0

D1

D2

D3

D4

D5

D6

D7

(msb)

(lsb)

25 of 73

DS2148/DS21Q48

Figure 3-3. Serial Port Operation for Read Access Mode 3

ICES = 0 (sample SDI on the rising edge of SCLK)

OCES = 0 (update SDO on falling edge of SCLK)

SCLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CS

SDI

A0

A1

A2

A3

A4

0

B

1

(lsb)

(msb)

SDO

D0

D1

D2

D3

D4

D5

D6

D7

(lsb)

(msb)

Figure 3-4. Serial Port Operation for Read Access Mode 4

ICES = 0 (sample SDI on the rising edge of SCLK)

OCES = 1 (update SDO on rising edge of SCLK)

SCLK

CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SDI

A0

A1

A2

A3

A4

B

0

1

(lsb)

(msb)

SDO

D0

D1

D2

D3

D4

D5

D6

D7

(lsb)

(msb)

D0

26 of 73

DS2148/DS21Q48

Figure 3-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2

ICES = 1 (sample SDI on the falling edge of SCLK)

SCLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CS

SDI

DO

D6

A0

A1

A2

A3

A4

0

B

D1

D2

D3

D4

D5

D7

(msb)

0

(lsb)

(msb)

(lsb)

WRITE ACCESS ENABLED

SDO

Figure 3-6. Serial Port Operation for Write Access (R = 0) Modes 3 and 4

ICES = 0 (sample SDI on the rising edge of SCLK)

SCLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CS

SDI

DO

D6

A0

A1

A2

A3

A4

0

B

D1

D2

D3

D4

D5

D7

(msb)

0

(lsb)

(msb)

(lsb)

WRITE ACCESS ENABLED

SDO

27 of 73

DS2148/DS21Q48

4 CONTROL REGISTERS

CCR1 (00H): COMMON CONTROL REGISTER 1

(MSB)

(LSB)

ETS

NRZE

RCLA

POSITION

CCR1.7

ECUE

JAMUX

TTOJ

TTOR

LOTCMC

SYMBOL

ETS

DESCRIPTION

E1/T1 Select.

0 = E1

1 = T1

NRZE

CCR1.6

NRZ Enable.

0 = Bipolar data at RPOS/RNEG and TPOS/TNEG

1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a

positive going pulse when device receives a BPV, CV, or EXZ.

See Figure 1-2 and Figure 1-3.

RCLA

ECUE

CCR1.5

CCR1.4

Receive Carrier Loss Alternate Criteria.

0 = RCL declared upon 255 (E1) or 192 (T1) consecutive zeros

1 = RCL declared upon 2048 (E1) or 1544 (T1) consecutive

zeros

Error Counter Update Enable. A 0 to 1-transition forces the

next clock cycle to load the error counter registers with the

latest counts and reset the counters. The user must wait a

minimum of two clocks cycles (976ns for E1 and 1296ns for

T1) before reading the error count registers to allow for a proper

update. See Section 4 and Figure 1-2 for details.

Jitter Attenuator MUX. Controls the source for JACLK. See

Figure 1-1.

JAMUX

CCR1.3

0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at

MCLK)

1 = JACLK sourced from internal PLL (2.048MHz at MCLK)

TCLK to JACLK. Internally connects TCLK to JACLK. See

Figure 1-3.

TTOJ

TTOR

CCR1.2

CCR1.1

CCR1.0

0 = disabled

1 = enabled

TCLK to RCLK. Internally connects TCLK to RCLK. See

Figure 1-3.

0 = disabled

1 = enabled

LOTCMC

Loss Of Transmit Clock Mux Control. Determines whether

the transmit logic should switch to JACLK if the TCLK input

should fail to transition. See Figure 1-3.

0 = do not switch to JACLK if TCLK stops

1 = switch to JACLK if TCLK stops

28 of 73

DS2148/DS21Q48

Table 4-1. MCLK Selection

JAMUX

MCLK

ETS

(CCR1.3)

(CCR1.7)

2.048MHz

1.544MHz

0

1

0

1

CCR2 (01H): COMMON CONTROL REGISTER 2

(MSB)

(LSB)

P25S

N/A

SCLD

POSITION

CCR2.7

CLDS

RHBE

THBE

TCES

RCES

SYMBOL

P25S

DESCRIPTION

Pin 25 Select. Forced to logic 0 in hardware mode.

0 = toggles high during a Receive Carrier Loss condition

1 = toggles high if TCLK does not transition for at least 5µs.

Not Assigned. Should be set to zero when written to.

Short Circuit Limit Disable (ETS = 0). Controls the 50mA

(RMS) current limiter.

-

CCR2.6

CCR2.5

SCLD

0 = enable 50mA current limiter

1 = disable 50mA current limiter

CLDS

CCR2.4

Custom Line Driver Select. Setting this bit to a one will

redefine the operation of the transmit line driver. When this bit

is set to a one and CCR4.5 = CCR4.6 = CCR4.7 = 0, then the

device will generate a square wave at the TTIP and TRING

outputs instead of a normal waveform. When this bit is set to a

one and CCR4.5 = CCR4.6 = CCR4.7 ≠ 0, then the device will

force TTIP and TRING outputs to become open drain drivers

instead of their normal push-pull operation. This bit should be

set to zero for normal operation of the device. Contact the

factory for more details on how to use this bit.

Receive HDB3/B8ZS Enable. See Figure 1-2.

0 = enable HDB3 (E1)/B8ZS (T1)

RHBE

THBE

TCES

CCR2.3

CCR2.2

CCR2.1

1 = disable HDB3 (E1)/B8ZS (T1)

Transmit HDB3/B8ZS Enable. See Figure 1-3.

0 = enable HDB3 (E1)/B8ZS (T1)

1 = disable HDB3 (E1)/B8ZS (T1)

Transmit Clock Edge Select. Selects which TCLK edge to

sample TPOS and TNEG. See Figure 1-3.

0 = sample TPOS and TNEG on falling edge of TCLK

1 = sample TPOS and TNEG on rising edge of TCLK

Receive Clock Edge Select. Selects which RCLK edge to

update RPOS and RNEG. See Figure 1-2.

RCES

CCR2.0

0 = update RPOS and RNEG on rising edge of RCLK

1 = update RPOS and RNEG on falling edge of RCLK

29 of 73

DS2148/DS21Q48

CCR3 (02H): COMMON CONTROL REGISTER 3

(MSB)

(LSB)

TUA1

ATUA1

TAOZ

TPRBSE

TLCE

LIRST

IBPV

IBE

SYMBOL

POSITION

DESCRIPTION

TUA1

CCR3.7

Transmit Unframed All Ones. The polarity of this bit is set such

that the device will transmit an all ones pattern on power-up or

device reset. This bit must be set to a one to allow the device to

transmit data. The transmission of this data pattern is always timed

off of the JACLK (See Figure 1-1).

0 = transmit all ones at TTIP and TRING

1 = transmit data normally

ATUA1

TAOZ

CCR3.6

CCR3.5

Automatic Transmit Unframed All Ones. Automatically transmit

an unframed all ones pattern at TTIP and TRING during a receive

carrier loss (RCL) condition or a receive all ones condition.

0 = disabled

1 = enabled

Transmit Alternate Ones and Zeros. Transmit a …101010…

pattern at TTIP and TRING. The transmission of this data pattern is

always timed off of TCLK (See Figure 1-1).

0 = disabled

1 = enabled

TPRBSE

TLCE

CCR3.4

CCR3.3

Transmit PRBS Enable. Transmit a 2¹⁵- 1 (E1) or a 2²⁰- 1 (T1)

PRBS at TTIP and TRING. See Figure 1-3.

0 = disabled

1 = enabled

Transmit Loop Code Enable. Enables the transmit side to

transmit the loop up code in the Transmit Code Definition registers

(TCD1 and TCD2). See Section 4 and Figure 1-3 for details.

0 = disabled

1 = enabled

LIRST

IBPV

CCR3.2

CCR3.1

Line Interface Reset. Setting this bit from a zero to a one will

initiate an internal reset that resets the clock recovery state machine

and re-centers the jitter attenuator. Normally this bit is only toggled

on power-up. Must be cleared and set again for a subsequent reset.

Insert BPV. A 0 to 1 transition on this bit will cause a single

Bipolar Violation (BPV) to be inserted into the transmit data

stream. Once this bit has been toggled from a 0 to a 1, the device

waits for the next occurrence of three consecutive ones to insert the

BPV. This bit must be cleared and set again for a subsequent error

to be inserted. See Figure 1-3.

IBE

CCR3.0

Insert Bit Error. A 0 to 1 transition on this bit will cause a single

logic error to be inserted into the transmit data stream. This bit

must be cleared and set again for a subsequent error to be inserted.

See Figure 1-3.

30 of 73

DS2148/DS21Q48

4.1 Device Power-Up and Reset

The DS2148 will reset itself upon power-up, setting all writeable registers to 00h and clearing the status

and information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After

the power supplies have settled following power-up, initialize all control registers to the desired settings,

then toggle the LIRST bit (CCR3.2). The DS2148 can be reset at anytime to the default settings by

bringing HRST (pin 29) low (level triggered) or by powering down and powering up again.

CCR4 (03H): COMMON CONTROL REGISTER 4

(MSB)

(LSB)

L2

L1

L0

POSITION

CCR4.7

EGL

JAS

JABDS

DJA

TPD

SYMBOL

L2

DESCRIPTION

Line Build-Out Select Bit 2. Sets the transmitter build out

(Table 7-1 for E1 and Table 7-2 for T1)

Line Build-Out Select Bit 1. Sets the transmitter build out

(Table 7-1 for E1 and Table 7-2 for T1)

Line Build-Out Select Bit 0. Sets the transmitter build out

(Table 7-1 for E1 and Table 7-2 for T1)

Receive Equalizer Gain Limit. This bit controls the sensitivity

of the receive equalizer (Table 4-2).

L1

CCR4.6

L0

CCR4.5

EGL

JAS

CCR4.4

CCR4.3

Jitter Attenuator Select.

0 = place the jitter attenuator on the receive side

1 = place the jitter attenuator on the transmit side

Jitter Attenuator Buffer Depth Select.

0 = 128 bits

JABDS

DJA

CCR4.2

CCR4.1

CCR4.0

1 = 32 bits (use for delay sensitive applications)

Disable Jitter Attenuator.

0 = jitter attenuator enabled

1 = jitter attenuator disabled

TPD

Transmit Power-Down.

0 = normal transmitter operation

1 = powers down the transmitter and tri-states the TTIP and

TRING pins

Table 4-2. Receive Sensitivity Settings

EGL

ETS

(CCR1.7)

0 (E1)

RECEIVE SENSITIVITY

(CCR4.4)

0

1

0

-12dB (short haul)

-43dB (long haul)

-30dB (limited long haul)

-36dB (long haul)

0 (E1)

1 (T1)

31 of 73

DS2148/DS21Q48

CCR5 (04H): COMMON CONTROL REGISTER 5

(MSB)

(LSB)

BPCS1

BPCS0

MM1

MM0

RSCLKE

TSCLKE

RT1

RT0

SYMBOL

POSITION DESCRIPTION

BPCS1

BPCS0

MM1

CCR5.7

CCR5.6

CCR5.5

CCR5.4

CCR5.3

Backplane Clock Select 1. See Table 4-3 for details.

Backplane Clock Select 0. See Table 4-3 for details.

Monitor Mode 1. See Table 4-4.

MM0

Monitor Mode 0. See Table 4-4.

RSCLKE

Receive Synchronization Clock Enable. This control bit determines

whether the line receiver should handle normal T1/E1 signals or a

synchronized signal.

E1 mode:

0 = receive normal E1 signal (Section 6 of G.703)

1 = receive 2.048 MHz synchronization signal (Section 10 of G.703)

T1 mode:

0 = receive normal T1 signal

1 = receive 1.544 MHz synchronization signal

Transmit Synchronization Clock Enable. This control bit determines

whether the transmitter should transmit normal T1/E1 signals or a

synchronized signal.

TSCLKE

CCR5.2

E1 mode:

0 = transmit normal E1 signal (Section 6 of G.703)

1 = transmit 2.048 MHz synchronization signal (Section 10 of G.703)

T1 mode:

0 = transmit normal T1 signal

1 = transmit 1.544 MHz synchronization signal

Receive Termination 1. See Table 4-5 for details.

Receive Termination 0. See Table 4-5 for details.

RT1

RT0

CCR5.1

CCR5.0

Table 4-3. Backplane Clock Select

BPCS1

BPCS0

BPCLK

FREQUENCY

16.384MHz

8.192MHz

(CCR5.7)

(CCR5.6)

0

1

0

1

0

1

4.096MHz

2.048MHz

Table 4-4. Monitor Gain Settings

MM1

MM0

INTERNAL LINEAR GAIN

(CCR5.5)

(CCR5.4)

BOOST (dB)

0

1

0

1

0

1

Normal operation (no boost)

20

26

32

32 of 73

DS2148/DS21Q48

Table 4-5. Internal Rx Termination Select

RT1

RT0

INTERNAL RECEIVE

TERMINATION CONFIGURATION

Internal receive-side termination disabled

Internal receive-side 120Ω enabled

Internal receive-side 100Ω enabled

Internal receive-side 75Ω enabled

(CCR5.1)

(CCR5.0)

0

1

0

1

0

1

CCR6 (05H): COMMON CONTROL REGISTER 6

(MSB)

(LSB)

LLB

RLB

ARLBE

ALB

RJAB

ECRS2

ECRS1

ECRS0

SYMBOL

POSITION

DESCRIPTION

LLB

CCR6.7

Local Loopback. In Local Loopback (LLB), transmit data will be

looped back to the receive path passing through the jitter attenuator if it

is enabled. Data in the transmit path will act as normal. See Figure 1-1

and Section 6.2.2 for details.

0 = loopback disabled

1 = loopback enabled

RLB

CCR6.6

CCR6.5

Remote Loopback. In Remote Loopback (RLB), data output from the

clock/data recovery circuitry will be looped back to the transmit path

passing through the jitter attenuator if it is enabled. Data in the receive

path will act as normal while data presented at TPOS and TNEG will be

ignored. See Figure 1-1 and Section 6.2.1 for details.

0 = loopback disabled

1 = loopback enabled

ARLBE

Automatic Remote Loopback Enable and Reset. When this bit is set

high, the device will automatically go into remote loopback when it

detects loop-up code programmed into the receive loop-up code

definition registers (RUPCD1 and RUPCD2) for a minimum of 5

seconds and it will also set the RIR2.1 status bit. Once in a RLB state, it

will remain in this state until it has detected the loop code programmed

into the receive loop-down code definition registers (RDNCD1 and

RDNCD2) for a minimum of 5 seconds at which point it will force the

device out of RLB and clear RIR2.1. Toggling this bit from a 1 to a 0

can reset the automatic RLB circuitry. The action of the automatic

remote loopback circuitry is logically ORed with the RLB (CCR6.6)

control bit (i.e., either one can cause a RLB to occur).

Analog Loopback. In analog loopback (ALB), signals at TTIP and

TRING will be internally connected to RTIP and RRING. The incoming

signals, from the line, at RTIP and RRING will be ignored. The signals

at TTIP and TRING will be transmitted as normal. See Figure 1-1 and

Section 6.2.3 for more details.

ALB

CCR6.4

0 = loopback disabled

1 = loopback enabled

33 of 73

DS2148/DS21Q48

SYMBOL

POSITION

DESCRIPTION

RJAB

CCR6.3

RCLK Jitter Attenuator Bypass. This control bit allows the recovered

received clock and data to bypass the jitter attenuation while still

allowing the BPCLK output to use the jitter attenuator. See Figure 1-1

and Section 7.1 for details.

0 = disabled

1 = enabled

ECRS2

ECRS1

ECRS0

CCR6.2

CCR6.1

CCR6.0

Error Count Register Select 2. See Section 6.4 for details.

Error Count Register Select 1. See Section 6.4 for details.

Error Count Register Select 0. See Section 6.4 for details.

5 STATUS REGISTERS

There are three registers that contain information on the current real-time status of the device, status

register (SR), and receive information registers 1 and 2 (RIR1/RIR2). When a particular event has

occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. Some of

the bits in SR, RIR1, and RIR2 are latched bits and some are real-time bits. The register descriptions

below list which status bits are latched and which are real-time bits. For latched status bits, when an event

or an alarm occurs the bit is set to a one and will remain set until the user reads that bit. The bit will be

cleared when it is read and it will not be set again until the event has occurred again. Two of the latched

status bits (RUA1 & RCL) will remain set after reading if the alarm is still present.

The user will always precede a read of any of the three status registers with a write. The byte written to

the register will inform the DS2148 which bits the user wishes to read and have cleared. The user will

write a byte to one of these registers with a one in the bit positions to be read and a zero in the other bit

positions. When a one is written to a bit location, that location will be updated with the latest information.

When a zero is written to a bit position, that bit position will not be updated and the previous value will

be held. A write to the status and information registers will be immediately followed by a read of the

same register. The read result should be logically ANDed with the mask byte that was just written and

this value should be written back into the same register to ensure that bit does indeed clear. This second

write step is necessary because the alarms and events in the status registers occur asynchronously with

respect to their access via the parallel port. This write-read-write scheme allows an external

microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the

register. This operation is key in controlling the DS2148 with higher-order software languages.

The bits in the SR register have the unique ability to initiate a hardware interrupt via the INT output pin.

Each of the alarms and events in the SR can be either masked or unmasked from the interrupt pin via the

interrupt mask register (IMR). The interrupts caused by the RCL, RUA1, and LOTC bits in SR act

differently than the interrupts caused by the other status bits in SR. The RCL, RUA1 and LOTC bits will

force the INT pin low whenever they change state (i.e., go active or inactive). The INT pin will be

allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the

interrupt to occur even if the alarm is still present. The other status bits in SR can force the INT pin low

when they are set. The INT pin will be allowed to return high (if no other interrupts are present) when the

user reads the event bit that caused the interrupt to occur.

34 of 73

DS2148/DS21Q48

Table 5-1. Received Alarm Criteria

ALARM

E1/T1

SET CRITERIA

Less than two zeros in two

frames (512 bits)

CLEAR CRITERIA

More than two zeros in two

frames (512 bits)

RUA1

E1

Over a 3ms window, five or less Over a 3ms window, six or more

RUA1

RCL¹

T1

E1

zeros are received

255 (or 2048)²consecutive zeros In 255 bit times, at least 32 ones

received

(G.775)

are received

192 (or 1544)²consecutive zeros 14 or more ones out of 112

are received

possible bit positions are

received starting with the first

one received

RCL¹

T1

NOTES:

1) Receive carrier loss (RCL) is also known as loss-of-signal (LOS) or Red Alarm in T1.

2) See CCR1.5 for details.

SR (06H): STATUS REGISTER

(MSB)

(LSB)

LUP

LDN

LOTC

POSITION

SR.7

RUA1

RCL

TCLE

TOCD

PRBSD

SYMBOL

DESCRIPTION

LUP

Loop Up Code Detected. Set when the loop up code defined in

registers RUPCD1 and RUPCD2 is being received. See Section

4 for details.

(latched)

LDN

SR.6

Loop Down Code Detected. Set when the loop down code

defined in registers RDNCD1 and RDNCD2 is being received.

See Section 4 for details.

(latched)

LOTC

(real time)

RUA1

SR.5

SR.4

SR.3

SR.2

Loss of Transmit Clock. Set when the TCLK pin has not

transitioned for 5µsec (±2µsec). Will force the LOTC pin high.

Receive Unframed All Ones. Set when an unframed all ones

code is received at RRING and RTIP. See Table 5-1 for details.

Receive Carrier Loss. Set when a receive carrier loss condition

exists at RRING and RTIP. See Table 5-1 for details.

Transmit Current Limit Exceeded. Set when the 50mA

(RMS) current limiter is activated whether the current limiter is

enabled or not.

(latched)

RCL

(latched)

TCLE

(real time)

TOCD

(real time)

PRBSD

SR.1

SR.0

Transmit Open Circuit Detect. Set when the device detects

that the TTIP and TRING outputs are open circuited.

PRBS Detect. Set when the receive-side detects a 2¹⁵-1 (E1) or

a 2²⁰-1 (T1) Pseudo Random Bit Sequence (PRBS).

(real time)

35 of 73

DS2148/DS21Q48

IMR (07H): INTERRUPT MASK REGISTER

(MSB)

(LSB)

LUP

LDN

LOTC

POSITION

IMR.7

RUA1

RCL

TCLE

TOCD

PRBSD

SYMBOL

LUP

DESCRIPTION

Loop Up Code Detected.

0 = interrupt masked

1 = interrupt enabled

LDN

LOTC

RUA1

RCL

IMR.6

IMR.5

IMR.4

IMR.3

IMR.2

IMR.1

IMR.0

Loop Down Code Detected.

0 = interrupt masked

1 = interrupt enabled

Loss of Transmit Clock.

0 = interrupt masked

1 = interrupt enabled

Receive Unframed All Ones.

0 = interrupt masked

1 = interrupt enabled

Receive Carrier Loss.

0 = interrupt masked

1 = interrupt enabled

TCLE

TOCD

PRBSD

Transmit Current Limiter Exceeded.

0 = interrupt masked

1 = interrupt enabled

Transmit Open Circuit Detect.

0 = interrupt masked

1 = interrupt enabled

PRBS Detection.

0 = interrupt masked

1 = interrupt enabled

36 of 73

DS2148/DS21Q48

RIR1 (08H): RECEIVE INFORMATION REGISTER 1

(MSB)

(LSB)

ZD

16ZD

HBD

POSITION

RIR1.7

RCLC

RUA1C

JALT

N/A

SYMBOL

DESCRIPTION

ZD

Zero Detect. Set when a string of at least four (ETS = 0) or

eight (ETS = 1) consecutive zeros (regardless of the length of

the string) have been received. Will be cleared when read.

Sixteen Zero Detect. Set when at least 16 consecutive zeros

(regardless of the length of the string) have been received. Will

be cleared when read.

(latched)

16ZD

RIR1.6

RIR1.5

(latched)

HBD

HDB3/B8ZS Word Detect. Set when an HDB3 (ETS = 0) or

B8ZS (ETS = 1) code word is detected independent of whether

the receive HDB3/B8ZS mode (CCR4.6) is enabled. Will be

cleared when read. Useful for automatically setting the line

coding.

(latched)

RCLC

RIR1.4

RIR1.3

RIR1.2

Receive Carrier Loss Clear. Set when the RCL alarm has met

the clear criteria defined in Error! Reference source not

found.. Will be cleared when read.

(latched)

RUA1C

(latched)

Receive Unframed All Ones Clear. Set when the unframed all

ones signal is no longer detected. Will be cleared when read.

See Error! Reference source not found..

JALT

Jitter Attenuator Limit Trip. Set when the jitter attenuator

FIFO reaches to within 4 bits of its useful limit. Will be cleared

when read. Useful for debugging jitter attenuation operation.

Not Assigned. Could be any value when read.

(latched)

N/A

RIR1.1

RIR1.0

Not Assigned. Could be any value when read.

37 of 73

DS2148/DS21Q48

RIR2 (09H): RECEIVE INFORMATION REGISTER 2

(MSB)

(LSB)

RL3

RL2

RL1

POSITION

RIR2.7

RL0

N/A

ARLB

SEC

SYMBOL

DESCRIPTION

RL3

(real time)

RL2

Receive Level Bit 3. See Table 5-2.

Receive Level Bit 2. See Table 5-2.

Receive Level Bit 1. See Table 5-2.

Receive Level Bit 0. See Table 5-2.

RIR2.6

(real time)

RL1

RIR2.5

(real time)

RL0

RIR2.4

(real time)

N/A

RIR2.3

RIR2.2

RIR2.1

Not Assigned. Could be any value when read.

N/A

ARLB

Automatic Remote Loopback Detected. This bit will be set to

a one when the automatic Remote Loopback (RLB) circuitry

has detected the presence of a loop up code for 5 seconds. It

will remain set until the automatic RLB circuitry has detected

the loop down code for 5 seconds. See Section 4 for more

details. This bit will be forced low when the automatic RLB

circuitry is disabled (CCR6.5 = 0).

(real time)

SEC

RIR2.0

One-Second Timer. This bit will be set to a one on one-second

boundaries as timed by the device based on the RCLK. It will

be cleared when read.

(latched)

Table 5-2. Receive Level Indication

RECEIVE LEVEL

(dB)

RL3

RL2

RL1

RL0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

< -2.5

-2.5 to -5.0

-5.0 to -7.5

-7.5 to -10.0

-10.0 to -12.5

-12.5 to -15.0

-15.0 to -17.5

-17.5 to -20.0

-20.0 to -22.5

-22.5 to -25.0

-25.0 to -27.5

-27.5 to -30.0

-30.0 to -32.5

-32.5 to -35.0

-35.0 to -37.5

> -37.5

38 of 73

DS2148/DS21Q48

6 DIAGNOSTICS

6.1 In-Band Loop Code Generation and Detection

The DS2148 can generate and detect a repeating bit pattern that is from one to eight or sixteen bits in

length. To transmit a pattern, the user will load the pattern to be sent into the Transmit Code Definition

(TCD1 and TCD2) registers and select the proper length of the pattern by setting the TC0 and TC1 bits in

the In-Band Code Control (IBCC) register. When generating a 1, 2, 4, 8, or 16 bit pattern both the

transmit code registers (TCD1 and TCD2) must be filled with the proper code. Generation of a 1, 3, 5, or

7-bit pattern only requires TCD1 to be filled. Once this is accomplished, the pattern will be transmitted as

long as the TLCE control bit (CCR3.3) is enabled. As an example, if the user wished to transmit the

standard “loop up” code for Channel Service Units which is a repeating pattern of ...10000100001... then

80h would be loaded into TCD1 and the length would set using TC1 and TC0 in the IBCC register to 5

bits.

The DS2148 can detect two separate repeating patterns to allow for both a loop-up code and a loop-down

code to be detected. The user will program the codes to be detected in the Receive Up Code Definition

(RUPCD1 and RUPCD2) registers and the Receive Down Code Definition (RDNCD1 and RDNCD2)

registers and the length of each pattern will be selected via the IBCC register. The DS2148 will detect

repeating pattern codes with bit error rates as high as 1x10^-2. The code detector has a nominal integration

period of 48ms, hence, after about 48ms of receiving either code, the proper status bit (LUP at SR.7 and

LDN at SR.6) will be set to a one. Normally codes are sent for a period of 5 seconds. It is recommended

that the software poll the DS2148 every 100ms to 1000ms until 5 seconds has elapsed to ensure that the

code is continuously present.

IBCC (0AH): IN–BAND CODE CONTROL REGISTER

(MSB)

(LSB)

TC1

TC0

RUP2

POSITION

IBCC.7

RUP1

RUP0

RDN2

RDN1

RDN0

SYMBOL

TC1

DESCRIPTION

Transmit Code Length Definition Bit 1. See Table 6-1.

Transmit Code Length Definition Bit 0. See Table 6-1.

Receive Up Code Length Definition Bit 2. See Table 6-2.

Receive Up Code Length Definition Bit 1. See Table 6-2.

Receive Up Code Length Definition Bit 0. See Table 6-2.

Receive Down Code Length Definition Bit 2. See Table 6-2.

Receive Down Code Length Definition Bit 1. See Table 6-2.

Receive Down Code Length Definition Bit 0. See Table 6-2.

TC0

IBCC.6

RUP2

RUP1

RUP0

RDN2

RDN1

RDN0

IBCC.5

IBCC.4

IBCC.3

IBCC.2

IBCC.1

IBCC.0

39 of 73

DS2148/DS21Q48

Table 6-1. Transmit Code Length

LENGTH SELECTED

TC1 TC0

(BITS)

0

1

0

1

0

1

5

6/3

7

16/8/4/2/1

Table 6-2. Receive Code Length

LENGTH

RUP2/RDN2 RUP1/RDN1 RUP0/RDN0

SELECTED

(BITS)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

16/8

TCD1 (0BH): TRANSMIT CODE DEFINITION REGISTER 1

(MSB)

(LSB)

C7

C6

C5

POSITION

TCD1.7

TCD1.6

TCD1.5

TCD1.4

TCD1.3

TCD1.2

TCD1.1

TCD1.0

C4

C3

C2

C1

C0

SYMBOL

C7

DESCRIPTION

Transmit Code Definition Bit 7. First bit of the repeating

pattern.

C6

Transmit Code Definition Bit 6.

C5

Transmit Code Definition Bit 5.

Transmit Code Definition Bit 4.

Transmit Code Definition Bit 3.

C4

C3

C2

Transmit Code Definition Bit 2. A Don’t Care if a 5-bit

length is selected.

C1

Transmit Code Definition Bit 1. A Don’t Care if a 5 or 6 bit

length is selected.

C0

Transmit Code Definition Bit 0. A Don’t Care if a 5, 6 or 7

bit length is selected.

40 of 73

DS2148/DS21Q48

TCD2 (0CH): TRANSMIT CODE DEFINITION REGISTER 2

(MSB)

(LSB)

C15

C14

C13

POSITION

TCD2.7

TCD2.6

TCD2.5

TCD2.4

TCD2.3

TCD2.2

TCD2.1

TCD2.0

C12

C11

C10

C9

C8

SYMBOL

C15

DESCRIPTION

Transmit Code Definition Bit 15

Transmit Code Definition Bit 14

Transmit Code Definition Bit 13

Transmit Code Definition Bit 12

Transmit Code Definition Bit 11

Transmit Code Definition Bit 10

Transmit Code Definition Bit 9

Transmit Code Definition Bit 8

C14

C13

C12

C11

C10

C9

C8

RUPCD1 (0DH): RECEIVE UP CODE DEFINITION REGISTER 1

(MSB)

(LSB)

C7

C6

C5

C4

C3

C2

C1

C0

SYMBOL

C7

POSITION

RUPCD1.7

RUPCD1.6

RUPCD1.5

RUPCD1.4

RUPCD1.3

RUPCD1.2

RUPCD1.1

RUPCD1.0

DESCRIPTION

Receive Up Code Definition Bit 7. First bit of the repeating

pattern.

C6

Receive Up Code Definition Bit 6. A Don’t Care if a 1-bit

length is selected.

C5

Receive Up Code Definition Bit 5. A Don’t Care if a 1 or 2

bit length is selected.

C4

Receive Up Code Definition Bit 4. A Don’t Care if a 1 to 3

bit length is selected.

C3

Receive Up Code Definition Bit 3. A Don’t Care if a 1 to 4

bit length is selected.

C2

Receive Up Code Definition Bit 2. A Don’t Care if a 1 to 5

bit length is selected.

C1

Receive Up Code Definition Bit 1. A Don’t Care if a 1 to 6

bit length is selected.

C0

Receive Up Code Definition Bit 0. A Don’t Care if a 1 to 7

bit length is selected.

41 of 73

DS2148/DS21Q48

RUPCD2 (0EH): RECEIVE UP CODE DEFINITION REGISTER 2

(MSB)

(LSB)

C15

C14

C13

POSITION

RUPCD2.7

RUPCD2.6

RUPCD2.5

RUPCD2.4

RUPCD2.3

RUPCD2.2

RUPCD2.1

RUPCD2.0

C12

C11

C10

C9

C8

SYMBOL

C15

DESCRIPTION

Receive Up Code Definition Bit 15

Receive Up Code Definition Bit 14

Receive Up Code Definition Bit 13

Receive Up Code Definition Bit 12

Receive Up Code Definition Bit 11

Receive Up Code Definition Bit 10

Receive Up Code Definition Bit 9

Receive Up Code Definition Bit 8

C14

C13

C12

C11

C10

C9

C8

RDNCD1 (0FH): RECEIVE DOWN CODE DEFINITION REGISTER 1

(MSB)

(LSB)

C7

C6

C5

C4

C3

C2

C1

C0

SYMBOL

C7

POSITION

RDNCD1.7

RDNCD1.6

RDNCD1.5

RDNCD1.4

RDNCD1.3

RDNCD1.2

RDNCD1.1

RDNCD1.0

DESCRIPTION

Receive Down Code Definition Bit 7. First bit of the

repeating pattern.

C6

Receive Down Code Definition Bit 6. A Don’t Care if a 1-bit

length is selected.

C5

Receive Down Code Definition Bit 5. A Don’t Care if a 1 or

2 bit length is selected.

C4

Receive Down Code Definition Bit 4. A Don’t Care if a 1 to 3

bit length is selected.

C3

Receive Down Code Definition Bit 3. A Don’t Care if a 1 to 4

bit length is selected.

C2

Receive Down Code Definition Bit 2. A Don’t Care if a 1 to 5

bit length is selected.

C1

Receive Down Code Definition Bit 1. A Don’t Care if a 1 to 6

bit length is selected.

C0

Receive Down Code Definition Bit 0. A Don’t Care if a 1 to 7

bit length is selected.

42 of 73

DS2148/DS21Q48

RDNCD2 (10H): RECEIVE DOWN CODE DEFINITION REGISTER 2

(MSB)

(LSB)

C15

C14

C13

C12

C11

C10

C9

C8

SYMBOL

C15

C14

C13

C12

C11

C10

C9

POSITION

RDNCD2.7

RDNCD2.6

RDNCD2.5

RDNCD2.4

RDNCD2.3

RDNCD2.2

RDNCD2.1

RDNCD2.0

DESCRIPTION

Receive Down Code Definition Bit 15

Receive Down Code Definition Bit 14

Receive Down Code Definition Bit 13

Receive Down Code Definition Bit 12

Receive Down Code Definition Bit 11

Receive Down Code Definition Bit 10

Receive Down Code Definition Bit 9

Receive Down Code Definition Bit 8

C8

6.2 Loopbacks

6.2.1 Remote Loopback (RLB)

When RLB (CCR6.6) is enabled, the DS2148 is placed into remote loopback. In this loopback, data from

the clock/data recovery state machine will be looped back to the transmit path passing through the jitter

attenuator if it is enabled. The data at the RPOS and RNEG pins will be valid while data presented at

TPOS and TNEG will be ignored (Figure 1-1).

If the Automatic Remote Loopback Enable (CCR6.5) is set to a one, the DS2148 will automatically go

into remote loopback when it detects the loop up code programmed in the Receive Up Code Definition

Registers (RUPCD1 and RUPCD2) for a minimum of 5 seconds. When the DS2148 detects the loop

down code programmed in the Receive Loop Down Code Definition registers (RDNCD1 and RDNCD2)

for a minimum of 5 seconds, the DS2148 will come out of remote loopback. Setting ARLBE to a zero

also can disable the ARLB.

6.2.2 Local Loopback (LLB)

When LLB (CCR6.7) is set to a one, the DS2148 is placed into local loopback. In this loopback, data on

the transmit-side will continue to be transmitted as normal. TCLK and TPOS/TNEG will pass through the

jitter attenuator (if enabled) and be output at RCLK and RPOS/RNEG. Incoming data from the line at

RTIP and RRING will be ignored. If Transmit Unframed All Ones (CCR3.7) is set to a one while in LLB,

TTIP and TRING will transmit all ones while TCLK and TPOS/TNEG will be looped back to RCLK and

RPOS/RNEG (Figure 1-1).

43 of 73

DS2148/DS21Q48

6.2.3 Analog Loopback (ALB)

Setting ALB (CCR6.4) to a one puts the DS2148 in Analog Loopback. Signals at TTIP and TRING will

be internally connected to RTIP and RRING. The incoming signals at RTIP and RRING will be ignored.

The signals at TTIP and TRING will be transmitted as normal. (See Figure 1-1.)

6.2.4 Dual Loopback (DLB)

Setting both CCR6.7 and CCR6.6 to a one, LLB and RLB respectively, puts the DS2148 into dual

loopback operation. The TCLK and TPOS/TNEG signals will be looped back through the jitter attenuator

(if enabled) and output at RCLK and RPOS/RNEG. Clock and data recovered from RTIP and RRING

will be looped back to the transmit-side and output at TTIP and TRING. This mode of operation is not

available when implementing hardware operation. (See Figure 1-1.)

6.3 PRBS Generation and Detection

Setting TPRBSE (CCR3.4) = 1 enables the DS2148 to transmit a 2¹⁵-1 (E1) or a 2²⁰-1 (T1) Pseudo

Random Bit Sequence (PRBS) depending on the ETS bit setting in CCR1.7. The receive-side of the

DS2148 will always search for these PRBS patterns independent of CCR3.4. The PRBS Bit Error Output

(PBEO) will remain high until the receiver has synchronized to one of the two patterns (64 bits received

without an error) at which time PBEO will go low and the PRBSD bit in the status register (SR) will be

set. Once synchronized, any bit errors received will cause a positive going pulse at PBEO, synchronous

with RCLK. This output can be used with external circuitry to keep track of bit error rates during the

PRBS testing. Setting CCR6.0 (ECRS) = 1 will allow the PRBS errors to be accumulated in the 16-bit

counter in registers ECR1 and ECR2. The PRBS synchronizer will remain in sync until it experiences 6

bit errors or more within a 64-bit span. Both PRBS patterns comply with the ITU-T O.151 specifications.

6.4 Error Counter

Error Count Register 1 (ECR1) is the most significant word and ECR2 is the least significant word of a

user-selectable 16-bit counter that records incoming errors including Bipolar Violations (BPV), Code

Violations (CV), Excessive Zero violations (EXZ) and/or PRBS Errors. See Table 6-3 and Table 6-4 and

Figure 1-2 for details.

Table 6-3. Definition of Received Errors

ERROR E1 OR T1

DEFINITION OF RECEIVED ERRORS

Two consecutive marks with the same polarity. Will ignore BPVs due to

HDB3 and B8ZS zero suppression when CCR2.3 = 0. Typically used with

AMI coding (CCR2.3 = 1). ITU-T O.161.

BPV

E1/T1

When HDB3 is enabled (CCR2.3 = 0) and the receiver detects two

consecutive BPVs with the same polarity. ITU-T O.161.

When four or more consecutive zeros are detected.

CV

E1

EXZ

When receiving AMI coded signals (CCR2.3 = 1), detection of 16 or more

zeros or a BPV. ANSI T1.403 1999.

EXZ

T1

When receiving B8ZS coded signals (CCR2.3 = 0), detection of 8 or more

zeros or a BPV. ANSI T1.403 1999.

A bit error in a received PRBS pattern. See Section 6.3 for details.

ITU-T O.151.

PRBS

E1/T1

44 of 73

DS2148/DS21Q48

Table 6-4. Function of ECRS Bits and RNEG Pin

E1 or T1

ECRS2

ECRS1

ECRS0

RHBE

FUNCTION OF ECR

COUNTERS/RNEG¹

(CCR1.7) (CCR6.2) (CCR6.1) (CCR6.0) (CCR2.3)

0

1

X

0

1

0

1

0

1

0

1

0

1

X

0

CVs

BPVs (HDB3 codewords not counted)

CVs + EXZs

1

BPVs + EXZs

X

BPVs (B8ZS codewords not counted)

BPVs + 8 EXZs

0

1

BPVs

1

X

BPVs + 16 EXZs

PRBS Errors²

NOTES:

1) RNEG outputs error data only when in NRZ mode (CCR1.6 = 1).

2) PRBS errors will always be output at PBEO independent of ECR control bits and NRZ mode and will

not be present at RNEG.

6.4.1 Error Counter Update

A transition of the ECUE (CCR1.4) control bit from 0 to 1 will update the ECR registers with the current

values and reset the counters. ECUE must be set back to zero and another 0 to 1 transition must occur for

subsequent reads/resets of the ECR registers. Note that the DS2148 can report errors at RNEG when in

NRZ mode (CCR1.6 = 1) by outputting a pulse for each error occurrence. The counter saturates at 65,535

and will not rollover.

ECR1 (11H): UPPER ERROR COUNT REGISTER 1

ECR2 (12H): LOWER ERROR COUNT REGISTER 2

(MSB)

E15

(LSB)

E8

E0

E14

E6

E13

E5

E12

E4

E11

E3

E10

E2

E9

E1

ECR1

ECR2

E7

SYMBOL

POSITION

DESCRIPTION

E15

E0

ECR1.7

ECR2.0

MSB of the 16-bit error count.

LSB of the 16-bit error count.

6.5 Error Insertion

When IBPV (CCR3.1) is transitioned from a zero to a one, the device waits for the next occurrence of

three consecutive ones to insert a BPV. IBPV must be cleared and set again for another BPV error

insertion. See Figure 1-3 for details on the insertion of the BPV into the datastream.

When IBE (CCR3.0) is transitioned from a zero to a one, the device will insert a logic error. IBE must be

cleared and set again for another logic error insertion. See Figure 1-3 for details on the insertion of the

logic error into the datastream.

45 of 73

DS2148/DS21Q48

7 ANALOG INTERFACE

7.1 Receiver

The DS2148 contains a digital clock recovery system. The DS2148 couples to the receive E1 or T1

twisted pair (or coaxial cable in 75Ω E1 applications) via a 1:1 transformer. See Table 7-3 or transformer

details. Figure 7-1, Figure 7-2, and Figure 7-3 along with Table 7-1 and Table 7-2 show the receive

termination requirements. The DS2148 has the option of using internal termination resistors.

The DS2148 is designed to be fully software-selectable for E1 and T1 without the need to change any

external resistors for the receive-side. The receive-side will allow the user to configure the DS2148 for

75Ω, 100Ω, or 120Ω receive termination by setting the RT1 (CCR5.1) and RT0 (CCR5.0) bits. When

using the internal termination feature, the Rr resistors should be 60Ω each (Figure 7-1). If external

termination is required, RT1 and RT0 should be set to 0 and both Rr resistors in Figure 7-1 will need to

be 37.5Ω, 50Ω, or 60Ω each depending on the line impedance.

The resultant E1 or T1 clock derived from the 2.048/1.544 PLL (JACLK in Figure 1-1) is internally

multiplied by 16 via another internal PLL and fed to the clock recovery system. The clock recovery

system uses the clock from the PLL circuit to form a 16 times oversampler, which is used to recover the

clock and data. This oversampling technique offers outstanding performance to meet jitter tolerance

specifications shown in Figure 7-6.

Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1

AMI/B8ZS waveform presented at the RTIP and RRING inputs. When no signal is present at RTIP and

RRING, a Receive Carrier Loss (RCL) condition will occur and the RCLK will be derived from the

JACLK source (Figure 1-1). If the jitter attenuator is placed in the receive path (as is the case in most

applications), the jitter attenuator restores the RCLK to an approximate 50% duty cycle. If the jitter

attenuator is either placed in the transmit path or is disabled, the RCLK output can exhibit slightly shorter

high cycles of the clock. This is due to the highly oversampled digital clock recovery circuitry. See the

Receive AC Timing Characteristics in Section 10 for more details.

The receive-side circuitry also contains a clock synthesizer, which outputs a user configurable clock (up

to 16.384MHz) synthesized to RCLK at BPCLK (pin 31). See Table 4-3 for details on output clock

frequencies at BPCLK. In hardware mode, BPCLK defaults to a 16.384MHz output.

The DS2148 has a bypass mode for the receive side clock and data. This allows the BPCLK to be derived

from RCLK after the jitter attenuator while the clock and data presented at RCLK, RPOS, and RNEG go

unaltered. This is intended for applications where the receive side jitter attenuation will be done after the

LIU. Setting RJAB (CCR6.3) to a logic 1 will enable the bypass. Be sure that the jitter attenuator is in the

receive path (CCR4.3 = 0). See Figure 1-1 for details.

The DS2148 will report the signal strength at RTIP and RRING in 2.5dB increments via RL3-RL0

located in the Receive Information Register 2. This feature is helpful when trouble shooting line

performance problems. See Table 5-2 for details.

Monitor applications in both E1 and T1 require various flat gain settings for the receive-side circuitry.

The DS2148 can be programmed to support these applications via the Monitor Mode control bits MM1

and MM0. When the monitor modes are enabled, the receiver will tolerate normal line loss up to –6dB.

See Table 4-4 for details.

46 of 73

DS2148/DS21Q48

7.2 Transmitter

The DS2148 uses a set of laser-trimmed delay lines along with a precision digital-to-analog converter

(DAC) to create the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by the

DS2148 meet the latest ETSI, ITU, ANSI, and AT&T specifications. The user will select which

waveform is to be generated by setting the ETS bit (CCR1.7) for E1 or T1 operation, then programming

the L2/L1/L0 bits in Common Control Register 4 for the appropriate application. See Table 7-1 and

Table 7-2 for the proper L2/L1/L0 settings.

A 2.048MHz or 1.544MHz TTL clock is required at TCLK for transmitting data at TPOS and TNEG.

ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs

require an accuracy of ±32ppm for T1 interfaces. The clock can be sourced internally by RCLK or

JACLK. See CCR1.2, CCR1.1, CCR1.0, and Figure 1-3 for details. Because of the nature of the DS2148

transmitter design, very little jitter (less than 0.005UI_P-Pbroadband from 10Hz to 100kHz) is added to the

jitter present on TCLK. Also, the waveforms created are independent of the duty cycle of TCLK. The

transmitter in the DS2148 couples to the E1 or T1 transmit twisted pair (or coaxial cable in some E1

applications) via a 1:1.36 step-up transformer. In order for the device to create the proper waveforms, the

transformer used must meet the specifications listed in Table 7-3.

The DS2148 has automatic short-circuit limiter that limits the source current to 50mA (RMS) into a 1Ω

load. This feature can be disabled by setting the SCLD bit (CCR2.5) = 1. When the current limiter is

activated, TCLE (SR.2) will be set even if short circuit limiter is disabled. The TPD bit (CCR4.0) will

power-down the transmit line driver and tri-state the TTIP and TRING pins. The DS2148 also can detect

when the TTIP or TRING outputs are open-circuited. When an open circuit is detected, TOCD (SR.1)

will be set.

7.3 Jitter Attenuator

The DS2148 contains an on-board jitter attenuator that can be set to a depth of either 32 bits or 128 bits

via the JABDS bit (CCR4.2). In hardware mode the depth is 128 bits and cannot be changed. The 128-bit

mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in

delay sensitive applications. The characteristics of the attenuation are shown in Figure 7-7. The jitter

attenuator can be placed in either the receive path or the transmit path by appropriately setting or clearing

the JAS bit (CCR4.3). Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA

bit (CCR4.1). In order for the jitter attenuator to operate properly, a 2.048MHz or 1.544MHz clock must

be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1.

TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces. There is an onboard PLL for

the jitter attenuator, which will convert the 2.048MHz clock to a 1.544MHz rate for T1 applications.

Setting JAMUX (CCR1.3) to a logic 0 bypasses this PLL. On-board circuitry adjusts either the recovered

clock from the clock/data recovery block or the clock applied at the TCLK pin to create a smooth jitter-

free clock that is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a

gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming

jitter exceeds either 120UI_P-P(buffer depth is 128 bits) or 28UI_P-P(buffer depth is 32 bits), then the

DS2148 will divide the internal nominal 32.768MHz (E1) or 24.704MHz (T1) clock by either 15 or 17

instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17,

it also sets the jitter attenuator limit trip (JALT) bit in the receive information register 1 (RIR1).

47 of 73

DS2148/DS21Q48

7.4 G.703 Synchronization Signal

The DS2148 is capable of receiving a 2.048MHz square-wave synchronization clock as specified in

Section 13 of ITU G.703 (10/98). To use the DS2148 in this mode, set the receive synchronization clock

enable (CCR5.3) = 1. The DS2148 can also transmit the 2.048MHz square-wave synchronization clock as

specified in Section 10 of G.703. To transmit the 2.048MHz clock, set the transmit synchronization clock

enable (CCR5.2) = 1.

Table 7-1. Line Build-Out Select for E1 in Register CCR4 (ETS = 0)

L2

0

L1

0

L0

0

V_DD

5V

APPLICATION

N

RETURN LOSS

N.M.

Rt

0Ω

1:1.36

75Ω normal

0

1

N.M.

120Ω normal

0Ω

1

0

21dB

75Ω w/ high return loss

120Ω w/ high return loss

18Ω

27Ω

1

0

1

21dB

N.M. = Not meaningful

Note: See Figure 7-1, Figure 7-2, and Figure 7-3.

Table 7-2. Line Build-Out Select for T1 in Register CCR4 (ETS = 1)

L2

L1

L0

V_DD

APPLICATION

DSX-1 (0 to 133 feet) /

0dB CSU

N

RETURN LOSS

Rt

0

5V

1:1.36

N.M.

0Ω

DSX-1 (133 to 266 feet)

DSX-1 (266 to 399 feet)

DSX-1 (399 to 533 feet)

DSX-1 (533 to 655 feet)

-7.5dB CSU

0

1

0

1

0

1

0

1

0

1

0

1

5V

1:1.36

N.M.

0Ω

-15dB CSU

-22.5dB CSU

N.M. = Not meaningful

Note: See Figure 7-1, Figure 7-2, and Figure 7-3..

Table 7-3. Transformer Specifications for 5V Operation

SPECIFICATION

Turns Ratio 5V Applications

Primary Inductance

RECOMMENDED VALUE

1:1(receive) and 1:1.36(transmit) ±2%

600µH minimum

1.0µH maximum

40pF maximum

Leakage Inductance

Interwinding Capacitance

Transmit Transformer DC Resistance

Primary (Device Side)

1.2Ω maximum

Secondary

Receive Transformer DC Resistance

Primary (Device Side)

Secondary

1.2Ω maximum

48 of 73

DS2148/DS21Q48

Figure 7-1. Basic Interface

+V_DD

DS2148

Rt

0.1µF

TTIP

V_DD(21)

_SS(22)

0.47µF

(non

Transmit

Line

V

10µF

0.01µF

0.1µF

polarized)

TRING

N:1

V_DD(36)

_SS(35)

(larger winding

toward the network)

V

10µF

2.048MHz

MCLK

RTIP

(this clock can also

be 1.544MHz for T1

only applications)

Receive

Line

RRING

1:1

Rr

0.1µF

NOTES:

1) All resistor values are ±1%.

2) In E1 applications, the Rt resistors are used to increase the transmitter return loss (Table 7-1). No return loss is required for T1

applications.

3) The Rr resistors should be set to 60Ω each if the internal receive-side termination feature is enabled. When this feature is disabled, Rr

= 37.5Ω for 75Ω, 60Ω for 120Ω E1 systems, or 50Ω for 100Ω T1 lines.

4) See Table 7-1 and Table 7-2 for the appropriate transmit transformer turns ratio (N).

49 of 73

DS2148/DS21Q48

Figure 7-2. Protected Interface Using Internal Receive Termination

+VDD

D2

D1

+VDD

DS2148

(optional)

Rp

Fuse

Rt

0.1uF

TTIP

VDD (21)

VSS (22)

0.47uF

Transmit

Line

S

(non-

C1

10uF

0.01uF

polarized)

68uF

TRING

VDD (36)

VSS (35)

Fuse

Rp

0.1uF

10uF

N:1

D3

D4

(larger winding

toward the network)

+VDD

D6

D5

Rp

Fuse

MCLK

2.048MHz

RTIP

(this clock can also

be 1.544MHz for T1

only applications)

Receive

Line

S

C2

RRING

Rp

1:1

(optional)

D8

D7

60

0.1uF

NOTES:

1) All resistor values are ±1%.

2) C1 = C2 = 0.1µF.

3) S is a 6V transient suppresser.

4) D1 to D8 are Schottky diodes.

5) The fuses are optional to prevent AC power line crosses from compromising the transformers.

6) Rp resistors exist to keep the Fuses from opening during a surge. If they are used, then the 60Ω receive termination resistance must

be adjusted to match the line impedance.

7) The Rt resistors are used to increase the transmitter return loss (Table 7-1). No return loss is required for T1 applications.

8) The transmit transformer turns ratio (N) would be 1:1.36 for 5V operation.

9) The 68µF is used to keep the local power plane potential within tolerance during a surge.

50 of 73

DS2148/DS21Q48

Figure 7-3. Protected Interface Using External Receive Termination

+V_DD

D2

D1

DS2148

+V_DD

(optional)

Rp

Fuse

Rt

0.1µF

TTIP

V_DD(21)

_SS(22)

0.47µF

Transmit

Line

S

(non-

V

C1

10µF

0.1µF

0.01µF

polarized)

68µF

TRING

V_DD(36)

_SS(35)

Fuse

Rp

N:1

D3

D4

V

(larger winding

10µF

toward the network)

Rp

Fuse

470

MCLK

2.048MHz

RTIP

(this clock can also

be 1.544MHz for T1

only applications)

Receive

Line

RRING

Rp

1:1

(optional)

Rr

0.1µF

NOTES:

1) All resistor values are ±1%.

2) C1 = 0.1µF.

3) S is a 6V transient suppresser.

4) D1 to D4 are Schottky diodes.

5) The fuses are optional to prevent AC power line crosses from compromising the transformers.

6) Rp resistors exist to keep the Fuses from opening during a surge. If they are used, then Rr must be adjusted to match the line

impedance.

7) Rr = 37.5Ω for 75Ω, 60Ω for 120Ω E1 systems, or 50Ω for 100Ω T1 lines.

8) The Rt resistors are used to increase the transmitter return loss (Table 7-1). No return loss is required for T1 applications.

9) The transmit transformer turns ratio (N) would be 1:1.36 for 5V operation.

10) The 68µF is used to keep the local power plane potential within tolerance during a surge.

51 of 73

DS2148/DS21Q48

Figure 7-4. E1 Transmit Pulse Template

1.2

1.1

1.0

0.9

0.8

0.7

269ns

G.703

Template

194ns

0.6

0.5

219ns

0.4

0.3

0.2

0.1

0

-0.1

-0.2

-250

-200

-150

-100

-50

0

50

100

150

200

250

TIME (ns)

52 of 73

DS2148/DS21Q48

Figure 7-5. T1 Transmit Pulse Template

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

MAXIMUM CURVE

UI Time Amp.

MINIMUM CURVE

UI Time Amp.

-0.77 -500 0.05

-0.39 -255 0.05

-0.27 -175 0.80

-0.27 -175 1.15

-0.77 -500 -0.05

-0.23 -150 -0.05

-0.23 -150 0.50

-0.15 -100 0.95

-0.12 -75

1.15

1.05

-0.07

0.05

0.00

0

0.95

0.00

0

0.15 100

0.23 150

0.46 300

0.66 430

0.93 600

1.16 750

0.90

0.27 175

0.35 225

0.93 600

1.16 750

0.50

-0.45

-0.20

-0.05

-0.1

T1.102/87, T1.403,

-0.2

-0.3

-0.4

-0.5

CB 119 (Oct. 79), &

I.431 Template

-500 -400 -300 -200 -100

0

100 200 300 400 500 600 700

TIME (ns)

53 of 73

DS2148/DS21Q48

Figure 7-6. Jitter Tolerance

1K

100

DS2148

TR 62411 (Dec. 90)

Tolerance

10

1

ITU-T G.823

0.1

1

10

100

1K

10K

100K

FREQUENCY (Hz)

Figure 7-7. Jitter Attenuation

0dB

ITU G.7XX

Prohibited Area

TBR12

Prohibited

Area

-20dB

-40dB

-60dB

E1

T1

TR 62411 (Dec. 90)

Prohibited Area

1

10

100

1K

10K

100K

FREQUENCY (Hz)

54 of 73

DS2148/DS21Q48

8 DS21Q48 QUAD LIU

The DS21Q48 is a quad version of the DS2148G utilizing CSBGA on carrier packaging technology. The

four LIUs are controlled via the parallel port mode. Serial and hardware modes are unavailable in this

package.

Table 8-1. DS21Q48 Pin Assignment

DS21Q48

PIN#

J1

PARALLEL PORT

MODE

Connect to V_SS

RD(DS)

WR(R/W)

ALE(AS)

A4

I/O

I

K3

J2

I

H1

I

K2

I

K1

I/O

I

L1

A3

H11

H12

G12

J10

H10

G11

J9

I

A2

I

A1

I

A0

I/O

I

D7/AD7

D6/AD6

D5/AD5

D4/AD4

D3/AD3

D2/AD2

D1/AD1

D0/AD0

VSM

E3

D4

F3

D5

G4

INT

K9

I/O

I

K7

TEST

HRST

L9

I

J6

I

MCLK

BIS0

L7

I

M8

M12

J3

I

BIS1

I

PBTS

CS1

I

CS2

CS3

CS4

D3

I

D10

K10

K5

I

O

PBEO1

PBEO2

PBEO3

PBEO4

RCL/LOTC1

RCL/LOTC2

RCL/LOTC3

G3

E10

K8

L6

D7

F9

55 of 73

DS2148/DS21Q48

DS21Q48

PIN#

J7

PARALLEL PORT

MODE

RCL/LOTC4

RTIP1

I/O

O

I

A1

A4

I

RTIP2

A7

I

RTIP3

RTIP4

A10

B2

I

RRING1

RRING2

RRING3

RRING4

BPCLK1

BPCLK2

BPCLK3

BPCLK4

TTIP1

B5

I

B8

I

B11

H4

I

O

I

D6

F10

L8

A2

A5

TTIP2

A8

TTIP3

A11

B3

TTIP4

TRING1

TRING2

TRING3

TRING4

RPOS1

B6

B9

B12

K4

E1

RPOS2

D11

K11

G2

RPOS3

RPOS4

RNEG1

RNEG2

RNEG3

RNEG4

RCLK1

RCLK2

RCLK3

RCLK4

TPOS1

E2

F11

M10

H3

F1

E11

L11

G1

F2

I

TPOS2

E12

M11

H2

I

TPOS3

I

TPOS4

I

TNEG1

TNEG2

TNEG3

TNEG4

TCLK1

TCLK2

TCLK3

M1

D12

K12

M2

L2

I

F12

I

56 of 73

DS2148/DS21Q48

DS21Q48

PIN#

L12

J5

PARALLEL PORT

MODE

TCLK4

V_DD1

I/O

I

-

D2

V_DD2

G9

V_DD3

M9

L5

V_DD4

V_DD1

E4

V_DD2

D8

V_DD3

J8

V_DD4

J4

V_SS1

D1

V_SS2

E9

V_SS3

L10

M4

F4

V_SS4

V_SS1

V_SS2

D9

H9

V_SS3

V_SS4

57 of 73

DS2148/DS21Q48

Figure 8-1. 144-Pin CSBGA (17mm x 17mm) Pinout

1

2

3

4

5

6

7

8

9

10

11

12

A

B

C

D

E

F

RTIP

1

TTIP

1

NC

RTIP

2

TTIP

2

NC

RTIP

3

TTIP

3

NC

RTIP

4

TTIP

4

NC

RRING TRING

NC

RRING TRING

NC

RRING TRING

NC

RRING TRING

1

2

3

4

NC

VSS

2

VDD

2

D2/

D0/ BPCLK RCL/

VDD

3

VSS

3

RPOS TNEG

CS2

CS3

AD2

AD0

2

LOTC2

3

RPOS RNEG

D3/

VDD

2

NC

VSS

3

PEBO RCLK TPOS

2

AD3

3

RCLK TPOS

D1/

VSS

2

NC

RCL/ BPCLK RNEG TCLK

2

AD1

LOTC3

3

G

H

J

TPOS RNEG PEBO VSM

VDD

3

NC

D5/

A0

1

2

AD5

TNEG RCLK BPCLK

VSS

4

D6/

A2

A1

WR

(R/W)

1

AD6

See

VSS

1

VDD MCLK RCL/

LOTC4

VDD

4

D4/

D7/

NC

RD

(DS)

CS1

Note 2

1

AD4

AD7

K

L

A4

ALE

See

RPOS PEBO

NC

TEST PEBO

4

RPOS TNEG

INT

CS4

(AS) Note 2

1

4

A3

TCLK

2

NC

VDD

1

RCL/

BIS0 BPCLK

4

VSS

4

RCLK TCLK

HRST

LOTC1

4

M

TNEG TCLK

VSS

1

NC

BIS1

VDD RNEG TPOS PBTS

2

1

4

NOTES:

1) Shaded areas are signals common to all four devices.

2) Connect to V_SS.

58 of 73

DS2148/DS21Q48

9 DC CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS*

Voltage Range on Any Pin Relative to Ground……………………………………………..-1.0V to +6.0V

Operating Temperature Range for DS2148TN……………………………………………..-40°C to +85°C

Storage Temperature Range……………………………………………………………….-55°C to +125°C

Soldering Temperature………………………………………….See IPC/JEDEC J-STD-020 Specification

* This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect device

reliability.

Table 9-1. Recommended DC Operating Conditions

(T_A= -40°C to +85°C)

PARAMETER

SYMBOL

V_IH

MIN

2.0

TYP

MAX

5.5

UNITS

NOTES

Logic 1

V

Logic 0

V_IL

–0.3

4.75

+0.8

5.25

Supply for 5V Operation

V_DD

5

1

Table 9-2. Capacitance

(T_A= +25°C)

PARAMETER

Input Capacitance

Output Capacitance

SYMBOL

C_IN

MIN

TYP

MAX

UNITS

pF

NOTES

5

7

C_OUT

pF

Table 9-3. DC Characteristics

(V_DD= 5.0V ±5%, T_A= -40°C to +85°C.)

PARAMETER

SYMBOL

MIN

TYP

MAX

+1.0

1.0

UNITS

µA

NOTES

Input Leakage

I_IL

I_LO

I_OH

I_OL

I_DD

–1.0

3

4

Output Leakage

µA

Output Current (2.4V)

Output Current (0.4V)

Supply Current

–1.0

+4.0

-

mA

95

125

mA

2, 5

NOTES:

1) Applies to V_DD.

2) TCLK = MCLK = 2.048MHz.

3) 0.0V < V_IN< V_DD.

4) Applied to INT when tri-stated.

5) Power dissipation with TTIP and TRING driving a 30Ω load, for an all-ones data density.

59 of 73

DS2148/DS21Q48

9.1 THERMAL CHARACTERISTICS

Table 9-4. Thermal Characteristics—DS21Q48 CSBGA Package

PARAMETER

Ambient Temperature

Junction Temperature

Theta-JA (θ_JA) in Still Air

Theta-JC (θ_JC) in Still Air

MIN

TYP

MAX

NOTES

-40ºC

-

+85ºC

1

-

+125ºC

+24ºC/W

+4.1ºC/W

-

2

3

NOTES:

1) The package is mounted on a four-layer JEDEC-standard test board.

2) Theta-JA (θ_JA) is the junction to ambient thermal resistance, when the package is mounted on a four-

layer JEDEC-standard test board.

3) While Theta-JC (θ_JC) is commonly used as the thermal parameter that provides a correlation between the

junction temperature (T_j) and the average temperature on top center of four of the chip-scale BGA

packages (T_C), the proper term is Psi-JT. It is defined by:

(T_J- T_C) / overall package power

The method of measurement of the thermal parameters is defined in EIA/JEDEC-standard document

EIA-JESD51-2.

Table 9-5. Theta-JA (θ_JA) vs. Airflow

FORCED AIR (m/s)

THETA-JA (θ_JA)

24ºC/W

0

1

21ºC/W

2.5

19ºC/W

60 of 73

DS2148/DS21Q48

10 AC CHARACTERISTICS

Table 10-1. AC Characteristics—Multiplexed Parallel Port

(BIS1 = 0, BIS0 = 0)

(V_DD= 5.0V ±5%, T_A= -40°C to +85°C.) (See Figure 10-1, Figure 10-2, and Figure 10-3.)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Cycle Time

t_CYC

200

ns

Pulse Width, DS Low or RD

High

PW_EL

100

ns

Pulse Width, DS High or RD

Low

PW_EH

100

ns

Input Rise/Fall times

R/W Hold Time

t_R, t_F

t_RWH

20

ns

10

50

R/W Setup Time Before DS

High

t_RWS

ns

CS Setup Time Before DS,

WR or RD Active

t_CS

20

ns

CS Hold Time

t_CH

t_DHR

t_DHW

t_ASL

t_AHL

0

10

0

ns

Read Data Hold Time

Write Data Hold Time

Muxed Address Valid to AS

or ALE Fall

50

80

15

10

20

30

10

ns

Muxed Address Hold Time

Delay Time DS, WR or RD to

AS or ALE Rise

Pulse Width AS or ALE High

Delay Time, AS or ALE to

DS, WR or RD

Output Data Delay Time

From DS or RD

Data Setup Time

t_ASD

PW_ASH

t_ASED

t_DDR

t_DSW

20

50

ns

61 of 73

DS2148/DS21Q48

Figure 10-1. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 0)

t

CYC

ALE

PW

ASH

t

ASD

WR*

RD*

t

ASED

t

ASD

PW

EH

t

CH

PW

CS

EL

CS*

t

ASL

t

DHR

DDR

AD0-AD7

t

AHL

Figure 10-2. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 0)

t

CYC

ALE

PW

ASH

t

ASD

RD*

WR*

t

ASED

ASD

PW

EH

t

CH

PW

EL

CS

CS*

t

ASL

DHW

AD0-AD7

t

AHL

DSW

62 of 73

DS2148/DS21Q48

Figure 10-3. Motorola Bus Timing (PBTS = 1, BIS1 = 0, BIS0 = 0)

PW

ASH

AS

PW

EH

t

ASED

ASD

DS

PW

EL

t

CYC

t

RWS

RWH

R/W*

t

DDR

t

ASL

DHR

AD0-AD7

(read)

t

AHL

t

CH

CS

CS*

t

DSW

t

ASL

t

AD0-AD7

(write)

t

DHW

AHL

63 of 73

DS2148/DS21Q48

Table 10-2. AC Characteristics—Nonmultiplexed Parallel Port

(BIS1 = 0, BIS0 = 1)

(V_DD= 5.0V ±5%, T_A= -40°C to +85°C.) (See Figure 10-4, Figure 10-5, Figure 10-6, and

Figure 10-7.)

PARAMETER

Setup Time for A0 to A4, Valid

to CS Active

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

t1

0

ns

Setup Time for CS Active to

Either RD, WR, or DS Active

Delay Time From Either RD or

DS Active to Data Valid

Hold Time From Either RD,

WR, or DS Inactive to CS

Inactive

t2

t3

0

ns

75

20

t4

0

ns

Hold Time From CS Inactive to

Data Bus tri-state

t5

t6

t7

t8

t9

5

ns

Wait Time From Either WR or

DS Active to Latch Data

Data Setup Time To Either WR

or DS Inactive

Data Hold Time From Either

WR or DS Inactive

Address Hold From Either WR

or DS Inactive

75

10

64 of 73

DS2148/DS21Q48

Figure 10-4. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 1)

A0 to A4

D0 to D7

Address Valid

Data Valid

t5

5ns min. / 20ns max.

WR*

CS*

RD*

t1

0ns min.

0ns min. t2

t3

t4

0ns min.

75ns max.

Figure 10-5. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 1)

A0 to A4

D0 to D7

RD*

Address Valid

t7

10ns

min.

t8

10ns

min.

t1

0ns min.

t2

CS*

t6

t4

0ns min.

75ns min.

WR*

65 of 73

DS2148/DS21Q48

Figure 10-6. Motorola Bus Read Timing (PBTS = 1, BIS1 = 0, BIS0 = 1)

A0 to A4

D0 to D7

R/W*

Address Valid

Data Valid

5ns min. / 20ns max.

t5

t1

0ns min.

t2

CS*

t3

t4

0ns min.

75ns max.

DS*

Figure 10-7. Motorola Bus Write Timing (PBTS = 1, BIS1 = 0, BIS0 = 1)

A0 to A4

D0 to D7

R/W*

Address Valid

10ns

min.

10ns

min.

t8

t7

t1

0ns min.

t2

CS*

t6

t4

0ns min.

75ns min.

DS*

66 of 73

DS2148/DS21Q48

Table 10-3. AC Characteristics—Serial Port (BIS1 = 1, BIS0 = 0)

(V_DD= 5.0V ±5%, T_A= -40°C to +85°C.) (See Figure 10-8)

PARAMETER

Setup Time CS to SCLK

Setup Time SDI to SCLK

Hold Time SCLK to SDI

SCLK High/Low Time

SCLK Rise/Fall Time

SCLK to CS Inactive

CS Inactive Time

SYMBOL

t_CSS

MIN

50

TYP

MAX

UNITS

ns

NOTES

t_SSS

50

ns

t_SSH

50

ns

t_SLH

200

ns

t_SRF

50

ns

t_LSC

50

250

ns

t_CM

ns

SCLK to SDO Valid

t_SSV

ns

SCLK to SDO Tri-state

CS Inactive to SDO Tri-state

t_SSH

100

ns

t_CSH

ns

Figure 10-8. Serial Bus Timing (BIS1 = 1, BIS0 = 0)

t_CM

CS*

t_LSC

t_SRF

t_SLH

t_CSS

1

SCLK

2

SCLK

SDI

t_SSS

LSB

t_SSH

t_CSH

MSB

LSB

MSB

t_SSH

t_SSV

HIGH Z

MSB

HIGH Z

SDO

NOTE 1: OCES =1 AND ICES = 0.

NOTE 2: OCES = 0 AND ICES = 1.

67 of 73

DS2148/DS21Q48

Table 10-4. AC Characteristics—Receive Side

(V_DD= 5.0V ±5%, T_A= -40°C to +85°C.) (See Figure 10-9)

PARAMETER

SYMBOL

MIN

TYP

488

648

MAX

UNITS NOTES

ns

1

RCLK Period

t_CP

ns

2

3

4

t_CH

t_CL

t_CH

t_CL

200

150

RCLK Pulse Width

ns

4

Delay RCLK to RPOS, RNEG,

PBEO, RBPV Valid

t_DD

50

ns

NOTES:

1) E1 Mode.

2) T1 or J1 Mode.

3) Jitter attenuator enabled in the receive path.

4) Jitter attenuator disabled or enabled in the transmit path.

Figure 10-9. Receive Side Timing

1

RCLK

t

CL

CH

2

RCLK

t

CP

t

DD

RPOS, RNEG

PBEO

bit

PRBS Detector Out of Sync

error

t

DD

BPV/

EXZ/

CV

3

BPV/

EXZ/

CV

RNEG

NOTE 1: RCES = 1 (CCR2.0) OR CES = 1.

NOTE 2: RCES = 0 (CCR2.0) OR CES = 0.

NOTE 3: RNEG IS IN NRZ MODE (CCR1.6 = 1).

68 of 73

DS2148/DS21Q48

Table 10-5. AC Characteristics—Transmit Side

(V_DD= 5.0V ±5%, T_A= -40°C to +85°C.) (See Figure 10-10.)

PARAMETER

SYMBOL

MIN

TYP

488

MAX

UNITS NOTES

ns

1

2

TCLK Period

t_CP

648

t_CH

t_CL

75

TCLK Pulse Width

TPOS/TNEG Setup to TCLK

Falling or Rising

t_SU

20

ns

TPOS/TNEG Hold From TCLK

Falling or Rising

t_HD

20

ns

TCLK Rise and Fall Times

t_R, t_F

25

NOTES:

1) E1 Mode.

2) T1 or J1 Mode.

Figure 10-10. Transmit Side Timing

t

CP

t

CL

CH

t

R

F

1

TCLK

2

TCLK

t

SU

t

TPOS, TNEG

HD

NOTE 1: TCES = 0 (CCR2.1) OR CES = 0.

NOTE 2: TCES = 1 (CCR2.1) OR CES = 1.

69 of 73

DS2148/DS21Q48

11 PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for

each package is a link to the latest package outline information.)

11.1 44-Pin TQFP (56-G4012-001)

SUGGESTED PAD LAYOUT

44 PIN TQFP, 10*10*1.0

SEE DETAIL "A"

DIMENSIONS ARE IN MILLIMETERS

70 of 73

DS2148/DS21Q48

11.2 49-Ball CSGBA (7mm x 7mm) (56-G6006-001)

71 of 73

DS2148/DS21Q48

11.3 144-Ball CSBGA (17mm x 17mm) (56-G6011-001)

A1 CORNER

3

A1 CORNER

12 11 10

9

8

7

6

5

4

3

2 1

1.27

13.97

0.20

1.52

Y

X

4

1.27

13.97

17.00

1.52

DETAIL A

TOP VIEW (DIE SIDE)

BOTTOM VIEW (BALL SIDE)

2.60

REF

1.99

0.59

0.76

0.61

Z

DETAIL B

SIDE VIEW

72 of 73

DS2148/DS21Q48

SOLDER BALL

φ 0.76 REF

L

X

Z

Y

Z

φ 0.76

DETAIL A

0.05 LABEL THICKNESS

0.24

Z

/ /

2.60

REF

0.17

Z

/ /

0.10

SEATING PLANE

2

Z

0.76

REF

DETAIL B

73 of 73

Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.

No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.


型号：	DS2148TN+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	5V E1/T1/J1 Line Interface Unit PC 电信电信集成电路
文件：	总73页 (文件大小：1129K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS2148TN+ [MAXIM]

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