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DS1856E-002R [MAXIM]

Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection; 双路，温控电阻，内置校准监视器和密码保护
DS1856E-002R
型号： DS1856E-002R
厂家： MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述：

Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
双路，温控电阻，内置校准监视器和密码保护

监视器
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Rev 1; 4/05  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
General Description  
Features  
♦ SFF-8472 Compatible  
The DS1856 dual, temperature-controlled, nonvolatile  
(NV) variable resistors with three monitors consists of  
two 256-position, linear, variable resistors; three analog  
monitor inputs (MON1, MON2, MON3); and a direct-to-  
digital temperature sensor. The device provides an  
ideal method for setting and temperature-compensating  
bias voltages and currents in control applications using  
minimal circuitry. The variable resistor settings are  
stored in EEPROM memory and can be accessed over  
the 2-wire serial bus.  
♦ Five Monitored Channels (Temperature, V  
,
CC  
MON1, MON2, MON3)  
♦ Three External Analog Inputs (MON1, MON2, MON3)  
That Support Internal and External Calibration  
♦ Scalable Dynamic Range for External Analog Inputs  
♦ Internal Direct-to-Digital Temperature Sensor  
♦ Alarm and Warning Flags for All Monitored  
Channels  
♦ Two Linear, 256-Position, Nonvolatile Temperature-  
Controlled Variable Resistors  
♦ Resistor Settings Changeable Every 2°C  
♦ Three Levels of Security  
♦ Access to Monitoring and ID Information  
Configurable with Separate Device Addresses  
♦ 2-Wire Serial Interface  
♦ Two Buffers with TTL/CMOS-Compatible Inputs and  
Open-Drain Outputs  
♦ Operates from a 3.3V or 5V Supply  
♦ -40°C to +95°C Operating Temperature Range  
Relative to other members of the family, the DS1856 is  
essentially a DS1859 with a DS1852-friendly memory  
map. In particular, the DS1856 can be configured so  
the 128 bytes of internal Auxiliary EEPROM memory is  
mapped into Main Device Table 00h and Table 01h,  
maintaining compatibility between both the  
DS1858/DS1859 and the DS1852. The DS1856 also  
features password protection equivalent to the DS1852,  
further enhancing compatibility between the two.  
Applications  
Optical Transceivers  
Ordering Information  
Optical Transponders  
Instrumentation and Industrial Controls  
RF Power Amps  
RES0/RES1  
PART  
RESISTANCE  
PIN-PACKAGE  
(kΩ)  
Diagnostic Monitoring  
DS1856E-050  
50/50  
50/50  
50/50  
16 TSSOP  
DS1856E-050/T&R  
DS1856B-050  
16 TSSOP  
16-Ball CSBGA  
Typical Operating Circuit  
Ordering Information continued at end of data sheet.  
+Denotes lead free.  
*Future product—contact factory for availability.  
T&R denotes tape-and-reel.  
V
CC  
V
CC  
= 3.3V  
All parts operate at the -40°C to +95°C temperature range.  
4.7kΩ  
2-WIRE  
4.7kΩ  
DECOUPLING  
CAPACITOR  
0.1µF  
Pin Configurations  
16  
1
V
CC  
SDA  
15  
14  
2
TO LASER BIAS  
CONTROL  
TOP VIEW  
H1  
L1  
INTERFACE  
SCL  
OUT1  
IN1  
SDA  
1
2
3
4
5
6
7
8
16 V  
CC  
3
4
A
B
C
D
V
IN1  
SCL  
SDA  
IN2  
H1  
L1  
CC  
TO LASER  
MODULATION  
CONTROL  
13  
12  
SCL  
OUT1  
IN1  
15 H1  
Tx-FAULT  
H0  
L0  
14 L1  
5
6
OUT2  
H0  
DS1856  
OUT2  
13 H0  
LOS  
DS1856  
11  
10  
9
Rx POWER*  
IN2  
MON3  
MON2  
MON1  
OUT2  
IN2  
12 L0  
N.C.  
OUT1  
MON3  
7
8
Tx POWER*  
Tx BIAS*  
DIAGNOSTIC  
INPUTS  
N.C.  
GND  
11 MON3  
10 MON2  
N.C.  
GND  
GND  
1
L0  
2
MON1  
3
MON2  
4
9
MON1  
*SATISFIES SFF-8472 COMPATIBILITY  
CSBGA (4mm x 4mm)  
1.0mm PITCH  
TSSOP  
______________________________________________ Maxim Integrated Products  
1
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
ABSOLUTE MAXIMUM RATINGS  
Voltage Range on V  
Voltage Range on Inputs Relative  
to Ground*..............................................-0.5V to (V  
Voltage Range on Resistor Inputs Relative  
to Ground*..............................................-0.5V to (V  
Relative to Ground ...........-0.5V to +6.0V  
Operating Temperature Range ...........................-40°C to +95°C  
Programming Temperature Range.........................0°C to +70°C  
Storage Temperature Range.............................-55°C to +125°C  
Soldering Temperature .......................................See IPC/JEDEC  
J-STD-020A  
CC  
+ 0.5V)  
CC  
+ 0.5V)  
CC  
Current into Resistors............................................................5mA  
*Not to exceed 6.0V.  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS  
(T = -40°C to +95°C, unless otherwise noted.)  
A
PARAMETER  
Supply Voltage  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
V
(Note 1)  
(Note 2)  
(Note 2)  
2.85  
5.50  
V
V
CC  
Input Logic 1 (SDA, SCL)  
Input Logic 0 (SDA, SCL)  
Resistor Inputs (L0, L1, H0, H1)  
Resistor Current  
V
0.7 x Vcc  
-0.3  
V
+ 0.3  
CC  
IH  
V
+0.3 x V  
V
IL  
CC  
-0.3  
V
+ 0.3  
+3  
V
CC  
I
-3  
mA  
µA  
RES  
High-Impedance Resistor Current  
I
0.001  
0.1  
ROFF  
Input logic 1  
Input logic 0  
1.6  
Input Logic Levels (IN1, IN2)  
V
0.9  
DC ELECTRICAL CHARACTERISTICS  
(V  
CC  
= 2.85V to 5.5V, T = -40°C to +95°C, unless otherwise noted.)  
A
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Supply Current  
Input Leakage  
I
(Note 3)  
1
2
mA  
CC  
I
-200  
+200  
0.4  
nA  
IL  
V
V
3mA sink current  
6mA sink current  
0
0
OL1  
OL2  
Low-Level Output Voltage  
(SDA, OUT1, OUT2)  
V
0.6  
Full-Scale Input (MON1, MON2,  
MON3)  
At factory setting  
(Note 4)  
2.4875  
2.5  
2.5125  
V
Full-Scale V  
Monitor  
At factory setting (Note 5)  
6.5208 6.5536 6.5864  
10  
V
pF  
V
CC  
I/O Capacitance  
C
I/O  
Digital Power-On Reset  
Analog Power-On Reset  
POD  
POA  
1.0  
2.0  
2.2  
2.6  
V
2
_____________________________________________________________________  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
ANALOG RESISTOR CHARACTERISTICS  
(V  
CC  
= 2.85V to 5.5V, T = -40°C to +95°C, unless otherwise noted.)  
A
PARAMETER  
CONDITIONS  
MIN  
0.65  
40  
TYP  
1.0  
MAX  
1.35  
60  
UNITS  
kΩ  
Position 00h Resistance (50kΩ)  
Position FFh Resistance (50kΩ)  
Position 00h Resistance (30kΩ)  
Position FFh Resistance (30kΩ)  
Position 00h Resistance (20kΩ)  
Position FFh Resistance (20kΩ)  
Position 00h Resistance (10kΩ)  
Position FFh Resistance (10kΩ)  
Position 00h Resistance (2.5kΩ)  
Position FFh Resistance (2.5kΩ)  
Absolute Linearity  
T
T
T
T
T
T
T
T
T
T
= +25°C  
= +25°C  
= +25°C  
= +25°C  
= +25°C  
= +25°C  
= +25°C  
= +25°C  
= +25°C  
= +25°C  
A
A
A
A
A
A
A
A
A
A
50  
kΩ  
0.40  
30  
kΩ  
kΩ  
0.20  
15  
0.40  
20  
0.55  
25  
kΩ  
kΩ  
0.40  
10  
kΩ  
kΩ  
0.1  
2.0  
-2  
0.175  
2.50  
0.250  
3.0  
kΩ  
kΩ  
(Note 6)  
(Note 7)  
(Note 8)  
+2  
LSB  
LSB  
ppm/°C  
Relative Linearity  
-1  
+1  
Temperature Coefficient  
50  
ANALOG VOLTAGE MONITORING  
(V  
CC  
= 2.85V to 5.5V, T = -40°C to +95°C, unless otherwise noted.)  
A
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
610  
1.6  
MAX  
UNITS  
µV  
Input Resolution  
∆VMON  
Supply Resolution  
∆V  
mV  
CC  
Input/Supply Accuracy  
(MON1, MON2, MON3, V  
% FS  
(full scale)  
A
At factory setting  
0.25  
47  
0
0.5  
60  
5
CC  
)
CC  
Update Rate for MON1, MON2,  
MON3, Temp, or V  
t
ms  
frame  
CC  
Input/Supply Offset  
(MON1, MON2, MON3, V  
V
(Note 14)  
LSB  
OS  
)
CC  
DIGITAL THERMOMETER  
(V  
CC  
= 2.85V to 5.5V, T = -40°C to +95°C, unless otherwise noted.)  
A
PARAMETER  
Thermometer Error  
SYMBOL  
CONDITIONS  
-40°C to +95°C  
MIN  
TYP  
MAX  
3.0  
UNITS  
T
°C  
ERR  
NONVOLATILE MEMORY CHARACTERISTICS  
(V  
CC  
= 2.85V to 5.5V)  
PARAMETER  
SYMBOL  
CONDITIONS  
+70°C (Note 14)  
MIN  
TYP  
MAX  
UNITS  
50,000  
Writes  
EEPROM Writes  
_____________________________________________________________________  
3
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
AC ELECTRICAL CHARACTERISTICS  
(V  
CC  
= 2.85V to 5.5V, T = -40°C to +95°C, unless otherwise noted. See Figure 6.)  
A
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
0
TYP  
MAX  
400  
UNITS  
Fast mode  
SCL Clock Frequency (Note 9)  
f
kHz  
SCL  
Standard mode  
Fast mode  
0
100  
1.3  
4.7  
0.6  
4.0  
1.3  
4.7  
0.6  
4.0  
0
Bus Free Time Between STOP and  
START Condition (Note 9)  
t
µs  
µs  
µs  
µs  
µs  
ns  
µs  
ns  
ns  
µs  
BUF  
Standard mode  
Fast mode  
Hold Time (Repeated)  
START Condition (Notes 9, 10)  
t
HD:STA  
Standard mode  
Fast mode  
LOW Period of SCL Clock (Note 9)  
HIGH Period of SCL Clock (Note 9)  
Data Hold Time (Notes 9, 11, 12)  
Data Setup Time (Note 9)  
t
LOW  
Standard mode  
Fast mode  
t
HIGH  
Standard mode  
Fast mode  
0.9  
t
HD:DAT  
Standard mode  
Fast mode  
0
100  
250  
0.6  
4.7  
20 + 0.1C  
t
SU:DAT  
Standard mode  
Fast mode  
START Setup Time (Note 9)  
t
SU:STA  
Standard mode  
Fast mode  
300  
1000  
300  
B
Rise Time of Both SDA and SCL  
Signals (Note 13)  
t
R
Standard mode  
Fast mode  
20 + 0.1C  
B
20 + 0.1C  
20 + 0.1C  
0.6  
B
B
Fall Time of Both SDA and SCL  
Signals (Note 13)  
t
F
Standard mode  
Fast mode  
300  
Setup Time for STOP Condition  
t
SU:STO  
Standard mode  
(Note 13)  
4.0  
Capacitive Load for Each Bus Line  
EEPROM Write Time  
C
400  
20  
pF  
B
t
10  
ms  
W
Note 1: All voltages are referenced to ground.  
Note 2: I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if V  
is switched off.  
CC  
Note 3: SDA and SCL are connected to V  
and all other input signals are connected to well-defined logic levels.  
CC  
Note 4: Full scale is user programmable. The maximum voltage that the MON inputs read is approximately full scale, even if the volt-  
age on the inputs is greater than full scale.  
Note 5: This voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum V voltage.  
CC  
Note 6: Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a  
straight line from measured minimum position to measured maximum position.  
Note 7: Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change  
is the slope of the straight line from measured minimum position to measured maximum position.  
Note 8: See the Typical Operating Characteristics.  
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement t  
> 250ns must then be met. This  
SU:DAT  
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the  
LOW period of the SCL signal, it must output the next data bit to the SDA line t  
before the SCL line is released.  
+ t  
= 1000ns + 250ns = 1250ns  
RMAX  
SU:DAT  
4
_____________________________________________________________________  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Note 10: After this period, the first clock pulse is generated.  
Note 11: The maximum t  
only has to be met if the device does not stretch the LOW period (t ) of the SCL signal.  
LOW  
HD:DAT  
Note 12: A device must internally provide a hold time of at least 300ns for the SDA signal (see the V  
of the SCL signal) to  
IH MIN  
bridge the undefined region of the falling edge of SCL.  
Note 13: C —total capacitance of one bus line, timing referenced to 0.9 x V  
and 0.1 x V  
.
CC  
B
CC  
Note 14: Guaranteed by design.  
Typical Operating Characteristics  
(V  
CC  
= 5.0V, T = +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.)  
A
SUPPLY CURRENT vs. TEMPERATURE  
SUPPLY CURRENT vs. VOLTAGE  
RESISTANCE vs. SETTING  
800  
800  
60  
50  
40  
30  
20  
10  
0
SDA = SCL = V  
CC  
50kΩ VERSION  
SDA = SCL = V  
CC  
750  
700  
650  
600  
550  
500  
450  
750  
700  
650  
600  
400  
-40  
-20  
0
20  
40  
60  
80  
100  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
0
50  
100  
150  
200  
250  
TEMPERATURE (°C)  
VOLTAGE (V)  
SETTING (DEC)  
ACTIVE SUPPLY CURRENT  
vs. SCL FREQUENCY  
RESISTOR 0 INL (LSB)  
RESISTANCE vs. SETTING  
1.0  
0.8  
20  
15  
10  
5
800  
780  
760  
740  
720  
700  
20kΩ VERSION  
SDA = V  
CC  
0.6  
0.4  
0.2  
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
0
0
25 50 75 100 125 150 175 200 225 250  
SETTING (DEC)  
0
50  
100  
150  
200  
250  
0
100  
200  
300  
400  
SETTING (DEC)  
SCL FREQUENCY (kHz)  
_____________________________________________________________________  
5
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Typical Operating Characteristics (continued)  
= 5.0V, T = +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.)  
A
(V  
CC  
RESISTOR 0 DNL (LSB)  
RESISTOR 1 INL (LSB)  
RESISTOR 1 DNL (LSB)  
1.0  
1.0  
0.8  
1.0  
0.8  
0.8  
0.6  
0.6  
0.6  
0.4  
0.4  
0.4  
0.2  
0.2  
0.2  
0
0
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
0
25 50 75 100 125 150 175 200 225 250  
SETTING (DEC)  
0
25 50 75 100 125 150 175 200 225 250  
SETTING (DEC)  
0
25 50 75 100 125 150 175 200 225 250  
SETTING (DEC)  
RESISTANCE  
vs. POWER-UP VOLTAGE  
RESISTANCE  
vs. POWER-UP VOLTAGE  
POSITION 00h RESISTANCE  
vs. TEMPERATURE  
120  
110  
100  
120  
110  
100  
1.01  
1.00  
0.99  
0.98  
0.97  
0.96  
50kΩ VERSION  
>1MΩ  
50kΩ VERSION  
>1MΩ  
20kΩ VERSION  
90  
80  
90  
80  
PROGRAMMED  
RESISTANCE  
(80h)  
70  
60  
50  
70  
60  
50  
PROGRAMMED  
RESISTANCE  
(80h)  
40  
30  
20  
40  
30  
20  
10  
0
10  
0
0
1
2
3
4
5
0
1
2
3
4
5
-40 -25 -10  
5
20 35 50 65 80 95  
POWER-UP VOLTAGE (V)  
POWER-UP VOLTAGE (V)  
TEMPERATURE (°C)  
6
_____________________________________________________________________  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Typical Operating Characteristics (continued)  
= 5.0V, T = +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.)  
A
(V  
CC  
POSITION 00h RESISTANCE  
vs. TEMPERATURE  
POSITION FFh RESISTANCE  
vs. TEMPERATURE  
POSITION FFh RESISTANCE  
vs. TEMPERATURE  
0.38  
0.37  
0.36  
0.35  
0.34  
0.33  
50.00  
20.00  
19.80  
19.60  
19.40  
19.20  
19.00  
20kΩ VERSION  
50kΩ VERSION  
20kΩ VERSION  
49.75  
49.50  
49.25  
49.00  
48.75  
48.50  
48.25  
48.00  
-40 -25 -10  
5
20 35 50 65 80 95  
-40 -25 -10  
5
20 35 50 65 80 95  
-40 -25 -10  
5
20 35 50 65 80 95  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE COEFFICIENT vs. SETTING  
TEMPERATURE COEFFICIENT vs. SETTING  
800  
700  
600  
500  
400  
300  
200  
100  
0
400  
350  
300  
250  
200  
150  
100  
50  
50kΩ VERSION  
20kΩ VERSION  
+25°C TO +95°C  
+25°C TO -40°C  
+25°C TO +95°C  
+25°C TO -40°C  
0
-50  
-100  
-100  
0
50  
100  
150  
200  
250  
0
50  
100  
150  
200  
250  
SETTING (DEC)  
SETTING (DEC)  
LSB ERROR vs. FULL-SCALE INPUT  
LSB ERROR vs. FULL-SCALE INPUT  
6
5
4
3
2
+3 SIGMA  
+3 SIGMA  
3
2
1
1
0
MEAN  
MEAN  
0
-1  
-2  
-3  
-4  
-5  
-6  
-7  
-8  
-1  
-2  
-3  
-4  
-3 SIGMA  
-3 SIGMA  
0
25  
50  
75  
100  
0
3.125  
6.250  
9.375  
12.500  
NORMALIZED FULL SCALE (%)  
NORMALIZED FULL SCALE (%)  
_______________________________________________________________________________________  
7
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Pin Description  
PIN  
1
BALL  
B2  
NAME  
SDA  
FUNCTION  
2-Wire Serial Data I/O Pin. Transfers serial data to and from the device.  
2-Wire Serial Clock Input. Clocks data into and out of the device.  
2
A2  
SCL  
3
C3  
A1  
OUT1 Open-Drain Buffer Output  
4
IN1  
TTL/CMOS-Compatible Input to Buffer  
5
B1  
OUT2 Open-Drain Buffer Output  
6
C2  
C1  
D1  
D3  
D4  
C4  
IN2  
N.C.  
GND  
TTL/CMOS-Compatible Input to Buffer  
7
No Connection  
Ground  
8
9
MON1 External Analog Input  
MON2 External Analog Input  
MON3 External Analog Input  
10  
11  
Low-End Resistor 0 Terminal. It is not required that the low-end terminals be connected to a potential  
less than the high-end terminals of the corresponding resistor. Voltage applied to any of the resistor  
terminals cannot exceed the power-supply voltage, V , or go below ground.  
CC  
12  
13  
D2  
B3  
L0  
High-End Resistor 0 Terminal. It is not required that the high-end terminals be connected to a  
potential greater than the low-end terminals of the corresponding resistor. Voltage applied to any of  
H0  
the resistor terminals cannot exceed the power-supply voltage, V , or go below ground.  
CC  
14  
15  
16  
B4  
A4  
A3  
L1  
Low-End Resistor 1 Terminal  
High-End Resistor 1 Terminal  
Supply Voltage  
H1  
V
CC  
The position values of each resistor can be indepen-  
Detailed Description  
dently programmed. The user can assign a unique  
value to each resistor for every 2°C increment over the  
-40°C to +102°C range.  
The user can read the registers that monitor the V  
,
CC  
MON1, MON2, MON3, and temperature analog signals.  
After each signal conversion, a corresponding bit is set  
that can be monitored to verify that a conversion has  
occurred. The signals also have alarm and warning flags  
that notify the user when the signals go above or below  
the user-defined value. Interrupts can also be set for  
each signal.  
Two buffers are provided to convert logic-level inputs  
into open-drain outputs. Typically, these buffers are  
used to implement transmit (Tx) fault and loss-of-signal  
(LOS) functionality. Additionally, OUT1 can be asserted  
in the event that one or more of the monitored values  
go beyond user-defined limits.  
8
_____________________________________________________________________  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
AD  
MD  
MD  
MD  
AD (AUXILIARY DEVICE ENABLE A0h)  
TABLE  
SELECT  
EEPROM  
128 x 8 BIT  
STANDARDS  
TABLE  
SELECT  
TABLE  
SELECT  
EEPROM  
72 x 8 BIT  
80h-C7h  
EEPROM  
72 x 8 BIT  
80h-C7h  
DEVICE  
ADDRESS  
MD (MAIN DEVICE ENABLE)  
IF ADEN = 0,  
[00h - 7Fh OF AD]  
IF ADEN = 1,  
[80h-FFh OF MD,  
TABLE 00/01h]  
ADDRESS  
ADDRESS  
R/W  
ADDRESS  
R/W  
DEVICE ADDRESS  
TABLE 04  
RESISTOR 0  
LOOK-UP  
TABLE  
TABLE 05  
RESISTOR 1  
LOOK-UP  
TABLE  
R/W  
ADEN ADFIX  
SDA  
SCL  
ADDRESS  
2-WIRE  
INTERFACE  
ADEN (BIT)  
TEMP INDEX  
TEMP INDEX  
DATA BUS  
R/W  
TxF  
Tx FAULT  
MD  
OUT1  
H0  
MONITORS LIMIT  
HIGH  
ADDRESS  
R/W  
RESISTOR 0  
256 POSITIONS  
EEPROM  
96 x 8 BIT  
00h-5Fh  
LIMITS  
MONITORS LIMIT  
LOW  
MINT  
L0  
TEMP INDEX  
MINT (BIT)  
H1  
IN1  
SRAM  
32 x 8 BIT  
60h-7Fh  
INV1  
RESISTOR 1  
256 POSITIONS  
TxF  
RxL  
LOS  
L1  
OUT2  
TABLE SELECT  
MEASUREMENT  
WARNING FLAGS  
MD R/W  
INV2  
ALARM FLAGS  
RIGHT  
INV1 (BIT)  
SHIFTING  
IN2  
TABLE SELECT  
INV2 (BIT)  
INTERNAL  
CALIBRATION  
TABLE 03  
EEPROM  
80h-B7h  
INTERNAL  
TEMP  
V
CC  
ADDRESS  
ADEN (BIT)  
ADFIX (BIT)  
DS1856  
ADC  
12-BIT  
DEVICE ADDRESS  
VENDOR  
MUX  
MON1  
MON2  
MON3  
MASKING (TMP, V , MON1, MON2, MON3)  
CC  
MONITORS LIMIT HIGH  
A/D  
CTRL  
MUX  
CTRL  
MONITORS LIMIT LOW  
V
CC  
MINT  
MEASUREMENT  
INTERRUPT  
V
CC  
GND  
COMPARATOR  
COMP CTRL  
WARNING FLAGS  
ALARM FLAGS  
Figure 1. Block Diagram  
_____________________________________________________________________  
9
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Table 1. Scales for Monitor Channels at  
Factory Setting  
Table 3. Look-Up Table Address for  
Corresponding Temperature Values  
+FS  
SIGNAL  
+FS  
(hex)  
-FS  
SIGNAL  
-FS  
(hex)  
TEMPERATURE  
(°C)  
CORRESPONDING LOOK-UP  
TABLE ADDRESS  
SIGNAL  
+127.984°  
6.5528V  
2.4997V  
2.4997V  
2.4997V  
Temperature  
7FFC  
FFF8  
FFF8  
FFF8  
FFF8  
-128°C  
0V  
8000  
0000  
0000  
0000  
0000  
<-40  
-40  
80h  
80h  
81h  
82h  
83h  
—
V
CC  
MON1  
MON2  
MON3  
0V  
-38  
0V  
-36  
0V  
-34  
—
+98  
+100  
+102  
>+102  
C5h  
C6h  
C7h  
C7h  
Table 2. Signal Comparison  
SIGNAL  
FORMAT  
Unsigned  
Unsigned  
Unsigned  
Unsigned  
V
CC  
MON1  
MON2  
Monitor Conversion Example  
MON3  
MSB (BIN)  
11000000  
10000000  
LSB (BIN)  
00000000  
10000000  
VOLTAGE (V)  
1.875  
Temperature  
Two’s complement  
Monitored Signals  
1.255  
Each signal (V , MON1, MON2, MON3, and tempera-  
CC  
ture) is available as a 16-bit value with 12-bit accuracy  
(left-justified) over the serial bus. See Table 1 for signal  
scales and Table 2 for signal format. The four LSBs  
should be masked when calculating the value. The 3  
LSBs are internally masked with 0s.  
To calculate V , convert the unsigned 16-bit value to  
CC  
decimal and multiply by 100µV.  
To calculate MON1, MON2, or MON3, convert the  
unsigned 16-bit value to decimal and multiply by  
38.147µV.  
The signals are updated every frame rate (t  
round-robin fashion.  
) in a  
frame  
To calculate the temperature, treat the two’s comple-  
ment value binary number as an unsigned binary num-  
ber, then convert to decimal and divide by 256. If the  
result is greater than or equal to 128, subtract 256 from  
the result.  
The comparison of all five signals with the high and low  
user-defined values are done automatically. The corre-  
sponding flags are set to 1 within a specified time of  
the occurrence of an out-of-limit condition.  
Temperature: high byte: -128°C to +127°C signed; low  
byte: 1/256°C.  
Calculating Signal Values  
The LSB = 100µV for V , and the LSB = 38.147µV for  
CC  
the MON signals when using factory default settings.  
Temperature Bit Weights  
6
5
4
3
2
1
0
S
2
2
2
2
2
2
2
Monitor/V  
Bit Weights  
-1  
-2  
-3  
-4  
-5  
-6  
-7  
-8  
CC  
2
2
2
2
2
2
2
2
15  
14  
13  
12  
11  
3
10  
2
9
1
8
0
MSB  
LSB  
2
2
2
2
2
2
2
2
2
2
7
6
5
4
Temperature Conversion Examples  
2
2
2
2
2
2
MSB (BIN)  
01000000  
01000000  
01011111  
11110110  
11011000  
LSB (BIN)  
00000000  
00001111  
00000000  
00000000  
00000000  
TEMPERATURE (°C)  
V
Conversion Examples  
+64  
+64.059  
+95  
CC  
MSB (BIN)  
LSB (BIN)  
10000000  
11111000  
VOLTAGE (V)  
3.29  
10000000  
11000000  
-10  
4.94  
-40  
10  
____________________________________________________________________  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Table 4. ADEN Address Configuration  
Table 5. ADEN and ADFIX Bits  
AUXILIARY  
ADDRESS  
ADEN  
(ADDRESS  
ENABLE)  
NO. OF SEPARATE  
DEVICE  
ADEN  
ADFIX  
MAIN ADDRESS  
ADDITIONAL  
INFORMATION  
ADDRESSES  
0
0
1
1
0
1
0
1
A0h  
A2h  
EEPROM  
(Table 03, 8Ch)  
0
1
2
See Figure 2  
See Figure 3  
A0h  
—
1 (Main Device Only)  
A2h  
EEPROM  
(Table 03, 8Ch)  
—
2-WIRE ADDRRESS A0h  
00h  
2-WIRE ADDRESS A2h (DEFAULT)  
00h  
DEC HEX  
DEC HEX  
0
0
0
0
NOTE 1: ADEN BIT = 0. AUXILIARY MEMORY IS ADDRESSED USING THE AUXILIARY DEVICE  
NOTE 1. 2-WIRE SLAVE ADDRESS OF A0h, AND THE REMAINDER OF THE MEMORY IS  
NOTE 1. ADDRESSED USING THE MAIN DEVICE 2-WIRE SLAVE ADDRESS OF A2h  
NOTE 1. (WHEN ADFIX = 0).  
AUXILIARY DEVICE  
MAIN DEVICE  
LOWER MEMORY  
EEPROM  
AUXILIARY MEMORY  
(128 BYTES)  
NOTE 2: TABLES 00h, 01h, AND 02h DO NOT EXIST.  
PASSWORD ENTRY  
(PWE) (4 BYTES)  
127 7F  
7Fh  
TABLE SELECT BYTE 7Fh  
127 7F  
128 80  
80h  
80h  
80h  
TABLE 03h  
TABLE 04h  
TABLE 05h  
CONFIGURATION  
TABLE  
RESISTOR 0  
LOOK-UP TABLE  
(72 BYTES)  
RESISTOR 1  
LOOK-UP TABLE  
(72 BYTES)  
183 B7  
B7h  
199 C7  
200 C8  
C7h  
FFh  
C7h  
FFh  
F0h  
F0h  
RESERVED AND  
CALIBRATION  
CONSTANTS  
RESERVED AND  
CALIBRATION  
CONSTANTS  
255 FF  
Figure 2. Memory Organization, ADEN = 0  
The user sets the resistors in manual mode by writing  
to addresses 82h and 83h in Table 03 to control resis-  
tors 0 and 1, respectively.  
Variable Resistors  
The value of each variable resistor is determined by  
a temperature-addressed look-up table, which can  
assign a unique value (00h to FFh) to each resistor for  
every 2°C increment over the -40°C to +102°C range  
(see Table 3). See the Temperature Conversion section  
for more information.  
Memory Description  
The memory of the DS1856 is divided into two areas  
referred to as the Main Device and the Auxiliary  
Device. The Main Device comprises all of the DS1856  
specific memory while the Auxiliary Device consists of  
128 bytes of general-purpose EEPROM and is espe-  
cially useful in GBIC applications. Main and Auxiliary  
The variable resistors can also be used in manual  
mode. If the TEN bit equals 0, the resistors are in man-  
ual mode and the temperature indexing is disabled.  
____________________________________________________________________ 11  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
2-WIRE ADDRRESS A2h (DEFAULT)  
00h  
DEC HEX  
0
0
NOTE 1: ADEN BIT = 1. ALL MEMORY (INCLUDING THE AUXILIARY MEMORY) IS ADDRESSED USING THE  
NOTE 1: MAIN DEVICE 2-WIRE SLAVE ADDRESS.  
LOWER MEMORY  
NOTE 2: TABLES 00h AND 01h ACCESS THE SAME PHYSICAL MEMORY.  
NOTE 3: TABLE 02h DOES NOT EXIST.  
PASSWORD ENTRY  
(PWE) (4 BYTES)  
127 7F  
TABLE SELECT BYTE 7Fh  
80h  
80h  
80h  
128 80 80h  
TABLE 03h  
TABLE 04h  
TABLE 05h  
TABLE 00h/01h  
CONFIGURATION  
TABLE  
RESISTOR 0  
LOOK-UP TABLE  
(72 BYTES)  
RESISTOR 1  
LOOK-UP TABLE  
(72 BYTES)  
EEPROM  
AUXILIARY MEMORY  
(128 BYTES)  
B7h  
183 B7  
C7h  
FFh  
C7h  
FFh  
199 C7  
200 C8  
F0h  
F0h  
RESERVED AND  
CALIBRATION  
CONSTANTS  
RESERVED AND  
CALIBRATION  
CONSTANTS  
FFh  
255 FF  
Figure 3. Memory Organization, ADEN = 1  
memories can be accessed by two separate 2-wire  
slave addresses (see Table 4). The Main Device  
address is A2h (or determined by the value in Table 03,  
byte 8Ch, when ADFIX = 1) and the Auxiliary Device  
address is A0h (fixed). A configuration bit, ADEN  
(Table 03, byte 89h, bit 5), determines whether the  
DS1856 uses one or two 2-wire slave addresses. This  
feature can be used to save component count in SFF  
applications or other applications where both GBIC  
and monitoring functions are implemented and two  
device addresses are needed.  
of the DS1856’s memory including the Auxiliary memo-  
ry is accessed using only the Main Device address.  
The Auxiliary Device memory is mapped into Table 00  
and Table 01 in the Main Device. Both tables map to  
the same block of physical memory. This is done to  
improve the compatibility between previous members  
of this IC family such as the DS1858/DS1859 and the  
DS1852. In this configuration, the DS1856 ignores com-  
munication using the Auxiliary Device address.  
The value of the Main Device address can be changed  
to a value other than the default value of A2h (see data  
sheet Table 5). There can be up to 128 devices sharing  
a common 2-wire bus, with each device having its own  
unique address. To change the Main Device address,  
first write the desired value to the Chip Address byte  
(Table 03, byte 8Ch). Then, enable the new address by  
setting ADFIX to a 1. Subsequent 2-wire communica-  
tion must be performed using the new Main Device  
address. When ADFIX = 0, the Chip Address byte is  
ignored, and the Main Device address is set to A2h.  
The memory organization for ADEN = 0 is shown in  
Figure 2. In this configuration, the 128 bytes of  
Auxiliary Device EEPROM are located at memory loca-  
tions 00h to 7Fh and accessed using the Auxiliary  
Device 2-wire slave address of A0h (fixed). The  
remainder of the DS1856’s memory is accessed using  
the Main Device address.  
The memory organization of the second configuration,  
ADEN = 1, is shown in Figure 3. In this configuration, all  
12  
____________________________________________________________________  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
The DS1856 2-wire interface uses 8-bit addressing,  
which allows up to 256 bytes to be addressed tradi-  
tionally on a given 2-wire slave address. However,  
since the Main Device contains more than 256 bytes, a  
table scheme is used. The lower 128 bytes of the Main  
Device, memory locations 00h to 7Fh, function as  
expected and are independent of the currently select-  
ed table. Byte 7Fh is the Table Select byte. This byte  
determines which memory table will be accessed by  
the 2-wire interface when address locations 80h to FFh  
are accessed. Memory locations 80h to FFh are acces-  
sible only through the Main Device address. The  
Auxiliary Device address has no access to the tables,  
but the Auxiliary Device memory can be mapped into  
the Main Device’s memory space (by setting ADEN =  
1). Valid values for the Table Select byte are shown in  
the table below.  
(PWE) bytes located in the Main Device at 7Bh to 7Eh.  
The value entered is compared to both the PW1 and  
PW2 settings located in Table 03, bytes B0h to B3h and  
Table 03, bytes B4h to B7h, respectively, to determine  
if access should be granted. Access is granted until  
the password is changed or until power is cycled.  
Writing PWE can be done with any level of access,  
although PWE can never be read.  
Writing PW1 and PW2 requires PW2 access. However,  
PW1 and PW2 can never be read, even with PW2 access.  
On power-up, PWE is set to all 1s (FFFFh). As long as  
neither of the passwords are ever changed to FFFFh,  
then User access is the power-up default. Likewise,  
password protection can be intentionally disabled by  
setting the PW2 password to FFFFh.  
Memory Map  
The following table is the legend used in the memory  
map to indicate the access level required for read and  
write access.  
Table 6. Table Select Byte  
TABLE SELECT  
TABLE NAME  
BYTE  
Each table in the following memory map begins with a  
higher level view of a particular portion of the memory  
showing information such as row (8 bytes) and byte  
names. The tables are then followed, where applicable,  
by an Expanded Bytes table, which shows bit names  
and values. Furthermore, both tables use the permis-  
sion legend to indicate the access required on a row,  
byte, and bit level.  
00  
01  
02  
03  
04  
05  
Auxiliary Device Memory  
(When ADEN = 1)  
Does Not Exist  
Configuration  
Resistor 0 Look-up Table  
Resistor 1 Look-up Table  
Before attempting to read and write any of the bits or  
bytes mentioned in this section, it is important to look at  
the memory map provided in a subsequent section to  
verify what level of password is required. Password  
protection is described in the following section.  
The memory map is followed by a Register Description  
section, which describes bytes and bits in further detail.  
Table 7. Password Permission  
PERMISSION  
READ  
WRITE  
Password Protection  
The DS1856 uses two 4-byte passwords to achieve  
three levels of access to various memory locations. The  
three levels of access are:  
At least one byte in the row is different than  
the rest of the row, so look at each byte  
separately for permissions.  
<0>  
<1>  
<2>  
all  
all  
PW2  
NA  
User Access: This is the default state after power-up. It  
allows read access to standard monitoring and status  
functions.  
all (The part also writes to  
this byte.)  
<3>  
all  
Level 1 Access: This allows access to customer data  
table (Tables 00 and 01) in addition to everything grant-  
ed by User access. This level is granted by entering  
Password 1 (PW1).  
<4>  
<5>  
<6>  
<7>  
<8>  
<9>  
<10>  
<11>  
PW2  
all  
PW2 + mode_bit  
all  
NA  
all  
Level 2 Access: This allows access to all memory, set-  
tings, and features, in addition to everything granted by  
Level 1 and User access. This level is granted by enter-  
ing Password 2 (PW2).  
PW1  
PW2  
NA  
PW1  
PW2  
PW2  
NA  
PW2  
all  
To obtain a particular level of access, the correspond-  
ing password must be entered in the Password Entry  
PW1  
____________________________________________________________________ 13  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Memory Map  
LOWER MEMORY  
Word 0  
Byte 0/8  
Temp Alarm Hi  
Alarm Hi  
Word 1  
Byte 2/A Byte 3/B  
Temp Alarm Lo  
Alarm Lo  
Word 2  
Byte 4/C Byte 5/D  
Temp Warn Hi  
Warn Hi  
Word 3  
Byte 6/E Byte 7/F  
Temp Warn Lo  
Warn Lo  
Row  
(hex)  
Row  
Name  
Byte 1/9  
00  
08  
10  
18  
20  
28  
30  
38  
40  
48  
50  
58  
60  
68  
70  
78  
<1>Threshold  
<1>Threshold  
<1>Threshold  
<1>Threshold  
<1>Threshold  
<1>user ROM  
<1>user ROM  
<1>user ROM  
<1>user ROM  
<1>user ROM  
<1>user ROM  
<1>user ROM  
0
1
2
3
4
V
V
V
V
CC  
CC  
CC  
CC  
Mon1 Alarm Hi  
Mon2 Alarm Hi  
Mon3 Alarm Hi  
Mon1 Alarm Lo  
Mon2 Alarm Lo  
Mon3 Alarm Lo  
Mon1 Warn Hi  
Mon2 Warn Hi  
Mon3 Warn Hi  
Mon1 Warn Lo  
Mon2 Warn Lo  
Mon3 Warn Lo  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
<2>Values  
<0>Values  
1
<2>Alrm Wrn  
Temp Value  
<2>Mon3 Value  
Alarm Alarm  
Vcc Value  
<2>Reserved  
Reserved Reserved  
<6>PWE msb  
EXPANDED BYTES  
Bit5 Bit4  
bit bit  
Mon1 Value  
<2>Reserved  
Warn Warn  
0
Mon2 Value  
0
<0>Status  
<3>Update  
Reserved  
<5>Tbl Sel  
Reserved  
1
0
1
<0>Table Select <6>Reserved <6>Reserved <6>Reserved  
<6>PWE lsb  
Bit7  
Bit6  
bit  
Bit3  
bit  
Bit2  
bit  
Bit1  
bit  
Bit0  
Byte  
(hex)  
Byte  
Name  
bit  
bit  
14  
bit  
bit  
11  
bit  
9
bit  
7
bit  
5
bit  
3
bit  
bit  
0
15  
13  
12  
10  
8
6
4
2
1
User EE  
Temp Alarm  
Temp Warn  
Volt Alarm  
Volt Warn  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
S
26  
25  
25  
213  
213  
24  
23  
23  
211  
211  
22  
21  
21  
29  
29  
20  
2-1  
2-1  
27  
2-2  
2-2  
26  
2-3  
2-3  
25  
2-4  
2-5  
2-5  
23  
2-6  
2-7  
2-7  
21  
2-8  
2-8  
20  
S
26  
214  
214  
24  
212  
212  
22  
210  
210  
20  
28  
28  
2-4  
24  
24  
2-6  
22  
22  
215  
215  
27  
26  
25  
23  
21  
20  
28  
30  
38  
40  
48  
50  
58  
User ROM  
User ROM  
User ROM  
User ROM  
User ROM  
User ROM  
User ROM  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
EE  
14  
____________________________________________________________________  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Memory Map (continued)  
60  
62  
64  
66  
68  
6E  
6F  
70  
71  
74  
75  
7B  
7D  
7F  
Temp Value  
Value  
S
26  
25  
24  
23  
22  
21  
29  
29  
29  
29  
20  
28  
28  
28  
28  
2-1  
27  
27  
27  
27  
2-2  
26  
26  
26  
26  
2-3  
25  
25  
25  
25  
2-4  
24  
24  
24  
24  
2-5  
23  
23  
23  
23  
2-6  
22  
22  
22  
22  
2-7  
21  
21  
21  
21  
2-8  
20  
20  
20  
20  
V
215  
215  
215  
215  
214  
214  
214  
214  
213  
213  
213  
213  
212  
212  
212  
212  
211  
211  
211  
211  
210  
210  
210  
210  
CC  
Mon1 Value  
Mon2 Value  
Mon3 Value  
Status  
<2>Rhiz  
<11>SoftHiz <2>Reserved <2>Reserved <2>Reserved  
<2>TxF  
<2>RxL  
<2>Rdyb  
Update  
Temp Rdy  
Temp Hi  
Mon3 Hi  
Temp Hi  
Mon3 Hi  
231  
215  
V
Rdy  
Mon1 Rdy  
Hi  
Mon2 Rdy  
Lo  
Mon3 Rdy  
Mon1 Hi  
Reserved  
Mon1 Lo  
Reserved  
Mon1 Lo  
Reserved  
221  
25  
Reserved  
Mon2 Hi  
Reserved  
Mon2 Hi  
Reserved  
219  
23  
Reserved  
Mon2 Lo  
Mint  
CC  
Alarm  
Alarm  
Temp Lo  
Mon3 Lo  
Temp Lo  
Mon3 Lo  
229  
213  
V
V
CC  
1
0
CC  
Reserved  
Hi  
Reserved  
Lo  
Reserved  
Mon1 Hi  
Warn  
Warn  
V
V
CC  
Mon2 Lo  
Reserved  
217  
21  
1
CC  
Reserved  
Reserved  
Reserved  
0
PWE msb  
PWE lsb  
Tbl Sel  
230  
214  
228  
212  
227  
211  
226  
210  
225  
29  
224  
28  
223  
27  
222  
26  
220  
24  
218  
22  
216  
20  
27  
26  
25  
24  
23  
22  
21  
20  
AUXILIARY (VALID WHEN ADEN = 0)  
Word 0  
Word 1  
Word 2  
Word 3  
Row  
Row  
(hex)  
Name  
<1>EE  
Byte 0/8  
EE  
Byte 1/9  
EE  
Byte 2/A  
EE  
Byte 3/B  
EE  
Byte 4/C  
EE  
Byte 5/D  
EE  
Byte 6/E  
EE  
Byte 7/F  
EE  
00–7F  
TABLE 00/01 (VALID WHEN ADEN = 1)  
Word 0  
Byte 1/9  
EE  
Word 1  
Word 2  
Word 3  
Row  
(hex)  
Row  
Name  
<7>EE  
Byte 0/8  
EE  
Byte 2/A  
EE  
Byte 3/B  
EE  
Byte 4/C  
EE  
Byte 5/D  
EE  
Byte 6/E  
EE  
Byte 7/F  
EE  
80–FF  
____________________________________________________________________ 15  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Memory Map (continued)  
TABLE 03 (CONFIGURATION)  
Word 0  
Byte 1/9  
Word 1  
Byte 2/A  
<4>Res0  
Word 2  
Byte 4/C Byte 5/D  
<8>Reserved <8>Reserved <8>Reserved <8>Reserved  
chip addr Reserved Rshift Rshift  
Mon1 Scale  
Word 3  
Row  
(hex)  
Row  
Name  
<0>Config  
<8>Config  
<8>Scale  
<8>Scale  
<8>Offset  
<8>Offset  
<9>Pwd Value  
Byte 0/8  
<8>Mode  
Byte 3/B  
<4>Res1  
Byte 6/E Byte 7/F  
80  
88  
90  
98  
A0  
A8  
B0  
<4>Tindex  
0
1
Int Enable  
Config  
Reserved  
Reserved  
1
0
Reserved  
Vcc Scale  
Mon2 Scale  
Reserved  
0
Mon3 Scale  
Reserved  
Reserved  
Vcc Offset  
Reserved  
MON1 Offset  
Reserved  
1
MON2 Offset  
0
MON3 Offset  
PW1 msb  
Reserved  
Internal Temp Offset*  
PW2 lsb  
1
PW1 lsb  
PW2 msb  
EXPANDED BYTES  
Bit7  
bit  
Bit6  
bit  
Bit5  
bit  
Bit4  
bit  
Bit3  
Bit2  
Bit1  
bit  
Bit0  
bit bit  
1
Byte  
(hex)  
Byte  
Name  
bit  
15  
bit  
13  
bit  
11  
bit  
9
bit  
bit  
6
bit  
5
bit  
4
bit  
3
14  
12  
10  
8
7
2
0
80  
81  
82  
83  
88  
89  
8C  
8E  
8F  
92  
94  
96  
98  
A2  
A4  
A6  
A8  
AE  
B0  
B2  
B4  
B6  
Mode  
Tindex  
Reserved  
27  
Reserved  
26  
Reserved  
25  
Reserved  
24  
Reserved  
23  
Reserved  
22  
TEN  
21  
21  
AEN  
20  
20  
Res0  
27  
27  
26  
26  
25  
25  
24  
24  
23  
23  
22  
22  
Res1  
21  
20  
Int Enable  
Config  
Temp  
Reserved  
27  
Vcc  
Mon1  
ADEN  
25  
Mon11  
Mon31  
Mon2  
ADFIX  
24  
Mon10  
Mon30  
Mon3  
Reserved  
23  
Reserved  
Reserved  
22  
Reserved  
Inv 1  
21  
Mon21  
Reserved  
Inv 2  
20  
Mon20  
Reserved  
26  
Mon12  
Chip Addr  
Rshift  
1
Reserved  
Reserved  
Reserved  
Reserved  
Mon22  
Rshift  
0
Mon32  
Reserved  
Reserved  
Reserved  
V
Scale  
215  
215  
215  
215  
S
214  
214  
214  
214  
S
213  
213  
213  
213  
215  
215  
215  
215  
27  
229  
213  
229  
213  
212  
212  
212  
212  
214  
214  
214  
214  
26  
228  
212  
228  
212  
211  
211  
211  
211  
213  
213  
213  
213  
25  
227  
211  
227  
211  
210  
210  
210  
210  
212  
212  
212  
212  
24  
226  
210  
226  
210  
29  
29  
29  
28  
28  
28  
27  
27  
27  
27  
29  
29  
29  
29  
21  
223  
27  
223  
27  
26  
26  
26  
26  
28  
28  
28  
28  
20  
222  
26  
222  
26  
25  
25  
25  
25  
27  
27  
27  
27  
2-1  
221  
25  
221  
25  
24  
24  
24  
24  
26  
26  
26  
26  
2-2  
220  
24  
220  
24  
23  
23  
23  
23  
25  
25  
25  
25  
2-3  
219  
23  
219  
23  
22  
22  
22  
22  
24  
24  
24  
24  
2-4  
218  
22  
218  
22  
21  
21  
21  
21  
23  
23  
23  
23  
2-5  
217  
21  
217  
21  
20  
20  
20  
20  
22  
22  
22  
22  
2-6  
216  
20  
216  
20  
CC  
Mon1 Scale  
Mon2 Scale  
Mon3 Scale  
29  
28  
V
Offset  
211  
211  
211  
211  
23  
210  
210  
210  
210  
22  
CC  
Mon1 Offset  
Mon2 Offset  
Mon3 Offset  
Temp Offset*  
PW1 msb  
S
S
S
S
S
S
28  
S
231  
215  
231  
215  
230  
214  
230  
214  
225  
29  
224  
28  
PW1 lsb  
PW2 msb  
225  
29  
224  
28  
PW2 lsb  
*The final result must be XOR’ed with BB40h.  
16  
____________________________________________________________________  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Memory Map (continued)  
TABLE 04 (LOOKUP TABLE FOR RESISTOR 0)  
Word 0  
Word 1  
Word 2  
Word 3  
Byte 6/E  
Row  
(hex)  
Row  
Name  
Byte 0/8  
Byte 1/9  
Byte 2/A  
Byte 3/B  
Byte 4/C  
Byte 5/D  
Byte 7/F  
80  
88  
90  
98  
A0  
A8  
B0  
B8  
C0  
C8  
D0  
D8  
E0  
E8  
F0  
F8  
<8>LUT  
<8>LUT  
<8>LUT  
<8>LUT  
<8>LUT  
<8>LUT  
<8>LUT  
<8>LUT  
<8>LUT  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
<10>Res0 data  
Resistor 0 Calibration Constants (see data sheet Table 8)  
EXPANDED BYTES  
Byte  
(hex)  
Byte  
Name  
Bit7  
27  
Bit6  
26  
Bit5  
25  
Bit4  
24  
Bit3  
23  
Bit2  
22  
Bit1  
21  
Bit0  
20  
80–C7  
F8–FF  
Res0  
Res0 data  
Resistor 0 Calibration Constants (see data sheet Table 8 for weighting)  
____________________________________________________________________ 17  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Memory Map (continued)  
TABLE 05 (LOOKUP TABLE FOR RESISTOR 1)  
Word 0  
Word 1  
Word 2  
Word 3  
Row  
Row  
(hex)  
Name  
Byte 0/8  
Byte 1/9  
Byte 2/A  
Byte 3/B  
Byte 4/C  
Byte 5/D  
Byte 6/E  
Byte 7/F  
80  
88  
90  
98  
A0  
A8  
B0  
B8  
C0  
C8  
D0  
D8  
E0  
E8  
F0  
F8  
<8>LUT  
<8>LUT  
<8>LUT  
<8>LUT  
<8>LUT  
<8>LUT  
<8>LUT  
<8>LUT  
<8>LUT  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Empty  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
<10>Res1 data  
Resistor 1 Calibration Constants (see data sheet Table 8)  
EXPANDED BYTES  
Byte  
(hex)  
Byte  
Name  
Bit7  
27  
Bit6  
26  
Bit5  
25  
Bit4  
24  
Bit3  
23  
Bit2  
22  
Bit1  
21  
Bit0  
20  
80–C7  
F8–FF  
Res1  
Res1 data  
Resistor 1 Calibration Constants (see data sheet Table 8 for weighting)  
18  
____________________________________________________________________  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Register Descriptions  
Name of Row  
•
•
Name of Byte............. <Read/Write><Volatile><Power-On-Value>  
Name of Byte............. <Read/Write><Nonvolitile><Factory-Default-Setting>  
Threshold0  
•
Temp High Alarm ..... <R-all/W-pw2><NV><7FFFh> Temperature measurements above this  
two's complement threshold set its corresponding alarm bit.  
Measurements below this threshold clear the alarm bit.  
•
•
•
Temp Low Alarm....... <R-all/W-pw2><NV><8000h> Temperature measurements below this  
two's complement threshold set its corresponding alarm bit.  
Measurements above this threshold clear the alarm bit.  
Temp High Warning . <R-all/W-pw2><NV><7FFFh> Temperature measurements above this  
two's complement threshold set its corresponding warning bit.  
Measurements below this threshold clear the warning bit.  
Temp Low Warning .. <R-all/W-pw2><NV><8000h> Temperature measurements below this  
two's complement threshold set its corresponding warning bit.  
Measurements above this threshold clear the warning bit.  
Threshold1  
•
V
CC  
V
CC  
V
CC  
V
CC  
High Alarm........ <R-all/W-pw2><NV><FFFFh> Voltage measurements of the V  
CC  
input above this unsigned threshold set its corresponding alarm bit.  
Measurements below this threshold clear the alarm bit.  
•
•
•
Low Alarm.......... <R-all/W-pw2><<NV><0000h> Voltage measurements of the V  
CC  
input below this unsigned threshold set its corresponding alarm bit.  
Measurements above this threshold clear the alarm bit.  
High Warning.... <R-all/W-pw2><NV><FFFFh> Voltage measurements of the V  
CC  
input above this unsigned threshold set its corresponding warning  
bit. Measurements below this threshold clear the warning bit.  
Low Warning..... <R-all/W-pw2><<NV><0000h> Voltage measurements of the V  
CC  
input below this unsigned threshold set its corresponding warning  
bit. Measurements above this threshold clear the warning bit.  
Threshold2  
•
Mon1 High Alarm..... <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon1  
input above this unsigned threshold set its corresponding alarm bit.  
Measurements below this threshold clear the alarm bit.  
•
•
•
Mon1 Low Alarm...... <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon1  
input below this unsigned threshold set its corresponding alarm bit.  
Measurements above this threshold clear the alarm bit.  
Mon1 High Warning. <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon1  
input above this unsigned threshold set its corresponding warning  
bit. Measurements below this threshold clear the warning bit.  
Mon1 Low Warning.. <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon1  
input below this unsigned threshold set its corresponding warning  
bit. Measurements above this threshold clear the warning bit.  
____________________________________________________________________ 19  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Register Descriptions (continued)  
Threshold3  
•
•
•
•
Mon2 High Alarm..... <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon2  
input above this unsigned threshold set its corresponding alarm bit.  
Measurements below this threshold clear the alarm bit.  
Mon2 Low Alarm...... <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon2  
input below this unsigned threshold set its corresponding alarm bit.  
Measurements above this threshold clear the alarm bit.  
Mon2 High Warning. <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon2  
input above this unsigned threshold set its corresponding warning  
bit. Measurements below this threshold clear the warning bit.  
Mon2 Low Warning.. <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon2  
input below this unsigned threshold set its corresponding warning  
bit. Measurements above this threshold clear the warning bit.  
Threshold4  
•
Mon3 High Alarm..... <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon3  
input above this unsigned threshold set its corresponding alarm bit.  
Measurements below this threshold clear the alarm bit.  
•
•
•
Mon3 Low Alarm...... <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon3  
input below this unsigned threshold set its corresponding alarm bit.  
Measurements above this threshold clear the alarm bit.  
Mon3 High Warning. <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon3  
input above this unsigned threshold set its corresponding warning  
bit. Measurements below this threshold clear the warning bit.  
Mon3 Low Warning.. <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon3  
input below this unsigned threshold set its corresponding warning  
bit. Measurements above this threshold clear the warning bit.  
User ROM  
•
User ROM ................. <R-all/W-pw2><NV><00h> Nonvolatile EEPROM memory.  
A2D Value0  
•
Temp Meas................ <R-all><W-NA><0000h> The signed two's complement Direct-to-  
Temperature measurement.  
•
•
•
V
Meas................... <R-all><W-NA><0000h> Unsigned voltage measurement.  
CC  
Mon1 Meas................ <R-all><W-NA><0000h> Unsigned voltage measurement.  
Mon2 Meas................ <R-all><W-NA><0000h> Unsigned voltage measurement.  
20  
____________________________________________________________________  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Register Descriptions (continued)  
A2D Value1  
•
•
•
Mon3 Meas................ <R-all><W-NA><0000h> Unsigned voltage measurement.  
Reserved.................... <R-all><W-NA><0000h>  
Status......................... <R-all><W-see bits><conditional>  
a) Rhiz.................... <R-all><W-NA><1b> High when resistor outputs are high impedance.  
b) Soft Hiz.............. <R-all><W-all><0b> Setting this bit will make resistor outputs high  
impedance.  
c) Reserved ............ <R-all><W-NA><0b>  
d) TxF ................... <R-all><W-NA><conditional> Reflects the logic level to be output on pin Out1.  
e) RxL ................... <R-all><W-NA><conditional> Reflects the logic level to be output on pin Out2.  
f) Rdyb................... <R-all><W-NA>< VCC dependant > Ready Bar. When the supply is  
above the Power-On-Analog (POA) trip point, this bit is active LOW.  
Thus, this bit reads a logic One if the supply is below POA or too low  
to communicate over the 2-wire bus.  
•
Update....................... <R-all/W-all><00h> Status of completed conversions. At Power-On,  
these bits are cleared and will be set as each conversion is completed.  
These bits can be cleared so that a completion of a new conversion  
may be verified.  
a) Temp Rdy.......... Temperature conversion is ready.  
b)  
V Rdy............. V conversion is ready.  
CC CC  
c) Mon1 Rdy.......... Mon1 conversion is ready.  
d) Mon2 Rdy.......... Mon2 conversion is ready.  
e) Mon3 Rdy.......... Mon3 conversion is ready.  
Status  
•
Alarm0 ....................... <R-all><W-NA><10h> High Alarm Status bits.  
a) Temp Hi............. High Alarm Status for Temperature measurement.  
b) Temp Lo ............ Low Alarm Status for Temperature measurement.  
c)  
d)  
V
CC  
V
CC  
Hi .............. High Alarm Status for V measurement.  
CC  
Lo.............. Low Alarm Status for V measurement. This bit is set when theV  
CC  
CC  
CC  
supply is below the POA trip point value. It clears itself when a V  
measurement is completed and the value is above the low threshold.  
e) MON1 Hi........... High Alarm Status for MON1 measurement.  
f) MON1 Lo .......... Low Alarm Status for MON1 measurement.  
g) MON2 Hi........... High Alarm Status for MON2 measurement.  
h) MON2 Lo .......... Low Alarm Status for MON2 measurement.  
Alarm1 ....................... <R-all><W-NA><00h> Low Alarm Status bits.  
a) MON3 HI........... High Alarm Status for MON3 measurement.  
b) MON3 Lo .......... Low Alarm Status for MON3 measurement.  
c) Mint ................... Maskable Interrupt. If an alarm is present and the alarm is enabled then  
this bit is high. Otherwise this bit is a zero.  
•
•
•
Reserved.................... <R-all><W-NA><00h>.  
Warning0 ................... <R-all><W-NA><00h> High Warning Status bits.  
a) Temp Hi............. High Warning Status for Temperature measurement.  
b) Temp Lo ............ Low Warning Status for Temperature measurement.  
c)  
V
Hi ............. High Warning Status for VCC measurement.  
CC  
____________________________________________________________________ 21  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Register Descriptions (continued)  
d)  
V
Lo .............. Low Warning Status for VCC measurement. This bit is set when the V  
CC  
CC  
supply is below the POA trip point value. It clears itself when a V  
CC  
measurement is completed and the value is above the low threshold.  
e) MON1 Hi........... High Warning Status for MON1 measurement.  
f) MON1 Lo .......... Low Warning Status for MON1 measurement.  
g) MON2 Hi........... High Warning Status for MON2 measurement.  
h) MON2 Lo .......... Low Warning Status for MON2 measurement.  
•
Warning1 ................... <R-all><W-NA><00h> Low warning Status bits.  
a) MON3 HI........... High Warning Status for MON3 measurement.  
b) MON3 Lo........... Low Warning Status for MON3 measurement.  
Table Select  
•
•
Reserved.................... <R-NA><W-all><00h>  
PWE........................... <R-NA><W-all><FFFFFFFFh> Password Entry. There are two  
passwords for the DS1856. The lower level password (PW1) has  
all the access of a normal user plus those made available with PW1.  
The higher level password (PW2) has all of the access of PW1  
plus those made available with PW2. The value of the password reside  
in EE inside of PW2 memory.  
•
TBL Sel...................... <R-all/W-all><00h> Table Select. The upper memory tables of the  
DS1856 are accessible by writing the correct table value in this register.  
a
If the device is configured to have a Table 01h then writing a 00h or  
01h in this byte will access that table.  
Config0  
•
Mode.......................... <R-pw2/W-pw2><NV><03h>  
a) TEN.................... At Power-On this bit is HIGH, which enables autocontrol of the LUT.  
If this bit is written to a ZERO then the resistor values are writeable by  
the user and the LUT recalls are disabled. This allows the user to  
interactively test their modules by manually writing resistor values. The  
resistors will update with the new value at the end of the write cycle.  
Thus both registers (Res0 and Res1) should be written in the same  
write cycle. The 2-wire Stop condition is the end of the write cycle.  
b) AEN................... At Power-On this bit is HIGH, which enables autocontrol of the LUT.  
If this bit is cleared to a ZERO then the temperature calculated index  
value ( T index ) is writeable by the user and the updates of calculated  
indexes are disabled. This allows the user to interactively test their  
modules by controlling the indexing for the look-up tables. The recalled  
values from the LUTs will appear in the resistor registers after the next  
completion of a temperature conversion (just like it would happen in  
auto mode). Both pots will update at the same time (just like it would  
happen in auto mode).  
.
•
T Index....................... <R-pw2><W-pw2+AENb><00h> Holds the calculated index based on  
the Temperature Measurement. This index is used for the address  
during Look-up of Tables 4 and 5.  
22  
____________________________________________________________________  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Register Descriptions (continued)  
.
0
1
•
Res0........................... <R-pw2><W-pw2+TENb><FFh> The base value used for Resistor  
and recalled from Table 4 at the memory address found in T Index.  
This register is updated at the end of the Temperature conversion.  
•
•
Res1........................... <R-pw2><W-pw2+TENb><FFh> The base value used for Resistor  
and recalled from Table 5 at the memory address found in T Index.  
This register is updated at the end of the Temperature conversion.  
Reserved.................... <R-pw2><W-pw2><00h> SRAM.  
Config  
1
•
Int Enable.................. <R-pw2/W-pw2><NV><F8h> Configures the maskable interrupt for  
the Out1 pin.  
a) Temp Enable...... Temperature measurements, outside of the threshold limits, are enabled  
to create an active interrupt on the Out1 pin.  
b)  
V
CC  
Enable......... V measurements, outside of the threshold limits, are enabled to create  
CC  
an active interrupt on the Out1 pin.  
c) MON1 Enable.... MON1 measurements, outside of the threshold limits, are enabled to  
create an active interrupt on the Out1 pin.  
d) MON2 Enable.... MON2 measurements, outside of the threshold limits, are enabled to  
create an active interrupt on the Out1 pin.  
e) MON3 Enable.... MON3 measurements, outside of the threshold limits, are enabled to  
create an active interrupt on the Out1 pin.  
f) Reserved ............ EE.  
Config........................ <R-pw2/W-pw2><NV><00h> Configure the memory location and the  
polarity of the digital outputs.  
•
a) Reserved ............ EE.  
b) ADEN ................ Auxiliary Device ENable. 128 bytes of EE are addressable depending  
on the value of this bit. When set to a 1, the memory is located in or as  
Table 01h. When set to a 0, the memory is addressed by using a Device  
address of A0h and the locations in memory are 00h to 7Fh.  
c) ADFIX............... Device Fixable Address. When this bit is set to a 1, the main memory  
of the DS1856 is a Device Address equal to the value found in byte  
chip_address. When this bit is set to a 0 the main memory of the DS1856  
is a Device Address of A2h.  
d) Inv1.................... Enable the inversion of the relationship between IN1 and OUT1.  
e) Inv2.................... Enable the inversion of the relationship between IN2 and OUT2.  
•
•
Chip Address............. This value becomes the Device address for the main memory when  
ADFIX bit is set.  
Right Shift1 ................ Allows for right-shifting the final answer of some voltage  
measurements. This allows for scaling the measurements to the smallest  
full-scale voltage and then right-shifting the final result so the reading is  
weighted to the correct lsb.  
•
Right Shift0 ................ Allows for right-shifting the final answer of some voltage  
measurements. This allows for scaling the measurements to the smallest  
full-scale voltage and then right-shifting the final result so the reading is  
weighted to the correct lsb.  
____________________________________________________________________ 23  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Register Descriptions (continued)  
Scale0  
•
•
•
V
Scale................... <R-pw2/W-pw2><NV><6.5535V> Controls the Scaling or Gain of the  
CC  
V
measurements.  
CC  
MON1 Scale.............. <R-pw2/W-pw2><NV><2.500V> Controls the Scaling or Gain of the  
MON1 measurements.  
MON2 Scale.............. <R-pw2/W-pw2><2.500V> Controls the Scaling or Gain of the  
MON2 measurements.  
Scale1  
•
MON3 Scale.............. <R-pw2/W-pw2><NV><2.500V> Controls the Scaling or Gain of the  
MON3 measurements.  
Offset0  
•
•
•
V
Offset.................. <R-pw2/W-pw2><NV><0000h> Allows for offset control of V  
CC  
CC  
measurement if desired.  
MON1 Offset............. <R-pw2/W-pw2><NV><0000h> Allows for offset control of MON1  
measurement if desired.  
MON2 Offset............. <R-pw2/W-pw2><NV><0000h> Allows for offset control of MON2  
measurement if desired.  
Offset1  
•
MON3 Offset............. <R-pw2/W-pw2><NV><0000h> Allows for offset control of MON3  
measurement if desired.  
•
Temp Offset............... <R-pw2/W-pw2><NV><0000h> Allows for offset control of Temp  
measurement if desired.  
PWD Value  
•
Password 1................ <R-NA/W-pw2><NV><FFFFFFFFh> The PWE value is compared  
against the value written to this location to enable PW1 access. At  
power-on, the PWE value is set to all ones. Thus writing these bytes to  
all ones grants PW1 access on power-up without writing the password entry.  
Password 2................ <R-NA/W-pw2><NV><FFFFFFFFh> The PWE value is compared  
against the value written to this location to enable PW2 access. At  
•
power-on, the PWE value is set to all ones. Thus writing these bytes to  
all ones grants PW2 access on power-up without writing the password entry.  
LUT  
•
•
Res0........................... The unsigned value for Resistor 0.  
Res1........................... The unsigned value for Resistor 1.  
24  
____________________________________________________________________  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
To scale the gain and offset of the converter for a spe-  
cific input, you must first know the relationship between  
the analog input and the expected digital result. The  
input that would produce a digital result of all zeros is  
the null value (normally this input is GND). The input  
that would produce a digital result of all ones is the full-  
scale (FS) value. The FS value is also found by multiply-  
ing an all-ones digital answer by the weighted LSB  
(e.g., since the digital reading is a 16-bit register, let us  
assume that the LSB of the lowest weighted bit is  
50µV, then the FS value is 65,535 x 50µV = 3.27675V).  
Programming the Look-up Table (LUT)  
The following equation can be used to determine which  
resistor position setting, 00h to FFh, should be written in  
the LUT to achieve a given resistance at a specific tem-  
perature.  
2
R − u x 1+ v x C − 25 + w x C − 25  
(
)
(
)
pos α,R,C =  
−
(
)
2
x
( )  
x 1+ y x C − 25 + z x C − 25  
(
)
(
)
R = the resistance desired at the output terminal  
C = temperature in degrees Celsius  
A binary search is used to scale the gain of the con-  
verter. This requires forcing two known voltages to the  
input pin. It is preferred that one of the forced voltages  
is the null input and the other is 90% of FS. Since the  
LSB of the least significant bit in the digital reading reg-  
ister is known, the expected digital results are also  
known for both inputs (null/LSB = CNT1 and 90%FS/  
LSB = CNT2).  
u, v, w, x , x , y, z, and α are calculated values found in  
1
0
the corresponding look-up tables. The variable x from the  
equation above is separated into x (the MSB of x) and x  
1
0
(the LSB of x). Their addresses and LSB values are given  
below. The variable y is assigned a value. All other vari-  
ables are unsigned. Resistor 0 variables are found in  
Table 04, and Resistor 1 variables are found in Table 05.  
The user might not directly force a voltage on the input.  
Instead they have a circuit that transforms light, fre-  
quency, power, or current to a voltage that is the input  
to the DS1856. In this situation, the user does not need  
to know the relationship of voltage to expected digital  
result but instead knows the relationship of light, fre-  
quency, power, or current to the expected digital result.  
When shipped from the factory, all other memory loca-  
tions in the LUTs are programmed to FFh.  
Table 8. Calibration Constants  
ADDRESS  
F8h  
VARIABLE  
LSB  
0
u
v
2
An explanation of the binary search used to scale the  
gain is best served with the following example pseudo-  
code:  
F9h  
20E-6  
FAh  
w
100E-9  
1
FBh  
x
x
2
1
0
/* Assume that the null input is 0.5V. */  
-7  
FCh  
2
/* In addition, the requirement for LSB is 50µV. */  
2E-6 (signed)  
8E-6 (signed) for 2.5k resistor  
10E-9  
FS = 65535 x 50E-6;  
CNT1 = 0.5 / 50E-6;  
/* 3.27675 */  
/* 10000 */  
FDh  
y
FEh  
FFh  
z
CNT2 = 0.90 x FS / 50E-6;  
/* 58981.5 */  
-2  
2
α
/* Thus the null input 0.5V and the 90% of FS input is  
2.949075V. */  
Internal Calibration  
Set the trim-offset-register to zero;  
The DS1856 has two methods for scaling an analog  
input to a digital result. The two methods are gain and  
Set Right-Shift register to zero (typically zero.  
See the Right-Shifting section);  
offset. Each of the inputs (V , MON1, MON2, and  
CC  
MON3) has a unique register for the gain and the offset  
found in Table 03h, 92h to 99h, and A2h to A9h.  
gain_result = 0h;  
Clamp = FFF8h/2^(Right_Shift_Register);  
For n = 15 down to 0  
begin  
____________________________________________________________________ 25  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
gain_result = gain_result + 2^n;  
value can be right-shifted four times without losing reso-  
lution. Table 9 shows when the right-shifting method can  
be used.  
Force the 90% FS input (2.949075V);  
Meas2 = read the digital result from  
the part;  
Temperature Conversion  
The direct-to-digital temperature sensor measures tem-  
perature through the use of an on-chip temperature  
measurement technique with a -40°C to +102°C operat-  
ing range. Temperature conversions are initiated upon  
power-up, and the most recent conversion is stored in  
memory locations 60h and 61h of the Main Device,  
If Meas2 >= Clamp then  
gain_result = gain_result – 2^n;  
Else  
Force the null input (0.5V);  
Meas1 = read the digital result from  
the part;  
which are updated every t  
. Temperature conver-  
frame  
sions do not occur during an active read or write to  
memory.  
if (Meas2 – Meas1) > (CNT2 –  
CNT1) then  
The value of each resistor is determined by the tempera-  
ture-addressed look-up table. The look-up table assigns  
a unique value to each resistor for every 2°C increment  
with a 1°C hysteresis at a temperature transition over the  
operating temperature range (see Figure 4).  
gain_result = gain_result – 2^n;  
end;  
Set the gain register to gain_result;  
The gain register is now set and the resolution of the  
conversion will best match the expected LSB. The next  
step is to calibrate the offset of the DS1856. With the  
correct gain value written to the gain register, again  
force the null input to the pin. Read the digital result  
from the part (Meas1). The offset value is equal to the  
negative value of Meas1.  
Table 9. Right Shifting  
OUTPUT RANGE USED  
WITH ZERO RIGHT-SHIFTS  
NUMBER OF  
RIGHT-SHIFTS NEEDED  
0h....FFFFh  
0h....7FFFh  
0h....3FFFh  
0h....1FFFh  
0h....0FFFh  
0
1
2
3
4
Meas1  
4
Offset_Register=  
The calculated offset is now written to the DS1856 and  
the gain and offset scaling is now complete.  
M6  
M5  
Right-Shifting A/D Conversion Result  
(Scalable Dynamic Ranging)  
The right-shifting method is used to regain some of the  
lost ADC range of a calibrated system. If a system is cali-  
brated so the maximum expected input results in a digi-  
tal output value of less than 7FFFh (1/2 FS), then it is a  
candidate for using the right-shifting method.  
DECREASING  
TEMPERATURE  
M4  
M3  
M2  
M1  
If the maximum desired digital output is less than 7FFFh,  
then the calibrated system is using less than 1/2 of the  
ADC’s range. Similarly, if the maximum desired digital  
output is less than 1FFFh, then the calibrated system is  
only using 1/8 of the ADC’s range. For example, if using  
a zero for the right-shift during internal calibration and  
the maximum expected input results in a maximum digi-  
tal output less than 1FFCh, only 1/8 of the ADC’s range is  
used. If left like this, the three MS bits of the ADC will  
never be used. In this example, a value of 3 for the right-  
shifting maximizes the ADC range. No resolution is lost  
since this is a 12-bit converter that is left justified. The  
INCREASING  
TEMPERATURE  
2
4
6
8
10  
12  
TEMPERATURE (°C)  
Figure 4. Look-Up Table Hysteresis  
26  
____________________________________________________________________  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Standby Mode: The DS1856 features a low-power  
mode that is automatically enabled after power-on,  
after a STOP command, and after the completion of all  
internal operations.  
Power-Up and Low-Voltage Operation  
During power-up, the device is inactive until V  
CC  
exceeds the digital power-on-reset voltage (POD). At this  
voltage, the digital circuitry, which includes the 2-wire  
interface, becomes functional. However, EEPROM-  
backed registers/settings cannot be internally read  
Device Addressing: The DS1856 must receive an 8-bit  
device address, the slave address byte, following a  
START condition to enable a specific device for a read  
or write operation. The address is clocked into this part  
MSB to LSB. The address byte consists of either A2h or  
the value in Table 03, 8Ch for the Main Device or A0h  
for the Auxiliary Device, then the R/W bit. This byte  
must match the address programmed into Table 03,  
8Ch or A0h (for the Auxiliary Device). If a device  
address match occurs, this part will output a zero for  
one clock cycle as an acknowledge and the corre-  
sponding block of memory is enabled (see the Memory  
Organization section). If the R/W bit is high, a read  
operation is initiated. If the R/W is low, a write operation  
is initiated (see the Memory Organization section). If the  
address does not match, this part returns to a low-  
power mode.  
(recalled into shadow SRAM) until V  
exceeds the ana-  
CC  
log power-on-reset voltage (POA), at which time the  
remainder of the device becomes fully functional. Once  
V
CC  
exceeds POA, the RDYB bit in byte 6Eh of the Main  
Device memory is timed to go from a 1 to a 0 and indi-  
cates when analog-to-digital conversions begin. If V  
CC  
ever dips below POA, the RDYB bit reads as a 1 again.  
Once a device exceeds POA and the EEPROM is  
recalled, the values remain active (recalled) until V falls  
CC  
below POD.  
For 2-wire device addresses sourced from EEPROM  
(ADFIX = 1), the device address defaults to A2h until V  
CC  
exceeds POA and the EEPROM values are recalled. The  
Auxiliary Device (A0h) is always available within this volt-  
age window (between POD and the EEPROM recall)  
regardless of the programmed state of ADEN.  
Write Operations  
After receiving a matching address byte with the R/W  
bit set low, if there is no write protect, the device goes  
into the write mode of operation (see the Memory  
Organization section). The master must transmit an 8-  
bit EEPROM memory address to the device to define  
the address where the data is to be written. After the  
byte has been received, the DS1856 transmits a zero  
for one clock cycle to acknowledge the address has  
been received. The master must then transmit an 8-bit  
data word to be written into this address. The DS1856  
again transmits a zero for one clock cycle to acknowl-  
edge the receipt of the data. At this point, the master  
must terminate the write operation with a STOP condi-  
tion. The DS1856 then enters an internally timed write  
Furthermore, as the device powers up, the V lo alarm  
CC  
flag (bit 4 of 70h in Main Device) defaults to a 1 until the  
first V  
analog-to-digital conversion occurs and sets or  
CC  
clears the flag accordingly.  
2-Wire Operation  
Clock and Data Transitions: The SDA pin is normally  
pulled high with an external resistor or device. Data on  
the SDA pin may only change during SCL-low time  
periods. Data changes during SCL-high periods will  
indicate a START or STOP condition depending on the  
conditions discussed below. See the timing diagrams  
in Figures 5 and 6 for further details.  
START Condition: A high-to-low transition of SDA with  
SCL high is a START condition that must precede any  
other command. See the timing diagrams in Figures 5  
and 6 for further details.  
process t to the EEPROM memory. All inputs are dis-  
w
abled during this byte write cycle.  
Page Write  
The DS1856 is capable of an 8-byte page write. A page  
is any 8-byte block of memory starting with an address  
evenly divisible by eight and ending with the starting  
address plus seven. For example, addresses 00h  
through 07h constitute one page. Other pages would  
be addresses 08h through 0Fh, 10h through 17h, 18h  
through 1Fh, etc.  
STOP Condition: A low-to-high transition of SDA with  
SCL high is a STOP condition. After a read or write  
sequence, the stop command places the DS1856 into a  
low-power mode. See the timing diagrams in Figures 5  
and 6 for further details.  
Acknowledge: All address and data bytes are trans-  
mitted through a serial protocol. The DS1856 pulls the  
SDA line low during the ninth clock pulse to acknowl-  
edge that it has received each word.  
____________________________________________________________________ 27  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
A page write is initiated the same way as a byte write,  
but the master does not send a STOP condition after the  
first byte. Instead, after the slave acknowledges the  
data byte has been received, the master can send up to  
seven more bytes using the same nine-clock sequence.  
The master must terminate the write cycle with a STOP  
condition or the data clocked into the DS1856 will not be  
latched into permanent memory.  
address read by sending the device address with the  
R/W bit set high. The DS1856 acknowledges the device  
address and serially clocks out the data byte.  
Sequential Address Read  
Sequential reads are initiated by either a current  
address read or a random address read. After the mas-  
ter receives the first data byte, the master responds  
with an acknowledge. As long as the DS1856 receives  
this acknowledge after a byte is read, the master can  
clock out additional data words from the DS1856. After  
reaching address FFh, it resets to address 00h.  
The address counter rolls on a page during a write. The  
counter does not count through the entire address  
space as during a read. For example, if the starting  
address is 06h and 4 bytes are written, the first byte  
goes into address 06h. The second goes into address  
07h. The third goes into address 00h (not 08h). The  
fourth goes into address 01h. If 9 bytes or more are  
written before a STOP condition is sent, the first bytes  
sent are overwritten. Only the last 8 bytes of data are  
written to the page.  
The sequential read operation is terminated when the  
master initiates a STOP condition. The master does not  
respond with a zero.  
The following section provides a detailed description of  
the 2-wire theory of operation.  
2-Wire Serial-Port Operation  
Acknowledge Polling: Once the internally timed write  
has started and the DS1856 inputs are disabled,  
acknowledge polling can be initiated. The process  
involves transmitting a START condition followed by the  
device address. The R/W bit signifies the type of opera-  
tion that is desired. The read or write sequence will only  
be allowed to proceed if the internal write cycle has  
completed and the DS1856 responds with a zero.  
The 2-wire serial-port interface supports a bidirectional  
data transmission protocol with device addressing. A  
device that sends data on the bus is defined as a trans-  
mitter, and a device that receives data as a receiver.  
The device that controls the message is called a mas-  
ter. The devices that are controlled by the master are  
slaves. The bus must be controlled by a master device  
that generates the serial clock (SCL), controls the bus  
access, and generates the START and STOP condi-  
tions. The DS1856 operates as a slave on the 2-wire  
bus. Connections to the bus are made through the  
open-drain I/O lines SDA and SCL. The following I/O  
terminals control the 2-wire serial port: SDA, SCL.  
Timing diagrams for the 2-wire serial port can be found  
in Figures 5 and 6. Timing information for the 2-wire  
serial port is provided in the AC Electrical  
Characteristics table for 2-wire serial communications.  
Read Operations  
After receiving a matching address byte with the R/W bit  
set high, the device goes into the read mode of opera-  
tion. There are three read operations: current address  
read, random read, and sequential address read.  
Current Address Read  
The DS1856 has an internal address register that main-  
tains the address used during the last read or write  
operation, incremented by one. This data is maintained  
The following bus protocol has been defined:  
as long as V  
is valid. If the most recent address was  
CC  
• Data transfer may be initiated only when the bus is  
not busy.  
the last byte in memory, then the register resets to the  
first address.  
• During data transfer, the data line must remain sta-  
ble whenever the clock line is high. Changes in the  
data line while the clock line is high will be interpret-  
ed as control signals.  
Once the device address is clocked in and acknowl-  
edged by the DS1856 with the R/W bit set to high, the  
current address data word is clocked out. The master  
does not respond with a zero, but does generate a  
STOP condition afterwards.  
Accordingly, the following bus conditions have been  
defined:  
Single Read  
A random read requires a dummy byte write sequence to  
load in the data byte address. Once the device and data  
address bytes are clocked in by the master and acknowl-  
edged by the DS1856, the master must generate another  
START condition. The master now initiates a current  
Bus not busy: Both data and clock lines remain high.  
Start data transfer: A change in the state of the data  
line from high to low while the clock is high defines a  
START condition.  
28  
____________________________________________________________________  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Stop data transfer: A change in the state of the data  
line from low to high while the clock line is high defines  
the STOP condition.  
plished on the 2-wire bus. Depending on the state of the  
R/W bit, two types of data transfer are possible.  
Each data transfer is initiated with a START condition  
and terminated with a STOP condition. The number of  
data bytes transferred between START and STOP con-  
ditions is not limited and is determined by the master  
device. The information is transferred byte-wise and  
each receiver acknowledges with a ninth bit.  
Data valid: The state of the data line represents valid  
data when, after a START condition, the data line is sta-  
ble for the duration of the high period of the clock signal.  
The data on the line can be changed during the low peri-  
od of the clock signal. There is one clock pulse per bit of  
data. Figures 5 and 6 detail how data transfer is accom-  
SDA  
MSB  
SLAVE ADDRESS  
R/W  
ACKNOWLEDGEMENT  
SIGNAL FROM RECEIVER  
DIRECTION  
BIT  
ACKNOWLEDGEMENT  
SIGNAL FROM RECEIVER  
SCL  
1
2
6
7
8
9
1
2
3–7  
8
9
ACK  
ACK  
START  
CONDITION  
STOP  
CONDITION  
OR REPEATED  
START  
REPEATED IF MORE BYTES  
ARE TRANSFERRED  
CONDITION  
Figure 5. 2-Wire Data Transfer Protocol  
SDA  
t
BUF  
t
SP  
t
HD:STA  
t
LOW  
t
t
F
R
SCL  
t
SU:STA  
t
HD:STA  
t
HIGH  
t
REPEATED  
START  
t
SU:DAT  
SU:STO  
STOP  
START  
t
HD:DAT  
Figure 6. 2-Wire AC Characteristics  
____________________________________________________________________ 29  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Within the bus specifications, a standard mode  
(100kHz clock rate) and a fast mode (400kHz clock  
rate) are defined. The DS1856 works in both modes.  
The master device generates all serial clock pulses and  
the START and STOP conditions. A transfer is ended with  
a STOP condition or with a repeated START condition.  
Since a repeated START condition is also the beginning  
of the next serial transfer, the bus is not released.  
Acknowledge: Each receiving device, when addressed,  
is obliged to generate an acknowledge after the byte has  
been received. The master device must generate an  
extra clock pulse, which is associated with this acknowl-  
edge bit.  
The DS1856 can operate in the following two modes:  
1) Slave Receiver Mode: Serial data and clock are  
received through SDA and SCL, respectively. After  
each byte is received, an acknowledge bit is trans-  
mitted. START and STOP conditions are recog-  
nized as the beginning and end of a serial transfer.  
Address recognition is performed by hardware  
after the slave (device) address and direction bit  
have been received.  
A device that acknowledges must pull down the SDA line  
during the acknowledge clock pulse in such a way that  
the SDA line is a stable low during the high period of the  
acknowledge-related clock pulse. Setup and hold times  
must be taken into account. A master must signal an end  
of data to the slave by not generating an acknowledge bit  
on the last byte that has been clocked out of the slave. In  
this case, the slave must leave the data line high to  
enable the master to generate the STOP condition.  
2) Slave Transmitter Mode: The first byte is  
received and handled as in the slave receiver  
mode. However, in this mode the direction bit  
indicates that the transfer direction is reversed.  
Serial data is transmitted on SDA by the DS1856,  
while the serial clock is input on SCL. START and  
STOP conditions are recognized as the beginning  
and end of a serial transfer.  
1) Data transfer from a master transmitter to a  
slave receiver. The first byte transmitted by the  
master is the command/control byte. Next follows  
a number of data bytes. The slave returns an  
acknowledge bit after each received byte.  
2) Data transfer from a slave transmitter to a mas-  
ter receiver. The master transmits the first byte  
(the command/control byte) to the slave. The slave  
then returns an acknowledge bit. Next follows a  
number of data bytes transmitted by the slave to  
the master. The master returns an acknowledge bit  
after all received bytes other than the last byte. At  
the end of the last received byte, a not acknowl-  
edge can be returned.  
30  
____________________________________________________________________  
Dual, Temperature-Controlled Resistors with Inter-  
nally Calibrated Monitors and Password Protection  
Ordering Information (continued)  
RES0/RES1  
RESISTANCE  
(kΩ)  
RES0/RES1  
RESISTANCE  
(kΩ)  
PART  
PIN-PACKAGE  
PART  
PIN-PACKAGE  
DS1856E-030+T&R*  
DS1856B-030+*  
DS1856B-030+T&R*  
DS1856E-002  
30/10  
30/10  
16 TSSOP  
DS1856B-050/T&R  
DS1856E-050+  
50/50  
50/50  
50/50  
50/50  
50/50  
20/20  
20/20  
20/20  
20/20  
20/20  
20/20  
20/20  
20/20  
30/10  
30/10  
30/10  
30/10  
30/10  
16-Ball CSBGA  
16 TSSOP  
16-Ball CSBGA  
16-Ball CSBGA  
16 TSSOP  
30/10  
DS1856E-050+T&R  
DS1856B-050+  
16 TSSOP  
10/2.5  
10/2.5  
10/2.5  
10/2.5  
10/2.5  
10/2.5  
10/2.5  
10/2.5  
2.5/2.5  
2.5/2.5  
2.5/2.5  
2.5/2.5  
2.5/2.5  
2.5/2.5  
2.5/2.5  
2.5/2.5  
16-Ball CSBGA  
16-Ball CSBGA  
16 TSSOP  
DS1856E-002/T&R  
DS1856B-002  
16 TSSOP  
DS1856B-050+T&R  
DS1856E-020*  
16-Ball CSBGA  
16-Ball CSBGA  
16 TSSOP  
DS1856B-002/T&R  
DS1856E-002+  
DS1856E-020/T&R*  
DS1856B-020*  
16 TSSOP  
16-Ball CSBGA  
16-Ball CSBGA  
16 TSSOP  
DS1856E-002+T&R  
DS1856B-002+  
16 TSSOP  
DS1856B-020/T&R*  
DS1856E-020+*  
DS1856E-020+T&R*  
DS1856B-020+*  
DS1856B-020+T&R*  
DS1856E-030*  
16-Ball CSBGA  
16-Ball CSBGA  
16 TSSOP  
DS1856B-002+T&R  
DS1856E-025  
16 TSSOP  
16-Ball CSBGA  
16-Ball CSBGA  
16 TSSOP  
DS1856E-025/T&R  
DS1856B-025  
16 TSSOP  
16-Ball CSBGA  
16-Ball CSBGA  
16 TSSOP  
DS1856B-025/T&R  
DS1856E-025+  
DS1856E-030/T&R*  
DS1856B-030*  
16 TSSOP  
16-Ball CSBGA  
16-Ball CSBGA  
16 TSSOP  
DS1856E-025+T&R  
DS1856B-025+  
16 TSSOP  
DS1856B-030/T&R*  
DS1856E-030+*  
16-Ball CSBGA  
16-Ball CSBGA  
DS1856B-025+T&R  
+Denotes lead free.  
*Future product—contact factory for availability.  
T&R denotes tape-and-reel.  
All parts operate at the -40°C to +95°C temperature range.  
Chip Information  
TRANSISTOR COUNT: 51,061  
SUBSTRATE CONNECTED TO GROUND  
Package Information  
For the latest package outline information, go to  
www.maxim-ic.com/DallasPackInfo.  
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are  
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.  
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31  
© 2005 Maxim Integrated Products  
Printed USA  
is a registered trademark of Maxim Integrated Products, Inc.  
DALLAS is a registered trademark of Dallas Semiconductor Corporation.  

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