DS1830S [MAXIM]
Power Supply Support Circuit, Fixed, 1 Channel, +4.62VV, PDSO8, 0.150 INCH, SOIC-8;
| 型号： | DS1830S |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Power Supply Support Circuit, Fixed, 1 Channel, +4.62VV, PDSO8, 0.150 INCH, SOIC-8 输入元件 光电二极管 |
| 文件： | 总7页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1830/A
Reset Sequence Pushbutton
www.maxim-ic.com
FEATURES
C 5V (DS1830) or 3.3V (DS1830A) power-on
reset
PIN ASSIGNMENT
C Excellent for systems that need power-on
resets in a consistent sequence
C Asserts resets during power transients
C Pushbutton reset input for system override
C Selectable reset timing
C Reduces need for discrete components
C Precision temperature-compensated voltage
reference
C 8-pin DIP, 8-pin SO, or space saving 8-pin
µSOP
C Operating temperature of -40°C to +85°C
C Open-drain, active-low inputs
PIN DESCRIPTION
- Pushbutton Reset Input
- Time Delay Select Input
- VCC Tolerance Select Input
- Ground
1 PBRST
2 TD
3 TOL
4 GND
8 VCC
- Power Supply
- Reset 1 Output
7 RST1
6 RST2
5 RST3
- Reset 2 Output
- Reset 3 Output
DESCRIPTION
The DS1830 Reset Sequencer monitors the power supply for an in-tolerance condition and the pushbutton
reset input for a manual reset. First a precision temperature-compensated reference and comparator circuit
monitors the status of the power supply and when an out-of-tolerance condition is detected, an internal
power fail signal is generated that forces the reset lines to go to an active state. If the power supply
returns to an in-tolerance condition, RST1 will release followed by RST2 and finally RST3 . Sequencing of
resets allows for systems to power-up in an orderly manner providing superior reliability.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any
device may be simultaneously available through various sales channels. For information about device errata, click here: http://dbserv.maxim-
ic.com/errata.cfm.
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060303
D1830/A
OPERATION — POWER MONITOR
The DS1830 provides the functions of detecting out-of-tolerance conditions on a power supply and
warning a processor based system of impending power failure. When VCC is detected as out-of-tolerance
all reset outputs will be forced active. When VCC returns to a valid state, RST1 will remain active for
period of time based on the condition of the TD input. Reset outputs RST2 and RST3 follow RST1 , each
one at the proper delays for the condition of the TD input. All resets will remain in the inactive state
(high) until the next VCC out-of-tolerance condition or pushbutton reset. On power-up all resets are kept
active for an appropriate period determined by the status of the TD input after the power supply inputs
have reached the selected tolerance. This allows the power supply and system power to stabilize before
the reset sequences are released.
BLOCK DIAGRAM Figure 1
OPERATION — TOLERANCE SELECT
The DS1830/A provides a TOL input for individual customization of the DS1830x to specific application
requirements (see Table 1). For the tolerance selection, see Table 1 below. The TOL input is only
sampled while VCC is below the lowest potential trip value and can not be changed after the VCC voltage
exceeds the lowest potential trip value.
TOL — TOLERANCE SELECT Table 1
TOL
VCC
GND
OPEN
(N.C.)
5V (DS1830)
5%
3.3V (DS1830A)
5%
10%
10%
15%
20%
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D1830/A
OPERATION — PUSHBUTTON RESET
The DS1830 provides a pushbutton switch for manual reset control. When any of the DS1830/A resets
are not active (low) a reset cycle can be initiated by a pushbutton reset. The pushbutton reset is generated
by pulling the PBRST pin low for at least 1ms. When the push- button is held low all resets are forced
active. The reset will remain active until the pushbutton input is released and then will start a sequenced
time-out based on the condition of the TD input. The Pushbutton input is pulled high through an internal
40kꢀ pull-up resistor and debounced via internal circuitry. See Figure 2 for an application example and
Figure 3 for the timing diagram.
PUSHBUTTON RESET Figure 2
TIMING DIAGRAM — PUSHBUTTON RESET Figure 3
OPERATION — TIME DELAY SELECT
The DS1830 provides an input to select three time delay characteristics for the reset outputs. The TD
input has 3 states high (VCC), low (ground) and no connect (N.C.). Table 2 details the minimum timing
based on the state of the TD input. If the TD input is connected to ground; RST1 will have a minimum
time delay of 10 ms after VCC is in tolerance. If the TD input is floated; RST1 will have a minimum time
delay of 20 ms after VCC is in tolerance. If the TD input is connected to VCC, RST1 will have a minimum
time delay of 50 ms after VCC is in tolerance. An oscillator and clock chain generate the reset timing with
each time delay based on the same device oscillator. The time delay for RST2 will be 5 times as long as
RST1 and RST3 will be 10 times the duration of RST1 .
TD CONTROL MINIMUM RESET TIMING Table 2
T
T
T
TD
RST1
RST2
RST3
TD = GND
TD = N.C.
TD = VCC
10ms
20ms
50ms
50ms
100ms
250ms
100ms
200ms
500ms
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D1830/A
APPLICATION DIAGRAM — CASCADE DELAY CONFIGURATIONS Figure 4
MASTER
SEE NOTE 2
SEE NOTE 1
SLAVE
SEE NOTE 2
Note 1: The RST3 output tied to the pushbutton reset would be pulled to VCC through the 40kꢀ resistor in
the pushbutton input. If a stronger pull-up is required an additional pull-up resistor could be added.
Note 2: When using the cascade configuration, it is important that the TOL pins of the master and the
slave are configured so that the master’s VCCTP is greater than the slave’s VCCTP. This will ensure that
when the master’s higher VCCTP is crossed, the resets will ripple through to the slave.
TIMING DIAGRAM — POWER-DOWN Figure 5
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D1830/A
TIMING DIAGRAM — POWER-UP Figure 6
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to
Ground
-0.5V to +6.0V
Operating Temperature
Storage Temperature
Soldering Temperature
-40°C to +85°C
-55°C to +125°C
See IPC/JEDEC J-STD-020A
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (-40°C to +85°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
VCC
Supply Voltage
1.0
5.5
V
V
1
PBRST Input High
VIH
VCC + 0.3
2.0
Level
PBRST Input Low
Level
VIL
-0.3
+0.5
V
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D1830/A
DC ELECTRICAL CHARACTERISTICS (-40°C to +85°C; VCC = 1.0V to 5.5V)
PARAMETER
VCC Trip Point (TOL=
VCC) DS1830
SYMBOL MIN TYP MAX UNITS NOTES
VCCTP
VCCTP
VCCTP
VCCTP
VCCTP
VCCTP
4.50
4.25
4.00
2.98
2.80
2.47
4.62 4.74
4.37 4.49
4.13 4.24
3.06 3.15
2.88 2.97
V
V
V
V
V
V
VCC Trip Point
(TOL=GND) DS1830
VCC Trip Point
(TOL=Open) DS1830
VCC Trip Point (TOL=
VCC) DS1830A
VCC Trip Point
(TOL=GND) DS1830A
VCC Trip Point
2.55 2.64
+1.0
(TOL=Open) DS1830A
Input Leakage
IIL
-1.0
20
µA
mA
2
3
IOL
Output Current @ 0.4V
Operating Current
(Standby)
DS1830
18
10
35
25
ICC
µA
4
DS1830A
AC ELECTRICAL CHARACTERISTICS (-40°C to +85°C; VCC = 1.0V to 5.5V)
PARAMETER
SYMBOL MIN TYP MAX UNITS NOTES
tPB
tPDLY
10
PBRST = VIL
ms
RESET Active Time
(RST1 /TD =GND)
RESET Active Time
(RST1 /TD =Float)
RESET Active Time
(RST1 /TD = VCC)
RESET Active Time
(RST2 )
RESET Active Time
(RST3 )
VCC Detect to RST
VCC Slew Rate
tRST1
15
30
75
20
40
ms
tRST1
tRST1
tRST2
tRST3
20
50
ms
ms
ms
ms
100
5x
t
RST1
10x
t
RST1
5
tRPD
tF
8
µs
µs
5
6
20
See RESET Active
Times
VCC Detect to RST
VCC Slew Rate
PBRST Stable Low to
tRPU
tR
ms
ns
7
0
tPDLY
1.0
1.5
2.0
ms
RST
CAPACITANCE (TA = +25°C)
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL MIN TYP MAX UNITS NOTES
CIN
5
7
pF
pF
COUT
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D1830/A
NOTES:
1. All voltages are referenced to ground.
2. PBRST is internally pulled up to VCC with an internal impedance of 40kꢀ typical.
3. Measured with PBRST = VCC and RST1 , RST2 , and RST3 open.
4. Measured with outputs open and all inputs at VCC or Ground (except TD and TOL can be floating).
5. Noise Immunity - Pulses < 2ms at V
minimum will not cause a reset.
CC TP
6. The tF value is for reference in defining values for tRPD and should not be considered a requirement for
proper operation or use of the device.
7. See tRST1, tRST2, and tRST3 for specific tRPU AC timing parameters.
ORDERING INFORMATION
PART #
PIN PACKAGE
8-DIP 300-MIL
8-SO 150-MIL
8-µSOP 118-MIL
8-DIP 300-MIL
8-SO 150-MIL
8-µSOP 118-MIL
TEMP
TYPE
DS1830
5V Reset Sequencer
5V Reset Sequencer
5V Reset Sequencer
3.3V Reset Sequencer
3.3V Reset Sequencer
3.3V Reset Sequencer
-40LC to +85LC
-40LC to +85LC
-40LC to +85LC
-40LC to +85LC
-40LC to +85LC
-40LC to +85LC
DS1830S
DS1830U
DS1830A
DS1830AS
DS1830AU
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