DS1744-70IND+ [MAXIM]
Y2K-Compliant, Nonvolatile Timekeeping RAMs; Y2K兼容，非易失时钟RAM
| 型号： | DS1744-70IND+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Y2K-Compliant, Nonvolatile Timekeeping RAMs |
| 文件： | 总16页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5502; Rev 9/10
DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
www.maxim-ic.com
FEATURES
PIN CONFIGURATIONS
. Integrated NV SRAM, Real-Time Clock,
Crystal, Power-Fail Control Circuit, and
Lithium Energy Source
. Clock Registers are Accessed Identically to
the Static RAM. These Registers are Resident
in the Eight Top RAM Locations.
. Century Byte Register (i.e., Y2K Compliant)
. Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
. BCD-Coded Century, Year, Month, Date,
Day, Hours, Minutes, and Seconds with
Automatic Leap-Year Compensation Valid
Up to the Year 2100
TOP VIEW
1
2
3
4
5
6
7
8
28 VCC
A14
A12
A7
A6
A5
A4
A3
A2
A1
DS1744
27
26
25
24
23
22
21
20
19
18
17
16
15
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
9
10
11
12
13
14
A0
DQ0
DQ1
DQ2
GND
. Battery Voltage-Level Indicator Flag
. Power-Fail Write Protection Allows for ±10%
EDIP
VCC Power-Supply Tolerance
. Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
. DIP Module Only
Standard JEDEC Byte-Wide 32k x 8 Static
RAM Pinout
. PowerCap Module Board Only
Surface-Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
Replaceable Battery (PowerCap)
Power-On Reset Output
Pin-for-Pin Compatible with Other Densities
of DS174xP Timekeeping RAM
. Also Available in Industrial Temperature
Range: -40°C to +85°C
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
N.C.
N.C.
N.C.
N.C.
RST
VCC
1
N.C.
A14
A13
A12
A11
A10
A9
2
3
DS1744P
4
5
6
7
8
9
10
11
12
13
14
15
16
17
WE
OE
CE
A8
DQ7
A7
A6
A5
A4
A3
A2
A1
A0
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
VBAT
X2
GND
X1
PowerCap MODULE BOARD
(Uses DS9034PCX PowerCap)
. UL Recognized
1 of 18
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PIN DESCRIPTION
PIN
PowerCap
32
NAME
FUNCTION
EDIP
1
A14
A12
A7
2
3
30
25
4
24
A6
5
23
A5
6
22
A4
7
21
A3
Address Input
8
20
A2
9
19
A1
10
21
23
24
25
26
11
12
13
15
16
17
18
19
14
18
28
29
27
26
31
16
15
14
13
12
11
10
9
17
A0
A10
A11
A9
A8
A13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
GND
Data Input/Output
Ground
20
22
8
7
CE
OE
Active-Low Chip-Enable Input
Active-Low Output-Enable Input
Active-Low Write-Enable Input
27
28
6
5
WE
VCC
Power-Supply Input
Active-Low Reset Output, Open Drain. Requires a pullup resistor for
proper operation.
—
—
—
4
RST
1, 2, 3, 33,
34
N.C.
No Connection
X1, X2,
VBAT
Crystal Connections, VBAT Battery Connection
2 of 16
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ORDERING INFORMATION
VOLTAGE
PART
TEMP RANGE
PIN-PACKAGE
TOP MARK**
(V)
DS1744-70+
5.0
5.0
3.3
3.3
5.0
5.0
3.3
3.3
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
28 EDIP
28 EDIP
28 EDIP
28 EDIP
34 PowerCap*
34 PowerCap*
34 PowerCap*
34 PowerCap*
DS1744+70
DS1744-70IND+
DS1744W-120+
DS1744W-120IND+
DS1744P-70+
DS1744P-70IND+
DS1744WP-120+
DS1744WP-120IND+
DS1744+70 IND
DS1744W+120
DS1744W+120 IND
DS1744P+70
DS1744P+70 IND
DS1744WP+120
DS1744WP+120 IND
+Denotes a lead(Pb)-free/RoHS-compliant package.
*DS9034-PCX+ or DS9034I-PCX+ required (must be ordered separately).
**A “+” anywhere in the top mark denotes a lead-free device. An “IND” denotes an industrial temperature grade device.
DESCRIPTION
The DS1744 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 32k x 8
NV SRAM. User access to all registers within the DS1744 is accomplished with a byte-wide interface as
shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM locations.
The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour
BCD format. Corrections for the date of each month and leap year are made automatically. The RTC clock
registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles.
The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by
access to time register data. The DS1744 also contains its own power-fail circuitry that deselects the
device when the VCC supply is in an out-of-tolerance condition. This feature prevents loss of data from
unpredictable system operation brought on by low VCC as errant access and update cycles are avoided.
3 of 16
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Figure 1. DS1744/DS1744P Block Diagram
DS1744/DS1744P
PACKAGES
The DS1744 is available in two packages (28-pin encapsulated DIP and 34-pin PowerCap module). The
28-pin EDIP module integrates the crystal, lithium energy source, and silicon all in one package. The 34-
pin PowerCap module board is designed with contacts for connection to a separate PowerCap
(DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on
top of the DS1744P after the completion of the surface-mount process. Mounting the PowerCap after the
surface-mount process prevents damage to the crystal and battery due to the high temperatures required
for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and
PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1744 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, bit 6 of the century register (Table 2). As long as a
1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is,
day, date, and time that was current at the moment the halt command was issued. However, the internal
clock registers of the double-buffered system continue to update so that the clock accuracy is not affected
by the access of data. All the DS1744 registers are updated simultaneously after the internal clock-register
updating process has been re-enabled. Updating is within a second after the read bit is written to 0. The
READ bit must be a 0 for a minimal of 500s to ensure the external registers are updated.
4 of 16
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 1. Truth Table
CE
OE
WE
VCC
MODE
DQ
POWER
VIH
VIL
VIL
VIL
X
X
X
VIL
VIH
X
X
VIL
VIH
VIH
X
Deselect
Write
Read
Read
Deselect
Deselect
High-Z
Data In
Data Out
High-Z
High-Z
High-Z
Standby
Active
Active
VCC > VPF
Active
CMOS Standby
Data-Retention Mode
VSO < VCC < VPF
VCC < VSO < VPF
X
X
X
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read
bit, halts updates to the DS1744 registers. The user can then load them with the correct day, date, and time
data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock
counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator can be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers (Table
2). Setting it to a 1 stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic 1 and the oscillator is running, the LSB of the seconds register toggles at 512Hz. When the seconds
register is being read, the DQ0 line toggles at the 512Hz frequency as long as conditions for access remain
valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and stable).
CLOCK ACCURACY (DIP MODULE)
The DS1744 is guaranteed to keep time accuracy to within 1 minute per month at +25C. The RTC is
calibrated at the factory by Maxim using nonvolatile tuning elements, and does not require additional
calibration. For this reason, methods of field clock calibration are not available and not necessary. Clock
accuracy is also affected by the electrical environment; caution should be taken to place the RTC in the
lowest-level EMI section of the PC board layout. For additional information, refer to Application Note 58:
Crystal Considerations with Dallas Real-Time Clocks.
CLOCK ACCURACY (PowerCap MODULE)
The DS1744 and DS9034PCX are individually tested for accuracy. Once mounted together, the module
typically keeps time accuracy to within 1.53 minutes per month (35ppm) at +25°C. Clock accuracy is
also affected by the electrical environment and caution should be taken to place the RTC in the lowest-
level EMI section of the PC board layout. For additional information, refer to Application Note 58:
Crystal Considerations with Dallas Real-Time Clocks.
5 of 16
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 2. Register Map
DATA
B4
ADDRESS
FUNCTION RANGE
B7
B6
B5
X
B3
B2
B1
B0
7FFF
7FFE
10 Year
Year
Year
00-99
01-12
10
Month
X
X
Month
Date
Month
7FFD
7FFC
7FFB
7FFA
7FF9
7FF8
X
BF
X
X
OSC
W
X
FT
X
10 Date
Date
Day
Hour
Minutes
Seconds
Century
01-31
01-07
00-23
00-59
00-59
00-39
X
X
X
Day
10 Hour
10 Minutes
10 Seconds
Hour
Minutes
Seconds
Century
R
10 Century
R = Read Bit
X = See Note
FT = Frequency Test
BF = Battery Flag
OSC = Stop Bit
W = Write Bit
Note: All indicated “X” bits are not used but must be set to a “0” during write cycle to ensure proper
clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1744 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and
CE (chip enable) is low. The device architecture allows ripple-through access to any of the address
locations in the NV SRAM. Valid data is available at the DQ pins within tAA after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and
states are not met, valid data is available at the latter of chip-enable access (tCEA) or at output-enable access
time (tOEA). The state of the DQ pins is controlled by CE and OE . If the outputs are activated before tAA
,
the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and
OE remain valid, output data remains valid for output-data hold time (tOH) but then goes indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1744 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal is high during a write cycle. However, OE can be active provided that
care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low, the
data bus can become active with read data defined by the address inputs. A low transition on WE then
disables the output tWEZ after WE goes active.
6 of 16
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DATA-RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF
.
However, when VCC is below the power-fail point, VPF (point at which write protection occurs), the
internal clock registers and SRAM are blocked from any access. At this time the power-fail reset-output
signal (RST ) is driven active and remains active until VCC returns to nominal levels. When VCC falls
below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to the
backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to
nominal levels. The 3.3V device is fully accessible, and data can be written or read only when VCC is
greater than VPF When VCC falls below VPF access to the device is inhibited. At this time the power-fail
.
reset-output signal (RST ) is driven active and remains active until VCC returns to nominal levels. If VPF is
less than VSO, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below
VPF If VPF is greater than VSO, the device power is switched from VCC to the backup supply (VBAT) when
.
VCC drops below VSO. RTC operation and SRAM data are maintained from the battery until VCC is
returned to nominal levels. The RST signal is an open-drain output and requires a pullup. Except for the
RST , all control, data, and address signals must be powered down when VCC is powered down.
BATTERY LONGEVITY
The DS1744 has a lithium power source that is designed to provide energy for clock activity and clock and
RAM data retention when the VCC supply is not present. The capability of this internal power supply is
sufficient to power the DS1744 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at +25C with the internal clock oscillator running
in the absence of VCC power. Each DS1744 is shipped from Maxim with its lithium energy source
disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the
lithium energy source is enabled for battery-backup operation. Actual life expectancy of the DS1744 is
much longer than 10 years since no lithium battery energy is consumed when VCC is present.
BATTERY MONITOR
The DS1744 constantly monitors the battery voltage of the internal battery. The battery flag bit (bit 7) of
the day register is used to indicate the voltage-level range of the battery. This bit is not writable and should
always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated, and both
the contents of the RTC and RAM are questionable.
7 of 16
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………..…….…...……..……..……...……………..…-0.3V to +6.0V
Storage Temperature Range
EDIP..........................……………………..………………………………………………………...-40°C to +85°C
PowerCap..................……………………..……………………………………………………….-55°C to +125°C
Lead Temperature (soldering, 10s)……….................................................................………………………………..+260°C
Note: EDIP is hand or wave-soldered only.
Soldering Temperature (reflow, PowerCap).................................................................................................................+260°C
This is a stress rating only and functional operation of the device at these or any other condition beyond those indicated in the operation sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
OPERATING RANGE
RANGE
Commercial
Industrial
TEMP RANGE
VCC
0°C to +70°C, Noncondensing
-40°C to +85°C, Noncondesnsing
3.3V 10% or 5V10%
3.3V 10% or 5V10%
RECOMMENDED DC OPERATING CONDITIONS
(TA = Over the operating range)
PARAMETER
SYMBOL
VIH
MIN
2.2
TYP
MAX
UNITS NOTES
Logic 1 Voltage (All Inputs)
VCC = 5V 10%
VCC = 3.3V 10%
Logic 0 Voltage (All Inputs)
VCC = 5V 10%
VCC = 3.3V 10%
VCC + 0.3V
VCC + 0.3V
0.8
V
V
V
V
1
VIH
2.0
VIL
-0.3
0.3
VIL
0.6
1
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V 10%, TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Active Supply Current
TTL Standby Current
ICC
75
mA
mA
2, 3, 10
2, 3
ICC1
6
(CE = VIH)
CMOS Standby Current
Icc2
IIL
4
mA
2, 3
(CE VCC - 0.2V)
Input Leakage Current (Any
Input)
Output Leakage Current
(Any Output)
-1
-1
+1
+1
A
A
IOL
Output Logic 1 Voltage
(IOUT = -1.0mA)
Output Logic 0 Voltage
(IOUT = +2.1mA)
VOH
VOL
2.4
1
1
0.4
Write Protection Voltage
VPF
VSO
4.25
4.50
V
1
Battery Switchover Voltage
VBAT
1, 4
8 of 16
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V 10%, TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX UNITS NOTES
Active Supply Current
TTL Standby Current
ICC
30
2
mA
mA
2, 3, 10
2, 3
ICC1
ICC2
(CE = VIH)
CMOS Standby Current
2
mA
2, 3
(CE VCC - 0.2V)
Input Leakage Current (Any
Input)
Output Leakage Current
(Any Output)
IIL
-1
-1
+1
+1
A
A
IOL
Output Logic 1 Voltage
(IOUT = -1.0mA)
Output Logic 0 Voltage
(IOUT = +2.1mA)
VOH
VOL
VPF
2.4
1
1
1
0.4
Write Protection Voltage
2.80
2.97
V
V
VBAT
or
Battery Switchover Voltage
VSO
1, 4
VPF
AC CHARACTERISTICS—READ CYCLE (5V)
(VCC = 5.0V 10%, TA = Over the operating range.)
PARAMETER
Read Cycle Time
SYMBOL
tRC
MIN
TYP
MAX
UNITS NOTES
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAA
70
tCEL
5
5
5
CE to DQ Low-Z
CE Access Time
tCEA
tCEZ
70
25
CE Data Off Time
OE to DQ Low-Z
OE Access Time
tOEL
tOEA
tOEZ
35
25
OE Data Off Time
Output Hold from Address
tOH
9 of 16
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC CHARACTERISTICS—READ CYCLE (3.3V)
(VCC = 3.3V 10%, TA = Over the operating range.)
PARAMETER
Read Cycle Time
SYMBOL
tRC
MIN
TYP
MAX
UNITS
ns
NOTES
120
Address Access Time
tAA
120
ns
tCEL
5
5
5
ns
CE to DQ Low-Z
CE Access Time
tCEA
tCEZ
120
40
ns
ns
CE Data Off Time
OE to DQ Low-Z
tOEL
ns
tOEA
tOEZ
100
35
ns
OE Access Time
ns
OE Data Off Time
Output Hold from Address
tOH
ns
READ CYCLE TIMING DIAGRAM
10 of 16
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC CHARACTERISTICS—WRITE CYCLE (5V)
(VCC = 5.0V 10%, TA = Over the operating range.)
PARAMETER
Write Cycle Time
SYMBOL
tWC
MIN
70
0
TYP
MAX
UNITS
ns
NOTES
Address Setup Time
tAS
ns
tWEW
tCEW
tDS
50
60
30
0
ns
WE Pulse Width
CE Pulse Width
Data Setup Time
Data Hold Time
Data Hold Time
Address Hold Time
Address Hold Time
ns
ns
tDH1
ns
8
9
8
9
tDH2
0
ns
tAH1
5
ns
tAH2
5
ns
tWEZ
tWR
25
ns
WE Data Off Time
Write Recovery Time
5
ns
AC CHARACTERISTICS—WRITE CYCLE (3.3V)
(VCC = 3.3V 10%, TA = Over the operating range.)
PARAMETER
Write Cycle Time
SYMBOL
tWC
MIN
120
0
TYP
MAX
UNITS
ns
NOTES
Address Setup Time
tAS
120
ns
tWEW
tCEW
tCEW
tDS
100
110
110
80
0
ns
WE Pulse Width
CE Pulse Width
ns
ns
CE and CE2 Pulse Width
Data Setup Time
Data Hold Time
ns
tDH1
ns
8
9
8
9
Data Hold Time
tDH2
0
ns
Address Hold Time
Address Hold Time
tAH1
0
ns
tAH2
10
ns
tWEZ
40
ns
WE Data Off Time
Write Recovery Time
tWR
10
ns
11 of 16
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
WRITE CYCLE TIMING DIAGRAM, WRITE-ENABLE CONTROLLED
WRITE CYCLE TIMING DIAGRAM, CHIP-ENABLE CONTROLLED
12 of 16
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
POWER-UP/DOWN AC CHARACTERISTICS (5V)
(VCC = 5.0V 10%, TA = Over the operating range.)
PARAMETER
SYMBOL
tPD
tF
tFB
tR
MIN
0
TYP
MAX
UNITS NOTES
s
s
CE or WE at VIH Before Power-Down
VCC Fall Time: VPF(MAX) to VPF(MIN)
300
VCC Fall Time: VPF(MIN) to VSO
VCC Rise Time: VPF(MIN) to VPF(MAX)
Power-Up Recover Time
10
0
s
s
tREC
35
ms
Expected Data-Retention Time
(Oscillator ON)
tDR
10
years
5, 6
POWER-UP/DOWN TIMING (5V DEVICE)
13 of 16
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
POWER-UP/DOWN CHARACTERISTICS (3.3V)
(VCC = 3.3V 10%, TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
CE or WE at VIH, Before Power-
Down
tPD
0
s
VCC Fall Time: VPF(MAX) to VPF(MIN)
VCC Rise Time: VPF(MIN) to VPF(MAX)
VPF to RST High
tF
tR
300
0
s
s
tREC
35
ms
Expected Data-Retention Time
(Oscillator ON)
tDR
10
years
5, 6
POWER-UP/DOWN WAVEFORM TIMING (3.3V DEVICE)
CAPACITANCE
(TA = +25°C)
PARAMETER
SYMBOL
CIN
MIN
TYP
MAX
UNITS
NOTES
Capacitance On All Input Pins
Capacitance On All Output Pins
14
10
pF
pF
CO
14 of 16
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC TEST CONDITIONS
Output Load: 50pF + 1TTL Gate
Input Pulse Levels: 0 to 3.0V
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
NOTES:
1) Voltages are referenced to ground.
2) Typical values are at +25C and nominal supplies.
3) Outputs are open.
4) Battery switchover occurs at the lower of either the battery terminal voltage or VPF
5) Data-retention time is at +25C.
.
6) Each DS1744 has a built-in switch that disconnects the lithium source until the user first applies VCC.
The expected tDR is defined for DIP modules and assembled PowerCap modules as a cumulative time
in the absence of VCC starting from the time power is first applied by the user.
7) RTC modules (DIP) can be successfully processed through conventional wave-soldering techniques as
long as temperature exposure to the lithium energy source contained within does not exceed +85C.
Post-solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is
not used.
In addition, for the PowerCap:
a.) Maxim recommends that PowerCap module bases experience one pass through solder reflow
oriented with the label side up (“live-bug”).
b.) Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3
seconds. To solder, apply flux to the pad, heat the lead frame pad, and apply solder. To remove
the part, apply flux, heat the lead frame pad until the solder reflows, and use a solder wick to
remove solder.
8) tAH1, tDH1 are measured from WE going high.
9) tAH2, tDH2 are measured from CE going high.
10) tWC = 200ns.
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-”
in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
28 EDIP
PACKAGE CODE
MDF28+3
DOCUMENT NO.
21-0245
LAND PATTERN NO.
—
—
34 PWRCP
PC2+2
21-0246
15 of 16
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
REVISION HISTORY
REVISION
PAGES
CHANGED
DESCRIPTION
DATE
Updated the Ordering Information table to include only lead-free parts; updated the
Absolute Maximum Ratings section to include the storage temperature range and lead and
soldering temperatures for EDIP and PowerCap packages; added Note 10 to the ICC
parameter in the DC Electrical Characteristics tables (for 5.0V and 3.3V) and the Notes
section; updated the Package Information table
9/10
3, 8, 9, 15
16 of 16
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses
are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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